LM8327
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LM8327 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and
ACCESS.bus Host Interface
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FEATURES, KEY
FEATURES, KEY DEVICE
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Internal RC Oscillator, no External Clock
Required
Internal PWM Clock Generation, no External
Clock Required
Programmable I2C-compatible ACCESS.Bus
Address (Default 0x8A)
Support for Keypad Matrices of up to of 8 x 12
Keys, Plus 8 Special Function (SF) Keys, for a
Full 104 Key Support
Support for up to 26 Direct Connect Keys
I2C-Compatible ACCESS.Bus Slave Interface at
100 kHz (Standard-Mode) and 400 kHz (FastMode)
Three Host-Programmable PWM Outputs for
Smooth LED Brightness Modulation
Supports General-Purpose I/O Expansion on
Pins not Otherwise Used for Keypad or PWM
Output
15-byte Key Event Buffer
Multiple Key Event Storage
Key Events, Errors, and Dedicated Hardware
Interrupts Request Host Service by Asserting
an IRQ Output
Automatic HALT Mode for Low Power
Operation
Wake-Up from HALT Mode on any Interface
(Rising Edge, Falling Edge or Pulse)
Three PWM Outputs with Dedicated Script
Buffer for up to 32 Commands
Register-Based Command Interpreter with
Auto-Increment Address
FEATURES, HOST-CONTROLLED
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PWM Scripting for Three PWM Outputs
Period of Inactivity that Triggers Entry into
HALT Mode
Debounce Time for Reliable Key Event Polling
Configuration of General Purpose I/O Ports
Various Initialization Options (Keypad Size,
etc.)
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1.8V ± 10% Single-Supply Operation
On-Chip Power-On Reset (POR)
ESD Glitch Filter on RESETN Pin
Watchdog Timer
Dedicated Slow Clock Input for 32 kHz up to
8MHz
−40°C to +85°C Temperature Range
36-pin csBGA Package
APPLICATIONS:
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Cordless Phones
Smart Handheld Devices
Keyboard Applications
DESCRIPTION
The LM8327 GenI/O-Expander and Keypad
Controller is a dedicated device to unburden a host
processor from scanning a matrix-addressed keypad
and to provide flexible and general purpose, hostprogrammable
input/output
functions.
Three
independent PWM timer outputs are provided for
dynamic LED brightness modulation.
It communicates with a host processor through an
I2C-compatible ACCESS.bus serial interface. It can
communicate in Standard (100 kHz) and Fast-Mode
(400 kHz) in slave Mode only.
All available input/output pins can alternately be used
as a direct key input connection, an input or an output
in a keypad matrix, or as a host-programmable
general purpose input or output.
Any pin programmed as an input can also sense
hardware interrupts. The interrupt polarity (“high-tolow” or “low-to-high” transition) is thereby
programmable.
The LM8327 follows a predefined register based set
of commands. Upon startup (power on) a
configuration file must be sent from the host to setup
the hardware of the device.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
LM8327
SNLS329A – SEPTEMBER 2011 – REVISED MAY 2013
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LM8327 Function Blocks
Pin Assignments
Figure 1. 36-Pin csBGA (Top View)
See Package Number NYB0036A
2
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SIGNAL DESCRIPTIONS
DEVICE PIN FUNCTIONS
KEY AND ALTERNATE FUNCTIONS OF ALL DEVICE PINS
Ball
Function 0
Function 1
D2
Direct Keypad24
Clock In
D1
Direct Keypad25
F3
A4
F4
Function 2
Function 3
Pin Count
Ball Name
Genio
1
DIRECT24
CLKIN
Genio
1
DIRECT25
Interrupt
1
IRQN
Supply Voltage
2
VCC
C1
ResetN
1
RESETN
E1
Main I2C - Clk
1
SCL
E2
Main I2C - Data
1
SDA
A6
Direct Keypad0
Keypad - I/O X0
Genio
1
DIRECT0
KPX0
A5
Direct Keypad1
Keypad - I/O X1
Genio
1
DIRECT1
KPX1
F1
Direct Keypad2
Keypad - I/O X2
Genio
1
DIRECT2
KPX2
F2
Direct Keypad3
Keypad - I/O X3
Genio
1
DIRECT3
KPX3
A2
Direct Keypad4
Keypad - I/O X4
Genio
1
DIRECT4
KPX4
B3
Direct Keypad5
Keypad - I/O X5
Genio
1
DIRECT5
KPX5
A3
Direct Keypad6
Keypad - I/O X6
Genio
1
DIRECT6
KPX6
B4
Direct Keypad7
Keypad - I/O X7
Genio
1
DIRECT7
KPX7
C6
Direct Keypad8
Keypad - I/O Y0
Genio
1
DIRECT8
KPY0
C5
Direct Keypad9
Keypad - I/O Y1
Genio
1
DIRECT9
KPY1
B6
Direct Keypad10
Keypad - I/O Y2
Genio
1
DIRECT10
KPY2
B5
Direct Keypad11
Keypad - I/O Y3
Genio
1
DIRECT11
KPY3
B2
Direct Keypad12
Keypad - I/O Y4
Genio
1
DIRECT12
KPY4
A1
Direct Keypad13
Keypad - I/O Y5
Genio
1
DIRECT13
KPY5
B1
Direct Keypad14
Keypad - I/O Y6
Genio
1
DIRECT14
KPY6
C2
Direct Keypad15
Keypad - I/O Y7
Genio
1
DIRECT15
KPY7
E3
Direct Keypad16
Keypad - I/O Y8
Genio
1
DIRECT16
KPY8
D5
Direct Keypad17
Keypad - I/O Y9
Genio
1
DIRECT17
KPY9
E6
Direct Keypad18
Keypad - I/O Y10
Genio
1
DIRECT18
KPY10
F6
Direct Keypad19
Keypad - I/O Y11
Genio
1
DIRECT19
KPY11
E4
Direct Keypad20
PWM output 0
Genio
1
DIRECT20
PWM0
Clockout
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KEY AND ALTERNATE FUNCTIONS OF ALL DEVICE PINS (continued)
Ball
Function 0
Function 1
F5
Direct Keypad21
E5
Direct Keypad22
D6
Direct Keypad23
C3
C4
D3
D4
Function 2
Function 3
Pin Count
Ball Name
PWM output 1
Genio
1
DIRECT21
PWM1
PWM output 2
Genio
1
DIRECT22
PWM2
Genio
1
DIRECT23
GENIO1
Ground
4
GND
TOTAL
36
PIN CONFIGURATION AFTER RESET
Upon power-up or RESET the LM8327 will have defined states on all pins. provides a comprehensive overview
on the states of all functional pins.
PIN CONFIGURATION AFTER RESET
Pins
DIRECT KEYPAD 0
DIRECT KEYPAD 1
DIRECT KEYPAD 2
DIRECT KEYPAD 3
DIRECT KEYPAD 4
DIRECT KEYPAD 5
DIRECT KEYPAD 6
DIRECT KEYPAD 7
DIRECT KEYPAD 8
DIRECT KEYPAD 9
DIRECT KEYPAD 10
DIRECT KEYPAD 11
DIRECT KEYPAD 12
DIRECT KEYPAD 13
DIRECT KEYPAD 14
DIRECT KEYPAD 15
DIRECT KEYPAD 16
DIRECT KEYPAD 17
DIRECT KEYPAD 18
DIRECT KEYPAD 19
DIRECT KEYPAD 20
DIRECT KEYPAD 21
DIRECT KEYPAD 22
DIRECT KEYPAD 23
DIRECT KEYPAD 24
DIRECT KEYPAD 25
IRQN
SCL
SDA
4
Pin States
Full Buffer mode input with an on-chip pull-up resistor enabled.
Open Drain mode with no pull resistor enabled, driven low.
NOTE: The IRQN is driven low after Power-On Reset due to PORIRQ signal. The
value 0x01 must be written to the RSTINTCLR register (0x84) to release the IRQN pin.
Open Drain mode with no pull resistor enabled.
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Typical Application Setup
Figure 2. LM8327 in a Typical Setup with Standard Handset Keypad
FEATURES
The following features are supported with the application example shown above:
Hardware
Hardware
• 4 x 8 keys and 8 Special Function (SF) keys for 40 keys.
• ACCESS.bus interface for communication with a host device.
– Communication speeds supported are: 100 kHz standard mode and 400 kHz fast mode of operation.
• Interrupt signal (IRQN) to indicate any keypad or hardware interrupt events to the host.
• Sophisticated PWM function block with 3 independent channels to control color LED.
• External clock input for accurate PWM clock (not used).
• Four host-programmable dedicated general-purpose output pins (GPIOs:KPY4:7) supporting I/O-expansion
capabilities for host device.
• Six host-programmable dedicated direct key connection input pins (DIRECT 16:19, 23, 25) with wake-up
supporting I/O-expansion capabilities for host device.
Communication Layer
• Versatile register-based command integration supported from on-chip command interpreter.
• Keypad event storage.
• Individual PWM script file storage and execution control for 3 PWM channels.
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Halt Mode
HALT MODE DESCRIPTION
The fully static architecture of the LM8327 allows stopping the internal RC clock in Halt mode, which reduces
power consumption to the minimum level. Figure 3 shows an estimate of the current in Halt mode at the
maximum VCC (1.98V) from 25°C to +85°C.
Figure 3. Halt Current vs. Temperature at 1.98V
Halt mode is entered when no key-press event, key-release event, or is detected for a certain period of time (by
default, 1020 milliseconds). The mechanism for entering Halt mode is always enabled in hardware, but the host
can program the period of inactivity which triggers entry into Halt mode using the autosleep function. (See
Table 50.)
ACCESS.BUS ACTIVITY
When the LM8327 is in Halt mode, only activity on the ACCESS.bus interface that matches the LM8327 Slave
Address will cause the LM8327 to exit from Halt mode. However, the LM8327 will not be able to acknowledge
the first bus cycle immediately following wake-up from Halt mode. It will respond with a negative
acknowledgement, and the host should then repeat the cycle. A peripheral that is continuously active can share
the bus since this activity will not prevent the LM8327 from entering Halt mode.
LM8327 Programming Interface
The LM8327 operation is controlled from a host device by a complete register set, accessed via the I2Ccompatible ACCESS.bus interface. The ACCESS.bus communication is based on a READ/WRITE structure,
following the I2C transmission protocol. All functions can be controlled by configuring one or multiple registers.
Please refer to LM8327 Register Set for the complete register set.
ACCESS.BUS COMMUNICATION
Figure 4 shows a typical read cycle initiated by the host.
Figure 4. Master/Slave Serial Communication (Host to LM8327)
6
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Table 1. Definition of Terms used in Serial Command Example
Term
Bits
S
Description
START Condition (always generated from the master device)
ADDRESS
7
Slave address of LM8327 sent from the host
R/W
1
This bit determines if the following data transfer is from master to slave (data write) or from slave to
master (data read).
0: Write
1: Read
ACK
1
An acknowledge bit is mandatory and must be appended on each byte transfer. The Acknowledge status
is actually provided from the slave and indicates to the master that the byte transfer was successful.
REG
8
The first byte after sending the slave address is the REGISTER byte which contains the physical address
the host wants to read from or write to.
RS
Repeated START condition
DATA
8
The DATA field contains information to be stored into a register or information read from a register.
NACK
1
Not Acknowledge Bit. The Not Acknowledge status is assigned from the Master receiving data from a
slave. The NACK status will actually be assigned from the master in order to signal the end of a
communication cycle transfer
P
STOP condition (always generated from the master device).
All actions associated with the non-shaded boxes in Figure 4 are controlled from the master (host) device.
All actions associated with the shaded boxes in Figure 4 are controlled from the slave (LM8327) device.
The master device can send subsequent REGISTER addresses separated by Repeated START conditions. A
STOP condition must be set from the master at the very end of a communication cycle.
It is recommended to use Repeated START conditions in multi-Master systems when sending subsequent
REGISTER addresses. This technique will make sure that the master device communicating with the LM8327
will not loose bus arbitration.
Starting a Communication Cycle
There are two reasons for the host device to start communication to the LM8327:
1. The LM8327 device has set the IRQN line low in order to signal a key - event or any other condition which
initializes a hardware interrupt from LM8327 to the host.
2. The host device wants to set a GENIO port, read from a GENIO port, configure a GENIO port, and read the
status from a register or initialize any other function which is supported from the LM8327. In case a GENIO
shall be read it will be most likely, that the LM8327 device will be residing in “sleep mode”. In this mode the
system clock will be off to establish the lowest possible current consumption. If the host device starts the
communication under this condition the LM8327 device will not be able to acknowledge the first attempt of
sending the slave address. The LM8327 will wake up because of the START condition but it can’t establish
the internal timing to scan the first byte received. The master device must therefore apply a second attempt
to start the communication with the LM8327 device.
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Communication Initialized from Host (Restart from Sleep Mode)
Figure 5. Host Starts Communication While LM8327 is in Sleep Mode
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•
In the timing diagram shown in Figure 5 the LM8327 resides in sleep mode. Since the LM8327 device can’t
acknowledge the slave address the host must generate a STOP condition followed by a second START
condition.
On the second attempt the slave address is being acknowledged from the LM8327 device because it is in
active mode now.
The host can send different WRITE and/or READ commands subsequently after each other.
The host must finally free the bus by generating a STOP condition.
ACCESS.Bus Communication Flow
The LM8327 will only be driven in slave mode. The maximum communication speed supported is Fast Mode
(FS) which is 400 kHz. The device can be heavily loaded as it is processing different kind of events caused from
the human interface and the host device. In such cases the LM8327 may temporarily be unable to accept new
commands and data sent from the host device.
Please Note: “It is a legitimate measure of the slave device to hold SCL line low in such cases in order to force
the master device into a waiting state!. It is therefore the obligation of the host device to detect such cases.
Typically there is a control bit set in the master device indicating the Busy status of the bus. As soon as the SCL
line is released the host can continue sending commands and data.”
Further Remarks:
• In systems with multiple masters it is recommended to separate commands with Repeat START conditions
rather than sending a STOP - and another START - condition to communicate with the LM8327 device.
• Delays enforced by the LM8327 during very busy phases of operation should typically not exceed a duration
of 100 µsec.
• Normally the LM8327 will clock stretch after the acknowledge bit is transmitted; however, there are some
conditions where the LM8327 will clock stretch between the SDA Start bit and the first rising edge of SCL.
Auto Increment
In order to improve multi-byte register access, the LM8327 supports the auto increment of the address pointer.
A typical protocol access sequence to the LM8327 starts with the I2C-compatible ACCESS.bus address, followed
by REG, the register to access (see Figure 4). After a REPEATED START condition the host reads/writes a data
byte from/to this address location. If more than one byte is transmitted, the LM8327 automatically increments the
address pointer for each data byte by 1. The address pointer keeps the status until the STOP condition is
received.
The LM8327 always uses auto increments unless otherwise noted.
Please refer to Table 2 and Table 3 for the typical ACCESS.bus flow of reading and writing multiple data bytes.
8
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Reserved Registers and Bits
The LM8327 includes reserved registers for future implementation options. Please use value 0 on a write to all
reserved register bits.
Global Call Reset
The LM8327 supports the Global Call Reset as defined in the I2C Specification, which can be used by the host to
reset all devices connected to interface. The Global call reset is a single byte ACCESS.bus/I2C write of data byte
0x06 to slave address 0x00.
The Global Call Reset changes the I2C-compatible ACCESS.bus Slave address of the LM8327 back to its default
value of 0x8A.
Table 2. Multi-Byte Write with Auto Increment
2
Step
Master/Slave
I C Com.
1
M
S
Value
2
M
ADDR.
0x8A
3
M
R/W
0
4
S
ACK
5
M
REG
6
S
ACK
7
M
DATA
8
S
ACK
9
M
10
11
Address Pointer
Comment
START condition
I2C-compatible ACCESS.bus Address
Write
Acknowledge
0xAA
0xAA
Register Address, used as Address Pointer
0xAA
Acknowledge
0x01
0xAA
Write Data to Address in Pointer
0
0xAB
Acknowledge, Address pointer incremented
DATA
0x05
0xAB
Write Data to address 0xAB
S
ACK
0
0xAC
Acknowledge, Address pointer incremented
M
P
STOP condition
Table 3. Multi-Byte Read with Auto Increment
2
Step
Master/Slave
I C Com.
Value
Address Pointer
Comment
1
M
S
2
M
ADDR.
0x8A
3
M
R/W
0
4
S
ACK
5
M
REG
0xAA
Register Address, used as Address pointer
6
S
ACK
0xAA
Acknowledge
7
M
RS
0xAA
Repeated Start
8
M
ADDR.
0x8A
0xAA
I2C-compatible ACCESS.bus Address
9
M
R/W
1
10
S
ACK
0
0xAA
Acknowledge
11
S
DATA
0x01
0xAA
Read Data from Address in Pointer
12
M
ACK
0
0xAB
Acknowledge, Address Pointer incremented
13
S
DATA
0x05
0xAB
Read Data from Address in Pointer
14
M
NACK
0
0xAC
No Acknowledge, stops transmission
15
M
P
START condition
I2C-compatible ACCESS.bus Address
Write
Acknowledge
0xAA
Read
STOP condition
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Keyscan Operation
KEYSCAN INITIALIZATION
Figure 6. Keyscan Initialization
KEYSCAN INITIALIZATION EXAMPLE
Table 4 shows all the LM8327 register configurations to initialize keyscan:
• Keypad matrix configuration is 8 rows x 12 columns.
Table 4. Keyscan Initialization Example
10
Register name
Adress
Access Type
Value
Comment
CLKEN
0x8A
byte
0x01
enable keyscan clock
KBDSETTLE
0x01
byte
0x80
set the keyscan settle time to 12 msec
KBDBOUNCE
0x02
byte
0x80
set the keyscan debounce time to 12 msec
set the keyscan matrix size to 8 rows x 12 columns
KBDSIZE
0x03
byte
0x8C
KBDDEDCFG
0x04
word
0xFFFF
IOCFG
0xA7
byte
0x00
IOPC0
0xAA
word
0xAAAA
configure KPX[7:2] and KPY[11:2] pins as keyboard matrix
write default value to enable all pins as keyboard matrix
configure pull-up resistors for KPX[7:0]
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Table 4. Keyscan Initialization Example (continued)
Register name
Adress
Access Type
Value
IOPC1
0xAC
word
0x5555
configure pull-down resistors for KPY[7:0]
Comment
configure pull-down resistors for KPY[11:8]
IOPC2
0xAE
word
0x0055
KBDIC
0x08
byte
0x03
clear any pending interrupts
KBDMSK
0x09
byte
0x03
enable keyboard interrupts
KEYSCAN PROCESS
The LM8327 keyscan functionality is based on a specific scanning procedure performed in a 4ms interval. On
each scan all assigned key matrix pins are evaluated for state changes.
In case a key event has been identified, the event is stored in the key event FIFO, accessible via the EVTCODE
register. A key event can either be a key press or a key release. In addition, key presses are also stored in the
KBDCODE[3:0] registers. As soon as the EVTCODE FIFO includes a event, the device sets the RAW keyboard
event interrupt REVTINT. The RSINT interrupt is set anytime the keyboard status has changed.
Depending on the interrupt masking for the keyboard events (KBDMSK) and the masked interrupt handling
(KBDMIS), the pin IRQN will follow the IRQST.KBDIRQ status, which is set as soon as one interrupt in KBDRIS
is set.
Figure 7 shows the basic flow of a scanning process and which registers are affected.
Figure 7. Example Keyscan Operation for
1 Key Press and Release
READING KEYSCAN STATUS BY THE HOST
In order to keep track of the keyscan status, the host either needs to regularly poll the EVTCODE register or
needs to react on the Interrupt signaled by the IRQN pin.
Figure 8 gives an example on which registers to read to get the keyboard events from the LM8327 and how they
influence the interrupt event registers. The example is based on the assumption that the LM8327 has indicated
the keyboard event by the IRQN pin.
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Since the interrupt pin has various sources, the host first checks the IRQST register for the interrupt source. If
KBDIRQ is set, the host can check the KBDMIS register to define the exact interrupt source. KBDMIS contains
the masked status of KBDRIS and reflects the source for raising the interrupt pin. The interrupt mask is defined
by KBDMSK. The complete status of all pending keyboard interrupts is available in the raw interrupt register
KBDRIS.
After evaluating the interrupt source the host starts reading the EVTCODE or KBDCODE register. In this
example the host first reads the KBDCODE to get possible key press events and afterwards reads the complete
event list by reading the EVTCODE register until all events are captured (0x7F indicates end of buffer).
Reading KBDCODE clears the RSINT interrupt bit if all keyboards events are emptied. In the same way,
REVTINT is cleared in case the EVTCODE FIFO reaches its empty state on read.
The event buffer content and the REVTINT and RELINT (lost event) interrupt bits are also cleared if the
KBDIC.EVTIC bit is set.
Interrupt bits in the masked interrupt register KBDMIS follow the masked KBDRIS status.
In order to support efficient Multi-byte reads from EVTCODE, the autoincrement feature is turned off for this
register. Therefore the host can continuously read the complete EVTCODE buffer by sending one command.
Figure 8. Example Host Reacting to
Interrupt for Keypad Event
MULTIPLE KEY PRESSES
The LM8327 supports up to four simultaneous key presses. Any time a single key is pressed KBDCODE0 is set
with the appropriate key code. If a second key is pressed, the key is stored in KBDCODE1 and the MULTIKEY
flag of KBDCODE0 is set. Additional key presses are stored in KBDCODE2 and KBDCODE3 accordingly. The
four registers signal the last multi-key press events.
All events are stored in parallel in the EVTCODE register for the complete set of events.
All KBDCODE[3:0] registers are cleared on read.
12
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Figure 9. Example Keyscan Operation for 2 Key Press Events
and 1 Key Release Event
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Direct Key Operation
DIRECT KEY INITIALIZATION
Figure 10. Direct Key Initialization
DIRECT KEY INITIALIZATION EXAMPLE
Table 5 shows all the LM8327 register configurations to initialize direct keys.
• Direct key configuration is for 26 direct keys.
Table 5. Direct Key Initialization Example
14
Register Name
Address
Access Type
Value
CLKEN
0x8A
byte
0x02
Enable direct key clock
Comment
DBOUNCE
0xE7
byte
0x04
Set the keyscan debounce time to 12 msec.
GPIOIBE0
0xCC
byte
0x00
Configure single key event detection for DK[7:0]
GPIOIBE1
0xCD
byte
0x00
Configure single key event detection for DK[15:8]
GPIOIBE2
0xCE
byte
0x00
Configure single key event detection for DK[23:16]
GPIOIEV0
0xCF
byte
0x00
Configure press key event detection DK[7:0]
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Table 5. Direct Key Initialization Example (continued)
Register Name
Address
Access Type
Value
GPIOIEV1
0xD0
byte
0x00
Configure press key event detection DK[15:8]
Comment
GPIOIEV2
0xD1
byte
0x00
Configure press key event detection DK[23:16]
GPIOIE0
0xD2
byte
0x00
Disable GPI interrupts for DK[7:0]
GPIOIE1
0xD3
byte
0x00
Disable GPI interrupts for DK[15:8]
GPIOIE2
0xD4
byte
0x00
Disable GPI interrupts for DK[23:16]
IOCFG
0xA7
byte
0x00
Write default value to enable all pins as direct keys
IOPC0
0xAA
word
0xAAAA
Configure pull-up resistors for DK[7:0]
IOPC1
0xAC
word
0xAAAA
Configure pull-up resistors for DK[15:8]
IOPC2
0xAE
word
0xAAAA
Configure pull-up resistors for DK[23:16]
DKBDIC
0xF2
byte
0x01
Clear any pending interrupts
DKBDMSK
0xF3
byte
0x00
Enable direct key and lost direct key interrupts
DIRECT0
0xEC
byte
0xFF
Enable pins as DK[7:0]
DIRECT1
0xED
byte
0xFF
Enable pins as DK[15:8]
DIRECT2
0xEE
byte
0xFF
Enable pins as DK[23:16]
DIRECT3
0xEF
byte
0x03
Enable pins as DK[25:24]
PWM Timer
The LM8327 supports a timer module dedicated to smooth LED control techniques (lighting controls).
The PWM timer module consists of three independent timer units of which each can generate a PWM output with
a fixed period and automatically incrementing or decrementing variable duty cycle. The timer units are all clocked
with a slow (32.768 kHz) clock whereas the interface operates with the main system clock.
OVERVIEW OF PWM FEATURES
• Each PWM can establish fixed - or variable - duty-cycle signal sequences on its output.
• Each PWM can trigger execution of any pre-programmed task on another PWM channel.
• The execution of any pre-programmed task is self-sustaining and does not require further interaction from the
host.
• 64-byte script buffer for each PWM for up to 32 consecutive instructions.
• Direct addressing within script buffer to support multiple PWM tasks in one buffer.
OVERVIEW ON PWM SCRIPT COMMANDS
The commands listed in Table 6 are dedicated to the slow PWM timers.
Please note: The PWM Script commands are not part of the command set supported by the LM8327 command
interpreter. These commands must be transferred from the host with help of the register-based command set.
Table 6. PWM Script Commands
13
1
2
Command
15
14
11
10
RAMP
0
PRESCALE
STEPTIME
SET_PWM
0
1
0
9
GO_TO_
8
7
6
5
SIGN
4
3
2
1
0
INCREMENT
PWMVALUE
0
START
BRANCH
1
0
1
END
1
1
0
TRIGGER
1
1
1
LOOPCOUNT
1
INT
ADDR
STEPNUMBER
X
WAITTRIGGER
SENDTRIGGER
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RAMP COMMAND
A RAMP command will vary the duty cycle of a PWM output in either direction (up or down). The INCREMENT
field specifies the amount of steps for the RAMP. The maximum amount of steps which can be executed with
one RAMP Command is 126 which is equivalent to 50%. The SIGN bit field determines the direction of a RAMP
(up or down). The STEPTIME field and the PRESCALE bit determine the duration of one step. Based on a
32.768 kHz clock, the minimum time resulting from these options would be 0.49 milliseconds and the maximum
time for one step would be 1 second.
Table 7. RAMP Command Bit Fields
15
14
13
0
PRESCALE
12
11
10
9
8
7
STEPTIME
6
5
4
SIGN
3
2
1
0
INCREMENT
Table 8. Description of Command Bit Fields of the RAMP Command
Bit or Field
Value
PRESCALE
STEPTIME
Description
0
Divide the 32.768 kHz clock by 16
1
Divide the 32.768 kHz clock by 512
1 - 63
SIGN
INCREMENT
Number of prescaled clock cycles per step
0
Increment RAMP counter
1
Decrement RAMP counter
Number of steps executed by this instruction; a value of 0 functions as a WAIT
determined by STEPTIME.
0 - 126
SET_PWM COMMAND
The SET_PWM command does not allow generation of a PWM output with a fixed duty cycle between 0% and
100%. This command will set the starting duty cycle MIN SCALE or FULL SCALE (0% or 100%). A RAMP
command following the SET_PWM command will finally establish the desired duty cycle on the PWM output.
Table 9. SET_PWM Command Bit Fields
15
14
13
12
11
10
9
8
0
1
0
0
0
0
0
0
7
6
5
4
3
2
1
0
DUTYCYCLE
Table 10. Description of Bit Fields of the SET_PWM Command
Bit or Field
Value
Description
0
DUTYCYCLE
Duty cycle is 0%.
255
Duty cycle is 100%.
GO_TO_START COMMAND
The GO_TO_START command jumps to the first command in the script command file.
Table 11. GO_TO_START Command Bit Fields
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
BRANCH COMMAND
The BRANCH command jumps to the specified command in the script command file. The BRANCH is executed
with either absolute or relative addressing. In addition, the command gives the option of looping for a specified
number of repetitions.
Please note: Nested loops are not allowed.
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Table 12. BRANCH Command Bit Fields
15
14
13
1
0
1
12
11
10
9
8
7
6
LOOPCOUNT
5
4
3
ADDR
2
1
0
STEPNUMBER
Table 13. Description of Command Bit Fields of the BRANCH Command
Bit or Field
Value
Description
0
LOOPCOUNT
Loop until a STOP PWM SCRIPT command is issued by the host.
1 - 63
ADDR
STEPNUMBER
Number of loops to perform.
0
Absolute addressing
1
Relative addressing
Depending on ADDR:
ADDR=0: Addr to jump to
ADDR=1: Number of backward steps
0 - 63
TRIGGER COMMAND
Triggers are used to synchronize operations between PWM channels. A TRIGGER command that sends a
trigger takes sixteen 32.768 kHz clock cycles, and a command that waits for a trigger takes at least sixteen
32.768 kHz clock cycles.
A TRIGGER command that waits for a trigger (or triggers) will stall script execution until the trigger conditions are
satisfied. On trigger it will clear the trigger(s) and continue to the next command.
When a trigger is sent, it is stored by the receiving channel and can only be cleared when the receiving channel
executes a TRIGGER command that waits for the trigger.
Table 14. TRIGGER Command Bit Fields
15
14
13
1
1
1
12
11
10
9
8
7
6
WAITTRIGGER
5
4
3
2
1
SENDTRIGGER
0
0
Table 15. Description of Command Bit Fields
Field
WAITTRIGGER
SENDTRIGGER
Value
Description
000xx1
Wait for trigger from channel 0
000x1x
Wait for trigger from channel 1
0001xx
Wait for trigger from channel 2
000xx1
Send trigger to channel 0
000x1x
Send trigger to channel 1
0001xx
Send trigger to channel 2
END COMMAND
The END command terminates script execution. It will only assert an interrupt to the host if the INT bit is set to
“1”.
When the END command is executed, the PWM output will be set to the level defined by PWMCFG.PWMPOL
for this channel. Also, the script counter is reset back to the beginning of the script command buffer.
Please note: If a PWM channel is waiting for the trigger (last executed command was "TRIGGER") and the
script execution is halted then the "END" command can’t be executed because the previous command is still
pending. This is an exception - in this case the IRQ signal will not be asserted.
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Table 16. END Command Bit Fields
15
14
13
12
11
1
1
0
1
INT
10
9
8
7
6
5
4
3
2
1
0
0
Table 17. Description of Command Bit Fields of the END Command
Field
Value
INT
Description
0
No interrupt will be sent.
1
Set TIMRIS.CDIRQ for this PWM channel to notify that program has ended.
LM8327 Register Set
KEYBOARD REGISTERS AND KEYBOARD CONTROL
Keyboard selection and control registers are mapped in the address range from 0x01 to 0x10. This paragraph
describes the functions of the associated registers down to the bit level.
KBDSETTLE - Keypad Settle Time Register
Table 18. KBDSETTLE - Keypad Settle Time Register
Register - Name
Address
Type
KBDSETTLE
0x01
R/W
Bit - Name
Bit
Default
Register Function
Initial time for keys to settle, before the key-scan process is started.
Bit Function
The default value 0x80 : 0xBF sets a time target of 12 msec
Further time targets are as follows:
0xC0 - 0xFF: 16 msec
WAIT[7:0]
7:0
0x80
0x80 - 0xBF: 12 msec
0x40 - 0x7F: 8 msec
0x01 - 0x3F: 4 msec
0x00 : no settle time
KBDBOUNCE - Debounce Time Register
Table 19. KBDBOUNCE - Debounce Time Register
Register - Name
Address
Type
KBDBOUNCE
0x02
R/W
Bit - Name
Bit
Default
Register Function
Time between first detection of key and final sampling of key.
Bit Function
The default value 0x80 : 0xBF sets a time target of 12 msec.
Further time targets are as follows:
0xC0 - 0xFF: 16 msec
WAIT[7:0]
7:0
0x80
0x80 - 0xBF: 12 msec
0x40 - 0x7F: 8 msec
0x01 - 0x3F: 4 msec
0x00: no debouncing time
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KBDSIZE - Set Keypad Size Register
Table 20. KBDSIZE - Set Keypad Size Register
Register - Name
Address
Type
KBDSIZE
0x03
R/W
Bit - Name
Bit
Default
Register Function
Defines the physical keyboard matrix size.
Bit Function
Number of rows in the keyboard matrix:
ROWSIZE[3:0]
7:4
0x2
0x0: free all rows to become GPIO, KPX[1:0] used as dedicated key inputs
if scanning is enabled by CLKEN.KBEN.
0x1: (illegal value)
0x2 - 0x8: Number of rows in the matrix
Number of columns in the keyboard matrix:
COLSIZE[3:0]
3:0
0x2
0x0: free all rows to become GPIO, KPY[1:0] used as dedicated key inputs
if scanning is enabled by CLKEN.KBEN
0x1: (illegal value)
0x2 - 0xC: Number of columns in the matrix
KBDDEDCFG - Dedicated Key Register
Table 21. KBDDEDCFG - Dedicated Key Register
Register - Name
Address
Type
KBDDEDCFG
0x04
R/W
Bit - Name
Bit
Default
Register Function
Defines if a key is used as a standard keyboard/GPIO pin or whether it is
used as dedicated key input.
Bit Function
Each bit in ROW [7:2] corresponds to ball KPX7 : KPX2.
Bit=0: the dedicated key function applies.
ROW[7:2]
15:10
0x3F
Bit=1: no dedicated key function is selected. The standard GPIO
functionality applies according to register IOCFG or defined keyboard
matrix.
Each bit in COL [11:10] corresponds to ball KPY11 : KPY10.
Bit=0: the dedicated key function applies.
COL[11:10]
9:8
0x03
Bit=1: no dedicated key function is selected. The standard GPIO
functionality applies according to register IOCFG or defined keyboard
matrix.
Each bit in COL [9:2] corresponds to ball KPY9 : KPY2 and can be
configured individually.
COL[9:2]
7:0
0xFF
Bit=0: the dedicated key function applies.
Bit=1: no dedicated key function is selected. The standard GPIO
functionality applies according to register IOCFG or defined keyboard
matrix.
KBDRIS - Keyboard Raw Interrupt Status Register
Table 22. KBDRIS - Keyboard Raw Interrupt Status Register
Register - Name
Address
Type
KBDRIS
0x06
R
Bit - Name
Bit
Default
(reserved)
7:4
Register Function
Returns the status of stored keyboard interrupts.
Bit Function
(reserved)
Raw event lost interrupt.
RELINT
3
0x0
More than 8 keyboard events have been detected and caused the event
buffer to overflow. This bit is cleared by setting bit EVTIC of the KBDIC
register.
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Table 22. KBDRIS - Keyboard Raw Interrupt Status Register (continued)
Register - Name
Address
Type
Register Function
Raw keyboard event interrupt.
REVTINT
2
0x0
At least one key press or key release is in the keyboard event buffer.
Reading from EVTCODE until the buffer is empty will clear this interrupt.
Raw key lost interrupt indicates a lost key-code.
RKLINT
1
0x0
RSINT
0
0x0
This interrupt is asserted when RSINT has not been cleared upon
detection of a new key press or key release, or when more than 4 keys
are pressed simultaneously.
Raw scan interrupt.
Interrupt generated after keyboard scan, if the keyboard status has
changed.
KBDMIS - Keypad Masked Interrupt Status Register
Table 23. KBDMIS - Keypad Masked Interrupt Status Register
Register - Name
KBDMIS
Address
Type
0x07
R
Bit - Name
Bit
Default
(reserved)
7:4
Register Function
Returns the status on masked keyboard interrupts after masking with the
KBDMSK register.
Bit Functions
(reserved)
Masked event lost interrupt.
MELINT
3
0x0
MEVTINT
2
0x0
More than 8 keyboard events have been detected and caused the event
buffer to overflow. This bit is cleared by setting bit EVTIC of the KBDIC
register.
Masked keyboard event interrupt.
At least one key press or key release is in the keyboard event buffer.
Reading from EVTCODE until the buffer is empty will clear this interrupt.
Masked key lost interrupt.
MKLINT
1
0x0
MSINT
0
0x0
Indicates a lost key-code. This interrupt is asserted when RSINT has not
been cleared upon detection of a new key press or key release, or when
more than 4 keys are pressed simultaneously.
Masked scan interrupt.
Interrupt generated after keyboard scan, if the keyboard status has
changed, after masking process.
KBDIC - Keypad Interrupt Clear Register
Table 24. KBDIC - Keypad Interrupt Clear Register
Register - Name
Address
Default
KBDIC
0x08
W
Bit - Name
Bit
Default
Register Function
Setting these bits clears Keypad active Interrupts.
Bit Function
Switches off scanning of special function (SF) keys, when keyboard has
no special function layout.
SFOFF
7
0: keyboard layout and SF keys are scanned
1: only keyboard layout is scanned, SF keys are not scanned
20
(reserved)
6:2
(reserved)
EVTIC
1
Clear event buffer and corresponding interrupts REVTINT and RELINT by
writing a 1 to this bit position.
KBDIC
0
Clear RSINT and RKLINT interrupt bits by writing a 1 to this bit position.
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KBDMSK - Keypad Interrupt Mask Register
Table 25. KBDMSK - Keypad Interrupt Mask Register
Register - Name
Address
Type
Register Function
Configures masking of keyboard interrupts. Masked interrupts do not
trigger an event on the Interrupt output.
KBDMSK
0x09
R/W
Bit - Name
Bit
Default
(reserved)
7:4
MSKELINT
3
0x1
MSKEINT
2
0x1
MSKLINT
1
0x0
MSKSINT
0
0x0
In case the interrupt processes registers KBDCODE[3:0], MSKELINT and
MSKEINT should be set to 1. When the Event FIFO is processed,
MSKLINT and MSKSINT should be set. For keyboard polling operations,
all bits should be set and the polling operation consists of reading out the
EVTCODE.
Bit Function
(reserved)
0: keyboard event lost interrupt RELINT triggers IRQ line
1: keyboard event lost interrupt RELINT is masked
0: keyboard event interrupt REVINT triggers IRQ line
1: keyboard event interrupt REVINT is masked
0: keyboard lost interrupt RKLINT triggers IRQ line
1: keyboard lost interrupt RKLINT is masked
0: keyboard status interrupt RSINT triggers IRQ line
1: keyboard status interrupt RSINT is masked
KBDCODE0 - Keyboard Code Register 0
The key code detected by the keyboard scan can be read from the registers KBDCODE0: KBDCODE3. Up to 4
keys can be detected simultaneously. Each KBDCODE register includes a bit (MULTIKEY) indicating if another
key has been detected.
Please note: Reading out all key code registers (KBDCODE0 to KBDCODE3) will automatically reset the
keyboard scan interrupt RSINT the same way as an active write access into bit KBDIC of the interrupt clear
register does. Reading 0x7F from the KBDCODE0 register means that no key was pressed.
Table 26. KBDCODE0 - Keyboard Code Register 0
Register - Name
Address
Default
KBDCODE0
0x0B
R
Bit - Name
Bit
Default
Register Function
Holds the row and column information of the first detected key.
Bit Function
MULTIKEY
7
0x0
If this bit is 1 another key is available in KBDCODE1 register.
KEYROW[2:0]
6:4
0x7
ROW index of detected key (0 to 7)
KEYCOL[3:0]
3:0
0xF
Column index of detected (0 to 11, 12 for special function key).
KBDCODE1 - Keyboard Code Register 1
Table 27. KBDCODE1 - Keyboard Code Register 1
Register - Name
Address
Default
KBDCODE1
0x0C
R
Register Function
Holds the row and column information of the second detected key.
Bit - Name
Bit
Default
MULTIKEY
7
0x0
If this bit is 1 another key is available in KBDCODE2 register.
Bit Function
KEYROW[2:0]
6:4
0x7
ROW index of detected key (0 to 7)
KEYCOL[3:0]
3:0
0xF
Column index of detected key (0 to 11, 12 for special function key).
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KBDCODE2 - Keyboard Code Register 2
Table 28. KBDCODE2 - Keyboard Code Register 2
Register - Name
Address
Default
KBDCODE2
0x0D
R
Register Function
Holds the row and column information of the third detected key.
Bit - Name
Bit
Default
MULTIKEY
7
0x0
If this bit is 1 another key is available in KBDCODE3 register.
Bit Function
KEYROW[2:0]
6:4
0x7
ROW index of detected key (0 to 7)
KEYCOL[3:0]
3:0
0xF
Column index of detected key (0 to 11, 12 for special function key).
KBDCODE3 - Keyboard Code Register 3
Table 29. KBDCODE3 - Keyboard Code Register 3
Register - Name
Address
Default
KBDCODE3
0x0E
R
Bit - Name
Bit
Default
Register Function
Holds the row and column information of the forth detected key.
Bit Function
MULTIKEY
7
0x0
If this bit is set to “1” then more than 4 keys are pressed simultaneously.
KEYROW[2:0]
6:4
0x7
ROW index of detected key (0 to 7)
KEYCOL[3:0]
3:0
0xF
Column index of detected key (0 to 11, 12 for special function key).
EVTCODE - Key Event Code Register
Table 30. EVTCODE - Key Event Code Register
Register - Name
Address
Default
Bit Function
With this register a FIFO buffer is addressed storing up to 15 consecutive
events.
EVTCODE
0x10
R
Reading the value 0x7F from this address means that the FIFO buffer is
empty. See further details below.
NOTE: Auto increment is disabled on this register. Multi-byte read will
always read from the same address.
Bit - Name
Bit
Default
Bit Function
This bit indicates, whether the keyboard event was a key press or a key
release event.
RELEASE
7
0x0
0: key was pressed
1: key was released
KEYROW[2:0]
6:4
0x7
Row index of key that is pressed or released.
KEYCOL[3:0]
3:0
0xF
Column index of key that is pressed (0...11, 12 for special function key) or
released.
PWM TIMER CONTROL REGISTERS
The LM8327 provides three host-programmable PWM outputs useful for smooth LED brightness modulation. All
PWM timer control registers are mapped in the range from 0x60 to 0x7F. This paragraph describes the functions
of the associated registers down to the bit level.
TIMCFGx - PWM Timer 0, 1 and 2 Configuration Registers
Table 31. TIMCFGx - PWM Timer 0, 1 and 2 Configuration Registers
22
Register - Name
Address
TIMCFG0
0x60
TIMCFG1
0x68
TIMCFG2
0x70
Type
R/W
Register Function
This register configures interrupt masking and handles PWM start/stop
control of the associated PWM channel.
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Table 31. TIMCFGx - PWM Timer 0, 1 and 2 Configuration Registers (continued)
Register - Name
Address
Type
Register Function
Bit - Name
(x = 0, 1 or 2)
Bit
Default
Bit Function
CYCIRQxMSK
4
0x0
(reserved)
3:0
0x0
Interrupt mask for PWM CYCIRQx (see Table 35):
0: interrupt enabled
1: interrupt masked
(reserved)
PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Registers
Table 32. PWMCFGx - PWM Timer 0, 1 and 2 Configuration Control Registers
Register - Name
Address
Type
Register Function
This register defines interrupt masking and the output behavior for the
associated PWM channel.
PWMCFG0
0x61
PWMCFG1
0x69
PWMCFG2
0x71
Bit - Name
(x = 0, 1 or 2)
Bit
Default
CDIRQxMSK
3
0x0
R/W
PGEx is used to start and stop the PWM script execution.
PWMENx sets the PWM output to either reflect the generated pattern or
the value configured in PWMPOLx.
Bit Function
Mask for CDIRQ:
0: CDIRQ enabled
1: CDIRQ disabled/masked
Pattern Generator Enable. Start/Stop PWM command processing for this
channel. Script execution is started always from beginning.
PGEx
2
0x0
0: Pattern Generator disabled
1: Pattern Generator enabled
PWMENx
1
0x0
0: PWM disabled. PWM timer output assumes value programmed in
PWMPOL.
1: PWM enabled
Off-state of PWM output, when PWMEN=0.
PWMPOLx
0
0x0
0: PWM off-state is low
1: PWM off-state is high
TIMSCALx - PWM Timer 0, 1 and 2 Prescale Registers
Table 33. TIMSCALx - PWM Timer 0, 1 and 2 Prescale Registers
Register - Name
Address
Type
Register Function
TIMSCAL0
TIMSCAL1
TIMSCAL2
0x62
0x6A
0x72
R/W
The registers determine the divider of the CLKIN external clock. The
resulting clock is only used for PWM generation. The value should only be
changed while PWM is stopped. Since all 3 PWM channels use the same
slow clock, TIMSCAL0 affects all 3 PWM channels. TIMSCAL1 and
TIMSCAL2 are directly linked to TIMSCAL0.
Bit - Name
Bit
Default
SCAL[7:0]
7:0
0x0
Bit Function
CLKIN is divided by (SCAL+1).
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TIMSWRES - PWM Timer Software Reset Registers
Table 34. TIMSWRES - PWM Timer Software Reset Registers
Register - Name
Address
Type
Register Function
Reset control on all PWM timers.
TIMSWRES
0x78
W
A reset forces the pattern generator to fetch the first pattern and stops it.
Each reset stops all state-machines and timer.
Patterns stored in the pattern configuration register remain unaffected.
Interrupts on each timer are not cleared, they need to be cleared writing
into register TIMIC.
Bit - Name
Bit
(reserved)
7:3
SWRES2
2
Default
Bit Function
(reserved)
Software reset of timer 2.
0: no action
1: Software reset on timer 2, needs not to be written back to 0.
Software reset of timer 1.
SWRES1
1
0: no action
1: Software reset on timer 1, needs not to be written back to 0.
Software reset of timer 0.
SWRES0
0
0: no action
1: software reset on timer 0, needs not to be written back to 0.
TIMRIS - PWM Timer Interrupt Status Register
Table 35. TIMRIS - PWM Timer Interrupt Status Register
Register - Name
Address
Type
Register Function
This register returns the raw interrupt status from the PMW timers 0, 1 and
2.
TIMRIS
0x7A
R
CYCIRQx - Interrupt from the timers when PWM cycle is complete
(applies to the current PWM command residing in the active command
register of a PWM block).
CDIRQx - Interrupt from the pattern generator when PWM pattern code is
complete (applies to a completed task residing in the script buffer of a
PWM block).
Bit - Name
Bit
(reserved)
7:6
Default
Bit Functions
(reserved)
Raw interrupt status for CDIRQ timer2:
CDIRQ2
5
0x0
0: no interrupt pending
1: unmasked interrupt generated
Raw interrupt status for CDIRQ timer1:
CDIRQ1
4
0x0
0: no interrupt pending
1: unmasked interrupt generated
Raw interrupt status for CDIRQ timer0:
CDIRQ0
3
0x0
0: no interrupt pending
1: unmasked interrupt generated
Raw interrupt status for CYCIRQ timer2:
CYCIRQ2
2
0x0
0: no interrupt pending
1: unmasked interrupt generated
Raw interrupt status for CYCIRQ timer1:
CYCIRQ1
1
0x0
0: no interrupt pending
1: unmasked interrupt generated
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Table 35. TIMRIS - PWM Timer Interrupt Status Register (continued)
Register - Name
Address
Type
Register Function
Raw interrupt status for CYCIRQ timer0:
CYCIRQ0
0
0x0
0: no interrupt pending
1: unmasked interrupt generated
TIMMIS - PWM Timer Masked Interrupt Status Register
Table 36. TIMMIS - PWM Timer Masked Interrupt Status Register
Register - Name
Address
Type
Register Function
This register returns the masked interrupt status from the PMW timers 0,1
and 2. The raw interrupt status (TIMRIS) is masked with the associated
TIMCFGx.CYCIRQxMSK and PWMCFGx.CDIRQxMSK bits to get the
masked interrupt status of this register.
TIMMIS
0x7B
R
CYCIRQ - Interrupt from the timers when PWM cycle is complete (applies
to the current PWM command residing in the active command register of a
PWM block).
CDIRQ - Interrupt from the pattern generator when PWM pattern code is
complete (applies to a completed task residing in the script buffer of a
PWM block).
Bit - Name
Bit
(reserved)
7:6
Default
Bit Function
(reserved)
Interrupt after masking, indicates active contribution to the interrupt ball,
when set. Status for CDIRQ timer2:
CDIRQ2
5
0x0
0: no interrupt pending
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt ball,
when set. Status for CDIRQ timer1:
CDIRQ1
4
0x0
0: no interrupt pending
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt ball,
when set. Status for CDIRQ timer0:
CDIRQ0
3
0x0
0: no interrupt pending
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt ball,
when set. Status for CYCIRQ timer2:
CYCIRQ2
2
0x0
0: no interrupt pending
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt ball,
when set. Status for CYCIRQ timer1:
CYCIRQ1
1
0x0
0: no interrupt pending
1: interrupt generated
Interrupt after masking, indicates active contribution to the interrupt ball,
when set. Status for CYCIRQ timer0:
CYCIRQ0
0
0x0
0: no interrupt pending
1: interrupt generated
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TIMIC - PWM Timer Interrupt Clear Register
Table 37. TIMIC - PWM Timer Interrupt Clear Register
Register - Name
Address
Type
Register Function
This register clears timer and pattern interrupts.
TIMIC
0x7C
W
CYCIRQ - Interrupt from the timers when PWM cycle is complete (applies
to the current PWM command residing in the active command register of a
PWM block).
CDIRQ - Interrupt from the pattern generator when PWM pattern code is
complete (applies to a completed task residing in the script buffer of a
PWM block).
Bit - Name
Bit
(reserved)
7:6
Default
Bit Function
(reserved)
Clears interrupt CDIRQ timer2:
CDIRQ2
5
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CDIRQ timer1:
CDIRQ1
4
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CDIRQ timer0:
CDIRQ0
3
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CYCIRQ timer2:
CYCIRQ2
2
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CYCIRQ timer1:
CYCIRQ1
1
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
Clears interrupt CYCIRQ timer0:
CYCIRQ0
0
0: no effect
1: interrupt is cleared. Does not need to be written back to 0
PWMWP - PWM Timer Pattern Pointer Register
Table 38. PWMWP - PWM Timer Pattern Pointer Register
Register - Name
Address
Type
Register Function
Pointer to the pattern position inside the configuration register, which will
be overwritten by the next write access to be PWMCFG register.
PWMWP
0x7D
R/W
Bit - Name
Bit
Default
(reserved)
7
0x0
NOTE: 1 pattern consist of 2 bytes and not the byte position (low or high).
It is incremented by 1 every time a full PWMCFG register access (word) is
performed.
Bit Function
(reserved)
0 ≤ POINTER < 32 : timer0 patterns 0 to 31
POINTER[6:0]
6:0
0x0
32 ≤ POINTER < 64 : timer1 patterns 0 to 31
64 ≤ POINTER < 96 : timer2 patterns 0 to 31
96 ≤ POINTER < 128: not valid
26
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PWMCFG - PWM Script Register (Two Byte)
Table 39. PWMCFG - PWM Script Register
Register - Name
Address
Type
Register Function
Two byte pattern storage register for a PWM script command indexed by
PWMWP. PWMWP is automatically incremented.
PWMCFG
0x7E
W
To be applied by two consecutive parameter bytes in one I2C Write
Transaction.
NOTE: Autoincrement is disabled on this register. Address will stay at
0x7E for each word access.
Bit - Name
Bit
Default
Bit Function
CMD[15:8]
15:8
High byte portion of a PWM script command.
CMD[7:0]
7:0
Low byte portion of a PWM script command.
INTERFACE CONTROL REGISTERS
The following section describes the functions of special control registers provided for the main controller.
The manufacturer code MFGCODE and the software revision number SWREV tell the main device which
configuration file has to be used for this device.
NOTE: I2CSA and MFGCODE use the same address. They just differentiate in the access type:
• Write - I2CSA
• Read - MFGCODE
I2CSA - I2C-Compatible ACCESS.bus Slave Address Register
Table 40. I2CSA - I2C-Compatible ACCESS.bus Slave Address Register
Register - Name
Address
Type
I2CSA
0x80
W
Bit - Name
Bit
Default
SLAVEADDR[7:1]
7:1
(reserved)
0
0x45
Register Function
I2C-compatible ACCESS.bus Slave Address.
The address is internally applied after the next I2C STOP.
Bit Function
2
7-bit address field for the I C-compatible ACCESS.bus slave address.
(reserved)
MFGCODE - Manufacturer Code Register
Table 41. MFGCODE - Manufacturer Code Register
Register - Name
Address
Type
MFGCODE
0x80
R
Bit - Name
Bit
Default
MFGBIT
7:0
0x00
Register Function
Manufacturer code of the LM8327.
Bit Function
8-bit field containing the manufacturer code.
SWREV - Software Revision Register
Table 42. SWREV - Software Revision Register
Register - Name
Address
Type
Register Function
Software revision code of the LM8327.
SWREV
0x81
R
Bit - Name
Bit
Default
SWBIT
7:0
0xC4
NOTE: Writing the SW revision with the inverted value triggers a reset
(see Table 43).
Bit Function
8-bit field containing the SW Revision number.
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SWRESET - Software Reset
Table 43. SWRESET - Software Reset Register
Register - Name
Address
Type
Register Function
Software reset.
SWRESET
0x81
W
NOTE: the reset is only applied if the supplied parameter has the inverted
value as SWBIT.
Reading this register provides the software revision (see Table 42).
Bit - Name
Bit
SWBIT
7:0
Default
Bit Function
Reapply inverted value for software reset.
RSTCTRL - System Reset Register
This register allows to reset specific blocks of the LM8327. For global reset of the I/OExpander the I2C command
'General Call reset' is used (see Global Call Reset). This will reset the slave address back to 0x8A. During an
active reset of a module, the LM8327 blocks the access to the module registers. A read will return 0, write
commands are ignored.
Table 44. RSTCTRL - System Reset Register
Register - Name
Address
Type
Register Function
RSTCTRL
0x82
R/W
Software reset of specific parts of the LM8327.
Bit - Name
Bit
Default
(reserved)
7:5
IRQRST
4
Bit Function
(reserved)
0x0
Interrupt controller reset. Does not change status on IRQN ball. Only
controls IRQ module register. Interrupt status read out is not possible
when this bit is set.
0: interrupt controller not reset
1: interrupt controller reset
Timer reset for Timers 0, 1, 2:
TIMRST
3
0x0
(reserved)
2
0x0
0: timer not reset
1: timer is reset
(reserved)
Keyboard interface reset:
KBDRST
1
0x0
0: keyboard is not reset
1: keyboard is reset
GENIO reset:
GPIRST
0
0x0
0: GENIO not reset
1: GENIO is reset.
RSTINTCLR - Clear NO Init/Power-On Interrupt Register
Table 45. RSTINTCLR - Clear NO Init/Power-On Interrupt Register
Register - Name
Type
Register Function
0x84
W
This register allows to de-assert the POR/No Init Interrupt set every time
the device returns from RESET (either POR, HW or SW Reset), the IRQN
line is assigned active (low) and the IRQST.PORIRQ bit is set.
Bit - Name
Bit
Default
reserved
7:1
IRQCLR
0
RSTINTCLR
28
Address
Bit Function
(reserved)
1: Clears the PORIRQ Interrupt signalled in IRQST register.
0: is ignored
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CLKMODE - Clock Mode Register
Table 46. CLKMODE - Clock Mode Register
Register - Name
Address
Type
CLKMODE
0x88
R/W
Bit - Name
Bit
Default
(reserved)
7:2
Register Function
This register controls the current operating mode of the LM8327 device.
Bit Function
(reserved)
Writing to 00 forces the device to immediately enter sleep mode,
regardless of any autosleep configuration. Reading this bit returns the
current operating mode, which should always be 01.
MODCTL[1:0]
1:0
0x01
00: SLEEP Mode
01: Operation Mode
1x: Future modes
CLKCFG - Clock Configuration Register
Table 47. CLKCFG - Clock Configuration Register
Register - Name
Address
Type
CLKCFG
0x89
R/W
Bit - Name
Bit
Default
(reserved)
7
0x0
Register Function
Configures clock sources and power options of the device.
NOTE: Don't change while a PWM script is in progress.
Bit Function
(reserved)
00: (reserved)
CLKSRCSEL[1:0]
6:5
0x2
4:0
0x0
01: use externally generated clock from CLKIN pin as PWM slow clock
1x: use internally generated PWM slow clock
(reserved)
(reserved)
CLKEN - Clock Enable Register
Table 48. CLKEN - Clock Enable Register
Register - Name
Address
Type
CLKEN
0x8A
R/W
Bit - Name
Bit
Default
Register Function
Controls the clock to different functional units. It shall be used to enable
the functional blocks globally and independently.
Bit Function
CLKOUT clock output enable:
00: CLKOUT clock disabled. Fixed to low level.
CLKOUTEN
7:6
0x0
01: CLKOUT frequency = PWM slow clock frequency.
10: reserved
11: reserved
(reserved)
5:3
TIMEN
2
(reserved)
PWM Timer 0, 1, 2 clock enable:
0x0
0: Timer 0, 1, 2 clock disabled
1: Timer 0, 1, 2 clock enabled.
Direct Key clock enable (starts/stops direct key scan):
DKBDEN (1)
1
0x0
0: Direct Key clock disabled
1: Direct Key clock enabled
Keyboard clock enable (starts/stops key scan):
KBDEN (1)
0
0x0
0: Keyboard clock disabled
1: Keyboard clock enabled
(1)
*Note: Only one of KBDEN or DKBDEN of CLKEN register can be set at a time, since Direct Key functions cannot be used at the same
time as Keypad (Matrix). Setting both bits to 1 at the same time will enable only Direct Key.
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AUTOSLP - Autosleep Enable Register
Table 49. AUTOSLP - Autosleep Enable Register
Register - Name
Address
Type
AUTOSLP
0x8B
R/W
Bit - Name
Bit
Default
(reserved)
7:1
Register Function
This register controls the Auto Sleep function of the LM8327 device.
Bit Function
(reserved)
Enables automatic sleep mode after a defined activity time stored in the
AUTOSLPTI register:
ENABLE
0
0x00
1: Enable entering auto sleep mode
0: Disable entering auto sleep mode
AUTOSLPTI - Auto Sleep Time Register
Table 50. AUTOSLPTI - Auto Sleep Time Register
Register - Name
Address
Type
AUTOSLPTIL
AUTOSLPTIH
0x8C
0x8D
R/W
Bit - Name
Bit
Default
(reserved)
15:11
(reserved)
10:8
7:0
Values of UPTIME[10:0] match to multiples of 4ms:
0x00: no autosleep, regardless if AUTOSLP.ENABLE is set
0x01: 4ms
0x02: 8ms
0x7A: 500 ms
0xFF: 1020 ms (default after reset)
0x100: 1024 ms
0x7FF: 8188 ms
UPTIME[10:8]
UPTIME[7:0]
0x00
0xFF
Register Function
This register defines the activity time. If this time passes without any
processing events then the device enters into sleep-mode, but only if
AUTOSLP.ENABLE bit is set to 1.
Bit Function
IRQST - Global Interrupt Status Register
Table 51. IRQST - Global Interrupt Status Register
Register - Name
Address
Type
IRQST
0x91
R
Bit - Name
Bit
Default
Register Function
Returns the interrupt status from various on-chip function blocks. If any of
the bits is set and an IRQN line is configured, the IRQN line is asserted
active
Bit Function
Supply failure on VCC.
PORIRQ
7
0x1
Also power-on is considered as an initial supply failure. Therefore, after
power-on, the bit is set.
0: no failure recorded
1: Failure, device was completely reset and requires re-programming.
Keyboard interrupt (further key selection in keyboard module):
KBDIRQ
6
0x0
0: inactive
1: active
Direct key interrupt (further key selection in direct key module):
DKBDIRQ
5
(reserved)
4
TIM2IRQ
3
0x0
0: inactive
1: active
(reserved)
Timer2 expiry (CDIRQ or CYCIRQ):
0x0
0: inactive
1: active
30
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Table 51. IRQST - Global Interrupt Status Register (continued)
Register - Name
Address
Type
Register Function
Timer1 expiry (CDIRQ or CYCIRQ):
TIM1IRQ
2
0x0
0: inactive
1: active
Timer0 expiry (CDIRQ or CYCIRQ):
TIM0IRQ
1
0x0
0: inactive
1: active
GPIO interrupt (further selection in GPIO module):
GPIOIRQ
0
0x0
0: inactive
1: active
GPIO FEATURE CONFIGURATION
GPIO Feature Mapping
The LM8327 has a flexible I/O structure which allows user to dynamically assign different functionality to each
ball. The functionality of each ball is determined by the complete configuration of the balls.
In
•
•
•
•
general the following priority is given:
Direct Key
Keypad
GPIO
PWM
With this, each ball will be available as keypad, GPIO, or PWM unless it is specified to be a direct key. The
configuration for direct key, keypad, GPIO or PWM usage is defined by the following registers:
• DIRECTn
– This register defines a ball as a direct key.
• KBDSIZE and KBDDEDCFG
– Both registers define a ball as either part of the keypad matrix or as dedicated key input. These settings
have highest priority and will overwrite settings made in other registers.
• IOCFG
– This register is used to define the usage of PWM[2:0] and EXTIO if not configured to be part of the
keymatrix, to be used as GPIO.
Table 52. Ball Configuration Options
BALL
Module connectivity
GPIOSEL
BALLCFG
0x0
0x1
0x2
0x3
0x4
0x5
0x6
GPIO[7:0]
-
-
-
-
-
-
KPX[7:0]
not used
KPY[7:0]
not used
GPIO[15:8]
-
-
-
-
-
-
KPY8
not used
GPIO16
-
-
-
-
-
-
KPY9
not used
GPIO17
-
-
-
-
-
-
KPY10
not used
GPIO18
-
-
-
-
-
-
KPY11
not used
GPIO19
-
-
-
-
-
-
PWM0
GPIO20
PWM0
-
-
-
-
-
-
PWM1
GPIO21
PWM1
-
-
-
-
-
-
PWM2
GPIO22
PWM2
-
-
-
-
-
-
EXTIO
GPIO23
-
-
-
-
-
-
-
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IOCGF - Input/Output Pin Mapping Configuration Register
Table 53. IOCGF - Input/Output Pin Mapping Configuration Register
Register - Name
Address
Type
IOCFG
0xA7
W
Bit - Name
Bit
Default
GPIOSEL
7:4
(reserved)
3
BALLCFG
2:0
Register Function
Configures usage of PWM[2:0] and EXTIO if not used as primary function.
Bit Function
TBD
(reserved)
Select column to configure, see Table 52
IOPC0 - Pull Resistor Configuration Register 0
Table 54. IOPC0 - Pull Resistor Configuration Register 0 (1)
Register - Name
Address
Type
IOPC0 (2)
OxAA
R/W
Bit - Name
Bit
Default
Register Function
Defines the pull resistor configuration for balls KPX[7:0].
Bit Function
Resistor enable for KPX7 ball:
KPX7PR[1:0]
15:14
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPX6 ball:
KPX6PR[1:0]
13:12
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPX5 ball:
KPX5PR[1:0]
11:10
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPX4 ball:
KPX4PR[1:0]
9:8
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPX3 ball:
KPX3PR[1:0]
7:6
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPX2 ball:
KPX2PR[1:0]
5:4
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPX1 ball:
KPX1PR[1:0]
3:2
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
(1)
(2)
32
Written values of 0x2 and 0x3 will always be read back as 0x3.
*Note: Only one of KBDEN or DKBDEN of CLKEN register can be set at a time, since Direct Key functions cannot be used at the same
time as Keypad (Matrix). Setting both bits to 1 at the same time will enable only Direct Key.
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Table 54. IOPC0 - Pull Resistor Configuration Register 0(1) (continued)
Register - Name
Address
Type
Register Function
Resistor enable for KPX0 ball:
KPX0PR[1:0]
1:0
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
IOPC1 - Pull Resistor Configuration Register 1
Table 55. IOPC1 - Pull Resistor Configuration Register 1
Register - Name
Address
Type
IOPC1 (1)
0xAC
R/W
Bit - Name
Bit
Default
Register Function
Defines the pull resistor configuration for balls KPY[7:0].
Bit Function
Resistor enable for KPY7 ball:
KPY7PR[1:0]
15:14
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY6 ball:
KPY6PR[1:0]
13:12
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY5 ball:
KPY5PR[1:0]
11:10
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY4 ball:
KPY4PR[1:0]
9:8
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY3 ball:
KPY3PR[1:0]
7:6
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY2 ball:
KPY2PR[1:0]
5:4
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY1 ball:
KPY1PR[1:0]
3:2
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY0 ball:
KPY0PR[1:0]
1:0
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
(1)
Written values of 0x2 and 0x3 will always be read back as 0x3.
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IOPC2 - Pull Resistor Configuration Register 2
Table 56. IOPC2 - Pull Resistor Configuration Register 2
Register - Name
Address
Type
Register Function
IOPC2 (1)
0xAE
R/W
Defines the pull resistor configuration for balls KPY[11:8], PWM[2:0],
EXTIO.
Bit - Name
Bit
Default
Bit Function
Resistor enable for EXTIO ball:
EXTIO[1:0]
15:14
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for PWM2 ball:
PWM2[1:0]
13:12
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for PWM1 ball:
PWM1[1:0]
11:10
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for PWM0 ball:
PWM0[1:0]
9:8
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY11 ball:
KPY11PR[1:0]
7:6
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY10 ball:
KPY10PR[1:0]
5:4
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY9 ball:
KPY9PR[1:0]
3:2
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
Resistor enable for KPY8 ball:
KPY8PR[1:0]
1:0
0x3
00: no pull resistor at ball
01: pull down resistor programmed
1x: pull up resistor programmed
(1)
34
Written values of 0x2 and 0x3 will always be read back as 0x3.
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GPIOOME0 - GPIO Open Drain Mode Enable Register 0
Table 57. GPIOOME0 - GPIO Open Drain Mode Enable Register 0
Register - Name
Address
Type
GPIOOME0
0xE0
R/W
Bit - Name
Bit
Default
KPX[7:0]ODE
7:0
0x0
Register Function
Configures KPX[7:0] for Open Drain or standard output functionality. The
Open Drain drive source is configured by GPIOOMS0.
Bit Function
Open Drain Enable on KPX[7:0]:
0: full buffer
1: open drain functionality
GPIOOMS0 - GPIO Open Drain Mode Select Register 0
Table 58. GPIOOMS0 - GPIO Open Drain Mode Select Register 0
Register - Name
Address
Type
GPIOOMS0
0xE1
R/W
Bit - Name
Bit
Default
KPX[7:0]ODM
7:0
0x0
Register Function
Configures the Open Drain drive source on KPX[7:0] if selected by
GPIOOME0.
Bit Function
0: Only NMOS transistor is active in output driver stage. Output can be
driven to gnd or Hi-Z.
1: Only PMOS transistor is active in output driver stage. Output can be
driven to VCC or Hi-Z.
GPIOOME1 - GPIO Open Drain Mode Enable Register 1
Table 59. GPIOOME1 - GPIO Open Drain Mode Enable Register 1
Register - Name
Address
Type
GPIOOME1
0xE2
R/W
Bit - Name
Bit
Default
Register Function
Configures KPY[7:0] for Open Drain or standard output functionality. The
Open Drain drive source is configured by GPIOOMS1.
Bit Function
Open Drain Enable on KPY[7:0]:
KPY[7:0]ODE
7:0
0x0
0: full buffer
1: open drain functionality
GPIOOMS1 - GPIO Open Drain Mode Select Register 1
Table 60. GPIOOMS1 - GPIO Open Drain Mode Select Register 1
Register - Name
Address
Type
GPIOOMS1
0xE3
R/W
Bit - Name
Bit
Default
KPY[7:0]ODM
7:0
0x0
Register Function
Configures the Open Drain drive source on KPY[7:0] if selected by
GPIOOME1.
Bit Function
0: Only NMOS transistor is active in output driver stage. Output can be
driven to GND or Hi-Z.
1: Only PMOS transistor is active in output driver stage. Output can be
driven to VCC or Hi-Z.
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GPIOOME2 - GPIO Open Drain Mode Enable Register 2
Table 61. GPIOOME2 - GPIO Open Drain Mode Enable Register 2
Register - Name
Address
Type
GPIOOME2
0xE4
R/W
Bit - Name
Bit
Default
Register Function
Configures KPY[11:8], PWM[2:0], EXTIO for Open Drain or standard
output functionality. The Open Drain drive source is configured by
GPIOOMS2.
Bit Function
Open Drain Enable on EXTIO:
EXTIOODM
7
0x0
0: full buffer
1: open drain functionality
Open Drain Enable on PWM[2:0]:
PWM[2:0]ODM
6:4
0x0
0: full buffer
1: open drain functionality
Open Drain Enable on KPY[11:8]:
KPY[11:8]ODE
3:0
0x0
0: full buffer
1: open drain functionality
GPIOOMS2 - GPIO Open Drain Mode Select Register 2
Table 62. GPIOOMS2 - GPIO Open Drain Mode Select Register 2
Register - Name
Address
Type
GPIOOMS2
0xE5
R/W
Bit - Name
Bit
Default
Register Function
Configures the Open Drain drive source on KPY[11:8], PWM[2:0], EXTIO
if selected by GPIOOME2.
Bit Function
0: only NMOS transistor is active in output driver stage. Output can be
driven to GND or Hi-Z.
EXTIOODM
7
0x0
PWM[2:0]ODM
6:4
0x0
same as above
KPY[11:8]ODM
3:0
0x0
same as above
1: only PMOS transistor is active in output driver stage. Output can be
driven to GND or Hi-Z.
GPIO DATA INPUT/OUTPUT
36
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GPIOPDATA0 - GPIO Data Register 0
Table 63. GPIOPDATA0 - GPIO Data Register 0
Register - Name
Address
Type
Register Function
This register is used for data input/output of KPX[7:0]. Every data I/O is
masked with the associated MASK register.
GPIODATA0
0xC0
If one of the I/Os is defined as output (see Table 66) values written to this
register are masked with MASK and then applied to the associated pin.
R/W
If one of the I/Os is defined as input (see Table 66) values read from this
register hold the masked input value of the associated pin.
Bit - Name
Bit
Default
MASK7
15
0x0
Bit Function
Mask Status for KPX7 when enabled as GPIO:
1: KPX7 enabled
0: KPX7 disabled
Mask Status for KPX6 when enabled as GPIO:
MASK6
14
0x0
1: KPX6 enabled
0: KPX6 disabled
Mask Status for KPX5 when enabled as GPIO:
MASK5
13
0x0
1: KPX5 enabled
0: KPX5 disabled
Mask Status for KPX4 when enabled as GPIO:
MASK4
12
0x0
1: KPX4 enabled
0: KPX4 disabled
Mask Status for KPX3 when enabled as GPIO:
MASK3
11
0x0
1: KPX3 enabled
0: KPX3 disabled
Mask Status for KPX2 when enabled as GPIO:
MASK2
10
0x0
1: KPX2 enabled
0: KPX2 disabled
Mask Status for KPX1 when enabled as GPIO:
MASK1
9
0x0
1: KPX1 enabled
0: KPX1 disabled
Mask Status for KPX0 when enabled as GPIO:
MASK0
8
0x0
1: KPX0 enabled
DATA7
7
0x0
Pin Status for KPX7 when enabled as GPIO.
DATA6
6
0x0
Pin Status for KPX6 when enabled as GPIO.
DATA5
5
0x0
Pin Status for KPX5 when enabled as GPIO.
DATA4
4
0x0
Pin Status for KPX4 when enabled as GPIO.
DATA3
3
0x0
Pin Status for KPX3 when enabled as GPIO.
DATA2
2
0x0
Pin Status for KPX2 when enabled as GPIO.
DATA1
1
0x0
Pin Status for KPX1 when enabled as GPIO.
DATA0
0
0x0
Pin Status for KPX0 when enabled as GPIO.
0: KPX0 disabled
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GPIOPDATA1 - GPIO Data Register 1
Table 64. GPIOPDATA1 - GPIO Data Register 1
Register - Name
Address
Type
Register Function
This register is used for data input/output of KPY[7:0]. Every data I/O is
masked with the associated MASK register.
GPIODATA1
0xC2
If one of the I/Os is defined as output (see Table 67) values written to this
register are masked with MASK and then applied to the associated pin.
R/W
If one of the I/Os is defined as input (see Table 67) values read from this
register hold the masked input value of the associated pin.
Bit - Name
Bit
Default
MASK15
15
0x0
Bit Function
Mask Status for KPY7 when enabled as GPIO:
1: KPY7 enabled
0: KPY7 disabled
Mask Status for KPY6 when enabled as GPIO:
MASK14
14
0x0
1: KPY6 enabled
0: KPY6 disabled
Mask Status for KPY5 when enabled as GPIO:
MASK13
13
0x0
1: KPY5 enabled
0: KPY5 disabled
Mask Status for KPY4 when enabled as GPIO:
MASK12
12
0x0
1: KPY4 enabled
0: KPY4 disabled
Mask Status for KPY3 when enabled as GPIO:
MASK11
11
0x0
1: KPY3 enabled
0: KPY3 disabled
Mask Status for KPY2 when enabled as GPIO:
MASK10
10
0x0
1: KPY2 enabled
0: KPY2 disabled
Mask Status for KPY1 when enabled as GPIO:
MASK9
9
0x0
1: KPY1 enabled
0: KPY1 disabled
Mask Status for KPY0 when enabled as GPIO:
MASK8
8
0x0
1: KPY0 enabled
DATA15
7
0x0
Pin Status for KPY7 when enabled as GPIO.
DATA14
6
0x0
Pin Status for KPY6 when enabled as GPIO.
DATA13
5
0x0
Pin Status for KPY5 when enabled as GPIO.
DATA12
4
0x0
Pin Status for KPY4 when enabled as GPIO.
DATA11
3
0x0
Pin Status for KPY3 when enabled as GPIO.
DATA10
2
0x0
Pin Status for KPY2 when enabled as GPIO.
DATA9
1
0x0
Pin Status for KPY1 when enabled as GPIO.
DATA8
0
0x0
Pin Status for KPY0 when enabled as GPIO.
0: KPY0 disabled
38
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GPIOPDATA2 - GPIO Data Register 2
Table 65. GPIOPDATA2 - GPIO Data Register 2
Register - Name
Address
Type
Register Function
This register is used for data input/output of KPY[11:8], PWM[2:0], EXTIO.
Every data I/O is masked with the associated MASK register.
GPIODATA2
0xC4
If one of the I/Os is defined as output (see Table 68) values written to this
register are masked with MASK and then applied to the associated pin.
R/W
If one of the I/Os is defined as input (see Table 68) values read from this
register hold the masked input value of the associated pin.
Bit - Name
Bit
Default
MASK23
15
0x0
Bit Function
Mask Status for EXTIO when enabled as GPIO:
1: EXTIO enabled
0: EXTIO disabled
Mask Status for PWM2 when enabled as GPIO:
MASK22
14
0x0
1: PWM2 enabled
0: PWM2 disabled
Mask Status for PWM1 when enabled as GPIO:
MASK21
13
0x0
1: PWM1 enabled
0: PWM1 disabled
Mask Status for PWM0 when enabled as GPIO:
MASK20
12
0x0
1: PWM0 enabled
0: PWM0 disabled
Mask Status for KPY11 when enabled as GPIO:
MASK19
11
0x0
1: KPY11 enabled
0: KPY11 disabled
Mask Status for KPY10 when enabled as GPIO:
MASK18
10
0x0
1: KPY10 enabled
0: KPY10 disabled
Mask Status for KPY9 when enabled as GPIO:
MASK17
9
0x0
1: KPY9 enabled
0: KPY9 disabled
Mask Status for KPY8 when enabled as GPIO:
MASK16
8
0x0
1: KPY8 enabled
DATA23
7
0x0
Pin Status for EXTIO when enabled as GPIO.
DATA22
6
0x0
Pin Status for PWM2 when enabled as GPIO.
DATA21
5
0x0
Pin Status for PWM1 when enabled as GPIO.
DATA20
4
0x0
Pin Status for PWM0 when enabled as GPIO.
DATA19
3
0x0
Pin Status for KPY11 when enabled as GPIO
DATA18
2
0x0
Pin Status for KPY10 when enabled as GPIO.
DATA17
1
0x0
Pin Status for KPY9 when enabled as GPIO.
DATA16
0
0x0
Pin Status for KPY8 when enabled as GPIO.
0: KPY8 disabled
GPIOPDIR0 - GPIO Port Direction Register 0
Table 66. GPIOPDIR0 - GPIO Port Direction Register 0
Register - Name
Address
Type
GPIODIR0
0xC6
R/W
Register Function
Port direction for KPX[7:0].
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Table 66. GPIOPDIR0 - GPIO Port Direction Register 0 (continued)
Register - Name
Address
Type
Register Function
Bit - Name
Bit
Default
Bit Function
KPX[7:0]DIR
7:0
0x00
Direction bits for KPX[7:0]:
0: input mode
1: output mode
GPIOPDIR1 - GPIO Port Direction Register 1
Table 67. GPIOPDIR1 - GPIO Port Direction Register 1
Register - Name
Address
Type
Register Function
GPIODIR1
0xC7
R/W
Port direction for KPY[7:0].
Bit - Name
Bit
Default
Bit Function
Direction bits for KPY[7:0]:
KPY[7:0]DIR
7:0
0x00
0: input mode
1: output mode
GPIOPDIR2 - GPIO Port Direction Register 2
Table 68. GPIOPDIR2 - GPIO Port Direction Register 2
Register - Name
Address
Type
Register Function
GPIODIR2
0xC8
R/W
Port direction for KPY[11:8], PWM[2:0], EXTIO.
Bit - Name
Bit
Default
Bit Function
Direction bits for EXTIO:
EXTIODIR
7
0x0
0: input mode
1: output mode
Direction bits for PWM[2:0:]:
PWM[2:0]DIR
6:4
0x0
0: input mode
1: output mode
Direction bits for KPY[11:8]:
KPY[11:8]DIR
3:0
0x00
0: input mode
1: output mode
GPIO INTERRUPT CONTROL
GPIOIS0 - Interrupt Sense Configuration Register 0
Table 69. GPIOIS0 - Interrupt Sense Configuration Register 0
Register - Name
Address
Type
GPIOIS0
0xC9
R/W
Bit - Name
Bit
Default
Register Function
Interrupt type on KPX[7:0].
Bit Function
Interrupt type bits for KPX[7:0]:
KPX[7:0]IS
7:0
0x0
0: edge sensitive interrupt
1: level sensitive interrupt
40
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GPIOIS1 - Interrupt Sense Configuration Register 1
Table 70. GPIOIS1 - Interrupt Sense Configuration Register 1
Register - Name
Address
Type
GPIOIS1
0xCA
R/W
Bit - Name
Bit
Default
Register Function
Interrupt type on KPY[7:0].
Bit Function
Interrupt type bits for KPY[7:0]:
KPY[7:0]IS
7:0
0x0
0: edge sensitive interrupt
1: level sensitive interrupt
GPIOIS2 - Interrupt Sense Configuration Register 2
Table 71. GPIOIS2 - Interrupt Sense Configuration Register 2
Register - Name
Address
Type
Register Function
GPIOIS2
0xCB
R/W
Interrupt type on KPY[11:8], PWM[2:0], EXTIO.
Bit - Name
Bit
Default
EXTIOIS
7
0x0
Bit Function
Interrupt type bits for EXTIO:
0: edge sensitive interrupt
1: level sensitive interrupt
Interrupt type bits for PWM[2:0:]:
PWM[2:0]IS
6:4
0x0
0: edge sensitive interrupt
1: level sensitive interrupt
Interrupt type bits for KPY[11:8]:
KPY[11:8]IS
3:0
0x0
0: edge sensitive interrupt
1: level sensitive interrupt
GPIOIBE0 - GPIO Interrupt Edge Configuration Register 0
Table 72. GPIOIBE0 - GPIO Interrupt Edge Configuration Register 0
Register - Name
Address
Type
Register Function
Defines whether an interrupt on KPX[7:0] is triggered on both edges or on
a single edge. See Table 75 for the edge configuration.
GPIOIBE0
0xCC
R/W
Bit - Name
Bit
Default
Bit Function
Interrupt both edges bits for KPX[7:0]:
KPX[7:0]IBE
7:0
0x0
0: interrupt generated at the active edge
1: interrupt generated after both edges
GPIOIBE1 - GPIO Interrupt Edge Configuration Register 1
Table 73. GPIOIBE1 - GPIO Interrupt Edge Configuration Register 1
Register - Name
Address
Type
Register Function
GPIOIBE1
0xCD
R/W
Defines whether an interrupt on KPY[7:0] is triggered on both edges or on
a single edge. See Table 76 for the edge configuration.
Bit - Name
Bit
Default
Bit Function
KPY[7:0]IBE
7:0
0x0
Interrupt both edges bits for KPY[7:0]:
0: interrupt generated at the configured edge
1: interrupt generated after both edges
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GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2
Table 74. GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2
Register - Name
Address
Type
Register Function
GPIOIBE2
0xCE
R/W
Defines whether an interrupt on KPY[11:8], PWM[2:0], EXTIO is triggered
on both edges or on a single edge. See Table 77 for the edge
configuration.
Bit - Name
Bit
Default
Bit Function
Interrupt both edges bits for EXTIO:
EXTIOIBE
7
0x0
0: interrupt generated at the active edge
1: interrupt generated after both edges
Interrupt both edges bits for PWM[2:0:]:
PWM[2:0]IBE
6:4
0x0
0: interrupt generated at the active edge
1: interrupt generated after both edges
Interrupt both edges bits for KPY[11:8]:
KPY[11:8]IBE
3:0
0x0
0: interrupt generated at the active edge
1: interrupt generated after both edges
GPIOIEV0 - GPIO Interrupt Edge Select Register 0
Table 75. GPIOIEV0 - GPIO Interrupt Edge Select Register 0
Register - Name
Address
Type
Register Function
GPIOIEV0
0xCF
R/W
Select Interrupt edge for KPX[7:0].
Bit - Name
Bit
Default
Bit Function
Interrupt edge select from KPX[7:0]:
KPX[7:0]EV
7:0
0x0
0: interrupt at low level or falling edge
1: interrupt at high level or rising edge
GPIOIEV1 - GPIO Interrupt Edge Select Register 1
Table 76. GPIOIEV1 - GPIO Interrupt Edge Select Register 1
Register - Name
Address
Type
Register Function
GPIOIEV1
0xD0
R/W
Select Interrupt edge for KPY[7:0].
Bit - Name
Bit
Default
Bit Function
Interrupt edge select from KPY[7:0]:
KPY[7:0]EV
7:0
0x0
0: interrupt at low level or falling edge
1: interrupt at high level or rising edge
GPIOIEV2 - GPIO Interrupt Edge Select Register 2
Table 77. GPIOIEV2 - GPIO Interrupt Edge Select Register 2
Register - Name
Address
Type
Register Function
GPIOIEV2
0xD1
R/W
Select Interrupt edge for KPY[11:8], PWM[2:0], EXTIO.
Bit - Name
Bit
Default
EXTIOEV
7
0x0
Bit Function
Interrupt edge select from EXTIO:
0: interrupt at low level or failig edge
1: interrupt at high level or rising edge
Interrupt edge select from PWM[2:0:]:
PWM[2:0]EV
6:4
0x0
0: interrupt at low level or failig edge
1: interrupt at high level or rising edge
42
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Table 77. GPIOIEV2 - GPIO Interrupt Edge Select Register 2 (continued)
Register - Name
Address
Type
Register Function
Interrupt edge select from KPY[11:8]:
KPY[11:8]EV
3:0
0x0
0: interrupt at low level or falling edge
1: interrupt at high level or rising edge
GPIOIE0 - GPIO Interrupt Enable Register 0
Table 78. GPIOIE0 - GPIO Interrupt Enable Register 0
Register - Name
Address
Type
GPIOIE0
0xD2
R/W
Bit - Name
Bit
Default
Register Function
Enable/disable interrupts on KPX[7:0].
Bit Function
Interrupt enable on KPX[7:0]:
KPX[7:0]IE
7:0
0x0
0: disable interrupt
1: enable interrupt
GPIOIE1 - GPIO Interrupt Enable Register 1
Table 79. GPIOIE1 - GPIO Interrupt Enable Register 1
Register - Name
Address
Type
GPIOIE1
0xD3
R/W
Bit - Name
Bit
Default
Register Function
Enable/disable interrupts on KPY[7:0]
Bit Function
Interrupt enable on KPY[7:0]:
KPY[7:0]IE
7:0
0x0
0: disable interrupt
1: enable interrupt
GPIOIE2 - GPIO Interrupt Enable Register 2
Table 80. GPIOIE2 - GPIO Interrupt Enable Register 2
Register - Name
Address
Type
GPIOIE2
0xD4
R/W
Bit - Name
Bit
Default
EXTIOIE
7
0x0
Register Function
Enable/disable interrupts on KPY[11:8], PWM[2:0], EXTIO.
Bit Function
Interrupt enable on EXTIO:
0: disable interrupt
1: enable interrupt
Interrupt enable on PWM[2:0:]:
PWM[2:0]IE
6:4
0x0
0: disable interrupt
1: enable interrupt
Interrupt enable on KPY[11:8]:
KPY[11:8]IE
3:0
0x0
0: disable interrupt
1: enable interrupt
GPIOIC0 - GPIO Clear Interrupt Register 0
Table 81. GPIOIC0 - GPIO Clear Interrupt Register 0
Register - Name
Address
Type
GPIOIC0
0xDC
W
Bit - Name
Bit
Default
Register Function
Clears the interrupt on KPX[7:0].
Bit Function
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Table 81. GPIOIC0 - GPIO Clear Interrupt Register 0 (continued)
Register - Name
Address
Type
Register Function
Clear Interrupt on KPX[7:0].
KPX[7:0]IC
7:0
0: no effect
1: Clear corresponding interrupt
GPIOIC1 - GPIO Clear Interrupt Register 1
Table 82. GPIOIC1 - GPIO Clear Interrupt Register 1
Register - Name
Address
Type
GPIOIC1
0xDD
W
Bit - Name
Bit
Default
Register Function
Clears the interrupt on KPY[7:0].
Bit Function
Clear Interrupt on KPY[7:0].
KPY[7:0]IC
7:0
0: no effect
1: Clear corresponding interrupt
GPIOIC2 - GPIO Clear Interrupt Register 2
Table 83. GPIOIC2 - GPIO Clear Interrupt Register 2
Register - Name
Address
Type
GPIOIC2
0xDE
W
Bit - Name
Bit
Default
Register Function
Clears the interrupt on KPY[11:8], PWM[2:0], EXTIO.
Bit Function
Clear interrupt on EXTIO:
EXTIOIC
7
0: no effect
1: Clear corresponding interrupt
Clear interrupt on PWM[2:0]:
PWM[2:0]IC
6:4
0: no effect
1: Clear corresponding interrupt
Clear Interrupt on KPY[11:8]:
KPY[11:8]IC
3:0
0: no effect
1: Clear corresponding interrupt
GPIO INTERRUPT STATUS
GPIORIS0 - Raw Interrupt Status Register 0
Table 84. GPIORIS0 - Raw Interrupt Status Register 0
Register - Name
Address
Type
GPIORIS0
0xD6
R
Bit - Name
Bit
Default
Register Function
Raw interrupt status on KPX[7:0].
Bit Function
Raw Interrupt status data on KPX[7:0]:
KPX[7:0]RIS
7:0
0x0
0: no interrupt condition at GPIO
1: interrupt condition at GPIO
GPIORIS1 - Raw Interrupt Status Register 1
Table 85. GPIORIS1 - Raw Interrupt Status Register 1
44
Register - Name
Address
Type
GPIORIS1
0xD7
R
Register Function
Raw interrupt status on KPY[7:0].
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Table 85. GPIORIS1 - Raw Interrupt Status Register 1 (continued)
Register - Name
Address
Type
Register Function
Bit - Name
Bit
Default
Bit Function
KPY[7:0]RIS
7:0
0x0
Raw Interrupt status data on KPY[7:0]:
0: no interrupt condition at GPIO
1: interrupt condition at GPIO
GPIORIS2 - Raw Interrupt Status Register 2
Table 86. GPIORIS2 - Raw Interrupt Status Register 2
Register - Name
Address
Type
GPIORIS2
0xD8
R
Bit - Name
Bit
Default
Register Function
Raw interrupt status on KPY[11:8], PWM[2:0], EXTIO.
Bit Function
Raw Interrupt status data on EXTIO:
EXTIORIS
7
0x0
0: no interrupt condition at GPIO
1: interrupt at GPIO is active
Raw Interrupt status data on PWM[2:0]:
PWM[2:0]RIS
6:4
0x0
0: no interrupt condition at GPIO
1: interrupt at GPIO is active
Raw Interrupt status data on KPY[11:8]:
KPY[11:8]RIS
3:0
0x0
0: no interrupt condition at GPIO
1: interrupt condition at GPIO
GPIOMIS0 - Masked Interrupt Status Register 0
Table 87. GPIOMIS0 - Masked Interrupt Status Register 0
Register - Name
Address
Type
GPIOMIS0
0xD9
R
Bit - Name
Bit
Default
Register Function
Masked interrupt status on KPX[7:0].
Bit Function
Masked Interrupt status data on KPX[7:0]:
KPX[7:0]MIS
7:0
0x0
0: no interrupt contribution from GPIO
1: interrupt GPIO is active
GPIOMIS1 - Masked Interrupt Status Register 1
Table 88. GPIOMIS1 - Masked Interrupt Status Register 1
Register - Name
Address
Type
GPIOMIS1
0xDA
R
Bit - Name
Bit
Default
KPY[7:0]MIS
7:0
0x0
Register Function
Masked interrupt status on KPY[7:0].
Bit Function
Masked Interrupt status data on KPY[7:0]:
0: no interrupt contribution from GPIO
1: interrupt GPIO is active
GPIOMIS2 - Masked Interrupt Status Register 2
Table 89. GPIOMIS2 - Masked Interrupt Status Register 2
Register - Name
Address
Type
GPIOMIS2
0xDB
R
Bit - Name
Bit
Default
Register Function
Masked interrupt status on KPY[11:8], PWM[2:0], EXTIO.
Bit Function
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Table 89. GPIOMIS2 - Masked Interrupt Status Register 2 (continued)
Register - Name
Address
Type
Register Function
Masked Interrupt status data on EXTIO:
EXTIOMIS
7
0x0
0: no interrupt condition from GPIO
1: interrupt at GPIO is active
Masked Interrupt status data on PWM[2:0]:
PWM[2:0]MIS
6:4
0x0
0: no interrupt condition from GPIO
1: interrupt at GPIO is active
Masked Interrupt status data on KPY[11:8]:
KPY[11:8]MIS
3:0
0x0
0: no interrupt contribution from GPIO
1: interrupt GPIO is active
GPIO WAKE-UP CONTROL
GPIOWAKE0 - GPIO Wake-Up Register 0
Table 90. GPIOWAKE0 - GPIO Wake-Up Register 0
Register - Name
Address
Type
Register Function
Configures wake-up conditions for KPX[7:0].
GPIOWAKE0
0xE9
R/W
Bit - Name
Bit
Default
KPX[7:0]WAKE
7:0
0x0
Each bit corresponds to a ball. When bit set, the corresponding ball
contributes to wakeup from auto sleep mode.
Bit Function
Wakeup enable on KPX[7:0]:
0: disable wakeup
1: enable wakeup
GPIOWAKE1 - GPIO Wake-Up Register 1
Table 91. GPIOWAKE1 - GPIO Wake-Up Register 1
Register - Name
Address
Type
Register Function
Configures wake-up conditions for KPY[7:0].
GPIOWAKE1
0xEA
R/W
Bit - Name
Bit
Default
KPY[7:0]WAKE
7:00
0x0
Each bit corresponds to a ball. When bit set, the corresponding ball
contributes to wakeup from auto sleep mode.
Bit Function
Wakeup enable on KPX[7:0]:
0: disable wakeup
1: enable wakeup
GPIOWAKE2 - GPIO Wake-Up Register 2
Table 92. GPIOWAKE2 - GPIO Wake-Up Register 2
Register - Name
Address
Type
Register Function
Configures wake-up conditions for KPY[11:8], PWM[2:0}, EXTIO.
46
GPIOWAKE2
0xEB
R/W
Bit - Name
Bit
Default
Each bit corresponds to a ball. When bit set, the corresponding ball
contributes to wakeup from auto sleep mode.
Bit Function
EXTIOWAKE
7
0x0
Wakeup enable on EXTIO:
0: disable wakeup
1: enable wakeup
PWM[2:0]WAKE
6:4
0x0
Wakeup enable on PWM[2:0]:
0: disable wakeup
1: enable wakeup
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Table 92. GPIOWAKE2 - GPIO Wake-Up Register 2 (continued)
Register - Name
KPY[11:8]WAKE
Address
Type
3:0
0x0
Register Function
Wakeup enable on KPY[11:8]:
0: disable wakeup
1: enable wakeup
DIRECT KEY REGISTERS AND DIRECT KEY CONTROL
Direct Key selection and control registers are mapped in the address range from 0xE6 to 0xF3. This paragraph
describes the functions of the associated registers down to the bit level.
DEVTCODE - Direct Key Event Code Register
Table 93. DEVTCODE - Direct Key Event Code Register
Register - Name
Type
Register Function
0xE6
R
With this register a FIFO buffer is addressed storing up to 15 consecutive
events.
Reading the value 0x3F from this address means that the FIFO buffer is
empty and a key is not pressed. Reading the value 0x1F form this address
means that the FIFO buffer is empty and a key is still pressed.
DKBDRIS.DREVTINT bit is cleared as soon as this FIFO reaches its
empty state. See further details below.
NOTE: Auto increment is disabled on this register. Multi-byte read will
always read from the same address.
Bit - Name
Bit
Default
(reserved)
7:6
DKEYSTAT
5
0x0
DKEYCODE
4:0
0x1F
DEVTCODE
Address
Bit Function
(reserved)
This bit indicates whether the direct key event was a key press or a key
release event.
0: direct key was pressed
1: direct key was released.
Column index of key is pressed (0...24, 25 for Direct keys).
DBOUNCE - Direct Key Debounce Time Register
Table 94. DBOUNCE - Direct Key Debounce Time Register
Register - Name
Address
Type
DBOUNCE
0xE7
R/W
Bit - Name
Bit
Default
(reserved)
7:5
(reserved)
4:0
De-bounce time for direct keys.
Values of DEBOUNCE[4:0] match to multiples of 3ms:
0x00: 0ms
0x01: 3ms
0x02: 6ms
0x03: 9ms
0x1F: 93 ms
DEBOUNCE
0x03
Register Function
Time between first detection of key and final sampling of key.
Bit Function
DIRECT0 - Direct Key Register 0
The direct key settings. If not enabled as a direct key, then that pin follows the IOCFG and keypad registers.
Direct Key bits take priority over anything else. Direct key bits must be cleared before IOCFG is accessed to set
other functions for the pins.
Table 95. DIRECT0 - Direct Key Register 0
Register - Name
Address
Type
DIRECT0
0xEC
R/W
Bit - Name
Bit
Default
Register Function
Enable Direct Key connections for DK[7:0].
Bit Function
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Table 95. DIRECT0 - Direct Key Register 0 (continued)
Register - Name
DK[7:0]
Address
Type
7:0
0xFF
Register Function
1: Direct Key connection
0: Direct Key follows IOCFG and keypad registers.
DIRECT1 - Direct Key Register 1
Table 96. DIRECT1 - Direct Key Register 1
Register - Name
Address
Type
DIRECT1
0xED
R/W
Bit - Name
Bit
Default
DK[15:8]
7:0
0xFF
Register Function
Enable Direct Key connections for DK[15:8].
Bit Function
1: Direct Key connection
0: Direct Key follows IOCFG and keypad registers.
DIRECT2 - Direct Key Register 2
Table 97. DIRECT2 - Direct Key Register 2
Register - Name
Address
Type
DIRECT2
0xEE
R/W
Bit - Name
Bit
Default
DK[23:16]
7:0
0xFF
Register Function
Enable Direct Key connections for DK[23:16].
Bit Function
1: Direct Key connection
0: Direct Key follows IOCFG and keypad registers.
DIRECT3 - Direct Key Register 3
Table 98. DIRECT3 - Direct Key Register 3
Register - Name
Address
Type
DIRECT3
0xEF
R/W
Bit - Name
Bit
Default
(reserved)
7:2
DK[25:24]
1:0
Register Function
Enable Direct Key connections for DK[25:24].
Bit Function
(reserved)
0x03
1: Direct Key connection
0: Direct Key follows IOCFG and keypad registers.
DKBDRIS - Direct Key Raw Interrupt Status Register
Table 99. DKBDRIS - Direct Key Raw Interrupt Status Register
48
Register - Name
Address
Type
DKBDRIS
0xF0
R
Register Function
Bit - Name
Bit
Default
(reserved)
7:2
DRELINT
1
0x0
Raw event lost interrupt.
More than 8 direct key events have been detected and caused the event
buffer to overflow. This bit is cleared by setting bit DEVTIC of the DKBDIC
register.
DREVTINT
0
0x0
Raw direct key event interrupt.
At least one direct key press or direct key release is in the direct key event
buffer. Reading from DEVTCODE until the buffer is empty will
automatically clear this interrupt.
Returns the status of stored direct key interrupts.
Bit Function
(reserved)
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DKBDMIS - Direct Key Masked Interrupt Status Register
Table 100. DKBDMIS - Direct Key Masked Interrupt Status Register
Register - Name
Address
Type
Register Function
DKBDMIS
0xF1
R
Bit - Name
Bit
Default
(reserved)
7:2
DMELINT
1
0x0
Masked event lost interrupt.
More than 8 direct key events have been detected and caused the event
buffer to overflow. This bit is cleared by setting bit DEVTIC of the DKBDIC
register.
DMEVTINT
0
0x0
Masked direct key event interrupt.
At least one direct key press or direct key release is in the direct key event
buffer. Reading from DEVTCODE until the buffer is empty will
automatically clear this interrupt.
Returns the status of masked direct key interrupts after masking with the
DKBDMSK register.
Bit Function
(reserved)
DKBDIC - Direct Key Interrupt Clear Register
Table 101. DKBDIC - Direct Key Interrupt Clear Register
Register - Name
Address
Type
DKBDIC
0xF2
W
Bit - Name
Bit
Default
(reserved)
7:1
DEVTIC
0
Register Function
Setting these bits clears direct key active interrupts.
Bit Function
(reserved)
Clear event buffer and corresponding interrupts DREVTINT and DRELINT
by writing a '1' to this bit position.
DKBDMSK - Direct Key Interrupt Mask Register
Table 102. DKBDMSK - Direct Key Interrupt Mask Register
Register - Name
DKBDMSK
Address
Type
Register Function
Configures masking of direct key interrupts. Masked interrupts do not
trigger an event of the interrupt output.
0xF3
R/W
Bit - Name
Bit
Default
(reserved)
7:2
MSKELINT
1
0x1
0: direct key event lost interrupt DRELINT triggers IRQ line
1: direct key event lost interrupt DRELINT is masked.
MSKEINT
0
0x1
0: direct key event interrupt DREVTINT triggers IRQ line
1: direct key event interrupt DREVTINT is masked.
Bit Function
(reserved)
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
(1) (2)
−0.3V to 2.2V
Supply Voltage (VCC)
−0.2V to VCC +0.2V
Voltage at Generic IOs
−0.3V to +4.25V
Voltage at Backdrive/Overvoltage IOs
Maximum Input Current Without Latchup
±100 mA
ESD Protection Level
(Human Body Model)
2kV
(Machine Model)
200V
(Charge Device Model)
750V
Total Current into VCC Pin (Source)
100 mA
Total Current out of GND Pin (Sink)
100 mA
−65°C to +140°C
Storage Temperature Range
(1)
(2)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not
ensured when operating the device at absolute maximum ratings.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
DC ELECTRICAL CHARACTERISTICS
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
(Temperature: −40°C ≤ TA ≤ +85°C, unless otherwise specified)
Parameter
Operating Voltage (VCC)
Conditions
Min
Max
Units
1.98
V
3.60
V
1.2
2.0
mA
VCC = 1.8V, TA = 25°C
Internal Clock = OFF, no internal functional
blocks running
VCC because the weak pull-down is enabled.
BACKDRIVE/OVERVOLTAGE I/O AC CHARACTERISTICS
Characteristics for pins CLKIN, IRQN/KPY11/PWM2, SDA and SCL
Parameter
tRise/Fall
(Max. Rise and Fall time)
(1)
tFall
(Max. Fall time) as ACCESS.bus (SDA, SCL
only) (1)
(1)
52
Conditions
Min
CLOAD=50 pF @ 1MHz
CLOAD=10 pF to 100 pF
VIHmin to VILmax
Typ
Max
Units
70
ns
10
120
Specified by design, not tested.
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REGISTERS
REGISTER MAPPING
Keyboard Registers
Table 103 shows the register map for keyboard functionality. In addition to Global Call Reset (see Global Call
Reset) or Software Reset using SWRESET (see Table 43), these registers are reset to 0x00 values by a module
reset using RSTCTRL.KBDRST and should be rewritten for desired settings (see RSTCTRL - System Reset
Register).
Table 103. Register Map for Keyboard Functionality
Register Name
Description
Register File
Address
Register Type
ACCESS Size
Default
value
Next RF
Address
KBDSETTLE
Keypad Settle Time
0x01
R/W
byte
0x80
0x02
KBDBOUNCE
Keypad Debounce Time
0x02
R/W
byte
0x80
0x03
KBDSIZE
Keypad Size
Configuration
0x03
R/W
byte
0x22
0x04
KBDDEDCFG0
Keypad Dedicated Key 0
0x04
R/W
byte
0xFF
0x05
KBDDEDCFG1
Keypad Dedicated Key 1
0x05
R/W
byte
0xFF
0x06
KBDRIS
Keypad Raw Interrupt
Status
0x06
R
byte
0x00
0x07
KBDMIS
Keypad Masked Interrupt
Status
0x07
R
byte
0x00
0x08
KBDIC
Keypad Interrupt Clear
0x08
W
byte
KBDMSK
Keypad Interrupt Mask
0x09
R
byte
0x0C
0x0A
KBDCODE0
Keypad Code 0
0x0B
R
byte
0x7F
0x0C
KBDCODE1
Keypad Code 1
0x0C
R
byte
0x7F
0x0D
KBDCODE2
Keypad Code 2
0x0D
R
byte
0x7F
0x0E
KBDCODE3
Keypad Code 3
0x0E
R
byte
0x7F
0x0F
EVTCODE
Key Event Code
0x10
R
byte
0x7F
0x10
0x09
Direct Key Registers
Table 104 shows the register map for keyboard functionality when using direct keys. In addition to Global Call
Reset (see Global Call Reset) or Software Reset using SWRESET (see SWRESET - Software Reset), these
registers are reset to 0x00 values by a module reset using RSTCTRL.KBDRST and should be rewritten for
desired settings (see RSTCTRL - System Reset Register).
Table 104. Register Map for Direct Key Registers
Register Name
Description
Register File
Address
Register Type
ACCESS Size
Default
value
Next RF
Address
DEVTCODE
Direct Key Event Code
0xE6
R
byte
0x3F
0xE6
DBOUNCE
Direct Key Debounce
Time
0xE7
R/W
byte
0x03
0xE8
DIRECT0
Direct Key Config 0
0xEC
R/W
byte
0xFF
0xED
DIRECT1
Direct Key Config 1
0xED
R/W
byte
0xFF
0xEE
DIRECT2
Direct Key Config 2
0xEE
R/W
byte
0xFF
0xEF
DIRECT3
Direct Key Config 3
0xEF
R/W
byte
0x03
0xF0
DKBDRIS
Direct Key Raw Interrupt
Status
0xF0
R
byte
0x00
0xF1
DKBDMIS
Direct Key Masked Int.
Status
0xF1
R
byte
0x00
0xF2
DKBDIC
Direct Key Interrupt Clear
0xF2
W
byte
DKBDMSK
Direct Key Interrupt Mask
0xF3
R/W
byte
0xF3
0x03
0xF4
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PWM Timer Registers
Table 105 shows the register map for PWM Timer functionality. In addition to Global Call Reset (see Global Call
Reset) or Software Reset using SWRESET (see Table 43), these registers are reset to default values by a
module reset using RSTCTRL.TIMRST (see RSTCTRL - System Reset Register).
Table 105. Register Map for PWM Timer Functionality
Register Name
Description
Register File
Address
Register Type ACCESS Size
Default value
Next RF
Address
TIMCFG0
PWM Timer Configuration 0
0x60
R/W
byte
0x00
0x61
PWMCFG0
PWM Configuration 0
0x61
R/W
byte
0x00
0x62
TIMSCAL0
PWM Timer Prescaler 0
0x62
R/W
byte
0x00
0x63
TIMCFG1
PWM Timer Configuration 1
0x68
R/W
byte
0x00
0x69
PWMCFG1
PWM Configuration 1
0x69
R/W
byte
0x00
0x6A
TIMSCAL1
PWM Timer Prescaler 1
0x6A
R/W
byte
0x00
0x6B
TIMCFG2
PWM Timer Configuration 2
0x70
R/W
byte
0x00
0x71
PWMCFG2
PWM Configuration 2
0x71
R/W
byte
0x00
0x72
TIMSCAL2
PWM Timer Prescaler 2
0x72
R/W
byte
0x00
0x73
TIMSWRES
PWM Timer SW Reset
0x78
W
byte
TIMRIS
PWM Timer Interrupt Status
0x7A
R
byte
0x00
0x7B
TIMMIS
PWM Timer Masked Int. Status
0x7B
R
byte
0x00
0x7C
TIMIC
Timer Interrupt Clear
0x7C
W
byte
PWMWP
PWM Command Write Pointer
0x7D
R/W
byte
PWMCFG
PWM Command Script
0x7E
W
word
0x79
0x7D
0x00
0x7E
0x7F
System Registers
Table 106 shows the register map for general system registers. These registers are not affected by any of the
module resets addressed by RSTCTRL (see RSTCTRL - System Reset Register). These registers can only be
reset to default values by a Global Call Reset (see Global Call Reset) or by a complete Software Reset using
SWRESET (seeTable 43).
Table 106. Register Map for System Control Functionality
Register Name
Description
Register File
Address
Register Type
ACCESS Size
Default
value
Next RF
Address
I2CSA
I2C Slave Address
0x80
W
byte
0x8A
0x81
MFGCODE
Manufacturer Code
0x80
R
byte
0x00
0x81
SW Revision
0x81
R
byte
0xC4
0x82
SWRESET
SW Reset
0x81
W
byte
RSTCTRL
System Reset
0x82
R/W
byte
Clear No Init/Power On
Interrupt
0x84
W
byte
SWREV
RSTINTCLR
CLKMODE
CLKCFG
CLKEN
AUTOSLP
0x82
0x00
0x83
0x85
Clock Mode
0x88
R/W
byte
0x01
0x89
Clock Configuration
0x89
R/W
byte
0x40
0x8A
Clock Enable
0x8A
R/W
byte
0x00
0x8B
Auto Sleep Enable
0x8B
R/W
byte
0x00
0x8C
AUTOSLPTI
Auto Sleep Time
0x8C
R/W
word
0x00FF
0x8D
MMASTER
Multi-Master Mode
0xF4
R/W
byte
0x00
0xF5
Global Interrupt Registers
Table 107 shows the register map for global interrupt functionality. In addition to Global Call Reset (see Global
Call Reset) or Software Reset using SWRESET (see Table 43), these registers are reset to default values by a
module reset using RSTCTRL.IRQRST (see RSTCTRL - System Reset Register).
54
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Table 107. Register Map for Global Interrupt Functionality
Register Name
IRQST
Description
Global Interrupt Status
Register File
Address
Register Type
ACCESS Size
Default
value
Next RF
Address
0x91
R
byte
0x80
0x92
GPIO Registers
Table 108 shows the register map for GPIO functionality. In addition to Global Call Reset (see Global Call Reset)
or Software Reset using SWRESET (see Table 43), these registers are reset to 0x00 values by a module reset
using RSTCTRL.GPIRST and should be rewritten for desired settings (see RSTCTRL - System Reset Register).
Table 108. Register Map for GPIO Functionality
Register Name
Description
Register File
Address
Register Type
ACCESS Size
Default
value
Next RF
Address
IOCFG
I/O Pin Mapping
Configuration
0xA7
W
byte
IOPC0
Pull Resistor
Configuration 0
0xAA
R/W
word
0xFFFF
0xAB
IOPC1
Pull Resistor
Configuration 1
0xAC
R/W
word
0xFFFF
0xAD
IOPC2
Pull Resistor
Configuration 2
0xAE
R/W
word
0xFFFF
0xAF
GPIODATA0
GPIO I/O Data 0
0xC0
R/W
byte
0x00
0xC1
GPIOMASK0
GPIO I/O Mask 0
0xC1
W
byte
GPIODATA1
GPIO I/O Data 1
0xC2
R/W
byte
GPIOMASK1
GPIO I/O Mask 1
0xC3
W
byte
GPIODATA2
GPIO I/O Data 2
0xC4
R/W
byte
GPIOMASK2
GPIO I/O Mask 2
0xC5
W
byte
GPIODIR0
GPIO I/O Direction 0
0xC6
R/W
byte
0x00
0xC7
GPIODIR1
GPIO I/O Direction 1
0xC7
R/W
byte
0x00
0xC8
GPIODIR2
GPIO I/O Direction 2
0xC8
R/W
byte
0x00
0xC9
GPIOIS0
GPIO Int Sense Config 0
0xC9
R/W
byte
0x00
0xCA
GPIOIS1
GPIO Int Sense Config 1
0xCA
R/W
byte
0x00
0xCB
GPIOIS2
GPIO Int Sense Config 2
0xCB
R/W
byte
0x00
0xCC
GPIOIBE0
GPIO Int Both Edges
Config 0
0xCC
R/W
byte
0x00
0xCD
GPIOIBE1
GPIO Int Both Edges
Config 1
0xCD
R/W
byte
0x00
0xCE
GPIOIBE2
GPIO Int Both Edges
Config 2
0xCE
R/W
byte
0x00
0xCF
GPIOIEV0
GPIO Int Edge Select 0
0xCF
R/W
byte
0x00
0xD0
GPIOIEV1
GPIO Int Edge Select 1
0xD0
R/W
byte
0x00
0xD1
GPIOIEV2
GPIO Int Edge Select 2
0xD1
R/W
byte
0x00
0xD2
GPIOIE0
GPIO Interrupt Enable 0
0xD2
R/W
byte
0x00
0xD3
GPIOIE1
GPIO Interrupt Enable 1
0xD3
R/W
byte
0x00
0xD4
GPIOIE2
GPIO Interrupt Enable 2
0xD4
R/W
byte
0x00
0xD5
GPIORIS0
GPIO Raw Int Status 0
0xD6
R
byte
0x00
0xD7
GPIORIS1
GPIO Raw Int Status 1
0xD7
R
byte
0x00
0xD8
GPIORIS2
GPIO Raw Int Status 2
0xD8
R
byte
0x00
0xD9
GPIOMIS0
GPIO Masked Int Status 0
0xD9
R
byte
0x00
0xDA
GPIOMIS1
GPIO Masked Int Status 1
0xDA
R
byte
0x00
0xDB
GPIOMIS2
GPIO Masked Int Status 2
0xDB
R
byte
0x00
0xDC
GPIO Interrupt Clear 0
0xDC
W
byte
GPIOIC0
0xA8
0xC2
0x00
0xC3
0xC4
0x00
0xC5
0xC6
0xDD
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Table 108. Register Map for GPIO Functionality (continued)
Register Name
Description
Register File
Address
Register Type
ACCESS Size
GPIOIC1
GPIO Interrupt Clear 1
0xDD
W
byte
0xDE
GPIOIC2
GPIO Interrupt Clear 2
0xDE
W
byte
0xDF
GPIOOME0
GPIO Open Drain Mode
Enable 0
0xE0
R/W
byte
0x00
0xE1
GPIOOMS0
GPIO Open Drain Mode
Select 0
0xE1
R/W
byte
0x00
0xE2
GPIOOME1
GPIO Open Drain Mode
Enable 1
0xE2
R/W
byte
0x00
0xE3
GPIOOMS1
GPIO Open Drain Mode
Select 1
0xE3
R/W
byte
0x00
0xE4
GPIOOME2
GPIO Open Drain Mode
Enable 2
0xE4
R/W
byte
0x08
0xE5
GPIOOMS2
GPIO Open Drain Mode
Select 2
0xE5
R/W
byte
0x00
0xE6
GPIOWAKE0
GPIO Wakeup Enable 0
0xE9
R/W
byte
0x00
0xEA
GPIOWAKE1
GPIO Wakeup Enable 1
0xEA
R/W
byte
0x00
0xEB
GPIOWAKE2
GPIO Wakeup Enable 2
0xEB
R/W
byte
0x00
0xEC
56
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Default
value
Next RF
Address
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Table 109. REGISTER LAYOUT - Control Bits in LM8327 Registers
Register
Addr.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
KBDSETTLE
0x01
KBDBOUNCE
0x02
Wait[7:0]
KBDSIZE
0x03
ROWSIZE3
ROWSIZE2
ROWSIZE1
ROWSIZE0
COLSIZE3
COLSIZE2
COLSIZE1
COLSIZE0
KBDDEDCFG0
0x04
COL9
COL8
COL7
COL6
COL5
COL4
COL3
COL2
KBDDEDCFG1
0x05
ROW7
ROW6
ROW5
ROW4
ROW3
ROW2
COL11
COL10
KBDRIS
0x06
RELINT
REVTINT
RKLINT
RSINT
KBDMIS
0x07
MELINT
MEVTINT
MKLINT
MSINT
KBDIC
0x08
EVTIC
KBDIC
KBDMSK
0x09
MSKELINT
MSKEINT
MSKLINT
MSKSINT
KBDCODE0
0x0B
MULTIKEY
KEYROW2
KEYROW1
KEYROW0
KEYCOL3
KEYCOL2
KEYCOL1
KEYCOL0
KBDCODE1
0x0C
MULTIKEY
KEYROW2
KEYROW1
KEYROW0
KEYCOL3
KEYCOL2
KEYCOL1
KEYCOL0
KBDCODE2
0x0D
MULTIKEY
KEYROW2
KEYROW1
KEYROW0
KEYCOL3
KEYCOL2
KEYCOL1
KEYCOL0
KBDCODE3
0x0E
MULTIKEY
KEYROW2
KEYROW1
KEYROW0
KEYCOL3
KEYCOL2
KEYCOL1
KEYCOL0
EVTCODE
0x10
RELEASE
KEYROW2
KEYROW1
KEYROW0
KEYCOL3
KEYCOL2
KEYCOL1
KEYCOL0
TIMCFG0
0x60
PWMCFG0
0x61
CDIRQ0MSK
PGE
PWMEN
PWMPOL
TIMSCAL0
0x62
TIMCFG1
0x68
PWMCFG1
0x69
PGE
PWMEN
PWMPOL
TIMSCAL1
0x6A
TIMCFG2
0x70
PWMCFG2
0x71
PGE
PWMEN
PWMPOL
TIMSCAL2
0x72
TIMSWRES
0x78
SWRES2
SWRES1
SWRES0
TIMRIS
0x7A
CDIRQ2
CDIRQ1
CDIRQ0
CYCIRQ2
CYCIRQ1
CYCIRQ0
TIMMIS
0x7B
CDIRQ2
CDIRQ1
CDIRQ0
CYCIRQ2
CYCIRQ1
CYCIRQ0
TIMIC
0x7C
CDIRQ2
CDIRQ1
CDIRQ0
CYCIRQ2
CYCIRQ1
CYCIRQ0
PWMWP
0x7D
PWMCFG(Low)
0x7E
CMD[7:0]
PWMCFG(High)
0x7F
CMD[15:8]
I2CSA
0x80
MFGCODE
0x80
MFGBIT[7:0]
SWREV
0x81
SWBIT[7:0]
SWRESET
0x81
SWBIT[7:0]
Wait[7:0]
SFOFF
CYCIRQ0MSK
START
SCAL[7:0]
CYCIRQ1MSK
START
CDIRQ1MSK
SCAL[7:0]
CYCIRQ2MSK
START
CDIRQ2MSK
SCAL[7:0]
0
PWMWP[6:0]
SLAVEADDR[7:1]
0
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57
LM8327
SNLS329A – SEPTEMBER 2011 – REVISED MAY 2013
www.ti.com
Table 109. REGISTER LAYOUT - Control Bits in LM8327 Registers (continued)
Register
Addr.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
IRQRST
TIMRST
BIT 2
BIT 1
BIT 0
RSTCTRL
0x82
RSTINTCLR
0x84
CLKMODE
0x88
CLKCFG
0X89
CLKEN
0x8A
AUTOSLP
0x8B
AUTOSLPTI (Low)
0x8C
AUTOSLPTI (High)
0x8D
IRQST
0x91
IOCFG
0xA7
IOPC0 (Low)
0xAA
KPX3PR[1:0]
KPX2PR[1:0]
KPX1PR[1:0]
KPX0PR[1:0]
IOPC0 (High)
0xAB
KPX7PR[1:0]
KPX6PR[1:0]
KPX5PR[1:0]
KPX4PR[1:0]
IOPC1 (Low)
0xAC
KPY3PR[1:0]
KPY2PR[1:0]
KPY1PR[1:0]
KPY0PR[1:0]
IOPC1 (High)
0xAD
KPY7PR[1:0]
KPY6PR[1:0]
KPY5PR[1:0]
KPY4PR[1:0]
IOPC2 (Low)
0xAE
KPY11PR[1:0]
KPY10PR[1:0]
KPY9PR[1:0]
KPY8PR[1:0]
IOPC2 (High)
0xAF
EXTIOPR[1:0]
PWM2PR[1:0]
PWM1PR{1:0]
PWM0PR[1:0]
GPIODATA0
0xC0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
GPIOMASK0
0xC1
MASK7
MASK6
MASK5
MASK4
MASK3
MASK2
MASK1
MASK0
GPIODATA1
0xC2
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
GPIOMASK1
0xC3
MASK15
MASK14
MASK13
MASK12
MASK11
DATA10
DATA9
DATA8
GPIODATA2
0xC4
DATA23
DATA22
DATA21
DATA20
DATA19
DATA18
DATA17
DATA16
GPIOMASK2
0xC5
MASK23
MASK22
MASK21
MASK20
MASK19
MASK18
MASK17
MASK16
GPIODIR0
0xC6
KPX7DIR
KPX6DIR
KPX5DIR
KPX4DIR
KPX3DIR
KPX2DIR
KPX1DIR
KPX0DIR
GPIODIR1
0xC7
KPY7DIR
KPY6DIR
KPY5DIR
KPY4DIR
KPY3DIR
KPY2DIR
KPY1DIR
KPY0DIR
GPIODIR2
0xC8
EXTIODIR
PWM2DIR
PWM1DIR
PWM0DIR
KP11DIR
KPY10DIR
KPY9DIR
KPY8DIR
GPIOIS0
0xC9
KPX7IS
KPX6IS
KPX5IS
KPX4IS
KPX3IS
KPX2IS
KPX1IS
KPX0IS
GPIOIS1
0xCA
KPY7IS
KPY6IS
KPY5IS
KPY4IS
KPY3IS
KPY2IS
KPY1IS
KPY0IS
GPIOIS2
0xCB
EXTIOIS
PWM2IS
PWM1IS
PWM0IS
KPY11IS
KPY10IS
KPY9IS
KPY8IS
GPIOIBE0
0xCC
KPX7IBE
KPX6IBE
KPX5IBE
KPX4IBE
KPX3IBE
KPX2IBE
KPX1IBE
KPX0IBE
GPIOIBE1
0xCD
KPY7IBE
KPY6IBE
KPY5IBE
KPY4IBE
KPY3IBE
KPY2IBE
KPY1IBE
KPY0IBE
GPIOIBE2
0xCE
EXTIOIBE
PWM2IBE
PWM1IBE
PWM0IBE
KPY11IBE
KPY10IBE
KPY9IBE
KPY8IBE
GPIOIEV0
0xCF
KPX7EV
KPX6EV
KPX5EV
KPX4EV
KPX3EV
KPX2EV
KPX1EV
KPX0EV
GPIOIEV1
0xD0
KPY7EV
KPY6EV
KPY5EV
KPY4EV
KPY3EV
KPY2EV
KPY1EV
KPY0EV
GPIOIEV2
0xD1
EXTIOIEV
PWM2IEV
PWM1IEV
PWM0IEV
KPY11IEV
KPY10IEV
KPY9IEV
KPY8IEV
58
KBDRST
GPIRST
IRQCLR
MODCTL[1:0]
CLKSRCSEL[1:0]
CLKOUTEN[1:0]
TIMEN
DKBDEN
KBDEN
ENABLE
UP-TIME [7:0]
UP-TIME [10:8]
PORIRQ
KBD1RQ
DKBDIRQ
TIM2IRQ
TIM1IRQ
TIM01RQ
GPIIRQ
IOCFGPM [7:0]
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Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LM8327
LM8327
www.ti.com
SNLS329A – SEPTEMBER 2011 – REVISED MAY 2013
Table 109. REGISTER LAYOUT - Control Bits in LM8327 Registers (continued)
Register
Addr.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
GPIOIE0
0xD2
KPX7IE
KPX6IE
KPX5IE
KPX4IE
KPX3IE
KPX2IE
KPX1IE
KPX0IE
GPIOIE1
0xD3
KPY7IE
KPY6IE
KPY5IE
KPY4IE
KPY3IE
KPY2IE
KPY1IE
KPY0IE
GPIOIE2
0xD4
EXTIOIE
PWM2IE
PWM1IE
PWM0IE
KPY11IE
KPY10IE
KPY9IE
KPY8IE
GPIORIS0
0xD6
KPX7RIS
KPX6RIS
KPX5RIS
KPX4RIS
KPX3RIS
KPX2RIS
KPX1RIS
KPX0RIS
GPIORIS1
0xD7
KPY7RIS
KPY6RIS
KPY5RIS
KPY4RIS
KPY3RIS
KPY2RIS
KPY1RIS
KPY0RIS
GPIORIS2
0xD8
EXTIORIS
PWM2RIS
PWM1RIS
PWM0RIS
KPY11RIS
KPY10RIS
KPY9RIS
KPY8RIS
GPIOMIS0
0xD9
KPX7MIS
KPX6MIS
KPX5MIS
KPX4MIS
KPX3MIS
KPX2MIS
KPX1MIS
KPX0MIS
GPIOMIS1
0xDA
KPY7MIS
KPY6MIS
KPY5MIS
KPY4MIS
KPY3MIS
KPY2MIS
KPY1MIS
KPY0MIS
GPIOMIS2
0xDB
EXTIOMIS
PWM2MIS
PWM1MIS
PWM0MIS
KPY11MIS
KPY10MIS
KPY9MIS
KPY8MIS
GPIOIC0
0xDC
KPX7IC
KPX6IC
KPX5IC
KPX4IC
KPX3IC
KPX2IC
KPX1IC
KPX0IC
GPIOIC1
0xDD
KPY7IC
KPY6IC
KPY5IC
KPY4IC
KPY3IC
KPY2IC
KPY1IC
KPY0IC
GPIOIC2
0xDE
EXTIOIC
PWM2IC
PWM1IC
PWM0IC
KPY11IC
KPY10IC
KPY9IC
KPY8IC
GPIOOME0
0xE0
KPX7ODE
KPX6ODE
KPX5ODE
KPX4ODE
KPX3ODE
KPX2ODE
KPX1ODE
KPX0ODE
GPIOOMS0
0xE1
KPX7ODM
KPX6ODM
KPX5ODM
KPX4ODM
KPX3ODM
KPX2ODM
KPX1ODM
KPX0ODM
GPIOOME1
0xE2
KPY7ODE
KPY6ODE
KPY5ODE
KPY4ODE
KPY3ODE
KPY2ODE
KPY1ODE
KPY0ODE
GPIOOMS1
0xE3
KPY7ODM
KPY6ODM
KPY5ODM
KPY4ODM
KPY3ODM
KPY2ODM
KPY1ODM
KPY0ODM
GPIOOME2
0xE4
EXTIO-ODE
PWM2-ODE
PWM1-ODE
PWM0-ODE
KPY11ODE
KPY10ODE
KPY9 ODE
KPY8 ODE
GPIOOMS2
0xE5
EXTIO-ODM
PWM2-ODM
PWM1-ODM
PWM0-ODM
KPY11ODM
KPY10ODM
KPY9 ODM
KPY8 ODM
DEVTCODE
0xE6
DKEYCODE[4:0]
DBOUNCE
0xE7
DBOUNCE[4:0]
GPIOWAKE0
0xE9
KPX7WAKE
KPX6WAKE
KPX5WAKE
KPX4WAKE
KPX3WAKE
KPX2WAKE
KPX1WAKE
KPX0WAKE
GPIOWAKE1
0xEA
KPY7WAKE
KPY6WAKE
KPY5WAKE
KPY4WAKE
KPY3WAKE
KPY2WAKE
KPY1WAKE
KPY0WAKE
GPIOWAKE2
0xEB
EXTIOWAKE
PWM2WAKE
PWM1WAKE
PWM0WAKE
KPY11WAKE
KPY10WAKE
KPY9WAKE
KPY8WAKE
DIRECT0
0xEC
DK07
DK06
DK05
DK04
DK03
DK02
DK01
DK00
DIRECT1
0xED
DK15
DK14
DK13
DK12
DK11
DK10
DK09
DK08
DIRECT2
0xEE
DK23
DK22
DK21
DK20
DK19
DK18
DK17
DK16
DIRECT3
0xEF
DK25
DK24
DKBDRIS
0xF0
DRELINT
DREVTINT
DKBDMIS
0xF1
DMELINT
DMEVTINT
DKBDIC
0xF2
DKBDMSK
0xF3
MMASTER
0xF4
DEVTIC
DMSKELINT
MSTADR[7:1]
DMSKEINT
MMSTEN
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Product Folder Links: LM8327
59
LM8327
SNLS329A – SEPTEMBER 2011 – REVISED MAY 2013
www.ti.com
REVISION HISTORY
Changes from Original (May 2013) to Revision A
•
60
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 59
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Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LM8327
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM8327JGR8/NOPB
ACTIVE
csBGA
NYB
36
1000
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
LM8327
LM8327JGR8X/NOPB
ACTIVE
csBGA
NYB
36
3500
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
LM8327
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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