LMC8101BPCONV

LMC8101 www.ti.com SNOS496F – AUGUST 2000 – REVISED MARCH 2013 LMC8101 Rail-to-Rail Input and Output, 2.7V Op Amp in DSBGA Package With Shutdown Check for Samples: LMC8101 FEATURES DESCRIPTION 1 • 2 • • • • • • • • • • • • + VS = 2.7V, TA = 25°C, RL to V /2, Typical Values Unless Specified. Rail-to-Rail Inputs Rail-to-Rail Output Swing Within 35mV of Supplies (RL =2kΩ) Packages Offered: – DSBGA package 1.39mm x 1.41mm – VSSOP package 3.0mm x 4.9mm Low Supply Current 1 MΩ to V+/2. Boldface limits apply at the temperature extremes. Symbol Parameter VOS Input Offset Voltage TCVOS Input Offset Voltage Average Drift IB Input Bias Current IOS Input Offset Current Rin Cin Conditions Limit (2) Units ±0.70 ±5 ±7 mV max μV/°C 4 See (3) ±1 ±64 pA max 0.5 32 pA max CM Input Common Mode Resistance 10 GΩ CM Input Common Mode Capacitance 10 pF CMRR Common Mode Rejection Ratio PSRR Power Supply Rejection Ratio CMVR 0V < = VCM < = 2.7V 78 60 VS = 3V 0V < = VCM < = 3V 78 64 60 VS = 2.7V to 3V 57 50 48 dB min VS = 2.7V CMRR > = 50dB 0.0 0.0 V max 3.0 2.7 V min VS = 3V CMRR > = 50dB −0.2 −0.1 V max 3.2 3.1 V min 3162 1000 562 Sinking RL = 2kΩ to V+/2 VO = 1.35V to 0.25V 3162 804 562 Sourcing RL = 10kΩ to V+/2 VO = 1.35V to 2.65V 4000 1778 1000 Sinking RL = 10kΩ to V+/2 VO = 1.35V to 0.05V 4000 Input Common-Mode Voltage Range AVOL Sourcing RL = 2kΩ to V+/2 VO = 1.35V to 2.45V Large Signal Voltage Gain VO Output Swing High Output Swing Low (1) (2) (3) Typ (1) dB min V/V min 1778 1000 V/V min RL = 2kΩ to V+/2 VID = 100mV 2.67 2.64 2.62 V min RL = 10kΩ to V+/2 VID = 100mV 2.69 2.68 2.67 V min RL = 2kΩ to V+/2 VID = −100mV 32 100 150 mV max RL = 10kΩ to V+/2 VID = −100mV 10 30 70 mV max Typical Values represent the most likely parametric norm. All limits are specified by testing or statistical analysis. Positive current corresponds to current flowing into the device. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC8101 3 LMC8101 SNOS496F – AUGUST 2000 – REVISED MARCH 2013 www.ti.com 2.7V Electrical Characteristics (continued) Unless otherwise specified, all limits specified for TJ = 25°C, V+ = 2.7V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ to V+/2. Boldface limits apply at the temperature extremes. Symbol Typ (1) Limit (2) Units V+/2 (4) Sourcing to VID = 100mV 20 14 6 mA min Sinking to V+/2 VID = −100mV (4) 10 5 4 mA min 1.0 1.2 mA max Parameter ISC Output Short Circuit Current IS Supply Current Conditions No load, normal operation 0.70 Shutdown mode 0.001 1 µA max 10 15 µs ±1 ±64 pA max 1 0.8 V/µs min Shutdown Turn-on time See (5) Toff Shutdown Turn-off time (5) Iin "SL" and "SD" Input Current (6) SR Slew Rate (7) AV = +1, RL = 10kΩ to V+/2 VI= 1VPP fu Unity Gain-Bandwidth VI = 10mV, RL = 2kΩ to V+/2 750 KHz GBW Gain Bandwidth Product f = 100KHz 1 MHz en Input-Referred Voltage Noise f = 10KHz, RS = 50Ω 36 nV/√Hz in Input-Referred Current Noise f = 10KHz 1.5 fA/√Hz Total Harmonic Distortion f = 1KHz, AV = +1, VO = 2.2Vpp, RL = 600Ω to V+/2 0.18 % Ton THD (4) See 1 µs Short circuit test is a momentary test. Output short circuit duration is infinite for VS < 6V. Otherwise, extended period output short circuit may damage the device. Shutdown Turn-on and Turn-off times are defined as the time required for the output to reach 90% and 10%, respectively, of its final peak to peak swing when set for Rail to Rail output swing with a 100KHz sine wave, 2KΩ load, and AV = +10. Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings. Slew rate is the slower of the rising and falling slew rates. (5) (6) (7) ±5V Electrical Characteristics Unless otherwise specified, all limits specified for TJ = 25°C, V+ =5V, V− = −5V, VCM = VO = 0V, and RL > 1 MΩ to gnd. Boldface limits apply at the temperature extremes. Symbol Parameter VOS Input Offset Voltage TCVos Input Offset Voltage Average Drift IB Input Bias Current IOS Rin Cin Conditions Units ±0.7 ±5 ±7 mV max ±1 ±64 pA max 32 pA max μV/°C 4 See (3) Input Offset Current 0.5 Input Common Mode Resistance 10 GΩ CM Input Common Mode Capacitance 10 pF PSRR Common-Mode Rejection Ratio −5V < = VCM < = 5V Power Supply Rejection Ratio VS = 5V to 10V CMVR Input Common-Mode Voltage Range 4 Limit (2) CM CMRR (1) (2) (3) Typ (1) CMRR ≥ 50 dB 87 70 67 dB min 80 76 72 dB min −5.3 −5.2 −5.0 V max 5.3 5.2 5.0 V min Typical Values represent the most likely parametric norm. All limits are specified by testing or statistical analysis. Positive current corresponds to current flowing into the device. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC8101 LMC8101 www.ti.com SNOS496F – AUGUST 2000 – REVISED MARCH 2013 ±5V Electrical Characteristics (continued) Unless otherwise specified, all limits specified for TJ = 25°C, V+ =5V, V− = −5V, VCM = VO = 0V, and RL > 1 MΩ to gnd. Boldface limits apply at the temperature extremes. Symbol Typ (1) Limit (2) Sourcing RL = 600Ω VO = 0V to 4V 34.5 17.8 10 Sinking RL = 600Ω VO = 0V to −4V 34.5 17.8 3.16 Sourcing RL = 2kΩ VO = 0V to 4.6V 138 31.6 17.8 Sinking RL = 2kΩ VO = 0V to −4.6V 138 Parameter AVOL Large Signal Voltage Gain VO Output Swing High Output Swing Low ISC Conditions V/mV min V/mV min RL = 600Ω VID = 100mV 4.73 4.60 4.54 V min RL = 2kΩ VID = 100mV 4.90 4.85 4.83 V min RL = 600Ω VID = −100mV −4.85 −4.75 −4.65 V max RL = 2kΩ VID = −100mV −4.95 4.90 −4.84 V max Sourcing, VID = 100mV (4) (5) 49 30 25 mA min Sinking, VID = −100mV (4) (5) 90 60 52 mA min No load, normal operation 1.1 1.7 1.9 mA max 0.001 1 µA 10 15 µs ±64 pA max Output Short Circuit Current IS 31.6 10 Units Supply Current Shutdown mode (6) Ton Shutdown Turn-on time See Toff Shutdown Turn-off time See (6) Iin "SL" and "SD" Input Current SR Slew Rate (7) AV = +10, RL = 10kΩ, VO = 10Vpp, CL = 1000pF 1.2 V/µs fu Unity Gain-Bandwidth VI = 10mV RL = 2kΩ 840 KHz GBW Gain Bandwidth Product f = 10KHz 1.3 MHz en Input-Referred Voltage Noise f = 10KHz, Rs = 50Ω 33 nV/√Hz in Input-Referred Current Noise f = 10KHz 1.5 fA/√Hz Total Harmonic Distortion f = 10KHz, AV = +1, VO =8Vpp, RL = 600Ω 0.2 % THD (4) (5) (6) (7) 1 ±1 µs Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature at 150°C. Output currents in excess of 40mA over long term may adversely affect reliability. Short circuit test is a momentary test. Output short circuit duration is infinite for VS < 6V. Otherwise, extended period output short circuit may damage the device. Shutdown Turn-on and Turn-off times are defined as the time required for the output to reach 90% and 10%, respectively, of its final peak to peak swing when set for Rail to Rail output swing with a 100KHz sine wave, 2KΩ load, and AV = +10. Slew rate is the slower of the rising and falling slew rates. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC8101 5 LMC8101 SNOS496F – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified 6 Gain/Phase vs. Frequency (RL = 2k, VS = ± 1.35V) Gain/Phase vs. Frequency (RL = 2k, VS = ± 5V) Figure 3. Figure 4. Gain/Phase vs. Frequency (RL = Open) Gain vs. Phase for various CL VS = ±1.35V Figure 5. Figure 6. Unity Gain Frequency vs. Supply Voltage Phase Margin vs. Supply Voltage Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC8101 LMC8101 www.ti.com SNOS496F – AUGUST 2000 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified Unity Gain Frequency and Phase Margin vs. Load Unity Gain Frequency and Phase Margin vs. Load Figure 9. Figure 10. PSRR vs. Frequency PSRR vs. Frequency Figure 11. Figure 12. CMRR vs. Frequency Input Bias Current vs. Common Mode Voltage @ 85°C Figure 13. Figure 14. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC8101 7 LMC8101 SNOS496F – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified 8 Input Current vs. Temperature VS = 10V VIN vs. VOUT Figure 15. Figure 16. VIN vs. VOUT VIN vs. VOUT Figure 17. Figure 18. VIN vs. VOUT Supply Current vs. Supply Voltage Figure 19. Figure 20. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC8101 LMC8101 www.ti.com SNOS496F – AUGUST 2000 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified Delta VOS vs. VCM (Ref VCM = 1.35V) Delta VOS vs. VCM (Ref VCM = 5V) Figure 21. Figure 22. Offset Voltage vs. VSUPPLY Output Positive Swing vs. Supply Voltage RL = 600Ω to V+/2 Figure 23. Figure 24. Output Positive Swing vs. Supply Voltage RL = 2k to V+/2 Output Negative Swing vs. Supply Voltage RL = 600Ω to V+/2 Figure 25. Figure 26. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC8101 9 LMC8101 SNOS496F – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified 10 Output Negative Swing vs. Supply Voltage, RL = 2k to V+/2 Short Circuit Sinking Current vs. Supply Voltage Figure 27. Figure 28. Short Circuit Sourcing Current vs. Supply Voltage Undistorted Output Voltage Swing vs. Output Load Resistance Figure 29. Figure 30. Step Response 1% settling time and % overshoot vs. Cap Load Large Signal Step Response Figure 31. Figure 32. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC8101 LMC8101 www.ti.com SNOS496F – AUGUST 2000 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified Small Signal Step Response Large Signal Step Response Figure 33. Figure 34. Small Signal Step Response Small Signal Step Response Figure 35. Figure 36. Large Signal Step Response Large Signal Step Response Figure 37. Figure 38. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC8101 11 LMC8101 SNOS496F – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified 12 Small Signal Step Response Slew Rate vs. Supply Voltage Figure 39. Figure 40. Slew Rate vs. Capacitive Load Slew Rate vs. Capacitive Load Figure 41. Figure 42. Slew Rate vs. Capacitive Load Slew Rate vs. Capacitive Load Figure 43. Figure 44. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC8101 LMC8101 www.ti.com SNOS496F – AUGUST 2000 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified Voltage Noise vs. Frequency Voltage Noise vs. VCM @ Various Frequencies Figure 45. Figure 46. THD+N vs. Amplitude THD+N vs. Frequency Figure 47. Figure 48. Sourcing Current vs. Output Voltage (VS = 2.7V) Sinking Current vs. Output Voltage (VS = 2.7V) Figure 49. Figure 50. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC8101 13 LMC8101 SNOS496F – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = 2.7V, Single Supply, VCM = V+/2, TA = 25°C unless specified 14 Sourcing Current vs. Output Voltage (VS = 10V) Sinking Current vs. Output Voltage (VS = 10V) Figure 51. Figure 52. Cap Load vs. IOUT Cap Load vs. Isolation Resistance Figure 53. Figure 54. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC8101 LMC8101 www.ti.com SNOS496F – AUGUST 2000 – REVISED MARCH 2013 APPLICATION NOTES SHUTDOWN FEATURES The LMC8101 is capable of being turned off in order to conserve power. Once in shutdown, the device supply current is drastically reduced (1µA maximum) and the output will be "Tri-stated". The shutdown feature of the LMC8101 is designed for flexibility. The threshold level of the SD input can be referenced to either V-or V+ by setting the level on the SL input. When the SL input is connected to V-, the SD threshold level is referenced to V-and vice versa. This threshold will be about 1.5V from the supply tied to the SL pin. So, for this example, the device will be in shutdown as long as the SD pin voltage is within 1V of V-. In order to ensure that the device would not "chatter" between active and shutdown states, hysteresis is built into the SD pin transition (see Figure 55 for an illustration of this feature). The shutdown threshold and hysteresis level are independent of the supply voltage. Figure 55 illustration applies equally well to the case when SL is tied to V+ and the horizontal axis is referenced to V+ instead. The SD pin should not be set within the voltage range from 1.1V to 1.9V of the selected supply voltage since this is a transition region and the device status will be undetermined. Figure 55. Supply Current vs. "SD" Voltage Table 1 summarizes the status of the device when the SL and SD pins are connected directly to V-or V+: Table 1. LMC8101 Status Summary SL SD LMC8101 Status V− V− Shutdown − + V V Active V+ V+ Shutdown V+ V− Active In case shutdown operation is not needed, as can be seen above, the two pins SL and SD can simply be connected to opposite supply nodes to achieve "Active" operation. The SL and SD should always be tied to a node; if left unconnected, these high impedance inputs will float to an undetermined state and the device status will be undetermined as well. With the device in shutdown, once "Active" operation is initiated, there will be a finite amount of time required before the device output is settled to its final value. This time is less than 15µs. In addition, there may be some output spike during this time while the device is transitioning into a fully operational state. Some applications may be sensitive to this output spike and proper precautions should be taken in order to ensure proper operation at all times. TINY PACKAGE The LMC8101 is available in the DSBGA package as well the 8 pin VSSOP package. The DSBGA package requires approximately 1/4 the board area of a SOT-23. This package is less than 1mm in height allowing it to be placed in absolute minimum height clearance areas such as cellular handsets, LCD panels, PCMCIA cards, etc. More information about the DSBGA package can be found at: http://www.ti.com/packaing. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC8101 15 LMC8101 SNOS496F – AUGUST 2000 – REVISED MARCH 2013 www.ti.com CONVERSION BOARDS In order to ease the evaluation of tiny packages such as the DSBGA, there is a conversion board (LMC8101CONV) available to board designers. This board converts a DSBGA device into an 8 pin DIP package (see Figure 56) for easier handling and evaluation. This board can be ordered from Texas Instruments by contacting http://www.ti.com. Figure 56. DSBGA Conversion Board pin-out INCREASED OUTPUT CURRENT Compared to the LMC7101, the LMC8101 has an improved output stage capable of up to three times larger output sourcing and sinking current. This improvement would allow a larger output voltage swing range compared to the LMC7101 when connected to relatively heavy loads. For lower supply voltages this is an added benefit since it increases the output swing range. For example, the LMC8101 can typically swing 2.5Vpp with 2mA sourcing and sinking output current (Vs = 2.7V) whereas the LMC7101 output swing would be limited to 1.9Vpp under the same conditions. Also, compared to the LMC7101 in the SOT-23 package, the LMC8101 can dissipate more power because both the VSSOP and the DSBGA packages have 40% better heat dissipation capability. LOWER 1/f NOISE The dominant input referred noise term for the LMC8101 is the input noise voltage. Input noise current for this device is of no practical significance unless the equivalent resistance it looks into is 5MΩ or higher. The LMC8101's low frequency noise is significantly lower than that of the LMC7101. For example, at 10Hz, the input referred spot noise voltage density is 85 nV√Hz as compared to about 200nV√Hz for the LMC7101. Over a frequency range of 0.1Hz to 100Hz, the total noise of the LMC8101 will be approximately 60% less than that of the LMC7101. LOWER THD When connected to heavier loads, the LMC8101 has lower THD compared to the LMC7101. For example, with 5V supply at 10KHz and 2Vpp swing (Av = −2), the LMC8101 THD (0.2%) is 60% less than the LMC7101's. The LMC8101 THD can be kept below 0.1% with 3Vpp at the output for up to 10KHz (refer to the Typical Performance Characteristics plots). IMPROVING THE CAP LOAD DRIVE CAPABILITY This can be accomplished in several ways: • Output resistive loading increase: The Phase Margin increases with increasing load (refer to the Typical Performance Characteristics plots). When driving capacitive loads, stability can generally be improved by allowing some output current to flow through a load. For example, the cap load drive capability can be increased from 8200pF to 16000pF if the output load is increased from 5kΩ to 600Ω (AV = +10, 25% overshoot limit, 10V supply). • Isolation resistor between output and cap load: 16 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC8101 LMC8101 www.ti.com SNOS496F – AUGUST 2000 – REVISED MARCH 2013 This resistor will isolate the feedback path (where excessive phase shift due to output capacitance can cause instability) from the capacitive load. With a 10V supply, a 100Ω isolation resistor allows unlimited capacitive load without oscillation compared to only 300pF without this resistor (AV = +1). • Higher supply voltage: Operating the LMC8101 at higher supply voltages allows higher cap load tolerance. At 10V, the LMC8101's low supply voltage cap load limit of 300pF improves to about 600pF (AV = +1). • Closed loop gain increase: As with all Op Amps, the capacitive load tolerance of the LMC8101 increases with increasing closed loop gain. In applications where the load is mostly capacitive and the resistive loading is light, stability increases when the LMC8101 is operated at a closed loop gain larger than +1. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC8101 17 LMC8101 SNOS496F – AUGUST 2000 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision E (March 2013) to Revision F • 18 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 17 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC8101 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LMC8101TP/NOPB ACTIVE DSBGA YPB 8 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 A 08 LMC8101TPX/NOPB ACTIVE DSBGA YPB 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 A 08 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of