LP-CC2651P3

CC2651P3 SWRS257 – MARCH 2022 CC2651P3 SimpleLink™ Single-Protocol 2.4 GHz Wireless MCU With Integrated Power Amplifier 1 Features Wireless microcontroller • • • • • • Powerful 48-MHz Arm® Cortex®-M4 processor 352KB flash program memory 32KB of ultra-low leakage SRAM 8KB of Cache SRAM (Alternatively available as general-purpose RAM) Programmable radio includes support for 2(G)FSK, 4-(G)FSK, MSK, Bluetooth® 5.2 Low Energy, IEEE 802.15.4 PHY and MAC Supports over-the-air upgrade (OTA) Low power consumption • • MCU consumption: – 2.91 mA active mode, CoreMark® – 61 μA/MHz running CoreMark – 0.8 μA standby mode, RTC, 32KB RAM – 0.1 μA shutdown mode, wake-up on pin Radio Consumption: – 6.4 mA RX – 7.1 mA TX at 0 dBm – 9.5 mA TX at +5 dBm – 22 mA TX at +10 dBm – 101 mA TX at +20 dBm (7x7 package) Wireless protocol support • • • • Zigbee® Bluetooth® 5.2 Low Energy SimpleLink™ TI 15.4-stack Proprietary systems High performance radio • • MCU peripherals • • • • • • • • Digital peripherals can be routed to any GPIO Four 32-bit or eight 16-bit general-purpose timers 12-bit ADC, 200 kSamples/s, 8 channels 8-bit DAC Analog Comparator UART, SSI, I2C, I2S Real-time clock (RTC) Integrated temperature and battery monitor Security enablers • • • AES 128-bit cryptographic accelerator True random number generator (TRNG) Additional cryptography drivers available in Software Development Kit (SDK) Development tools and software • • • • LP-CC2651P3 Development Kit SimpleLink™ CC13xx and CC26xx Software Development Kit (SDK) SmartRF™ Studio for simple radio configuration SysConfig system configuration tool Operating range • • • On-chip buck DC/DC converter 1.8-V to 3.8-V single supply voltage -40 to +105°C Package • • • 7-mm × 7-mm RGZ VQFN48 (26 GPIOs) 5-mm × 5-mm RKP VQFN40 (18 GPIOs) RoHS-compliant package -104 dBm for Bluetooth® Low Energy 125-kbps Output power up to +20 dBm with temperature compensation Regulatory compliance • Suitable for systems targeting compliance with these standards: – ETSI EN 300 328, EN 300 440 Cat. 2 and 3 – FCC CFR47 Part 15 – ARIB STD-T66 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CC2651P3 www.ti.com SWRS257 – MARCH 2022 2 Applications • • 2400 to 2500 MHz ISM and SRD systems 1 with down to 4 kHz of receive bandwidth Building automation – Building security systems – motion detector, electronic smart lock, door and window sensor, garage door system, gateway – HVAC – thermostat, wireless environmental sensor, HVAC system controller, gateway – Fire safety system – smoke and heat detector, fire alarm control panel (FACP) – Video surveillance – IP network camera – Elevators and escalators – elevator main control panel for elevators and escalators • • • • • • Industrial transport – asset tracking Factory automation and control Medical Electronic point of sale (EPOS) – Electronic Shelf Label (ESL) Communication equipment – Wired networking – wireless LAN or Wi-Fi access points, edge router , small business router Personal electronics – Home theater & entertainment – smart speakers, smart display, set-top box – Wearables (non-medical) – smart trackers, smart clothing 3 Description The SimpleLink™ CC2651P3 device is a single-protocol 2.4-GHz wireless microcontroller (MCU) supporting Zigbee®, Bluetooth®5.2 Low Energy, IEEE 802.15.4g, TI 15.4-Stack (2.4 GHz). The CC2651P3 is based on an Arm® Cortex® M4 main processor and optimized for low-power wireless communication and advanced sensing in grid infrastructure, building automation, retail automation, personal electronics and medical applications. The CC2651P3 has a software defined radio powered by an Arm® Cortex® M0, which allows support for multiple physical layers and RF standards. The device supports operation in the 2360 to 2500-MHz frequency band. The CC2651P3 has an efficient built-in PA that supports +10 dBm TX at 21 mA and +20 dBm TX at 101 mA (7x7 package). CC2651P3 has a receive sensitivity of -104 dBm for 125-kbps Bluetooth® Low Energy Coded PHY. The CC2651P3 has a low sleep current of 0.8 μA with RTC and 32KB RAM retention. Consistent with many customers’ 10 to 15 years or longer life cycle requirements, TI has a product life cycle policy with a commitment to product longevity and continuity of supply. The CC2651P3 device is part of the SimpleLink™ MCU platform, which consists of Wi-Fi®, Bluetooth® Low Energy, Thread, Zigbee, Wi-SUN®, Amazon Sidewalk, mioty, Sub-1 GHz MCUs, and host MCUs. CC2651P3 is part of a scalable portfolio with flash sizes from 32KB to 704KB with pin-to-pin compatible package options. The common SimpleLink™CC13xx and CC26xx Software Development Kit (SDK) and SysConfig system configuration tool supports migration between devices in the portfolio. A comprehensive number of software stacks, application examples and SimpleLink™ Academy training sessions are included in the SDK. For more information, visit wireless connectivity. Device Information PART NUMBER(1) PACKAGE BODY SIZE (NOM) CC2651P31T0RGZR VQFN (48) 7.00 mm × 7.00 mm CC2651P31T0RKPR VQFN (40) 5.00 mm × 5.00 mm (1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 12, or see the TI website. 1 2 See RF Core for additional details on supported protocol standards, modulation formats, and data rates. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 G 2. 4 20 -d B m H z PA 4 Functional Block Diagram RF Core cJTAG Main CPU 40KB ROM ADC ADC ® ® Arm Cortex -M4 Processor 352KB Flash with 8KB Cache Digital PLL DSP Modem 48 MHz 32KB SRAM SRAM Arm® Cortex®-M0 Processor ROM General Hardware Peripherals and Modules I2C 4× 32-bit Timers 8-bit DAC UART SSI (SPI) 12-bit ADC, 200 ks/s I2S Watchdog Timer Low-Power Comparator Up to 26 GPIOs 32 ch. µDMA Time-to-Digital Converter AES & TRNG RTC Temperature and Battery Monitor LDO, Clocks, and References Optional DC/DC Converter Figure 4-1. CC2651P3 Functional Block Diagram Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 2 3 Description.......................................................................2 4 Functional Block Diagram.............................................. 3 5 Revision History.............................................................. 4 6 Device Comparison......................................................... 5 7 Pin Configuration and Functions...................................6 7.1 Pin Diagram – RGZ Package (Top View)....................6 7.2 Signal Descriptions – RGZ Package...........................7 7.3 Pin Diagram – RKP Package (Top View)....................9 7.4 Signal Descriptions – RKP Package...........................9 7.5 Connections for Unused Pins and Modules.............. 11 8 Specifications................................................................ 12 8.1 Absolute Maximum Ratings...................................... 12 8.2 ESD Ratings............................................................. 12 8.3 Recommended Operating Conditions.......................12 8.4 Power Supply and Modules...................................... 12 8.5 Power Consumption - Power Modes........................ 13 8.6 Power Consumption - Radio Modes......................... 14 8.7 Nonvolatile (Flash) Memory Characteristics............. 14 8.8 Thermal Resistance Characteristics......................... 14 8.9 RF Frequency Bands................................................ 15 8.10 Bluetooth Low Energy - Receive (RX).................... 16 8.11 Bluetooth Low Energy - Transmit (TX).................... 19 8.12 Zigbee - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - RX.............................20 8.13 Zigbee - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - TX............................. 21 8.14 Timing and Switching Characteristics..................... 22 8.15 Peripheral Characteristics.......................................25 8.16 Typical Characteristics............................................ 31 9 Detailed Description......................................................39 9.1 Overview................................................................... 39 9.2 System CPU............................................................. 39 9.3 Radio (RF Core)........................................................40 9.4 Memory..................................................................... 41 9.5 Cryptography............................................................ 42 9.6 Timers....................................................................... 43 9.7 Serial Peripherals and I/O.........................................44 9.8 Battery and Temperature Monitor............................. 44 9.9 µDMA........................................................................ 44 9.10 Debug..................................................................... 44 9.11 Power Management................................................ 45 9.12 Clock Systems........................................................ 46 9.13 Network Processor..................................................46 10 Application, Implementation, and Layout................. 47 10.1 Reference Designs................................................. 47 11 Device and Documentation Support..........................48 11.1 Device Nomenclature..............................................48 11.2 Tools and Software..................................................49 11.3 Documentation Support.......................................... 51 11.4 Support Resources................................................. 51 11.5 Trademarks............................................................. 51 11.6 Electrostatic Discharge Caution.............................. 52 11.7 Glossary.................................................................. 52 12 Mechanical, Packaging, and Orderable Information.................................................................... 53 5 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE March 2022 4 REVISION * NOTES Initial Release Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 6 Device Comparison X 7 X 7 mm VQFN (48) X 5 X 5 mm VQFN (40) RAM + GPIO Cache (KB) 5 X 5 mm VQFN (32) X FLASH (KB) 4 X 4 mm VQFN (32) X X +20 dBm PA X X Multiprotocol X CC1311P3 Thread CC1311R3 PACKAGE SIZE ZigBee X Bluetooth® 5.2 LE X Sidewalk X Wi-SUN® mioty CC1310 Device 2.4GHz Prop. Wireless M-Bus Sub-1 GHz Prop. RADIO SUPPORT 32-128 16-20 + 8 10-30 352 32 + 8 22-30 352 32 + 8 26 X 352 80 + 8 30 X 704 144 + 8 30 X X X X X CC1312R X X X X CC1312R7 X X X X CC1352R X X X X X X X X X 352 80 + 8 28 X CC1352P X X X X X X X X X X 352 80 + 8 26 X CC1352P7 X X X X X X X X X X X X X 704 144 + 8 26 CC2640R2F X 128 20 + 8 10-31 CC2642R X 352 80 + 8 31 X CC2642R-Q1 X 352 80 + 8 31 X 352 32 + 8 23-31 X X 352 32 + 8 22-26 X X CC2651R3 X X X CC2651P3 X X X X X X X X CC2652R X X X X X 352 80 + 8 31 X CC2652RB X X X X X 352 80 + 8 31 X CC2652R7 X X X X X 704 144 + 8 31 X CC2652P X X X X X X 352 80 + 8 26 X CC2652P7 X X X X X X 704 144 + 8 26 X Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 5 CC2651P3 www.ti.com SWRS257 – MARCH 2022 7 Pin Configuration and Functions 38 DIO_25 37 DIO_24 40 DIO_27 39 DIO_26 42 DIO_29 41 DIO_28 44 VDDS 43 DIO_30 46 X48M_N 45 VDDR 48 VDDR_RF 47 X48M_P 7.1 Pin Diagram – RGZ Package (Top View) 34 VDDS_DCDC 4 33 DCDC_SW 5 32 DIO_22 TX_20DBM_N 6 31 DIO_21 RX_TX 7 30 DIO_20 X32K_Q1 8 29 DIO_19 X32K_Q2 9 28 DIO_18 DIO_5 10 27 DIO_17 DIO_6 11 26 DIO_16 DIO_7 12 25 JTAG_TCKC DCOUPL 23 JTAG_TMSC 24 3 NC TX_20DBM_P DIO_15 21 VDDS3 22 NC DIO_13 19 DIO_14 20 35 RESET_N DIO_11 17 DIO_12 18 36 DIO_23 2 DIO_9 15 DIO_10 16 1 VDDS2 13 DIO_8 14 RF_P RF_N Figure 7-1. RGZ (7-mm × 7-mm) Pinout, 0.5-mm Pitch (Top View) The following I/O pins marked in Figure 7-1 in bold have high-drive capabilities: • • • • • • Pin 10, DIO_5 Pin 11, DIO_6 Pin 12, DIO_7 Pin 24, JTAG_TMSC Pin 26, DIO_16 Pin 27, DIO_17 The following I/O pins marked in Figure 7-1 in italics have analog capabilities: • • • • • • • • 6 Pin 36, DIO_23 Pin 37, DIO_24 Pin 38, DIO_25 Pin 39, DIO_26 Pin 40, DIO_27 Pin 41, DIO_28 Pin 42, DIO_29 Pin 43, DIO_30 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 7.2 Signal Descriptions – RGZ Package Table 7-1. Signal Descriptions – RGZ Package PIN NAME NO. I/O TYPE DESCRIPTION DCDC_SW 33 — Power Output from internal DC/DC converter(1) DCOUPL 23 — Power For decoupling of internal 1.27 V regulated digital-supply (2) DIO_5 10 I/O Digital GPIO, high-drive capability DIO_6 11 I/O Digital GPIO, high-drive capability DIO_7 12 I/O Digital GPIO, high-drive capability DIO_8 14 I/O Digital GPIO DIO_9 15 I/O Digital GPIO DIO_10 16 I/O Digital GPIO DIO_11 17 I/O Digital GPIO DIO_12 18 I/O Digital GPIO DIO_13 19 I/O Digital GPIO DIO_14 20 I/O Digital GPIO DIO_15 21 I/O Digital GPIO DIO_16 26 I/O Digital GPIO, JTAG_TDO, high-drive capability DIO_17 27 I/O Digital GPIO, JTAG_TDI, high-drive capability DIO_18 28 I/O Digital GPIO DIO_19 29 I/O Digital GPIO DIO_20 30 I/O Digital GPIO DIO_21 31 I/O Digital GPIO DIO_22 32 I/O Digital GPIO DIO_23 36 I/O Digital or Analog GPIO, analog capability DIO_24 37 I/O Digital or Analog GPIO, analog capability DIO_25 38 I/O Digital or Analog GPIO, analog capability DIO_26 39 I/O Digital or Analog GPIO, analog capability DIO_27 40 I/O Digital or Analog GPIO, analog capability DIO_28 41 I/O Digital or Analog GPIO, analog capability DIO_29 42 I/O Digital or Analog GPIO, analog capability DIO_30 43 I/O Digital or Analog GPIO, analog capability EGP — — GND Ground – exposed ground pad(3) JTAG_TMSC 24 I/O Digital JTAG TMSC, high-drive capability JTAG_TCKC 25 I Digital JTAG TCKC RESET_N 35 I Digital Reset, active low. No internal pullup resistor RF_P 1 — RF Positive RF input signal to LNA during RX Positive RF output signal from PA during TX RF_N 2 — RF Negative RF input signal to LNA during RX Negative RF output signal from PA during TX RX_TX 7 — RF Optional bias pin for the RF LNA TX_20DBM_P 5 — RF Positive high-power TX signal TX_20DBM_N 6 — RF Negative high-power TX signal VDDR 45 — Power Internal supply, must be powered from the internal DC/DC converter or the internal LDO(2) (4) (6) VDDR_RF 48 — Power Internal supply, must be powered from the internal DC/DC converter or the internal LDO(2) (5) (6) VDDS 44 — Power 1.8-V to 3.8-V main chip supply(1) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 7 CC2651P3 www.ti.com SWRS257 – MARCH 2022 Table 7-1. Signal Descriptions – RGZ Package (continued) PIN I/O TYPE 13 — Power 1.8-V to 3.8-V DIO supply(1) VDDS3 22 — Power 1.8-V to 3.8-V DIO supply(1) VDDS_DCDC 34 — Power 1.8-V to 3.8-V DC/DC converter supply X48M_N 46 — Analog 48-MHz crystal oscillator pin 1 X48M_P 47 — Analog 48-MHz crystal oscillator pin 2 X32K_Q1 8 — Analog 32-kHz crystal oscillator pin 1 X32K_Q2 9 — Analog 32-kHz crystal oscillator pin 2 NAME NO. VDDS2 (1) (2) (3) (4) (5) (6) 8 DESCRIPTION For more details, see the device technical reference manual listed in Section 11.3. Do not supply external circuitry from this pin. EGP is the only ground connection for the device. Good electrical connection to device ground on printed circuit board (PCB) is imperative for proper device operation. If internal DC/DC converter is not used, this pin is supplied internally from the main LDO. If internal DC/DC converter is not used, this pin must be connected to VDDR for supply from the main LDO. Output from internal DC/DC and LDO is trimmed to 1.68 V. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 31 DIO_18 32 DIO_19 33 DIO_20 34 DIO_21 35 DIO_22 36 VDDS 37 VDDR 38 X48M_N 39 X48M_P 40 VDDR_RF 7.3 Pin Diagram – RKP Package (Top View) RF_P 1 30 DIO_17 RF_N 2 29 DIO_16 NC 3 28 DIO_15 20 DIO_10 DIO_11 19 21 18 10 JTAG_TCKC DIO_5 JTAG_TMSC DIO_12 17 DIO_13 22 DCOUPL 23 9 16 8 X32K_Q2 15 X32K_Q1 DIO_9 DIO_14 VDDS3 DCDC_SW 24 14 25 7 13 6 RX_TX DIO_8 TX_10DBM_N VDDS2 VDDS_DCDC 12 RESET_N 26 11 27 5 DIO_7 4 DIO_6 NC TX_10DBM_P Figure 7-2. RKP (5-mm × 5-mm) Pinout, 0.4-mm Pitch (Top View) The following I/O pins marked in Figure 7-2 in bold have high-drive capabilities: • • • • • • Pin 10, DIO_5 Pin 11, DIO_6 Pin 12, DIO_7 Pin 18, JTAG_TMSC Pin 20, DIO_10 Pin 21, DIO_11 The following I/O pins marked in Figure 7-2 in italics have analog capabilities: • • • • • • • • Pin 28, DIO_15 Pin 29, DIO_16 Pin 30, DIO_17 Pin 31, DIO_18 Pin 32, DIO_19 Pin 33, DIO_20 Pin 34, DIO_21 Pin 35, DIO_22 7.4 Signal Descriptions – RKP Package Table 7-2. Signal Descriptions – RKP Package PIN NAME NO. I/O TYPE DESCRIPTION DCDC_SW 25 — Power Output from internal DC/DC converter(1) DCOUPL 17 — Power For decoupling of internal 1.27 V regulated digital-supply (2) DIO_5 10 I/O Digital GPIO, high-drive capability DIO_6 11 I/O Digital GPIO, high-drive capability DIO_7 12 I/O Digital GPIO, high-drive capability Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 9 CC2651P3 www.ti.com SWRS257 – MARCH 2022 Table 7-2. Signal Descriptions – RKP Package (continued) PIN I/O TYPE 14 I/O Digital GPIO 15 I/O Digital GPIO DIO_10 20 I/O Digital GPIO, JTAG_TDO, high-drive capability DIO_11 21 I/O Digital GPIO, JTAG_TDI, high-drive capability DIO_12 22 I/O Digital GPIO DIO_13 23 I/O Digital GPIO DIO_14 24 I/O Digital GPIO DIO_15 28 I/O Digital GPIO, analog capability DIO_16 29 I/O Digital GPIO, analog capability DIO_17 30 I/O Digital GPIO, analog capability DIO_18 31 I/O Digital GPIO, analog capability DIO_19 32 I/O Digital GPIO, analog capability DIO_20 33 I/O Digital GPIO, analog capability DIO_21 34 I/O Digital GPIO, analog capability DIO_22 35 I/O Digital GPIO, analog capability EGP — — GND Ground – exposed ground pad(3) JTAG_TSMC 18 I/O Digital JTAG TMSC, high-drive capability JTAG_TCKC 19 I Digital JTAG TCKC RESET_N 27 I Digital Reset, active low. No internal pullup resistor RF_P 1 — RF Positive RF input signal to LNA during RX Positive RF output signal from PA during TX RF_N 2 — RF Negative RF input signal to LNA during RX Negative RF output signal from PA during TX RX_TX 7 — RF Optional bias pin for the RF LNA TX_20DBM_P 5 — RF Positive high-power TX signal TX_20DBM_N 6 — RF Negative high-power TX signal VDDR 37 — Power Internal supply, must be powered from the internal DC/DC converter or the internal LDO(2) (4) (6) VDDR_RF 40 — Power Internal supply, must be powered from the internal DC/DC converter or the internal LDO(2) (5) (6) VDDS 36 — Power 1.8-V to 3.8-V main chip supply(1) VDDS2 13 — Power 1.8-V to 3.8-V DIO supply(1) VDDS3 16 — Power 1.8-V to 3.8-V DIO supply(1) VDDS_DCDC 26 — Power 1.8-V to 3.8-V DC/DC converter supply X48M_N 38 — Analog 48-MHz crystal oscillator pin 1 X48M_P 39 — Analog 48-MHz crystal oscillator pin 2 X32K_Q1 8 — Analog 32-kHz crystal oscillator pin 1 X32K_Q2 9 — Analog 32-kHz crystal oscillator pin 2 NAME NO. DIO_8 DIO_9 (1) (2) (3) (4) (5) (6) 10 DESCRIPTION For more details, see the device technical reference manual listed in Section 11.3. Do not supply external circuitry from this pin. EGP is the only ground connection for the device. Good electrical connection to device ground on printed circuit board (PCB) is imperative for proper device operation. If internal DC/DC converter is not used, this pin is supplied internally from the main LDO. If internal DC/DC converter is not used, this pin must be connected to VDDR for supply from the main LDO. Output from internal DC/DC and LDO is trimmed to 1.68 V. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 7.5 Connections for Unused Pins and Modules Table 7-3. Connections for Unused Pins – RGZ Package FUNCTION GPIO 32.768-kHz crystal No Connects DC/DC converter(2) (1) (2) SIGNAL NAME DIO_n PIN NUMBER ACCEPTABLE PRACTICE(1) PREFERRED PRACTICE(1) 10–12 14–21 26–32 36–43 NC or GND NC NC or GND NC X32K_Q1 8 X32K_Q2 9 NC 3–4 NC NC DCDC_SW 33 NC NC VDDS_DCDC 34 VDDS VDDS NC = No connect When the DC/DC converter is not used, the inductor between DCDC_SW and VDDR can be removed. VDDR and VDDR_RF must still be connected and the 22 uF DCDC capacitor must be kept on the VDDR net. Table 7-4. Connection for Unused Pins and Modules – RKP Package FUNCTION GPIO 32.768-kHz crystal No Connects DC/DC converter SIGNAL NAME DIO_n PIN NUMBER ACCEPTABLE PRACTICE PREFERRED PRACTICE 10-12 14-15 20-24 28-35 NC or GND NC NC or GND NC X32K_Q1 3 X32K_Q2 4 NC 3–4 NC NC DCDC_SW 25 NC NC VDDS_DCDC 26 VDDS VDDS Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 11 CC2651P3 www.ti.com SWRS257 – MARCH 2022 8 Specifications 8.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) (2) VDDS(3) (6) MIN MAX –0.3 4.1 V –0.3 VDDS + 0.3, max 4.1 V –0.3 VDDR + 0.3, max 2.25 V Voltage scaling enabled –0.3 VDDS Voltage scaling disabled, internal reference –0.3 1.49 Voltage scaling disabled, VDDS as reference –0.3 VDDS / 2.9 Supply voltage Voltage on any digital pin(4) (5) Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2, X48M_N and X48M_P Vin Voltage on ADC input Input level, RF pins (RF_P and RF_N) Tstg (1) (2) (3) (4) (5) (6) 5 Storage temperature –40 UNIT V dBm 150 °C Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime All voltage values are with respect to ground, unless otherwise noted. VDDS_DCDC, VDDS2 and VDDS3 must be at the same potential as VDDS. Including analog capable DIOs. Injection current is not supported on any GPIO pin Connect VDDR to the external PA bias voltage for +10dBm and VDDS to the external PA bias voltage for +14dBm to +20dBm 8.2 ESD Ratings VESD (1) (2) Electrostatic discharge VALUE UNIT Human body model (HBM), per ANSI/ESDA/JEDEC JS001(1) All pins ±2000 V Charged device model (CDM), per JESD22-C101(2) All pins ±500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 8.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Operating ambient temperature(1) (2) –40 105 °C Operating junction temperature(1) (2) –40 115 °C Operating supply voltage (VDDS) 1.8 3.8 V Rising supply voltage slew rate 0 100 mV/µs Falling supply voltage slew rate(3) 0 20 mV/µs (1) (2) (3) Operation at or near maximum operating temperature for extended durations will result in lifetime reduction. For thermal resistance characteristics refer to Section 8.8. For small coin-cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor must be used to ensure compliance with this slew rate. 8.4 Power Supply and Modules over operating free-air temperature range (unless otherwise noted) PARAMETER MIN VDDS Power-on-Reset (POR) threshold TYP MAX UNIT 1.1 - 1.55 V VDDS Brown-out Detector (BOD) Rising threshold 1.77 V VDDS Brown-out Detector (BOD), before initial boot (1) Rising threshold 1.70 V VDDS Brown-out Detector (BOD) Falling threshold 1.75 V (1) 12 Brown-out Detector is trimmed at initial boot, value is kept until device is reset by a POR reset or the RESET_N pin Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 8.5 Power Consumption - Power Modes When measured on the CC26x1-P3EM-XD24-PA24 reference design with Tc = 25 °C, VDDS = 3.0 V with DC/DC enabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Core Current Consumption Reset. RESET_N pin asserted or VDDS below power-on-reset threshold 150 Shutdown. No clocks running, no retention 100 RTC running, CPU, 32KB RAM and (partial) register retention. RCOSC_LF 0.8 µA RTC running, CPU, 32KB RAM and (partial) register retention XOSC_LF 0.9 µA RTC running, CPU, 32KB RAM and (partial) register retention. RCOSC_LF 2.4 µA RTC running, CPU, 32KB RAM and (partial) register retention. XOSC_LF 2.6 µA Idle Supply Systems and RAM powered RCOSC_HF 650 µA Active MCU running CoreMark at 48 MHz RCOSC_HF 2.91 mA Delta current with domain enabled 56.0 Serial power domain Delta current with domain enabled 5.0 Reset and Shutdown Standby without cache retention Icore Standby with cache retention nA Peripheral Current Consumption Peripheral power domain Iperi (1) RF Core Delta current with power domain enabled, clock enabled, RF core idle 144 µDMA Delta current with clock enabled, module is idle 68.6 Timers Delta current with clock enabled, module is idle(1) 102 I2C Delta current with clock enabled, module is idle 12.1 I2S Delta current with clock enabled, module is idle 30.8 SSI Delta current with clock enabled, module is idle 71.7 UART Delta current with clock enabled, module is idle 147 CRYPTO (AES) Delta current with clock enabled, module is idle 28.1 TRNG Delta current with clock enabled, module is idle 27.1 µA Only one GPTimer running Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 13 CC2651P3 www.ti.com SWRS257 – MARCH 2022 8.6 Power Consumption - Radio Modes When measured on the CC26x1-P3EM-XD24-PA24 reference design with Tc = 25 °C, VDDS = 3.0 V with DC/DC enabled unless otherwise noted. High-power PA connected to VDDS unless otherwise noted. PARAMETER TEST CONDITIONS Radio receive current Radio transmit current 2.4 GHz PA (Bluetooth Low Energy) TYP MAX UNIT 6.4 mA 0 dBm output power setting 2440 MHz 7.1 mA +5 dBm output power setting 2440 MHz 9.5 mA 101 mA 22 mA setting(1) Radio transmit current High-power PA +20 dBm output power 2440 MHz. VDDS = 3.3 V Radio transmit current High-power PA, 10 dBm configuration(2) +10 dBm output power setting 2440 MHz VDDR = 1.67 V (1) (2) MIN 2440 MHz +20 dBm is only available on the RGZ (7x7) package Measured on evaluation board as described in https://www.ti.com/lit/pdf/swra636. 8.7 Nonvolatile (Flash) Memory Characteristics Over operating free-air temperature range and VDDS = 3.0 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Flash sector size TYP MAX 8 UNIT KB Supported flash erase cycles before failure, full bank(1) (5) 30 k Cycles Supported flash erase cycles before failure, single sector(2) 60 k Cycles Maximum number of write operations per row before sector erase(3) 83 Flash retention 105 °C Flash sector erase current Average delta current 9.7 Zero cycles 10 Flash sector erase time(4) 11.4 Average delta current, 4 bytes at a time 4 bytes at a time (3) (4) (5) mA ms 4000 Flash write time(4) (1) (2) Years 30k cycles Flash write current Write Operations ms 5.3 mA 21.6 µs A full bank erase is counted as a single erase cycle on each sector. Up to 4 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k cycles Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum per write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum number of write operations per row is reached. This number is dependent on Flash aging and increases over time and erase cycles Aborting flash during erase or program modes is not a safe operation. 8.8 Thermal Resistance Characteristics PACKAGE THERMAL METRIC(1) RGZ (VQFN) RKP (VQFN) UNIT 48 PINS 40 PINS RθJA Junction-to-ambient thermal resistance 25.0 30.9 °C/W(2) RθJC(top) Junction-to-case (top) thermal resistance 14.5 20.2 °C/W(2) RθJB Junction-to-board thermal resistance 8.7 10.3 °C/W(2) ψJT Junction-to-top characterization parameter 0.2 0.2 °C/W(2) ψJB Junction-to-board characterization parameter 8.6 10.3 °C/W(2) RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 2.1 °C/W(2) (1) (2) 14 For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. °C/W = degrees Celsius per watt. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 8.9 RF Frequency Bands Over operating free-air temperature range (unless otherwise noted). PARAMETER MIN Frequency bands 2360 TYP MAX UNIT 2500 MHz Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 15 CC2651P3 www.ti.com SWRS257 – MARCH 2022 8.10 Bluetooth Low Energy - Receive (RX) Measured on the CC26x1-P3EM-7XD24-PA24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with DC/DC enabled and high power PA connected to VDDS unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is measured at a dedicated antenna connection. All measurements are performed conducted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 125 kbps (LE Coded) Receiver sensitivity Differential mode. BER = 10–3 –104 dBm Receiver sensitivity Single ended mode. Measured on CC26x1P3EM-5XS24, at the SMA connector, BER = 10–3 –104 dBm Receiver saturation Differential mode. BER = 10–3 >5 dBm Frequency error tolerance Difference between the incoming carrier frequency and the internally generated carrier frequency > (–300 / 300) kHz Data rate error tolerance Difference between incoming data rate and the internally generated data rate (37-byte packets) > (–320 / 240) ppm Data rate error tolerance Difference between incoming data rate and the internally generated data rate (255-byte packets) > (–125 / 125) ppm Co-channel rejection(1) Wanted signal at –79 dBm, modulated interferer in channel, BER = 10–3 Selectivity, ±1 MHz(1) –1.5 dB Wanted signal at –79 dBm, modulated interferer at ±1 MHz, BER = 10–3 8 / 4.5(2) dB Selectivity, ±2 MHz(1) Wanted signal at –79 dBm, modulated interferer at ±2 MHz, BER = 10–3 44 / 39(2) dB Selectivity, ±3 MHz(1) Wanted signal at –79 dBm, modulated interferer at ±3 MHz, BER = 10–3 46 / 44(2) dB Selectivity, ±4 MHz(1) Wanted signal at –79 dBm, modulated interferer at ±4 MHz, BER = 10–3 44 / 46(2) dB Selectivity, ±6 MHz(1) Wanted signal at –79 dBm, modulated interferer at ≥ ±6 MHz, BER = 10–3 48 / 44(2) dB Selectivity, ±7 MHz Wanted signal at –79 dBm, modulated interferer at ≥ ±7 MHz, BER = 10–3 51 / 45(2) dB Selectivity, Image frequency(1) Wanted signal at –79 dBm, modulated interferer at image frequency, BER = 10–3 39 dB Selectivity, Image frequency ±1 MHz(1) Note that Image frequency + 1 MHz is the Co- channel –1 MHz. Wanted signal at –79 dBm, modulated interferer at ±1 MHz from image frequency, BER = 10–3 4.5 / 44 (2) dB 500 kbps (LE Coded) Receiver sensitivity Differential mode. BER = 10–3 –100 dBm Receiver sensitivity Single ended mode. Measured on CC26x1P3EM-5XS24, at the SMA connector, BER = 10–3 –100 dBm 10–3 Receiver saturation Differential mode. BER = >5 dBm Frequency error tolerance Difference between the incoming carrier frequency and the internally generated carrier frequency > (–300 / 300) kHz Data rate error tolerance Difference between incoming data rate and the internally generated data rate (37-byte packets) > (–450 / 450) ppm Data rate error tolerance Difference between incoming data rate and the internally generated data rate (255-byte packets) > (–175 / 175) ppm Co-channel rejection(1) Wanted signal at –72 dBm, modulated interferer in channel, BER = 10–3 Selectivity, ±1 MHz(1) –3.5 dB Wanted signal at –72 dBm, modulated interferer at ±1 MHz, BER = 10–3 8 / 4(2) dB Selectivity, ±2 MHz(1) Wanted signal at –72 dBm, modulated interferer at ±2 MHz, BER = 10–3 44 / 37(2) dB Selectivity, ±3 MHz(1) Wanted signal at –72 dBm, modulated interferer at ±3 MHz, BER = 10–3 46 / 46(2) dB Selectivity, ±4 MHz(1) Wanted signal at –72 dBm, modulated interferer at ±4 MHz, BER = 10–3 45 / 47(2) dB Selectivity, ±6 MHz(1) Wanted signal at –72 dBm, modulated interferer at ≥ ±6 MHz, BER = 10–3 46 / 45(2) dB 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 8.10 Bluetooth Low Energy - Receive (RX) (continued) Measured on the CC26x1-P3EM-7XD24-PA24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with DC/DC enabled and high power PA connected to VDDS unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is measured at a dedicated antenna connection. All measurements are performed conducted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Selectivity, ±7 MHz Wanted signal at –72 dBm, modulated interferer at ≥ ±7 MHz, BER = 10–3 Selectivity, Image frequency(1) Wanted signal at –72 dBm, modulated interferer at image frequency, BER = 10–3 37 dB Selectivity, Image frequency ±1 MHz(1) Note that Image frequency + 1 MHz is the Co- channel –1 MHz. Wanted signal at –72 dBm, modulated interferer at ±1 MHz from image frequency, BER = 10–3 4 / 46(2) dB 49 / 45(2) dB 1 Mbps (LE 1M) Receiver sensitivity Differential mode. BER = 10–3 –97 dBm Receiver sensitivity Single ended mode. Measured on CC26x1P3EM-5XS24, at the SMA connector, BER = 10–3 –97 dBm Receiver saturation Differential mode. BER = 10–3 >5 dBm Frequency error tolerance Difference between the incoming carrier frequency and the internally generated carrier frequency > (–350 / 350) kHz Data rate error tolerance Difference between incoming data rate and the internally generated data rate (37-byte packets) > (–750 / 750) ppm Co-channel rejection(1) Wanted signal at –67 dBm, modulated interferer in channel, BER = 10–3 Selectivity, ±1 MHz(1) –6 dB Wanted signal at –67 dBm, modulated interferer at ±1 MHz, BER = 10–3 7 / 4(2) dB Selectivity, ±2 MHz(1) Wanted signal at –67 dBm, modulated interferer at ±2 MHz,BER = 10–3 40 / 33(2) dB Selectivity, ±3 MHz(1) Wanted signal at –67 dBm, modulated interferer at ±3 MHz, BER = 10–3 36 / 41(2) dB Selectivity, ±4 MHz(1) Wanted signal at –67 dBm, modulated interferer at ±4 MHz, BER = 10–3 37 / 45(2) dB Selectivity, ±5 MHz or more(1) Wanted signal at –67 dBm, modulated interferer at ≥ ±5 MHz, BER = 10–3 40 dB Selectivity, image frequency(1) Wanted signal at –67 dBm, modulated interferer at image frequency, BER = 10–3 33 dB Selectivity, image frequency ±1 MHz(1) Note that Image frequency + 1 MHz is the Co- channel –1 MHz. Wanted signal at –67 dBm, modulated interferer at ±1 MHz from image frequency, BER = 10–3 4 / 41(2) dB Out-of-band blocking(3) 30 MHz to 2000 MHz –10 dBm Out-of-band blocking 2003 MHz to 2399 MHz –18 dBm Out-of-band blocking 2484 MHz to 2997 MHz –12 dBm Out-of-band blocking 3000 MHz to 12.75 GHz –2 dBm Intermodulation Wanted signal at 2402 MHz, –64 dBm. Two interferers at 2405 and 2408 MHz respectively, at the given power level –42 dBm Spurious emissions, 30 to 1000 MHz Measurement in a 50-Ω single-ended load. < –59 dBm Spurious emissions, 1 to 12.75 GHz Measurement in a 50-Ω single-ended load. < –47 dBm RSSI dynamic range 70 dB RSSI accuracy ±4 dB 2 Mbps (LE 2M) Receiver sensitivity Differential mode. Measured at SMA connector, BER = 10–3 –92 dBm Receiver sensitivity Single ended mode. Measured on CC26x1P3EM-5XS24, at the SMA connector, BER = 10–3 –92 dBm Receiver saturation Differential mode. Measured at SMA connector, BER = 10–3 >5 dBm Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 17 CC2651P3 www.ti.com SWRS257 – MARCH 2022 8.10 Bluetooth Low Energy - Receive (RX) (continued) Measured on the CC26x1-P3EM-7XD24-PA24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with DC/DC enabled and high power PA connected to VDDS unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is measured at a dedicated antenna connection. All measurements are performed conducted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency error tolerance Difference between the incoming carrier frequency and the internally generated carrier frequency > (–500 / 500) kHz Data rate error tolerance Difference between incoming data rate and the internally generated data rate (37-byte packets) > (–700 / 750) ppm Co-channel rejection(1) Wanted signal at –67 dBm, modulated interferer in channel,BER = 10–3 Selectivity, ±2 MHz(1) –7 dB Wanted signal at –67 dBm, modulated interferer at ±2 MHz, Image frequency is at –2 MHz, BER = 10–3 8 / 4(2) dB Selectivity, ±4 MHz(1) Wanted signal at –67 dBm, modulated interferer at ±4 MHz, BER = 10–3 36 / 31(2) dB Selectivity, ±6 MHz(1) Wanted signal at –67 dBm, modulated interferer at ±6 MHz, BER = 10–3 37 / 36(2) dB Selectivity, image frequency(1) Wanted signal at –67 dBm, modulated interferer at image frequency, BER = 10–3 4 dB Selectivity, image frequency ±2 MHz(1) Note that Image frequency + 2 MHz is the Co-channel. Wanted signal at –67 dBm, modulated interferer at ±2 MHz from image frequency, BER = 10–3 –7 / 36(2) dB Out-of-band blocking(3) 30 MHz to 2000 MHz –16 dBm Out-of-band blocking 2003 MHz to 2399 MHz –21 dBm Out-of-band blocking 2484 MHz to 2997 MHz –15 dBm Out-of-band blocking 3000 MHz to 12.75 GHz –12 dBm Intermodulation Wanted signal at 2402 MHz, –64 dBm. Two interferers at 2408 and 2414 MHz respectively, at the given power level –38 dBm (1) (2) (3) 18 Numbers given as I/C dB X / Y, where X is +N MHz and Y is –N MHz Excluding one exception at Fwanted / 2, per Bluetooth Specification Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 8.11 Bluetooth Low Energy - Transmit (TX) Measured on the CC26x1-P3EM-7XD24-PA24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with DC/DC enabled and high power PA connected to VDDS unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is measured at a dedicated antenna connection. All measurements are performed conducted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT General Parameters Max output power, high power PA Differential mode, delivered to a single-ended 50 Ω load through a balun 20 dBm Output power programmable range high power PA Differential mode, delivered to a single-ended 50 Ω load through a balun 6 dB Max output power, high power PA, 10 dBm configuration(3) Differential mode, delivered to a single-ended 50 Ω load through a balun 10.5 dBm Max output power, high power PA, 10 dBm configuration(3) Single-ended mode. Measured on CC26x1-P3EM-5XS24, delivered to a single-ended 50 Ω load through a balun 9 dBm Output power programmable range high power PA, 10 dBm configuration(3) Differential mode, delivered to a single-ended 50 Ω load through a balun 5 dB Max output power, regular PA Differential mode, delivered to a single-ended 50 Ω load through a balun 5 dBm Max output power, regular PA Single-ended mode. Measured on CC26x1-P3EM-5XS24, delivered to a single-ended 50 Ω load through a balun 3 dBm Output power programmable range, regular PA Differential mode, delivered to a single-ended 50 Ω load through a balun 26 dB Spurious emissions and harmonics Spurious emissions, high-power PA(1) f < 1 GHz, outside restricted bands < -36 dBm f < 1 GHz, restricted bands FCC < -55 dBm -37 dBm -35 dBm f > 1 GHz, including harmonics Harmonics, high-power PA(2) +20 dBm setting Second harmonic Third harmonic -42 dBm < -36 dBm < -54 dBm < -55 dBm -41 dBm Second harmonic < -42 dBm Third harmonic < -42 dBm f < 1 GHz, outside restricted bands < –36 dBm f < 1 GHz, restricted bands ETSI < –54 dBm f < 1 GHz, restricted bands FCC < –55 dBm f < 1 GHz, outside restricted bands Spurious emissions, f < 1 GHz, restricted bands ETSI high-power PA, 10 (1) (3) f < 1 GHz, restricted bands FCC dBm configuration f > 1 GHz, including harmonics Harmonics, high-power PA, 10 dBm configuration(3) Spurious emissions, regular PA f > 1 GHz, including harmonics Harmonics, regular PA (1) (2) (3) +10 dBm setting(3) +5 dBm setting < –42 dBm Second harmonic < –42 dBm Third harmonic < –42 dBm To ensure margins for passing FCC band edge requirements at 2483.5 MHz, a lower than maximum output-power setting or less than 100% duty cycle may be used when operating at the upper Bluetooth Low Energy channel(s). To ensure margins for passing FCC requirements for harmonic emission, duty cycling may be required. The CC2651P3 LaunchPad reference design should also be reviewed as the filter provides higher attenuation of harmonics compared to the CC26x1-P3EM-XD24PA24 reference design. Measured on evaluation board as described in www.ti.com/lit/pdf/swra636. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 19 CC2651P3 www.ti.com SWRS257 – MARCH 2022 8.12 Zigbee - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - RX Measured on the CC26x1-P3EM-7XD24-PA24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with DC/DC enabled and high power PA connected to VDDS unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is measured at a dedicated antenna connection. All measurements are performed conducted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT General Parameters Receiver sensitivity Differential mode PER = 1% –100 dBm Receiver sensitivity Single-Ended mode. Measured on CC26x1-P3EM-5XS24 at the SMA connector. PER = 1% -99 dBm Receiver saturation PER = 1% >5 dBm Adjacent channel rejection Wanted signal at –82 dBm, modulated interferer at ±5 MHz, PER = 1% 36 dB Alternate channel rejection Wanted signal at –82 dBm, modulated interferer at ±10 MHz, PER = 1% 57 dB Channel rejection, ±15 MHz or more Wanted signal at –82 dBm, undesired signal is IEEE 802.15.4 modulated channel, stepped through all channels 2405 to 2480 MHz, PER = 1% 59 dB Blocking and desensitization, 5 MHz from upper band edge Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 57 dB Blocking and desensitization, 10 MHz from upper band edge Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 63 dB Blocking and desensitization, 20 MHz from upper band edge Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 63 dB Blocking and desensitization, 50 MHz from upper band edge Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 66 dB Blocking and desensitization, –5 MHz from lower band edge Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 60 dB Blocking and desensitization, –10 MHz from lower band edge Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 60 dB Blocking and desensitization, –20 MHz from lower band edge Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 63 dB Blocking and desensitization, –50 MHz from lower band edge Wanted signal at –97 dBm (3 dB above the sensitivity level), CW jammer, PER = 1% 65 dB Spurious emissions, 30 MHz to 1000 MHz Measurement in a 50-Ω single-ended load(1) –66 dBm Spurious emissions, 1 GHz to 12.75 GHz Measurement in a 50-Ω single-ended load(1) –53 dBm Frequency error tolerance Difference between the incoming carrier frequency and the internally generated carrier frequency > 350 ppm Symbol rate error tolerance Difference between incoming symbol rate and the internally generated symbol rate > 1000 ppm RSSI dynamic range 95 dB RSSI accuracy ±4 dB (1) 20 Suitable for systems targeting compliance with EN 300 328, EN 300 440 class 2, FCC CFR47, Part 15 and ARIB STD-T-66 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 8.13 Zigbee - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - TX Measured on the CC26x1-P3EM-7XD24-PA24 reference design with Tc = 25 °C, VDDS = 3.0 V, fRF= 2440 MHz with DC/DC enabled and high power PA connected to VDDS unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is measured at a dedicated antenna connection. All measurements are performed conducted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT General Parameters Max output power, high power PA Differential mode, delivered to a single-ended 50-Ω load through a balun 20 dBm Output power programmable range, high power PA Differential mode, delivered to a single-ended 50-Ω load through a balun 6 dB Max output power, high power PA, 10 dBm configuration(4) Differential mode, delivered to a single-ended 50-Ω load through a balun 10.5 dBm Max output power, high power PA, 10 dBm configuration(4) Single-ended mode. Measured on CC26x1-P3EM-5XS24, delivered to a single-ended 50Ω load through a balun 9 dBm Output power programmable range, high power PA, 10 dBm configuration(4) Differential mode, delivered to a single-ended 50-Ω load through a balun 5 dB Max output power, regular PA Differential mode, delivered to a single-ended 50-Ω load through a balun 5 dBm Output power programmable range, regular PA Differential mode, delivered to a single-ended 50-Ω load through a balun 26 dB Spurious emissions and harmonics Spurious emissions, high-power PA(2) f < 1 GHz, outside restricted bands < -39 dBm < -49 dBm -40 dBm Second harmonic -35 dBm Third harmonic -42 dBm f < 1 GHz, outside restricted bands < -36 dBm f < 1 GHz, restricted bands ETSI < -47 dBm f < 1 GHz, restricted bands FCC < -55 dBm -42 dBm Second harmonic < -42 dBm Third harmonic < -42 dBm f < 1 GHz, outside restricted bands < -36 dBm f < 1 GHz, restricted bands ETSI < -47 dBm f < 1 GHz, restricted bands FCC < -55 dBm f > 1 GHz, including harmonics < –42 dBm Second harmonic < -42 dBm Third harmonic < -42 dBm f < 1 GHz, restricted bands FCC f > 1 GHz, including harmonics Harmonics, high-power PA(3) Spurious emissions, high-power PA, 10 dBm configuration(2) (4) +20 dBm setting +10 dBm setting(4) f > 1 GHz, including harmonics Harmonics, high-power PA, 10 dBm configuration(4) Spurious emissions, regular PA (1) Harmonics, regular PA +5 dBm setting IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) Error vector magnitude, high power PA +20 dBm setting 2 % Error vector magnitude, high power PA, 10 dBm configuration(4) +10 dBm setting 2 % Error vector magnitude Regular PA +5 dBm setting 2 % (1) To ensure margins for passing FCC band edge requirements at 2483.5 MHz, a lower than maximum output-power setting or less than 100% duty cycle may be used when operating at 2480 MHz. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 21 CC2651P3 www.ti.com SWRS257 – MARCH 2022 (2) (3) (4) To ensure margins for passing FCC band edge requirements at 2483.5 MHz, a lower than maximum output-power setting or less than 100% duty cycle may be used when operating at the upper 802.15.4 channel(s). To ensure margins for passing FCC requirements for harmonic emission, duty cycling may be required. The CC2651P3 LaunchPad reference design should also be reviewed as the filter provides higher attenuation of harmonics compared to the CC26x1P3EM-7XD24-PA24 reference design. Measured on evaluation board as described in https://www.ti.com/lit/pdf/swra636. 8.14 Timing and Switching Characteristics 8.14.1 Reset Timing PARAMETER MIN RESET_N low duration TYP MAX UNIT 1 µs 8.14.2 Wakeup Timing Measured over operating free-air temperature with VDDS = 3.0 V (unless otherwise noted). The times listed here do not include software overhead. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT MCU, Reset to Active(1) 850 - 4000 µs MCU, Shutdown to Active(1) 850 - 4000 µs MCU, Standby to Active 160 µs MCU, Active to Standby 36 µs MCU, Idle to Active 14 µs (1) The wakeup time is dependent on remaining charge on VDDR capacitor when starting the device, and thus how long the device has been in Reset or Shutdown before starting up again. The wake up time increases with a higher capacitor value. 8.14.3 Clock Specifications 8.14.3.1 48 MHz Crystal Oscillator (XOSC_HF) Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted.(1) PARAMETER MIN TYP Crystal frequency 48 ESR Equivalent series resistance 6 pF < CL ≤ 9 pF 20 ESR Equivalent series resistance 5 pF < CL ≤ 6 pF LM Motional inductance, relates to the load capacitance that is used for the crystal (CL in Farads)(5) CL Crystal load capacitance(4) Start-up (1) (2) (3) (4) (5) MAX MHz 60 Ω 80 Ω < 3 × 10–25 / CL 2 H 7(3) 5 time(2) UNIT 9 200 pF µs Probing or otherwise stopping the crystal while the DC/DC converter is enabled may cause permanent damage to the device. Start-up time using the TI-provided power driver. Start-up time may increase if driver is not used. On-chip default connected capacitance including reference design parasitic capacitance. Connected internal capacitance is changed through software in the Customer Configuration section (CCFG). Adjustable load capacitance is integrated into the device. External load capacitors are required for systems targeting compliance with certain regulations. See the device errata for further details. The crystal manufacturer's specification must satisfy this requirement for proper operation. 8.14.3.2 48 MHz RC Oscillator (RCOSC_HF) Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted. MIN TYP MAX UNIT Frequency 48 MHz Uncalibrated frequency accuracy ±1 % Calibrated frequency accuracy(1) ±0.25 % 5 µs Start-up time (1) 22 Accuracy relative to the calibration source (XOSC_HF) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 8.14.3.3 32.768 kHz Crystal Oscillator (XOSC_LF) Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted. MIN TYP Crystal frequency ESR Equivalent series resistance CL Crystal load capacitance (1) MAX UNIT 32.768 6 kHz 30 100 kΩ 7(1) 12 pF Default load capacitance using TI reference designs including parasitic capacitance. Crystals with different load capacitance may be used. 8.14.3.4 32 kHz RC Oscillator (RCOSC_LF) Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted. MIN TYP Calibrated frequency Calibrated RTC variation(1) Calibrated periodically against XOSC_HF(2) Temperature coefficient. (1) MAX UNIT 32.8 kHz ±600(3) ppm 50 ppm/°C When using RCOSC_LF as source for the low frequency system clock (SCLK_LF), the accuracy of the SCLK_LF-derived Real Time Clock (RTC) can be improved by measuring RCOSC_LF relative to XOSC_HF and compensating for the RTC tick speed. This functionality is available through the TI-provided Power driver. TI driver software calibrates the RTC every time XOSC_HF is enabled. Some device's variation can exceed 1000 ppm. Further calibration will not improve variation. (2) (3) 8.14.4 Synchronous Serial Interface (SSI) Characteristics 8.14.4.1 Synchronous Serial Interface (SSI) Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER NO. PARAMETER MIN TYP UNIT 65024 System Clocks (2) S1 tclk_per SSIClk cycle time S2(1) tclk_high SSIClk high time 0.5 tclk_per S3(1) tclk_low SSIClk low time 0.5 tclk_per (1) (2) 12 MAX Refer to SSI timing diagrams Figure 8-1, Figure 8-2, and Figure 8-3. When using the TI-provided Power driver, the SSI system clock is always 48 MHz. S1 S2 SSIClk S3 SSIFss SSITx SSIRx MSB LSB 4 to 16 bits Figure 8-1. SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 23 CC2651P3 www.ti.com SWRS257 – MARCH 2022 S2 S1 SSIClk S3 SSIFss SSITx MSB LSB 8-bit control SSIRx 0 MSB LSB 4 to 16 bits output data Figure 8-2. SSI Timing for MICROWIRE Frame Format (FRF = 10), Single Transfer S1 S2 SSIClk (SPO = 0) S3 SSIClk (SPO = 1) SSITx (Master) MSB SSIRx (Slave) MSB LSB LSB SSIFss Figure 8-3. SSI Timing for SPI Frame Format (FRF = 00), With SPH = 1 8.14.5 UART 8.14.5.1 UART Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER MIN UART rate 24 TYP MAX 3 Submit Document Feedback UNIT MBaud Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 8.15 Peripheral Characteristics 8.15.1 ADC 8.15.1.1 Analog-to-Digital Converter (ADC) Characteristics Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1) Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers. PARAMETER TEST CONDITIONS Input voltage range MIN TYP 0 Resolution ksps –0.24 LSB Gain error Internal 4.3 V equivalent reference(2) 7.14 LSB >–1 LSB ±4 LSB INL Integral nonlinearity Internal 4.3 V equivalent reference(2), 200 kSamples/s, 9.6 kHz input tone reference(2), Internal 4.3 V equivalent 9.6 kHz input tone, DC/DC enabled SFDR Bits 200 Internal 4.3 V equivalent reference(2) Differential nonlinearity SINAD, SNDR V Offset DNL(4) THD UNIT 12 Sample Rate ENOB MAX VDDS Effective number of bits Total harmonic distortion Signal-to-noise and distortion ratio Spurious-free dynamic range 200 kSamples/s, 9.8 9.8 VDDS as reference, 200 kSamples/s, 9.6 kHz input tone 10.1 Internal reference, voltage scaling disabled, 32 samples average (software), 200 kSamples/s, 300 Hz input tone 11.1 Internal reference, voltage scaling disabled, 14-bit mode, 200 kSamples/s, 300 Hz input tone (5) 11.3 Internal reference, voltage scaling disabled, 15-bit mode, 200 kSamples/s, 300 Hz input tone (5) 11.6 Internal 4.3 V equivalent reference(2), 200 kSamples/s, 9.6 kHz input tone –65 VDDS as reference, 200 kSamples/s, 9.6 kHz input tone –70 Internal reference, voltage scaling disabled, 32 samples average, 200 kSamples/s, 300 Hz input tone –72 Internal 4.3 V equivalent reference(2), 200 kSamples/s, 9.6 kHz input tone 60 VDDS as reference, 200 kSamples/s, 9.6 kHz input tone 63 Internal reference, voltage scaling disabled, 32 samples average (software), 200 kSamples/s, 300 Hz input tone 68 Internal 4.3 V equivalent reference(2), 200 kSamples/s, 9.6 kHz input tone 70 VDDS as reference, 200 kSamples/s, 9.6 kHz input tone 73 Internal reference, voltage scaling disabled, 32 samples average (software), 200 kSamples/s, 300 Hz input tone 75 dB dB dB Conversion time Serial conversion, time-to-output, 24 MHz clock Current consumption Internal 4.3 V equivalent reference(2) 0.39 mA Current consumption VDDS as reference 0.56 mA Reference voltage Equivalent fixed internal reference (input voltage scaling enabled). For best accuracy, the ADC conversion should be initiated through the TI-RTOS API in order to include the gain/ offset compensation factors stored in FCFG1 Reference voltage Fixed internal reference (input voltage scaling disabled). For best accuracy, the ADC conversion should be initiated through the TI-RTOS API in order to include the gain/offset compensation factors stored in FCFG1. This value is derived from the scaled value (4.3 V) as follows: Vref = 4.3 V × 1408 / 4095 Reference voltage Reference voltage 50 Bits Clock Cycles 4.3(2) (3) V 1.48 V VDDS as reference, input voltage scaling enabled VDDS V VDDS as reference, input voltage scaling disabled VDDS / 2.82(3) V Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 25 CC2651P3 www.ti.com SWRS257 – MARCH 2022 8.15.1.1 Analog-to-Digital Converter (ADC) Characteristics (continued) Tc = 25 °C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1) Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers. PARAMETER Input impedance (1) (2) (3) (4) (5) TEST CONDITIONS MIN 200 kSamples/s, voltage scaling enabled. Capacitive input, Input impedance depends on sampling frequency and sampling time TYP MAX >1 UNIT MΩ Using IEEE Std 1241-2010 for terminology and test methods Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V Applied voltage must be within Absolute Maximum Ratings at all times No missing codes ADC_output = Σ(4n samples ) >> n, n = desired extra bits 8.15.2 DAC 8.15.2.1 Digital-to-Analog Converter (DAC) Characteristics Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT General Parameters Resolution VDDS FDAC Supply voltage Clock frequency Voltage output settling time 8 1.8 3.8 External Load(4), any VREF, pre-charge OFF, DAC charge-pump OFF 2.0 3.8 Any load, VREF = DCOUPL, pre-charge ON 2.6 3.8 Buffer ON (recommended for external load) 16 250 Buffer OFF (internal load) 16 1000 VREF = VDDS, buffer OFF, internal load VREF = VDDS, buffer ON, external capacitive load = 20 13 pF(3) 20 External resistive load 200 10 kHz pF MΩ Short circuit current 400 VDDS = 3.8 V, DAC charge-pump OFF 50.8 VDDS = 3.0 V, DAC charge-pump ON 51.7 VDDS = 3.0 V, DAC charge-pump OFF 53.2 Max output impedance Vref = VDDS, buffer ON, CLK 250 VDDS = 2.0 V, DAC charge-pump ON kHz VDDS = 2.0 V, DAC charge-pump OFF V 1 / FDAC 13.8 External capacitive load ZMAX Bits Any load, any VREF, pre-charge OFF, DAC charge-pump ON 48.7 µA kΩ 70.2 VDDS = 1.8 V, DAC charge-pump ON 46.3 VDDS = 1.8 V, DAC charge-pump OFF 88.9 Internal Load - Continuous Time Comparator / Low Power Clocked Comparator Differential nonlinearity VREF = VDDS, load = Continuous Time Comparator or Low Power Clocked Comparator FDAC = 250 kHz ±1 Differential nonlinearity VREF = VDDS, load = Continuous Time Comparator or Low Power Clocked Comparator FDAC = 16 kHz ±1.2 DNL Offset error(2) Load = Continuous Time Comparator 26 LSB(1) VREF = VDDS = 3.8 V ±0.64 VREF = VDDS= 3.0 V ±0.81 VREF = VDDS = 1.8 V ±1.27 VREF = DCOUPL, pre-charge ON ±3.43 VREF = DCOUPL, pre-charge OFF ±2.88 VREF = ADCREF ±2.37 Submit Document Feedback LSB(1) Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 8.15.2.1 Digital-to-Analog Converter (DAC) Characteristics (continued) Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted. PARAMETER Offset error(2) Load = Low Power Clocked Comparator Max code output voltage variation(2) Load = Continuous Time Comparator Max code output voltage variation(2) Load = Low Power Clocked Comparator Output voltage range(2) Load = Continuous Time Comparator Output voltage range(2) Load = Low Power Clocked Comparator TEST CONDITIONS MIN TYP VREF = VDDS= 3.8 V ±0.78 VREF = VDDS = 3.0 V ±0.77 VREF = VDDS= 1.8 V ±3.46 VREF = DCOUPL, pre-charge ON ±3.44 VREF = DCOUPL, pre-charge OFF ±4.70 VREF = ADCREF ±4.11 VREF = VDDS = 3.8 V ±1.53 VREF = VDDS = 3.0 V ±1.71 VREF = VDDS= 1.8 V ±2.10 VREF = DCOUPL, pre-charge ON ±6.00 VREF = DCOUPL, pre-charge OFF ±3.85 VREF = ADCREF ±5.84 VREF = VDDS= 3.8 V ±2.92 VREF =VDDS= 3.0 V ±3.06 VREF = VDDS= 1.8 V ±3.91 VREF = DCOUPL, pre-charge ON ±7.84 VREF = DCOUPL, pre-charge OFF ±4.06 VREF = ADCREF ±6.94 VREF = VDDS = 3.8 V, code 1 0.03 VREF = VDDS = 3.8 V, code 255 3.62 VREF = VDDS= 3.0 V, code 1 0.02 VREF = VDDS= 3.0 V, code 255 2.86 VREF = VDDS= 1.8 V, code 1 0.01 VREF = VDDS = 1.8 V, code 255 1.71 VREF = DCOUPL, pre-charge OFF, code 1 0.01 VREF = DCOUPL, pre-charge OFF, code 255 1.21 VREF = DCOUPL, pre-charge ON, code 1 1.27 VREF = DCOUPL, pre-charge ON, code 255 2.46 VREF = ADCREF, code 1 0.01 VREF = ADCREF, code 255 1.41 VREF = VDDS = 3.8 V, code 1 0.03 VREF = VDDS= 3.8 V, code 255 3.61 VREF = VDDS= 3.0 V, code 1 0.02 VREF = VDDS= 3.0 V, code 255 2.85 VREF = VDDS = 1.8 V, code 1 0.01 VREF = VDDS = 1.8 V, code 255 1.71 VREF = DCOUPL, pre-charge OFF, code 1 0.01 VREF = DCOUPL, pre-charge OFF, code 255 1.21 VREF = DCOUPL, pre-charge ON, code 1 1.27 VREF = DCOUPL, pre-charge ON, code 255 2.46 VREF = ADCREF, code 1 0.01 VREF = ADCREF, code 255 1.41 MAX UNIT LSB(1) LSB(1) LSB(1) V V External Load (Keysight 34401A Multimeter) INL Integral nonlinearity DNL Differential nonlinearity VREF = VDDS, FDAC = 250 kHz ±1 VREF = DCOUPL, FDAC = 250 kHz ±1 VREF = ADCREF, FDAC = 250 kHz ±1 VREF = VDDS, FDAC = 250 kHz ±1 LSB(1) LSB(1) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 27 CC2651P3 www.ti.com SWRS257 – MARCH 2022 8.15.2.1 Digital-to-Analog Converter (DAC) Characteristics (continued) Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted. PARAMETER Offset error Max code output voltage variation Output voltage range Load = Low Power Clocked Comparator (1) (2) (3) (4) 28 TEST CONDITIONS MIN TYP VREF = VDDS= 3.8 V ±0.20 VREF = VDDS= 3.0 V ±0.25 VREF = VDDS = 1.8 V ±0.45 VREF = DCOUPL, pre-charge ON ±1.55 VREF = DCOUPL, pre-charge OFF ±1.30 VREF = ADCREF ±1.10 VREF = VDDS= 3.8 V ±0.60 VREF = VDDS= 3.0 V ±0.55 VREF = VDDS= 1.8 V ±0.60 VREF = DCOUPL, pre-charge ON ±3.45 VREF = DCOUPL, pre-charge OFF ±2.10 VREF = ADCREF ±1.90 VREF = VDDS = 3.8 V, code 1 0.03 VREF = VDDS = 3.8 V, code 255 3.61 VREF = VDDS = 3.0 V, code 1 0.02 VREF = VDDS= 3.0 V, code 255 2.85 VREF = VDDS= 1.8 V, code 1 0.02 VREF = VDDS = 1.8 V, code 255 1.71 VREF = DCOUPL, pre-charge OFF, code 1 0.02 VREF = DCOUPL, pre-charge OFF, code 255 1.20 VREF = DCOUPL, pre-charge ON, code 1 1.27 VREF = DCOUPL, pre-charge ON, code 255 2.46 VREF = ADCREF, code 1 0.02 VREF = ADCREF, code 255 1.42 MAX UNIT LSB(1) LSB(1) V 1 LSB (VREF 3.8 V/3.0 V/1.8 V/DCOUPL/ADCREF) = 14.10 mV/11.13 mV/6.68 mV/4.67 mV/5.48 mV Includes comparator offset A load > 20 pF will increases the settling time Keysight 34401A Multimeter Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 8.15.3 Temperature and Battery Monitor 8.15.3.1 Temperature Sensor Measured on a Texas Instruments reference design with Tc = 25 °C, VDDS = 3.0 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP Resolution MAX UNIT 2 °C Accuracy -40 °C to 0 °C ±4.0 °C Accuracy 0 °C to 105 °C ±2.5 °C 3.9 °C/V Supply voltage (1) coefficient(1) The temperature sensor is automatically compensated for VDDS variation when using the TI-provided driver. 8.15.3.2 Battery Monitor Measured on a Texas Instruments reference design with Tc = 25 °C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP Resolution MAX 25 Range mV 1.8 3.8 Integral nonlinearity (max) Accuracy UNIT VDDS = 3.0 V V 23 mV 22.5 mV Offset error -32 mV Gain error -1 % 8.15.4 Comparator 8.15.4.1 Continuous Time Comparator Tc = 25°C, VDDS = 3.0 V, unless otherwise noted. PARAMETER TEST CONDITIONS Input voltage range(1) TYP 0 Offset Measured at VDDS / 2 Decision time Step from –10 mV to 10 mV Current consumption Internal reference (1) MIN MAX UNIT VDDS V ±5 mV 0.78 µs 9.2 µA The input voltages can be generated externally and connected throughout I/Os or an internal reference voltage can be generated using the DAC 8.15.5 GPIO 8.15.5.1 GPIO DC Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TA = 25 °C, VDDS = 1.8 V GPIO VOH at 8 mA load IOCURR = 2, high-drive GPIOs only 1.56 V GPIO VOL at 8 mA load IOCURR = 2, high-drive GPIOs only 0.24 V GPIO VOH at 4 mA load IOCURR = 1 1.59 V GPIO VOL at 4 mA load IOCURR = 1 0.21 V GPIO pullup current Input mode, pullup enabled, Vpad = 0 V 73 µA GPIO pulldown current Input mode, pulldown enabled, Vpad = VDDS 19 µA GPIO low-to-high input transition, with hysteresis IH = 1, transition voltage for input read as 0 → 1 1.08 V GPIO high-to-low input transition, with hysteresis IH = 1, transition voltage for input read as 1 → 0 0.73 V GPIO input hysteresis IH = 1, difference between 0 → 1 and 1 → 0 points 0.35 V GPIO VOH at 8 mA load IOCURR = 2, high-drive GPIOs only 2.59 V GPIO VOL at 8 mA load IOCURR = 2, high-drive GPIOs only 0.42 V GPIO VOH at 4 mA load IOCURR = 1 2.63 V GPIO VOL at 4 mA load IOCURR = 1 0.40 V TA = 25 °C, VDDS = 3.0 V Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 29 CC2651P3 www.ti.com SWRS257 – MARCH 2022 8.15.5.1 GPIO DC Characteristics (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TA = 25 °C, VDDS = 3.8 V GPIO pullup current Input mode, pullup enabled, Vpad = 0 V 282 µA GPIO pulldown current Input mode, pulldown enabled, Vpad = VDDS 110 µA GPIO low-to-high input transition, with hysteresis IH = 1, transition voltage for input read as 0 → 1 1.97 V GPIO high-to-low input transition, with hysteresis IH = 1, transition voltage for input read as 1 → 0 1.55 V GPIO input hysteresis IH = 1, difference between 0 → 1 and 1 → 0 points 0.42 V TA = 25 °C VIH Lowest GPIO input voltage reliably interpreted as a High VIL Highest GPIO input voltage reliably interpreted as a Low 30 Submit Document Feedback 0.8*VDDS V 0.2*VDDS V Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 8.16 Typical Characteristics All measurements in this section are done with Tc = 25 °C and VDDS = 3.0 V, unless otherwise noted. See Recommended Operating Conditions, Section 8.3, for device limits. Values exceeding these limits are for reference only. 8.16.1 MCU Current Figure 8-4. Active Mode (MCU) Current vs. Supply Voltage (VDDS) Figure 8-5. Standby Mode (MCU) Current vs. Temperature 8.16.2 RX Current Figure 8-6. RX Current vs. Temperature (BLE 1 Mbps, 2.44 GHz) Figure 8-7. RX Current vs. Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 31 CC2651P3 www.ti.com SWRS257 – MARCH 2022 8.16.3 TX Current TX Current vs. Temperature TX Current vs. Temperature Bluetooth Low Energy 1 Mbps, 2.44 GHz, +10 dBm BLE 1 Mbps, 2.44 GHz, +20 dBm PA, VDDS = 3.3 V 25 24 22 Current [mA] Current [mA] 23 21 20 19 18 17 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature [C] Figure 8-8. TX Current vs. Temperature (BLE 1 Mbps, 2.44 GHz) 130 125 120 115 110 105 100 95 90 85 80 75 70 65 60 55 50 45 40 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 Temperature [°C] D020 Figure 8-9. TX Current vs. Temperature (BLE 1 Mbps, 2.44 GHz, VDDS = 3.3 V) TX Current vs. VDDS TX Current vs. Temperature Bluetooth Low Energy 1 Mbps 2.44GHz, + 10 dBm PA IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), 2.44 GHz, +10 dBm PA 45 33 +10 dBm +9 dBm +8 dBm +7 dBm +6 dBm 40 35 Current [mA] 30 Current [mA] +20 dBm +19 dBm +18 dBm +17 dBm +16 dBm +15 dBm +14 dBm 27 24 30 25 20 21 15 18 10 1.8 15 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Figure 8-10. TX Current vs. Temperature (250 kbps, 2.44 GHz, +10 dBm PA) 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 120 116 112 108 104 100 96 92 88 84 80 76 72 68 64 60 56 52 48 44 40 1.8 1.9 2 Figure 8-11. TX Current vs. Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz) TX Current vs. VDDS TX Current vs. VDDS BLE 1 Mbps, 2.44 GHz, +20 dBm PA IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), 2.44 GHz, +10 dBm PA 50 +20 dBm +19 dBm +18 dBm +17 dBm +16 dBm +15 dBm +14 dBm 45 40 Current [mA] Current [mA] 2.2 Voltage [V] Temperature [°C] +10 dBm +9 dBm + 8dBm +7 dBm +6 dBm 35 30 25 20 15 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Voltage [V] 10 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 D025 Figure 8-12. TX Current vs. Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz, +20 dBm PA) 32 2 Voltage [V] Figure 8-13. TX Current vs. Supply Voltage (VDDS) (250 kbps, 2.44 GHz, +10 dBm PA) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 Table 8-1. Typical TX Current and Output Power, regular PA CC2651P3 at 2.4 GHz, VDDS = 3.0 V (Measured on CC2651-P3EM-7XD24-PA24) txPower TX Power Setting (SmartRF Studio) Typical Output Power [dBm] Typical Current Consumption [mA] 0x701F 5 5.5 12.5 0x3A17 4 4.5 11.9 0x3A64 3 3.1 11.2 0x325F 2 2.0 10.8 0x2C5C 1 1.3 10.5 0x2659 0 0.4 10.2 0x1697 -3 -2.8 9.4 0x1693 -5 -4.8 8.9 0x1292 -6 -5.4 8.8 0xCD3 -9 -9.0 8.4 0xAD1 -10 -10.4 8.2 0xACF -12 -12.0 8.1 0x6CD -15 -13.7 7.9 0x6CA -18 -16.8 7.7 0x4C8 -20 -19.3 7.6 Table 8-2. Typical TX Current and Output Power, high power PA, 10 dBm mode CC2651P3 at 2.4 GHz, VDDS = 3.0 V (Measured on CC261-P3EM-5XS24-PA24_10dBm) txPower TX Power Setting (SmartRF Studio) Typical Output Power [dBm] Typical Current Consumption [mA] 0x14395A 10 10.1 23.6 0x142F55 9 9.0 22.1 0x62F35 8 7.8 21.1 0x63930 7 6.9 20.1 0x6292B 6 5.9 19.1 Table 8-3. Typical TX Current and Output Power, high power PA, 20 dBm mode CC2651P3 at 2.4 GHz, VDDS = 3.3 V (Measured on CC2651-P3EM-7XD24-PA24) txPower TX Power Setting (SmartRF Studio) Typical Output Power [dBm] Typical Current Consumption [mA] 0x3F75F5 20 20.0 100.1 0x3F61E2 19 19.4 91.1 0x3047E0 18 19.0 86.4 0x1B4FE5 17 18.1 78.3 0x1B39DE 16 17.3 71.8 0x1B2FDA 15 16.7 67.1 0x1B27D6 14 15.9 61.8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 33 CC2651P3 www.ti.com SWRS257 – MARCH 2022 Sensitivity vs. Frequency Sensitivity vs. Frequency BLE 1 Mbps, 2.44 GHz IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps) -92 -95 -93 -96 -94 -97 -95 -98 Sensitivity [dBm ] Sensitivity [dBm] 8.16.4 RX Performance -96 -97 -98 -99 -100 -104 -102 2.4 -105 2.4 2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48 2.432 2.44 2.448 2.456 2.464 2.472 Sensitivity vs. Temperature BLE 1 Mbps, 2.44 GHz IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), 2.44 GHz -96 -94 -97 -95 -98 -96 -97 -98 -99 -99 -100 -101 -102 -100 -103 -101 -104 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] -105 -40 100 -30 -20 -10 0 10 20 30 40 50 60 70 Sensitivity vs. VDDS BLE 1 Mbps, 2.44 GHz, DCDC Off -92 -93 -93 -94 -94 -95 -95 Sensitivity [dBm] -92 -98 -99 -100 100 D032 BLE 1 Mbps, 2.44 GHz -97 90 Figure 8-17. Sensitivity vs. Temperature (250 kbps, 2.44 GHz) Sensitivity vs. VDDS -96 80 Temperature [°C] D031 Figure 8-16. Sensitivity vs. Temperature (BLE 1 Mbps, 2.44 GHz) 2.48 D029 Sensitivity vs. Temperature -95 -20 2.424 Figure 8-15. Sensitivity vs. Frequency (250 kbps, 2.44 GHz) -93 -30 2.416 Frequency [GHz] -92 -102 -40 2.408 D028 Sensitivity [dBm] Sensitivity [dBm] -102 -103 Figure 8-14. Sensitivity vs. Frequency (BLE 1 Mbps, 2.44 GHz) Sensitivity [dBm] -101 -101 Frequency [GHz] -96 -97 -98 -99 -100 -101 -101 -102 1.8 -102 1.8 2 2.2 2.4 2.6 2.8 Voltage [V] 3 3.2 3.4 3.6 3.8 2 2.2 2.4 2.6 2.8 Voltage [V] D034 Figure 8-18. Sensitivity vs. Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz) 34 -99 -100 3 3.2 3.4 3.6 3.8 D035 Figure 8-19. Sensitivity vs. Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz, DCDC Off) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 Sensitivity vs. VDDS IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), 2.44 GHz -95 -96 Sensitivity [dBm ] -97 -98 -99 -100 -101 -102 -103 -104 -105 1.8 2 2.2 2.4 2.6 2.8 3 3.2 Voltage [V] 3.4 3.6 3.8 D036 Figure 8-20. Sensitivity vs. Supply Voltage (VDDS) (250 kbps, 2.44 GHz) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 35 CC2651P3 www.ti.com SWRS257 – MARCH 2022 8.16.5 TX Performance Output Power vs. Temperature Output Power vs. Temperature BLE 1 Mbps, 2.44 GHz, +5 dBm 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 -40 Output Power [dBm] Output Power [dBm] BLE 1 Mbps, 2.44 GHz, 0 dBm -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature [°C] -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] D041 Figure 8-21. Output Power vs. Temperature (BLE 1 Mbps, 2.44 GHz) 100 D042 Figure 8-22. Output Power vs. Temperature (BLE 1 Mbps, 2.44 GHz, +5 dBm) Output Power vs. Temperature Output Power vs. Temperature BLE 1 Mbps, 2.44 GHz, +20 dBm PA, VDDS = 3.3 V IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), 2.44 GHz, +10 dBm PA 26 14 +20 dBm +19 dBm +18 dBm +17 dBm +16 dBm +15 dBm +14 dBm 22 +10 dBm +9 dBm +8 dBm +7 dBm +6 dBm 13 Output Power [dBm] 24 Output Power [dBm] 7 6.8 6.6 6.4 6.2 6 5.8 5.6 5.4 5.2 5 4.8 4.6 4.4 4.2 4 3.8 3.6 3.4 3.2 3 -40 20 18 16 12 11 10 9 8 14 7 12 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] 6 -40 100 -30 -20 -10 Figure 8-23. Output Power vs. Temperature (BLE 1 Mbps, 2.44 GHz, +20 dBm PA) 2.4 2.6 2.8 Output Power [dBm] Voltage [V] 3 3.2 40 50 60 70 80 90 100 BLE 1 Mbps, 2.44 GHz, +5 dBm 3.4 3.6 3.8 7 6.8 6.6 6.4 6.2 6 5.8 5.6 5.4 5.2 5 4.8 4.6 4.4 4.2 4 3.8 3.6 3.4 3.2 3 1.8 2 2.2 2.4 2.6 2.8 Voltage [V] D046 Figure 8-25. Output Power vs. Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz) 36 30 Output power vs. VDDS Output Power [dBm] 2.2 20 Figure 8-24. Output Power vs. Temperature (2.44 GHz, +10 dBm PA) BLE 1 Mbps, 2.44 GHz, 0 dBm 2 10 Temperature [°C] Output Power vs. VDDS 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 1.8 0 D043 3 3.2 3.4 3.6 3.8 D048 Figure 8-26. Output Power vs. Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz, +5 dBm) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 Output power vs. VDDS Output Power vs. VDDS BLE 1 Mbps, 2.44 GHz, +20 dBm PA IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), 2.44 GHz, +10 dBm PA 22 Output Power [dBm] 20 18 Output Power [dBm] +20 dBm +19 dBm +18 dBm +17 dBm +16 dBm +15 dBm +14 dBm 16 14 12 10 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Voltage [V] 3.8 14 13.5 13 12.5 12 11.5 11 10.5 10 9.5 9 8.5 8 7.5 7 6.5 6 5.5 1.8 +10 dBm +9 dBm +8dBm +7 dBm +6 dBm 2 2.2 Figure 8-27. Output Power vs. Supply Voltage (VDDS) (BLE 1 Mbps, 2.44 GHz, +20 dBm PA) 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48 Output Power [dBm] 3.6 3.8 2.408 2.416 2.424 2.432 2.44 2.448 2.456 2.464 2.472 2.48 D059 Figure 8-30. Output Power vs. Frequency (BLE 1 Mbps, 2.44 GHz, +5 dBm) Output Power vs. Frequency Output Power vs. Frequency BLE 1 Mbps, +20 dBm PA, VDDS = 3.3 V IEEE 802.15.4 (OQPSK DSSS1:8, 250 kbps), +10 dBm PA 14 +20 dBm +19 dBm +18 dBm +17 dBm +16 dBm +15 dBm +14 dBm 13 12 Output Power [dBm] Output Power [dBm] 21 3.4 Frequency [GHz] 25 22 7 6.8 6.6 6.4 6.2 6 5.8 5.6 5.4 5.2 5 4.8 4.6 4.4 4.2 4 3.8 3.6 3.4 3.2 3 2.4 D058 Figure 8-29. Output Power vs. Frequency (BLE 1 Mbps, 2.44 GHz) 23 3.2 BLE 1 Mbps, 2.44 GHz, +5 dBm Frequency [GHz] 24 3 Output Power vs. Frequency Output Power [dBm] 2.416 2.8 Figure 8-28. Output Power vs. Supply Voltage (VDDS) (2.44 GHz, +10 dBm PA) BLE 1 Mbps, 2.44 GHz, 0 dBm 2.408 2.6 Voltage [V] Output Power vs. Frequency 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 2.4 2.4 D050 20 19 18 17 16 +10 dBm +9 dBm + 8dBm +7 dBm +6 dBm 11 10 9 8 7 15 6 14 13 2.4 2.408 2.416 2.424 2.432 2.44 2.448 Frequency [GHz] 2.456 2.464 2.472 2.48 5 2405 2415 Figure 8-31. Output Power vs. Frequency (BLE 1 Mbps, 2.44 GHz, +20 dBm PA) 2425 2435 2445 2455 2465 2475 2480 Frequency [MHz] D060 Figure 8-32. Output Power vs. Frequency (250 kbps, +10 dBm PA) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 37 CC2651P3 www.ti.com SWRS257 – MARCH 2022 8.16.6 ADC Performance ENOB vs. Input Frequency ENOB vs. Sampling Frequency Vin = 3.0 V Sine wave, Internal reference, Fin = Fs / 10 11.4 Internal Reference, No Averaging Internal Unscaled Reference, 14-bit Mode 10.2 11.1 10.15 10.1 ENOB [Bit] ENOB [Bit] 10.8 10.5 10.2 10.05 10 9.95 9.9 9.9 9.85 9.6 0.2 9.8 0.3 0.5 0.7 1 2 3 4 5 6 7 8 10 20 30 40 50 1 70 100 Frequency [kHz] 20 30 40 50 70 100 200 D062 INL vs. ADC Code DNL vs. ADC Code Vin = 3.0 V Sine wave, Internal reference, 200 kSamples/s Vin = 3.0 V Sine wave, Internal reference, 200 kSamples/s 1.5 2.5 1 2 0.5 1.5 DNL [LSB] INL [LSB] 4 5 6 7 8 10 Figure 8-34. ENOB vs. Sampling Frequency 0 1 -0.5 0.5 -1 0 -1.5 -0.5 0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 ADC Code 0 1200 1600 2000 2400 2800 3200 ADC Accuracy vs. VDDS Vin = 1 V, Internal reference, 200 kSamples/s Vin = 1 V, Internal reference, 200 kSamples/s 1.008 1.008 1.007 1.007 Voltage [V] 1.01 1.009 1.006 1.005 1.004 1.006 1.005 1.004 1.003 1.003 1.002 1.002 1.001 1.001 -10 0 10 20 30 40 50 60 70 80 4000 D065 ADC Accuracy vs. Temperature -20 3600 Figure 8-36. DNL vs. ADC Code 1.01 -30 800 ADC Code 1.009 1 -40 400 D064 Figure 8-35. INL vs. ADC Code Voltage [V] 3 Frequency [kHz] Figure 8-33. ENOB vs. Input Frequency 90 1 1.8 100 Temperature [°C] 2 2.2 2.4 2.6 2.8 Voltage [V] D066 Figure 8-37. ADC Accuracy vs. Temperature 38 2 D061 3 3.2 3.4 3.6 3.8 D067 Figure 8-38. ADC Accuracy vs. Supply Voltage (VDDS) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 9 Detailed Description 9.1 Overview Section 4 shows the core modules of the CC2651P3 device. 9.2 System CPU The CC2651P3 SimpleLink™ Wireless MCU contains an Arm® Cortex®-M4 system CPU, which runs the application and the higher layers of radio protocol stacks. The system CPU is the foundation of a high-performance, low-cost platform that meets the system requirements of minimal memory implementation, and low-power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Its features include the following: • ARMv7-M architecture optimized for small-footprint embedded applications • Arm Thumb®-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit Arm core in a compact memory size • Fast code execution permits increased sleep mode time • Deterministic, high-performance interrupt handling for time-critical applications • Single-cycle multiply instruction and hardware divide • Hardware division and fast digital-signal-processing oriented multiply accumulate • Saturating arithmetic for signal processing • Full debug with data matching for watchpoint generation – Data Watchpoint and Trace Unit (DWT) – JTAG Debug Access Port (DAP) – Flash Patch and Breakpoint Unit (FPB) • Trace support reduces the number of pins required for debugging and tracing – Instrumentation Trace Macrocell Unit (ITM) – Trace Port Interface Unit (TPIU) with asynchronous serial wire output (SWO) • Optimized for single-cycle flash memory access • Tightly connected to 8-KB 4-way random replacement cache for minimal active power consumption and wait states • Ultra-low-power consumption with integrated sleep modes • 48 MHz operation • 1.25 DMIPS per MHz Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 39 CC2651P3 www.ti.com SWRS257 – MARCH 2022 9.3 Radio (RF Core) The RF Core is a highly flexible and future proof radio module which contains an Arm Cortex-M0 processor that interfaces the analog RF and base-band circuitry, handles data to and from the system CPU side, and assembles the information bits in a given packet structure. The RF core offers a high level, command-based API to the main CPU that configurations and data are passed through. The Arm Cortex-M0 processor is not programmable by customers and is interfaced through the TI-provided RF driver that is included with the SimpleLink Software Development Kit (SDK). The RF core can autonomously handle the time-critical aspects of the radio protocols, thus offloading the main CPU, which reduces power and leaves more resources for the user application. Several signals are also available to control external circuitry such as RF switches or range extenders autonomously. The various physical layer radio formats are partly built as a software defined radio where the radio behavior is either defined by radio ROM contents or by non-ROM radio formats delivered in form of firmware patches with the SimpleLink SDKs. This allows the radio platform to be updated for support of future versions of standards even with over-the-air (OTA) updates while still using the same silicon. 9.3.1 Bluetooth 5.2 Low Energy The RF Core offers full support for Bluetooth 5.2 Low Energy, including the high-sped 2-Mbps physical layer and the 500-kbps and 125-kbps long range PHYs (Coded PHY) through the TI provided Bluetooth 5.2 stack or through a high-level Bluetooth API. The new high-speed mode allows data transfers up to 2 Mbps, twice the speed of Bluetooth 4.2 and five times the speed of Bluetooth 4.0, without increasing power consumption. In addition to faster speeds, this mode offers significant improvements for energy efficiency and wireless coexistence with reduced radio communication time. Bluetooth 5.2 also enables unparalleled flexibility for adjustment of speed and range based on application needs, which capitalizes on the high-speed or long-range modes respectively. Data transfers are now possible at 2 Mbps, enabling development of applications using voice, audio, imaging, and data logging that were not previously an option using Bluetooth low energy. With high-speed mode, existing applications deliver faster responses, richer engagement, and longer battery life. Bluetooth 5.2 enables fast, reliable firmware updates. 9.3.2 802.15.4 (Zigbee and 6LoWPAN) Through a dedicated IEEE radio API, the RF Core supports the 2.4-GHz IEEE 802.15.4-2011 physical layer (2 Mchips per second Offset-QPSK with DSSS 1:8), used in Zigbee and 6LoWPAN protocols. TI provides royalty-free protocol stacks for Zigbee as part of the SimpleLink SDK, enabling a robust end-to-end solution. 40 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 9.4 Memory The up to 352-KB nonvolatile (Flash) memory provides storage for code and data. The flash memory is in-system programmable and erasable. The last flash memory sector must contain a Customer Configuration section (CCFG) that is used by boot ROM and TI provided drivers to configure the device. This configuration is done through the ccfg.c source file that is included in all TI provided examples. The ultra-low leakage system static RAM (SRAM) is a single 32-KB block and can be used for both storage of data and execution of code. Retention of SRAM contents in Standby power mode is enabled by default and included in Standby mode power consumption numbers. To improve code execution speed and lower power when executing code from nonvolatile memory, a 4-way nonassociative 8-KB cache is enabled by default to cache and prefetch instructions read by the system CPU. The cache can be used as a general-purpose RAM by enabling this feature in the Customer Configuration Area (CCFG). The ROM contains a serial (SPI and UART) bootloader that can be used for initial programming of the device. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 41 CC2651P3 www.ti.com SWRS257 – MARCH 2022 9.5 Cryptography The CC2651P3 device comes with a wide set of cryptography-related hardware accelerators, reducing code footprint and execution time for cryptographic operations. It also has the benefit of being lower power and improves availability and responsiveness of the system because the cryptography operations run in a background hardware thread. The hardware accelerator modules are: • True Random Number Generator (TRNG) module provides a true, nondeterministic noise source for the purpose of generating keys, initialization vectors (IVs), and other random number requirements. The TRNG is built on 24 ring oscillators that create unpredictable output to feed a complex nonlinear-combinatorial circuit. • Advanced Encryption Standard (AES) with 128 bit key lengths Together with the hardware accelerator module, a large selection of open-source cryptography libraries provided with the Software Development Kit (SDK), this allows for secure and future proof IoT applications to be easily built on top of the platform. The TI provided cryptography drivers are: • Key Agreement Schemes – Elliptic curve Diffie–Hellman with static or ephemeral keys (ECDH and ECDHE) • Signature Generation – Elliptic curve Diffie-Hellman Digital Signature Algorithm (ECDSA) • Curve Support – Short Weierstrass form (full hardware support), such as: • NIST-P256 – Montgomery form (hardware support for multiplication), such as: • Curve25519 • Hash – SHA256 • MACs – HMAC with SHA256 – AES CBC-MAC • Block ciphers – AESECB – AESCBC – AESCTR • Authenticated Encryption – AESCCM • Random number generation – True Random Number Generator – AES CTR DRBG 42 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 9.6 Timers A large selection of timers are available as part of the CC2651P3 device. These timers are: • Real-Time Clock (RTC) • A 70-bit 3-channel timer running on the 32 kHz low frequency system clock (SCLK_LF) This timer is available in all power modes except Shutdown. The timer can be calibrated to compensate for frequency drift when using the LF RCOSC as the low frequency system clock. If an external LF clock with frequency different from 32.768 kHz is used, the RTC tick speed can be adjusted to compensate for this. When using TI-RTOS, the RTC is used as the base timer in the operating system and should thus only be accessed through the kernel APIs such as the Clock module. By default, the RTC halts when a debugger halts the device. General Purpose Timers (GPTIMER) • The four flexible GPTIMERs can be used as either 4× 32 bit timers or 8× 16 bit timers, all running on up to 48 MHz. Each of the 16- or 32-bit timers support a wide range of features such as one-shot or periodic counting, pulse width modulation (PWM), time counting between edges and edge counting. The inputs and outputs of the timer are connected to the device event fabric, which allows the timers to interact with signals such as GPIO inputs, other timers, DMA and ADC. The GPTIMERs are available in Active and Idle power modes. Radio Timer • A multichannel 32-bit timer running at 4 MHz is available as part of the device radio. The radio timer is typically used as the timing base in wireless network communication using the 32-bit timing word as the network time. The radio timer is synchronized with the RTC by using a dedicated radio API when the device radio is turned on or off. This ensures that for a network stack, the radio timer seems to always be running when the radio is enabled. The radio timer is in most cases used indirectly through the trigger time fields in the radio APIs and should only be used when running the accurate 48 MHz high frequency crystal is the source of SCLK_HF. Watchdog timer The watchdog timer is used to regain control if the system operates incorrectly due to software errors. It is typically used to generate an interrupt to and reset of the device for the case where periodic monitoring of the system components and tasks fails to verify proper functionality. The watchdog timer runs on a 1.5 MHz clock rate and cannot be stopped once enabled. The watchdog timer pauses to run in Standby power mode and when a debugger halts the device. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 43 CC2651P3 www.ti.com SWRS257 – MARCH 2022 9.7 Serial Peripherals and I/O The SSI is a synchronous serial interface that is compatible with SPI, MICROWIRE, and TI's synchronous serial interfaces. The SSI support both SPI master and slave up to 4 MHz. The SSI module support configurable phase and polarity. The UART implement universal asynchronous receiver and transmitter functions. It support flexible baud-rate generation up to a maximum of 3 Mbps. The I2S interface is used to handle digital audio and can also be used to interface pulse-density modulation microphones (PDM). The I2C interface is also used to communicate with devices compatible with the I2C standard. The I2C interface can handle 100 kHz and 400 kHz operation, and can serve as both master and slave. The I/O controller (IOC) controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals to be assigned to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a programmable pullup and pulldown function, and can generate an interrupt on a negative or positive edge (configurable). When configured as an output, pins can function as either push-pull or open-drain. Five GPIOs have high-drive capabilities, which are marked in bold in Section 7. All digital peripherals can be connected to any digital pin on the device. For more information, see the CC13x1x3, CC26x1x3 SimpleLink™ Wireless MCU Technical Reference Manual. 9.8 Battery and Temperature Monitor A combined temperature and battery voltage monitor is available in the CC2651P3 device. The battery and temperature monitor allows an application to continuously monitor on-chip temperature and supply voltage and respond to changes in environmental conditions as needed. The module contains window comparators to interrupt the system CPU when temperature or supply voltage go outside defined windows. These events can also be used to wake up the device from Standby mode through the Always-On (AON) event fabric. 9.9 µDMA The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload data-transfer tasks from the system CPU, thus allowing for more efficient use of the processor and the available bus bandwidth. The µDMA controller can perform a transfer between memory and peripherals. The µDMA controller has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory when the peripheral is ready to transfer more data. Some features of the µDMA controller include the following (this is not an exhaustive list): • • • • Highly flexible and configurable channel operation of up to 32 channels Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral Data sizes of 8, 16, and 32 bits Ping-pong mode for continuous streaming of data 9.10 Debug The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1) interface. The device boots by default into cJTAG mode and must be reconfigured to use 4-pin JTAG. 44 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 9.11 Power Management To minimize power consumption, the CC2651P3 supports a number of power modes and power management features (see Table 9-1). Table 9-1. Power Modes SOFTWARE CONFIGURABLE POWER MODES MODE ACTIVE IDLE STANDBY SHUTDOWN RESET PIN HELD CPU Active Off Off Off Off Flash On Available Off Off Off SRAM On On Retention Off Off Supply System On On Duty Cycled Off Off Register and CPU retention Full Full Partial No No SRAM retention Full Full Full No No 48 MHz high-speed clock (SCLK_HF) XOSC_HF or RCOSC_HF XOSC_HF or RCOSC_HF Off Off Off 32 kHz low-speed clock (SCLK_LF) XOSC_LF or RCOSC_LF XOSC_LF or RCOSC_LF XOSC_LF or RCOSC_LF Off Off Peripherals Available Available Off Off Off Wake-up on RTC Available Available Available Off Off Wake-up on pin edge Available Available Available Available Off Wake-up on reset pin On On On On On Brownout detector (BOD) On On Duty Cycled Off Off Power-on reset (POR) On On On Off Off Watchdog timer (WDT) Available Available Paused Off Off In Active mode, the application system CPU is actively executing code. Active mode provides normal operation of the processor and all of the peripherals that are currently enabled. The system clock can be any available clock source (see Table 9-1). In Idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not clocked and no code is executed. Any interrupt event brings the processor back into active mode. In Standby mode, only the always-on (AON) domain is active. An external wake-up event or RTC event is required to bring the device back to active mode. MCU peripherals with retention do not need to be reconfigured when waking up again, and the CPU continues execution from where it went into standby mode. All GPIOs are latched in standby mode. In Shutdown mode, the device is entirely turned off (including the AON domain), and the I/Os are latched with the value they had before entering shutdown mode. A change of state on any I/O pin defined as a wake from shutdown pin wakes up the device and functions as a reset trigger. The CPU can differentiate between reset in this way and reset-by-reset pin or power-on reset by reading the reset status register. The only state retained in this mode is the latched I/O state and the flash memory contents. Note The power, RF and clock management for the CC2651P3 device require specific configuration and handling by software for optimized performance. This configuration and handling is implemented in the TI-provided drivers that are part of the CC2651P3 software development kit (SDK). Therefore, TI highly recommends using this software framework for all application development on the device. The complete SDK with TI-RTOS (optional), device drivers, and examples are offered free of charge in source code. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 45 CC2651P3 www.ti.com SWRS257 – MARCH 2022 9.12 Clock Systems The CC2651P3 device has several internal system clocks. The 48 MHz SCLK_HF is used as the main system (MCU and peripherals) clock. This can be driven by the internal 48 MHz RC Oscillator (RCOSC_HF) or an external 48 MHz crystal (XOSC_HF). Radio operation requires an external 48 MHz crystal. SCLK_LF is the 32.768 kHz internal low-frequency system clock. It can be used for the RTC and to synchronize the radio timer before or after Standby power mode. SCLK_LF can be driven by the internal 32.8 kHz RC Oscillator (RCOSC_LF), a 32.768 kHz watch-type crystal, or a clock input on any digital IO. When using a crystal or the internal RC oscillator, the device can output the 32 kHz SCLK_LF signal to other devices, thereby reducing the overall system cost. 9.13 Network Processor Depending on the product configuration, the CC2651P3 device can function as a wireless network processor (WNP - a device running the wireless protocol stack with the application running on a separate host MCU), or as a system-on-chip (SoC) with the application and protocol stack running on the system CPU inside the device. In the first case, the external host MCU communicates with the device using SPI or UART. In the second case, the application must be written according to the application framework supplied with the wireless protocol stack. 46 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CC2651P3 CC2651P3 www.ti.com SWRS257 – MARCH 2022 10 Application, Implementation, and Layout Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. For general design guidelines and hardware configuration guidelines, refer to CC13xx/CC26xx Hardware Configuration and PCB Design Considerations Application Report. For optimum RF performance, especially when using the high-power PA, it is important to accurately follow the reference design with respect to component values and layout. Failure to do so may lead to reduced RF performance due to balun mismatch. The amplitude- and phase balance through the balun must be