LSF0204-Q1
LSF0204-Q1
SLVSEM4B – JUNE 2018 – REVISED
APRIL 2021
SLVSEM4B – JUNE 2018 – REVISED APRIL 2021
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LSF0204-Q1 Automotive Qualified 4-Bit Auto-Bidirectional Multi-Voltage Level
Translator
1 Features
•
•
•
•
•
•
•
•
•
•
AEC-Q100 qualified for automotive applications
– Temperature grade 1: –40°C ≤ TA ≤ 125°C
– Device HBM ESD classification level 2
– CDM ESD classification level C6
Provides auto-bidirectional voltage translation
without direction pin
Supports open drain or push-pull applications such
as I2C, I2S, SPI, UART, JTAG, MDIO, SDIO, and
GPIO
Supports up to 100-MHz up translation and greater
than 100-MHz down translation
at ≤ 30-pF capacitor load and up to 40-MHz up/
down translation at 50-pF capacitor load
Supports Ioff, partial power down mode (see
Section 7.3)
Allows bidirectional voltage level translation
between
– 0.95 V ↔ 1.8, 2.5, 3.3, 5.5 V
– 1.2 V ↔ 1.8, 2.5, 3.3, 5.5 V
– 1.8 V ↔ 2.5, 3.3, 5.5 V
– 2.5 V ↔ 3.3, 5.5 V
– 3.3 V ↔ 5.5 V
5-V tolerance on I/O ports
Low Ron enables better signal integrity
Flow-through pinout for easy PCB trace routing
Latch-up performance exceeds 100 mA per
JESD17
When the An or Bn port is LOW, the switch is in
the ON-state and a low resistance connection exists
between the An and Bn ports. The low Ron of the
switch allows connections to be made with minimal
propagation delay and minimal signal distortion. The
voltage on the A or B side will be limited to Vref_A and
can be pulled up to any level between Vref_A and 5.5
V
The supply voltage (VPUn) for each channel may be
individually set up with a pull up resistor. For example,
CH1 may be used in up-translation mode (1.2 V ↔
3.3 V) and CH2 in down-translation mode (2.5 V ↔
1.8 V).
When EN is HIGH, the translator switch is on, and
the An I/O is connected to the Bn I/O, respectively,
allowing bidirectional data flow between ports. When
EN is LOW, the translator switch is off, and a highimpedance state exists between ports. The EN input
circuit is designed to be supplied by Vref_A. EN must
be LOW to ensure the high-impedance state during
power-up or power-down.
Device Information(1)
PART NUMBER
PACKAGE
LSF0204QPWRQ1
(1)
•
•
•
•
•
5.00 mm × 4.40 mm
For all available packages, see the orderable addendum at
the end of the datasheet.
LSF0204-Q1
2 Applications
•
BODY SIZE (NOM)
TSSOP (14)
200 KΩ
Vref_B
I2C,
I2S, JTAG, SPI, SDIO, UART,
MDIO, PMBus,
SMBus and other interfaces
Infotainment head unit
Graphical cluster
ADAS fusion
ADAS front camera
HEV battery management system
3 Description
The LSF0204-Q1 is automotive qualified four channel
auto bidirectional voltage translator that operate from
0.8 V to 4.5 V (Vref_A) and 1.8 V to 5.5 V (Vref_B).
This range allows for bidirectional voltage translations
between 0.8 V and 5.5 V without the need for a
direction pin.
Vref_A
Level Converter
EN
A1
B1
A2
B2
A3
B3
A4
B4
Simplified Schematic
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics: AC Performance
(Translating Down, 3.3 V to 1.8 V)................................ 6
6.7 Switching Characteristics: AC Performance
(Translating Down, 3.3 V to 1.2 V)................................ 6
6.8 Switching Characteristics: AC Performance
(Translating Up, 1.8 V to 3.3 V)..................................... 7
6.9 Switching Characteristics: AC Performance
(Translating Up, 1.2 V to 1.8 V)..................................... 7
6.10 Typical Characteristics.............................................. 8
7 Detailed Description...................................................... 11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................12
8 Application and Implementation.................................. 13
8.1 Application Information............................................. 13
8.2 Typical Applications.................................................. 13
9 Power Supply Recommendations................................17
10 Layout...........................................................................17
10.1 Layout Guidelines................................................... 17
10.2 Layout Example...................................................... 17
11 Device and Documentation Support..........................18
11.1 Documentation Support.......................................... 18
11.2 Receiving Notification of Documentation Updates.. 18
11.3 Support Resources................................................. 18
11.4 Trademarks............................................................. 18
11.5 Electrostatic Discharge Caution.............................. 18
11.6 Glossary.................................................................. 18
12 Mechanical, Packaging, and Orderable
Information.................................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2018) to Revision B (April 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated the Bidrectional Translation section to include inclusive terminology.................................................14
Changes from Revision * (June 2018) to Revision A (September 2018)
Page
• Changed product status from Advanced Information to Production Data ..........................................................1
2
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5 Pin Configuration and Functions
VREF_A
1
14
VREF_B
A1
2
13
B1
A2
3
12
B2
A3
4
11
B3
A4
5
10
B4
NC
6
9
NC
GND
7
8
EN
Not to scale
Figure 5-1. PW Package
14-Pin TSSOP
Top View
Table 5-1. Pin Functions 2
PIN
NAME
NO.
I/O
DESCRIPTION
VREF_A
1
—
Reference supply voltage; see Section 8 section
A1
2
I/O
Input/output 1.
A2
3
I/O
Input/output 2.
A3
4
I/O
Input/output 3.
A4
5
I/O
Input/output 4.
NC
6
—
No connection. Not internally connected.
GND
7
—
Ground
EN
8
I
Translation enable input, EN is active-high
NC
9
—
No connection. Not internally connected.
B4
10
I/O
Input/output 4.
B3
11
I/O
Input/output 3.
B2
12
I/O
Input/output 2.
B1
13
I/O
Input/output 1.
VREF_B
14
—
Reference supply voltage; see Section 8 section
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Input voltage, VI (2)
Input and output voltage, VI/O
MAX
–0.5
(2)
–0.5
VI < 0
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
V
7
Continuous channel current
Input clamp current, IIK
UNIT
7
–65
V
128
mA
–50
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002(1)
±2000
Charged-device model (CDM), per AEC Q100-001
±1000
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VI/O
Input/output voltage
0
5.5
V
Vref_A/B/EN
Reference voltage
0
5.5
V
IPASS
Pass transistor current
64
mA
TA
Operating free-air temperature
–40
125
°C
6.4 Thermal Information
LSF0204-Q1
THERMAL METRIC(1)
PW (TSSOP)
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
°C
RθJC(top)
Junction-to-case (top) thermal resistance
82.3
°C
RθJB
Junction-to-board thermal resistance
100.0
°C
ψJT
Junction-to-top characterization parameter
22.9
°C
ψJB
Junction-to-board characterization parameter
99.0
°C
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C
(1)
4
157.9
For more information about traditional and new thermal metrics, refer to the Semiconductor and IC Package Thermal Metrics
application report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP(1)
MAX
UNIT
–1.2
V
VI = 5 V, VEN = 0
5.0
µA
Leakage from
Vref_B to Vref_A
Vref_B = 3.3 V, Vref_A = 1.8 V, VEN = Vref_A IO = 0, VI = 3.3 V or
GND
3.5
µA
ICCA + ICCB (3)
Total Current
through GND
Vref_B = 3.3 V, Vref_A = 1.8 V, VEN = Vref_A IO = 0, VI = 3.3 V or
GND
IIN
Control pin current Vref_B = 5.5 V, Vref_A = 4.5 V, VEN = 0 to Vref_A IO = 0
±1
µA
Ioff
Power Off
Leakage Current
Vref_B = Vref_A = 0 V, VEN = GND IO = 0, VI = 5 V or GND
±1
µA
CI(ref_A/B/EN)
Input capacitance
VI = 3 V or 0
Cio(off)
I/O pin off-state
capacitance
VO = 3 V or 0, VEN = 0
Cio(on)
I/O pin on-state
capacitance
VO = 3 V or 0, VEN = Vref_A
VIH (EN pin)
High-level input
voltage
Vref_A = 1.5 V to 4.5 V
VIL (EN pin)
Low-level input
voltage
Vref_A = 1.5 V to 4.5 V
VIH (EN pin)
High-level input
voltage
Vref_A= 1.0 V to 1.5 V
VIL (EN pin)
Low-level input
voltage
Vref_A = 1.0 V to 1.5 V
VIK
Input clamp
voltage
II = -18 mA, VEN = 0
IIH
I/O input high
leakage
ICCBA
VI = 0, IO = 32 mA
(1)
(2)
(3)
µA
pF
5.0
6.0
pF
10.5
13
pF
0.7×Vref_A
V
0.3×Vref_A
0.8×Vref_A
0.3×Vref_A
Vref_A = VEN = 3.3 V; Vref_B = 5 V
3
Vref_A = VEN = 1.8 V; Vref_B = 5 V
4
Vref_A = VEN = 1.0 V; Vref_B = 5 V
9
Vref_A = VEN = 1.8 V; Vref_B = 5 V
4
VI = 0, IO = 32 mA , Vref_A = VEN = 2.5 V; Vref_B = 5 V
V
V
10
VI = 0, IO = 64 mA
On-state
resistance
0.2
7
Input transition rise
∆t/∆v (EN pin) or fall rate for EN
pin
ron (2)
MIN
V
ns/V
Ω
Ω
10
Ω
VI = 1.8 V, IO = 15 mA, Vref_A = VEN = 3.3 V; Vref_B = 5 V
5
Ω
VI = 1.0 V, IO = 10 mA, Vref_A = VEN = 1.8 V; Vref_B = 3.3 V
8
Ω
VI = 0 V, IO = 10 mA, Vref_A = VEN = 1.0 V; Vref_B = 3.3 V
6
Ω
VI = 0 V, IO = 10 mA, Vref_A = VEN = 1.0 V; Vref_B = 1.8 V
6
Ω
All typical values are at TA = 25°C.
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is
determined by the lowest voltage of the two (A or B) terminals.
The actual supply current for LSF0204 is ICCA + ICCB; the leakage from Vref_B to Vref_A can be measured on Vref_A and Vref_B pin
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6.6 Switching Characteristics: AC Performance (Translating Down, 3.3 V to 1.8 V)
over recommended operating free-air temperature range, Vrev-A = 1.8 V, Vrev-B = 3.3 V, VEN = 1.8 V, Vpu_1 = 3.3 V,
Vpu_2 = 1.8 V, RL = NA, VIH = 3.3 V, VIL = 0 VM = 1.15 V (unless otherwise noted)
PARAMETER
tPLH
tPHL
tPLZ
tPZL
fMAX
Propagation delay time
(low-to-high output)
Propagation delay time
(high-to-low output)
Disable time
(from low level)
Disable time
Maximum time
TEST CONDITION
(Input) A or B-to-B or A (Output)
(Input) A or B-to-B or A (Output)
(Input) A or B-to-B or A (Output)
(Input) A or B-to-B or A (Output)
(Input) A or B-to-B or A (Output)
TYP
MAX
CL = 50 pF
MIN
0.7
5.49
CL = 30 pF
0.5
5.29
CL = 15 pF
0.3
5.19
CL = 50 pF
0.9
4.9
CL = 30 pF
0.7
4.7
CL = 15 pF
0.5
4.5
CL = 50 pF
13
18
CL = 30 pF
12
16.5
CL = 15 pF
11
15
CL = 50 pF
33
45
CL = 30 pF
30
40
CL = 15 pF
23
37
CL = 50 pF
50
CL = 30 pF
100
CL = 15 pF
100
UNIT
ns
ns
ns
ns
MHz
6.7 Switching Characteristics: AC Performance (Translating Down, 3.3 V to 1.2 V)
over recommended operating free-air temperature range Vrev-A = 1.2 V, Vrev-B = 3.3 V, VEN = 1.2 V, Vpu_1 = 3.3 V,
Vpu_2 = 1.2 V, RL = NA, VIH = 3.3V, VIL = 0 VM = 0.85 V (unless otherwise noted)
PARAMETER
tPLH
tPHL
fMAX
6
Propagation delay time
(low-to-high output)
Propagation delay time
(high-to-low output)
Maximum time
TEST CONDITION
(Input) A or B-to-B or A (Output)
(Input) A or B-to-B or A (Output)
(Input) A or B-to-B or A (Output)
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TYP
MAX
CL = 50 pF
MIN
0.8
4.1
CL = 30 pF
0.5
3.9
CL = 15 pF
0.3
3.8
CL = 50 pF
0.9
4.7
CL = 30 pF
0.7
4.5
4.3
CL = 15 pF
0.6
CL = 50 pF
50
CL = 30 pF
100
CL = 15 pF
100
UNIT
ns
ns
MHz
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6.8 Switching Characteristics: AC Performance (Translating Up, 1.8 V to 3.3 V)
over recommended operating free-air temperature range Vrev-A = 1.8 V, Vrev-B = 3.3 V, VEN = 1.8 V, Vpu_1 = 3.3 V,
Vpu_2 = 1.8V, RL = 500 Ω, VIH = 1.8V,VIL = 0 VM = 0.9V (unless otherwise noted)
PARAMETER
tPLH
tPHL
tPLZ
tPZL
fMAX
Propagation delay time
(low-to-high output)
Propagation delay time
(high-to-low output)
Disable time
(from low level)
Disable time
Maximum time
TEST CONDITION
(Input) A or B-to-B or A (Output)
(Input) A or B-to-B or A (Output)
(Input) A or B-to-B or A (Output)
(Input) A or B-to-B or A (Output)
(Input) A or B-to-B or A (Output)
MIN
TYP
MAX
CL = 50 pF
0.6
CL = 30 pF
0.4
5.3
CL = 15 pF
0.2
5.13
CL = 50 pF
1.3
6.7
CL = 30 pF
1
6.4
CL = 15 pF
0.7
5.3
CL = 50 pF
13
18
CL = 30 pF
12
16.5
CL = 15 pF
11
15
CL = 50 pF
33
45
CL = 30 pF
30
40
37
CL = 15 pF
23
CL = 50 pF
50
CL = 30 pF
100
CL = 15 pF
100
UNIT
5.7
ns
ns
ns
ns
MHz
6.9 Switching Characteristics: AC Performance (Translating Up, 1.2 V to 1.8 V)
over recommended operating free-air temperature range, Vrev-A = 1.2 V, Vrev-B = 1.8 V, VEN = 1.2 V, Vpu_1 = 1.8 V,
Vpu_2 = 1.2 V, RL = 500 Ω, VIH = 1.2V, VIL = 0 VM = 0.6 V (unless otherwise noted)
PARAMETER
tPLH
tPHL
fMAX
TEST CONDITION
Propagation delay time
(Input) A or B-to-B or A (Output)
(low-to-high output)
Propagation delay time
(Input) A or B-to-B or A (Output)
(high-to-low output)
Maximum time
(Input) A or B-to-B or A (Output)
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MIN
TYP
MAX
CL = 50 pF
0.65
7.25
CL = 30 pF
0.4
7.05
CL = 15 pF
0.2
6.85
CL = 50 pF
1.6
7.03
CL = 30 pF
1.3
6.5
5.4
CL = 15 pF
1
CL = 50 pF
50
CL = 30 pF
100
CL = 15 pF
100
UNIT
ns
ns
MHz
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6.10 Typical Characteristics
4
Input
Output
3.5
3
Voltage (V)
2.5
2
1.5
1
0.5
0
-0.5
0
5
10
Time (ns)
15
20
Figure 6-1. Signal Integrity (1.8 V to 3.3 V Translation Up at 50 MHz)
8
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Parameter Measurement Information
The outputs are measured one at a time, with one transition per measurement. All input pulses are supplied by
generators that have the following characteristics:
• PRR ≤ 10 MHz
• ZO = 50 Ω
• Tr ≤ 2 ns
• Tf ≤ 2 ns
VT
RL
S1
Open
From Output
Under Test
S2
CL(1)
A.
CL includes probe and jig capacitance.
Figure 7-1. Load Circuit for Outputs
USAGE
SWITCH
Translating up
Translating down
S1
S2
3.3 V
Input
VM
VM
VIL
5V
Output
VM
VM
VOL
TRANSLATING UP
5V
Input
VM
VM
VIL
2V
Output
VM
VM
VOL
Figure 7-2. Translating Down
Vref_B
S1
500 Ω
Open
From Output
Under Test
15 pF
TEST
S1
tPZL/tPLZ
Vref_B
Figure 7-3. Load Circuit for Enable/Disable Time Measurement
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7.1 Load Circuit AC Waveform for Outputs
tr 2.0 ns
tf 2.0 ns
VCCA
90%
Input
(An, Bn)
50%
10%
GND
VOH
Output
(Bn, An)
VOL
tpLH
tpHL
Figure 7-4. tPLH, tPHL
tr 2.0 ns
tf 2.0 ns
VCCA
90%
Output Enabled
Control OE, OE
50%
10%
GND
tpLZ
tpZL
VOH
Output (An or Bn)
Low to off to Low
50%
10%
Outputs
enabled
Outputs
disabled
Outputs
enabled
Figure 7-5. tPLZ, tPZL
10
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7 Detailed Description
7.1 Overview
The LSF0204-Q1 may be used in level translation applications for interfacing devices or systems operating
at different interface voltages. The LSF0204-Q1 is ideal for use in applications where an open-drain driver is
connected to the data I/Os. LSF0204-Q1 can achieve 100 MHz data rate with the appropriate pull-up resistors
and layout design. The LSF0204-Q1 can also be used in applications where a push-pull driver is connected to
the data I/Os.
7.2 Functional Block Diagram
LSF0204-Q1
200 KΩ
Vref_B
Vref_A
Level Converter
EN
A1
B1
A2
B2
A3
B3
A4
B4
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7.3 Feature Description
7.3.1 Auto-Bidirectional Voltage Translation Without DIR Pin Terminal
The LSF0204-Q1 device is an auto bidirectional voltage level translator that operates from 0.95 V to 4.5 V on
Vref_A and 1.8 V to 5.5 V on Vref_B. This allows bidirectional voltage translation between 0.95 V and 5.5 V
without the need for a direction pin in open-drain or push-pull applications.
7.3.2 Support Multiple High Speed Translation Interfaces
The LSF0204-Q1 device is able to perform voltage translation for open-drain interfaces such as I2C, MDIO,
SMBUS, and PMBUS or push-pull interfaces such as I2S, SPI, UART, SDIO, and GPIO. The LSF0204-Q1
device supports level translation applications with transmission speeds greater than 100 MHz using a 200-Ω
pullup resistor with a 15-pF capacitive load. See the Down Translation with the LSF family and Up Translation
with the LSF family videos.
7.3.3 5-V Tolerance on IO Port and 125°C Support
The LSF0204-Q1, provides up to 5-V over-voltage tolerance on each of its IO channels. The device operating
ambient temperature from –40°C to 125°C is critical in supporting automotive applications.
7.3.4 Channel Specific Translation
The LSF0204-Q1 can work as multi-voltage level translator using specific pullup voltage (Vpu) on each IO
channel. Watch the Multi-Voltage Translation with the LSF Family video.
7.3.5 Ioff, Partial Power Down Mode
When Vref_A or Vref_B = 0, all the data IO pins are in high impedance.
EN logic circuit is referenced to Vref_A supply. No power sequence is required to enable and operate LSF0204Q1.
7.4 Device Functional Modes
Table 7-1 lists the device functional modes of the LSF0204-Q1 device.
Table 7-1. Function Table
(1)
12
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INPUT EN(1) TERMINAL
FUNCTION
H
An = Bn
L
Hi-Z
EN is controlled by Vref_A logic levels.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
LSF0204-Q1 performs voltage translation for open-drain or push-pull interface. Table 8-1 provides examples of
interfaces as reference in regards to the different channel numbers that are supported by the LSF0204-Q1.
Table 8-1. Voltage Translator by Interface
PART NAME
CHANNEL
NUMBER
LSF0204-Q1
4
INTERFACE
Open Drain : I2C, MDIO, SMBus, PMBus, GPIO
Push Pull: GPIO, SPI, I2S, UART, JTAG, SD
8.2 Typical Applications
8.2.1 I2C, PMBus, SMBus, GPIO Application
Vpu_1 = 3.3 V
Vpu_2 = 1.8 V
Vrev_A = 1.8 V Vrev_B = 3.3 V
1.8 V
enable signal
ON
LSF0204-Q1
Rpu
SDA
SCL
A2
A3
A4
Rpu
Rpu
EN
Rpu
A1
Vcc
Off
SW
SW
SW
SW
B1
B2
Vcc
SDA
SCL
B3
B4
GND
Figure 8-1. Bidirectional Translation to Multiple Voltage Levels
8.2.1.1 Design Requirements
8.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines
The LSF0204-Q1 has an EN input that is used to disable the device by setting EN LOW, which places all I/Os
in the high-impedance state. Since LSF0204-Q1 is switch-type voltage translator, the power consumption is very
low. It is recommended to always enable LSF0204-Q1 for bidirectional application (I2C, SMBus, PMBus, or
MDIO).
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Table 8-2. Application Operating Condition
SYMBOL
MIN
Vref_A
Reference voltage (A)
0.8
Vref_B
Reference voltage (B)
VI(EN) (1)
Input voltage on EN terminal
Pull-up supply voltage
Vpu
(1)
PARAMETER
TYP
MAX
UNIT
4.5
V
Vref_A + 0.8
5.5
V
0
Vref_A
V
0
Vref_B
V
Refer VIH and VIL for VI(EN)
Vref_B is recommended to be 1.0 V higher than Vref_A for best signal integrity.
The LSF0204-Q1 device enables multi-voltage translation by using the desired pull up voltage on each of the
channels.
Note
Vref_A must be set as lowest voltage level while using the device in multi-voltage translation
application.
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Bidirectional Translation
The controller output driver may be push-pull (pull-up resistors may be required) or open-drain (pull-up resistors
required) and the peripheral device output can be push-pull or open-drain (pull-up resistors are required to pull
the Bn outputs to Vpu).
Note
However, if either output is push-pull, data must be unidirectional or the outputs must be 3-state and
be controlled by some direction-control mechanism to prevent HIGH-to-LOW contentions in either
direction. If both outputs are open-drain, no direction control is needed.
In Figure 8-1, the reference supply voltage (Vref_A) is connected to the processor core power supply voltage.
When Vref_B is connected through to a 3.3 V Vpu power supply, and Vref_A is set 1.0 V. The output of A3
and B4 has a maximum output voltage equal to Vref_A, and the bidirectional interface (Ch1/2, MDIO) has a
maximum output voltage equal to Vpu.
8.2.1.2.1.1 Pull-Up Resistor Sizing
The pull-up resistor value needs to limit the current through the pass transistor when it is in the ON state to about
15 mA. This ensures a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher
than 15 mA, the pass voltage also is higher in the ON state. To set the current through each pass transistor at 15
mA, to calculate the pull-up resistor value use Equation 1.
Rpu = (Vpu – 0.35 V) / 0.015 A
(1)
Table 8-3 summarizes resistor values, reference voltages, and currents at 15 mA, 10 mA, and 3 mA. The resistor
value shown in the +10% column (or a larger value) should be used to ensure that the pass voltage of the
transistor is 350 mV or less. The external driver must be able to sink the total current from the resistors on both
sides of the LSF0204-Q1 device at 0.175 V, although the 15 mA applies only to current flowing through the
LSF0204-Q1 device.
The LSF0204-Q1 does not provide any drive capability. Therefore higher frequency applications will require
higher drive strength from the host side. No pullup resistor is needed on the host side (3.3 V) if the LSF0204-Q1
is being driven by standard CMOS totem pole output driver. Best practice is to minimize the trace length from the
LSF0204-Q1 on the sink side (1.8 V) to minimize signal degradation.
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Table 8-3. Pull-Up Resistor Values
PULLUP RESISTOR VALUE (Ω)
VDPU
(1)
15 mA
10mA
NOMINAL
+10%(1)
5V
310
3.3 V
2.5 V
3 mA
NOMINAL
+10%(1)
NOMINAL
+10%(1)
341
465
512
1550
1705
197
217
295
325
983
1082
143
158
215
237
717
788
1.8 V
97
106
145
160
483
532
1.5 V
77
85
115
127
383
422
1.2 V
57
63
85
94
283
312
+10% to compensate for VDD range and resistor tolerance.
8.2.1.3 Application Curve
4
Input
Output
Voltage (V)
3
2
1
0
±1
0
50
100
150
200 250 300 350
Time (ns)
400 450
500
Figure 8-2. Captured Waveform From Above I2C Set-Up (1.8 V to 3.3 V at 2.5 MHz)
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8.2.2 MDIO Application
Vpu_1 = 3.3 V
Vpu_2 = 1.0 V
Vrev_A = 1.0 V Vrev_B = 3.3 V
1.0 V
enable signal
ON
LSF0204-Q1
Rpu
SW
MDC
A2
MDIO
Rpu
Rpu
EN
Rpu
A1
Vcc
Off
SW
A3
SW
A4
SW
Vcc
B1
MDC
B2
MDIO
B3
B4
GND
Figure 8-3. Typical Application Circuit (MDIO/Bidirectional Interface)
8.2.2.1 Design Requirements
See the Design Requirements.
8.2.2.2 Detailed Design Procedure
See the Detailed Design Procedure.
8.2.3 Multiple Voltage Translation in Single Device, Application
Vrev_A = 1.8 V
Vrev_B = 3.3 V
Vpu_1 = 3.3 V
Vpu_2 = 1.8 V
1.8 V
enable signal
ON
LSF0204-Q1
Rpu Rpu
MDC
MDIO
A2
A3
A4
Rpu
Rpu
EN
Rpu
A1
Vcc
Off
SW
SW
SW
SW
B1
B2
B3
B4
Vcc
MDC
MDIO
Vpu = 1.0 V
Vcc
GPIO
GPIO
GND
Figure 8-4. Bidirectional Translation to Multiple voltage levels
8.2.3.1 Design Requirements
See the Design Requirements.
8.2.3.2 Detailed Design Procedure
See the Detailed Design Procedure.
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9 Power Supply Recommendations
There are no power sequence requirements for the LSF0204-Q1. See Table 8-2 for recommended operating
voltages for all supply and input pins.
10 Layout
10.1 Layout Guidelines
The signal integrity of the switch-type based LSF0204-Q1 level translator is dependent on the pull-up resistor
and the PCB board parasitic capacitance. Consider the following recommendations when designing with the
LSF0204-Q1:
•
•
•
•
Minimize the trace length to reduce the parasitic capacitance
The trace length should be less than half the time of flight to reduce ringing and line reflections or nonmonotonic behavior in the switching region
Minimize stubs on the signal path
Place the LSF0204-Q1 device near the high voltage side
10.2 Layout Example
Short signal trace
VREF_A
1
14
VREF_B
A1
2
13
B1
A2
3
12
B2
A3
4
11
B3
A4
5
10
B4
NC
6
9
NC
GND
7
8
EN
Minimize stub
Not to scale
Figure 10-1. Short Trace Layout
TP1
SD Controller
(1.8V IO)
LSF0204-Q1
SDIO level translator
SDIO Connector
(3.3V IO)
Device PCB
TP2
Figure 10-2. Device Placement
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TI Logic Minute: Introduction – Voltage Level Translation with the LSF Family video
• Texas Instruments, Voltage-Level Translation with the LSF Family application report
• Texas Instruments, Biasing requirements for TXS, TXB, LSF Translators application report
• Texas Instruments, Factors affecting Vol for TXS and LSF translation devices application report
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LSF0204QPWRQ1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LSF204Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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