OPA365-Q1, OPA2365-Q1
OPA365-Q1,
OPA2365-Q1
SBOS512E – MARCH 2010
– REVISED NOVEMBER
2020
SBOS512E – MARCH 2010 – REVISED NOVEMBER 2020
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OPAx365-Q1 50-MHz Low-Distortion High-CMRR Rail-to-Rail I/O,
Single-Supply Operational Amplifiers
1 Features
3 Description
•
•
The OPAx365-Q1 zero-crossover family, rail-to-rail,
high-performance, CMOS operational amplifiers are
optimized for very low voltage, single-supply
applications. Rail-to-rail input/output, low noise (4.5
nV/√ Hz) and high speed operation (50-MHz gain
bandwidth) make these devices ideal for driving
sampling data converters (such as the ADS7822-Q1
or the ADS1115-Q1), specifically in short to mid-range
radar applications. The OPAx356-Q1 family of
operational amplifiers are also well-suited for HEV/EV
and Powertrain applications in DC-DC converters and
as transmission control in engine control units.
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified with the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C3B
OPA2365-Q1 Functional Safety-Capable:
– Documentation Available to Aid Functional
Safety System Design
Gain Bandwidth: 50 MHz
Zero-Crossover Distortion Topology
– Excellent THD+N: 0.0004%
– CMRR: 100 dB (Minimum)
– Rail-to-Rail Input and Output
– Input 100 mV Beyond Supply Rail
Low Noise: 4.5 nV/√ Hz at 100 kHz
Slew Rate: 25 V/µs
Fast Settling: 0.3 µs to 0.01%
Precision
– Low Offset: 100 µV
– Low Input Bias Current: 0.2 pA
2.2-V to 5.5-V Operation
Special features include an excellent common-mode
rejection ratio (CMRR), no input stage crossover
distortion, high input impedance, and rail-to-rail input
and output swing. The input common-mode range
includes both the negative and positive supplies. The
output voltage swing is within 10 mV of the rails.
The OPA365-Q1 (single version) is available in the 5pin SOT-23 package. The OPA2365-Q1 (dual version)
is available in the 8-pin SOIC package. All versions
are specified for operation from −40°C to 125°C.
Single and dual versions have identical specifications
for maximum design flexibility.
2 Applications
•
•
•
•
•
•
•
•
•
•
•
Device Information (1)
Automotive
ADAS
HEV/EV and Powertrain
Body and Lighting
Blind Spot Detection
Engine Control Units
DC-DC Converters
Short to Mid Range Radars
Collision Warning
Industrial
Heads Up Display
PART NUMBER
PACKAGE
BODY SIZE (NOM)
OPA2365-Q1
SOIC (8)
4.90 mm × 3.91 mm
OPA365-Q1
SOT-23 (5)
2.90 mm × 1.60 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
R2
2kΩ
C2
2.2pF
V−
V−
U1
U2
SD1
BAT17
OPA365
VOUT
OPA365
R1
7.5Ω
VIN
V+
C1
10nF
V+
Fast-Settling Peak Detector
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
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2020 Texas Instruments
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................ 7
7 Detailed Description...................................................... 11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram......................................... 11
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................13
8 Application and Implementation.................................. 14
8.1 Application Information............................................. 14
8.2 Typical Application.................................................... 18
9 Power Supply Recommendations................................20
10 Layout...........................................................................21
10.1 Layout Guidelines................................................... 21
10.2 Layout Example...................................................... 21
11 Device and Documentation Support..........................22
11.1 Documentation Support.......................................... 22
11.2 Support Resources................................................. 22
11.3 Trademarks............................................................. 22
11.4 Electrostatic Discharge Caution.............................. 22
11.5 Glossary.................................................................. 22
12 Mechanical, Packaging, and Orderable
Information.................................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (December 2015) to Revision E (November 2020)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Added Functional Safety-Capable - Documentation information to the Features section.................................. 1
• Updated Related Documentation section ........................................................................................................ 22
Changes from Revision C (April 2012) to Revision D (December 2015)
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1
Changes from Revision B (January 2012) to Revision C (April 2012)
Page
• Added another row with VOS for OPA2365-Q1 only............................................................................................5
• Changed IQ upper limit to 5.3 from 5.5............................................................................................................... 5
2
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5 Pin Configuration and Functions
VOUT
1
V–
2
+IN
5
3
4
V+
VOUTA
1
8
V+
−IN A
2
7
VOUTB
+IN A
3
6
−IN B
V−
4
5
+IN B
–IN
Figure 5-1. DBV Package 5-Pin SOT-23 Top View
Figure 5-2. D Package 8-Pin SOIC Top View
Table 5-1. Pin Functions
PIN
NAME
SOT-23
SOIC
I/O
DESCRIPTION
+IN
3
—
I
Noninverting input
–IN
4
—
I
Inverting input
+IN A
—
3
I
Noninverting input
–IN A
—
2
I
Inverting input
+IN B
—
5
I
Noninverting input
–IN B
—
6
I
Inverting input
V+
5
8
I
Positive (highest) supply
V–
4
4
I
Negative (lowest) supply
VOUT
I
—
O
Output
VOUTA
—
1
O
Output
VOUTB
—
7
O
Output
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
VCC
voltage(2)
VI
Signal input terminals,
II
Signal input terminals, current(2)
tOSC
Output short-circuit duration(3)
TOP
Operating temperature
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
MAX
UNIT
5.5
V
Supply voltage
(V−) − 0.5
(V+) + 0.5
V
–10
10
mA
150
°C
150
°C
150
°C
Continuous
–40
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails
should be current-limited to 10 mA or less.
Short-circuit to ground, one amplifier per package
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002(1)
±2000
Charged-device model (CDM), per AEC Q100-011
±750
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
VS
Supply voltage V– to V+
2.2
3.3
5.5
UNIT
V
TA
Operating free-air temperature
–40
25
125
°C
6.4 Thermal Information
THERMAL METRIC(1)
OPA365-Q1
D (SOIC)
DBV (SOT-23)
UNIT
8 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
115.5
208.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
60.1
123.7
°C/W
RθJB
Junction-to-board thermal resistance
56.9
54.6
°C/W
ψJT
Junction-to-top characterization parameter
9.5
37.2
°C/W
ψJB
Junction-to-board characterization parameter
56.3
36.3
°C/W
(1)
4
OPA2365-Q1
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
VS = 2.2 V to 5.5 V, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA (1)
MIN
TYP
MAX
UNIT
25°C
100
200
µV
25°C
100
230
OFFSET VOLTAGE
VOS
VOS
Input offset voltage
(3)
Input offset voltage
dVOS/ dT Input offset voltage drift
PSRR
Input offset voltage vs
power supply
VS = 2.2 V to 5.5 V
Channel separation, DC
Full range
1
Full range
10
25°C
0.2
25°C
±0.2
µV
µV/°C
100
µV/V
µV/V
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
Full range
±10
pA
±10
pA
See Section 6.6
25°C
±0.2
NOISE
en
Input voltage noise
f = 0.1 Hz to 10 Hz
25°C
5
µVPP
en
Input voltage noise density
f = 100 kHz
25°C
4.5
nV/√ Hz
in
Input current noise density
f = 10 kHz
25°C
4
fA/√ Hz
INPUT VOLTAGE RANGE
VCM
Common-mode voltage
CMRR
Common-mode rejection
ratio
25°C
(V-) – 0.1 V ≤ VCM ≤ (V+) + 0.1 V
Full range
(V-) –
0.1
100
(V+) + 0.1
V
120
dB
INPUT CAPACITANCE
Differential
25°C
6
pF
Common-mode
25°C
2
pF
OPEN-LOOP GAIN
RL = 10 kΩ, 100 mV < VO < (V+) – 100 mV
AOL
Open-loop voltage gain
Full range
100
120
RL = 600 Ω, 200 mV < VO < (V+) – 200 mV
25°C
100
120
dB
RL = 600 Ω, 200 mV < VO < (V+) – 200 mV
Full range
94
25°C
50
MHz
25°C
25
V/µs
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
tS
Settling time
THD+N
Voltage output swing from
rail
RL = 10 kΩ, VS = 5.5 V
VS = 5 V, G = 1
0.1%, VS = 5 V, 4-V Step, G = 1
25°C
200
0.01%, VS = 5 V, 4-V Step, G = 1
25°C
300
Overload recovery time
VS = 5 V, VIN × Gain > VS
25°C
< 0.1
Total harmonic distortion +
noise(2)
VS = 5 V, RL = 600 Ω, VO = 4 VPP,
G = 1, f = 1 kHz
25°C
0.0004%
ns
µs
OUTPUT
Full range
ISC
Short-circuit current
25°C
CL
Capacitive load drive
25°C
Open-loop output
impedance
f = 1 MHz, IO = 0
10
20
±65
mV
mA
See Section 6.6
25°C
30
Ω
POWER SUPPLY
VS
Specified voltage
IQ
Quiescent current per
amplifier
25°C
IO = 0
25°C
Full range
2.2
5.5
4.6
5
5.3
V
mA
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VS = 2.2 V to 5.5 V, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA (1)
MIN
25°C
–40
TYP
MAX
UNIT
125
°C
TEMPERATURE RANGE
Specified
θJA
(1)
(2)
(3)
6
Thermal resistance
SOT23-5
25°C
SO-8
25°C
200
°C/W
Full range TA = −40°C to 125°C
Third-order filter, bandwidth 80 kHz at −3 dB.
For OPA2365-Q1 only
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6.6 Typical Characteristics
TA = 25°C, VS = 5 V, CL = 0 pF (unless otherwise noted)
140
0
140
CMRR
120
Phase
80
−90
60
40
Gain
20
−135
100
PSRR, CMRR (dB)
−45
100
Phase (°)
Voltage Gain (dB)
120
80
PSRR
60
40
20
0
−20
10
100
1k
10k
100k
1M
10M
−180
100M
0
10
100
1k
Frequency (Hz)
10k
100k
1M
10M
100M
Frequency (Hz)
.
.
Figure 6-1. Open-Loop Gain and Phase vs Frequency
Figure 6-2. Power Supply and Common Mode Rejection Ratio
vs Frequency
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
−200
−180
−160
−140
−120
−100
−80
−60
−40
−20
0
20
40
60
80
100
120
140
160
180
200
Population
Population
VS = 5.5V
Offset Voltage Drift (µV/°C)
Offset Voltage (µV)
.
.
Figure 6-3. Offset Voltage Production Distribution
Figure 6-4. Offset Voltage Drift Production Distribution
500
1000
900
400
700
300
600
IB (pA)
Input Bias (pA)
800
500
400
200
VCM Specified Range
300
100
200
100
0
−50
−25
0
25
50
75
100
125
0
−25
−0.5 0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Temperature (°C)
VCM (V)
.
.
Figure 6-5. Input Bias Current vs Temperature
Figure 6-6. Input Bias Current vs Common Mode Voltage
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6.6 Typical Characteristics (continued)
TA = 25°C, VS = 5 V, CL = 0 pF (unless otherwise noted)
3
1
−40°C
−40°C
0
+25°C
+125°C
VS = ±1.1V
VS = ±2.75V
2
Output Voltage (V)
2
Output Voltage (V)
3
VS = ±1.1V
VS = ±2.75V
+25°C
+125°C
−1
−2
1
+25°C
0
+25°C −40°C
+125°C
+125°C
−1
−2
−3
−3
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
Output Current (mA)
50
60
70
80
90
100
.
Figure 6-7. OPA365-Q1 Output Voltage vs Output Current
Figure 6-8. OPA2365-Q1 Output Voltage Swing vs Output
Current
4.75
Dual
Quiescent Current (mA)
70
60
50
40
30
20
10
0
−10
−20
−30
−40
−50
−60
−70
−80
40
Output Current (mA)
.
Short−Circuit Current (mA)
−40°C
Single
VS = ±2.75V
4.50
4.25
4.00
3.75
−50
−25
0
25
50
75
100
125
3.0
2.2 2.5
3.5
4.0
4.5
5.0
5.5
Supply Voltage (V)
Temperature (°C)
.
.
Figure 6-10. Quiescent Current vs Supply Voltage
Figure 6-9. Short-Circuit Current vs Temperature
4.74
4.68
2µV/div
Quiescent Current (mA)
4.80
4.62
4.56
4.50
−50
−25
0
25
50
75
100
Temperature (°C)
125
1s/div
.
.
Figure 6-12. 0.1-Hz to 10-Hz Input Voltage Noise
Figure 6-11. Quiescent Current vs Temperature
8
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6.6 Typical Characteristics (continued)
TA = 25°C, VS = 5 V, CL = 0 pF (unless otherwise noted)
0.01
1k
VO = 1VRMS
0.001
Voltage Noise (nV/ √Hz)
THD+N (%)
G = 10, RL = 600Ω
VO = 1.448VRMS
100
10
VO = 1VRMS
G = +1, RL = 600Ω
0.0001
1
10
100
1k
10k
20k
10
100
Frequency (Hz)
.
10k
100k
.
Figure 6-13. Total Harmonic Distortion + Noise vs Frequency
Figure 6-14. Input Voltage Noise Spectral Density
50
Output Voltage (50mV/div)
60
Overshoot (%)
1k
Frequency (Hz)
G = +1
40
G = −1
30
G = +10
20
10
G=1
RL = 10kΩ
VS = ± 2.5
G = − 10
0
100
0
1k
Time (50ns/div)
Capacitive Load (pF)
.
.
Figure 6-16. Small-Signal Step Response
G=1
RL = 10kΩ
VS = ± 2.5
Output Voltage (50mV/div)
Output Voltage (1V/div)
Figure 6-15. Overshoot vs Capacitive Load
G=1
RL = 600Ω
VS = ± 2.5
Time (250ns/div)
Time (50ns/div)
.
.
Figure 6-17. Large-Signal Step Response
Figure 6-18. Small-Signal Step Response
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6.6 Typical Characteristics (continued)
TA = 25°C, VS = 5 V, CL = 0 pF (unless otherwise noted)
Output Voltage (1V/div)
G=1
RL = 600Ω
VS = ± 2.5
Time (250ns/div)
.
Figure 6-19. Large-Signal Step Response
10
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7 Detailed Description
7.1 Overview
The OPAx365-Q1 zero-crossover family of rail-to-rail, high-performance, CMOS operational amplifiers are
optimized for very low voltage, single-supply applications. Their rail-to-rail input and output, low-noise (4.5 nV/√
Hz), and high-speed operation (50-MHz gain bandwidth) make these devices ideal for driving sampling analogto-digital converters (ADCs). Applications include audio, signal conditioning, and sensor amplification. The highgain bandwidth of 50 MHz makes this family suited for amplifying low signal levels and high frequency such as
radar signal processing .
7.2 Functional Block Diagram
VS
Regulated
Charge Pump
VO U T = VC C +1.8V
VC C + 1. 8 V
IB IA S
Patent Pending
Very Low Ripple
Topology
IB IA S
IBI AS
VIN −
VO U T
VI N +
IB IA S
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7.3 Feature Description
7.3.1 Operating Characteristics
The OPA365-Q1 amplifier parameters are fully specified from 2.2 V to 5.5 V. Many of the specifications apply
from −40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in Section 6.6.
7.3.2 Basic Amplifier Configurations
As with other single-supply operational amplifiers, the OPA365-Q1 may be operated with either a single supply
or dual supplies (see Figure 7-1). A typical dual-supply connection is shown in Figure 7-1, which is accompanied
by a single-supply connection. The OPA365-Q1 device is configured as a basic inverting amplifier with a gain of
−10 V/V. The dual-supply connection has an output voltage centered on zero, while the single− supply
connection has an output centered on the common-mode voltage V CM. For the circuit shown, this voltage is 1.5
V, but may be any value within the common-mode input voltage range. The OPA365-Q1 VCM range extends 100
mV beyond the power-supply rails.
R2
10kΩ
R2
10kΩ
+3V
+1.5V
R1
1kΩ
C1
100nF
V+
OPA365
VIN
C1
100nF
R1
1kΩ
V+
OPA365
V OUT
V IN
V−
V OUT
V−
C2
100nF
V CM =1.5V
−1.5V
a) Dual Supply Connection
b) Single Supply Connection
Figure 7-1. Basic Circuit Connections
Figure 7-2 shows a single-supply, electret microphone application where V CM is provided by a resistive divider.
The divider also provides the bias voltage for the electret element.
49kΩ
Clean 3.3V Supply
3.3V
4kΩ
OPA365
Electret
Microphone
6kΩ
VOUT
5kΩ
1µF
Figure 7-2. Microphone Preamplifier
12
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7.3.3 Input and ESD Protection
The OPA365-Q1 device incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the
case of input and output pins, this protection primarily consists of current steering diodes connected between the
input and power-supply pins. These ESD protection diodes also provide in-circuit, input overdrive protection,
provided that the current is limited to 10 mA as stated in the Section 6.1. Figure 7-3 shows how a series input
resistor may be added to the driven input to limit the input current. The added resistor contributes thermal noise
at the amplifier input and its value should be kept to the minimum in noise-sensitive applications.
V+
I OVERLOAD
10mA max
VOUT
OPA365
VIN
5kΩ
Figure 7-3. Input Current Protection
7.3.4 Rail-to-Rail Input
The OPA365-Q1 product family features true rail-to-rail input operation, with supply voltages as low as ±1.1 V
(2.2 V). A unique zero-crossover input topology eliminates the input offset transition region typical of many railto-rail, complementary stage operational amplifiers. This topology also allows the OPA365-Q1 device to provide
superior common-mode performance over the entire input range, which extends 100 mV beyond both powersupply rails, as shown in Figure 7-4. When driving ADCs, the highly linear VCM range of the OPA365-Q1 device
assures that the operational amplifier/ADC system linearity performance is not compromised.
OFFSET VOLTAGE vs COMMON MODE VOLTAGE
200
VS = ±2.75V
150
100
VOS (µV)
OPA365
50
0
−50
−100
Competitors
−150
−200
−3
−2
−1
0
1
2
3
Common Mode Voltage (V)
Figure 7-4. OPA365-Q1 Has Linear Offset Over the Entire Common-Mode Range
7.4 Device Functional Modes
The OPAx365-Q1 family of devices is powered on when the supply is connected. The device can be operated as
a single-supply operational amplifier or a dual-supply amplifier depending on the application.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Capacitive Loads
The OPA365-Q1 device may be used in applications where driving a capacitive load is required. As with all
operational amplifiers, there may be specific instances where the OPA365-Q1 device can become unstable,
leading to oscillation. The particular operational amplifier circuit configuration, layout, gain and output loading are
some of the factors to consider when establishing whether an amplifier will be stable in operation. An operational
amplifier in the unity-gain (1 V/V) buffer configuration and driving a capacitive load exhibits a greater tendency to
be unstable than an amplifier operated at a higher noise gain. The capacitive load, in conjunction with the
operational amplifier output resistance, creates a pole within the feedback loop that degrades the phase margin.
The degradation of the phase margin increases as the capacitive loading increases.
When operating in the unity-gain configuration, the OPA365-Q1 device remains stable with a pure capacitive
load up to approximately 1 nF. The equivalent series resistance (ESR) of some very large capacitors (CL > 1 µF)
is sufficient to alter the phase characteristics in the feedback loop such that the amplifier remains stable.
Increasing the amplifier closed-loop gain allows the amplifier to drive increasingly larger capacitance. This
increased capability is evident when observing the overshoot response of the amplifier at higher voltage gains.
See Figure 6-15.
One technique for increasing the capacitive load drive capability of the amplifier operating in unity gain is to
insert a small resistor, typically 10 Ω to 20 Ω, in series with the output; see Figure 8-1. This resistor significantly
reduces the overshoot and ringing associated with large capacitive loads. A possible problem with this technique
is that a voltage divider is created with the added series resistor and any resistor connected in parallel with the
capacitive load. The voltage divider introduces a gain error at the output that reduces the output swing. The error
contributed by the voltage divider may be insignificant. For instance, with a load resistance, R L = 10 kΩ, and R S
= 20 Ω, the gain error is only about 0.2%. However, when R L is decreased to 600 Ω, which the OPA365-Q1
device is able to drive, the error increases to 7.5%.
V+
RS
VOUT
OPA365
VIN
10Ω to
20Ω
RL
CL
Figure 8-1. Improving Capacitive Load Drive
14
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8.1.2 Achieving an Output Level of Zero Volts (0 V)
Certain single-supply applications require the operational amplifier output to swing from 0 V to a positive fullscale voltage and have high accuracy. An example is an operational amplifier employed to drive a single-supply
ADC having an input range from 0 V to 5 V. Rail-to-rail output amplifiers with very light output loading may
achieve an output level within millivolts of 0 V (or +V S at the high end), but not 0 V. Furthermore, the deviation
from 0 V only becomes greater as the load current required increases. This increased deviation is a result of
limitations of the CMOS output stage.
When a pulldown resistor is connected from the amplifier output to a negative voltage source, the OPA365-Q1
can achieve an output level of 0 V, and even a few millivolts below 0 V. Below this limit, nonlinearity and limiting
conditions become evident. Figure 8-2 illustrates a circuit using this technique.
V+=+5V
OPA365
VOUT
VIN
500µA
Op Amp
Negative
Supply
Grounded
RP = 10 kΩ
−V = −5V
(Additional
Negative Supply)
Figure 8-2. Swing-to-Ground
A pulldown current of approximately 500 µA is required when OPA365-Q1 is connected as a unity-gain buffer. A
practical termination voltage (V NEG) is −5 V, but other convenient negative voltages also may be used. The
pulldown resistor RL is calculated from RL = [(V O −VNEG)/(500 µA)]. Using a minimum output voltage (VO) of 0 V,
R L = [0 V−(−5V)]/(500 µA)] = 10 kΩ. Keep in mind that lower termination voltages result in smaller pulldown
resistors that load the output during positive output voltage excursions.
This technique does not work with all operational amplifier, and should only be applied to operational amplifiers,
such as the OPA365-Q1, that have been specifically designed to operate in this manner. Also, operating the
OPA365-Q1 output at 0 V changes the output stage operating conditions, resulting in somewhat lower open-loop
gain and bandwidth. Keep these precautions in mind when driving a capacitive load because these conditions
can affect circuit transient response and stability.
8.1.3 Active Filtering
The OPA365-Q1 device is well-suited for active filter applications requiring a wide bandwidth, fast slew rate, lownoise, and single-supply operational amplifier. Figure 8-3 shows a 500 kHz, 2nd-order, low-pass filter utilizing the
multiple-feedback (MFB) topology. The components have been selected to provide a maximally-flat Butterworth
response. Beyond the cutoff frequency, roll-off is −40 dB/dec. The Butterworth response is ideal for applications
requiring predictable gain characteristics such as the anti-aliasing filter used ahead of an ADC.
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R3
549Ω
C2
150pF
V+
R1
549Ω
R2
1.24kΩ
VIN
OPA365
VOUT
C1
1nF
V−
Figure 8-3. Second-Order Butterworth 500-kHz Low-Pass Filter
One point to observe when considering the MFB filter is that the output is inverted, relative to the input. If this
inversion is not required, or not desired, a noninverting output can be achieved through one of these options:
1. adding an inverting amplifier;
2. adding an additional 2nd-order MFB stage;
3. using a noninverting filter topology such as the Sallen-Key (shown in Figure 8-4).
MFB and Sallen-Key, low-pass and high-pass filter synthesis is quickly accomplished using TI's FilterPro
program. This software is available as a free download at www.ti.com.
C3
220pF
R1
1.8kΩ
R2
19.5kΩ
R3
150kΩ
VIN = 1VRMS
C1
3.3nF
C2
47pF
OPA365
VOUT
Figure 8-4. Configured as a 3-Pole, 20 kHz, Sallen-Key Filter
8.1.4 Driving an ADS7822-Q1 Analog-to-Digital Converter
The OPAx365-Q1 operational amplifiers are optimized for driving medium to high speed sampling A/D
converters. The OPAx365-Q1 op amps buffer the A/D’s input capacitance and resulting charge injection while
providing signal gain. Figure 8-5 shows the OPAx365-Q1 in a basic noninverting configuration driving the
ADS7822-Q1. The ADS7822-Q1 is a 12-bit, micro-power sampling converter in the MSOP-8 package. When
used with the low-power, miniature packages of the OPAx365-Q1, the combination is ideal for space-limited, low
power applications. In this configuration, an RC network at the A/D’s input can be used to filter charge injection.
16
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5V
0.1nF
0.1µF
0.1µF
–
V+
100 W
IN+
Vref
ADS7822-Q1
OPA365
IN–
+
1 nF
GND
VIN
0 to 4.096 V
Figure 8-5. Driving the ADS7822-Q1
8.1.5 Driving ADS1115-Q1 Analog-to-Digital Converter
Some applications such as mutli-channels mid range radar need selection between channels. OPA2365-Q1
combined with ADS1115-Q1 fit very well for 2 channels radar selection. The circuit in Figure 8-6 shows the same
band pass filter but the components can be modified for different desired band pass.
The DAS1115-Q1 inputs are set as differential. the inputs accept up the ±2 V. The OPA2365-Q1 flat gain is 100
so the input signal peak is 20 mV.
5V
5V
100 K
0.1 µF
4.7 µF
+
100 K
VDD
AIN0
OPA365
–
AIN1
AIN2
ADS1115-Q1
AIN3
GND
0.22 µF
VIN1
470 W
51 K
5V
100 K
0.1 µF
+
100 K
OPA365
–
0.22 µF
VIN1
470 W
51 K
Figure 8-6. Driving the ADS1115-Q1
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8.2 Typical Application
8.2.1 Fast Settling Peak Detector
R2
2kΩ
C2
2.2pF
V−
V−
U1
U2
SD1
BAT17
OPA365
VOUT
OPA365
R1
7.5Ω
VIN
V+
V+
C1
10nF
Figure 8-7. Fast Settling Peak Detector Schematic
Some applications require peak signal measurement. High unity gain bandwidth, wide supply voltage range, railto-rail input and output, and very low input bias current make the OPA2365-Q1 device very suitable for a peak
detector circuit.
8.2.1.1 Design Requirements
Use the following design parameters for this application:
• Supply voltage: 2.2 V to 5 V
• Input signal: 0 V to 4.5 V
• Input signal frequency: 0 MHz to 1 MHz
8.2.1.2 Detailed Design Procedure
The circuit in Figure 8-7 detects the peak of an input signal and generates a DC output equal to the peak level
VOUT = VINpeak. The capacitor C1 is charged through the SD1 diode and limiting resistor R1. The only
discharging path for C1 is the OPA2365-Q1 very high input impedance. This allows the peak detection of low
frequency and low-duty cycle signal.
8.2.1.3 Application Curves
Figure 8-8. Supply Voltage 2.2 V, Peak Signal 1 V
18
Figure 8-9. Supply Voltage 5 V Peak Signal 4.5 V
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8.2.2 Bandpass Filter 1.5 kHz to 160 kHz and 40-db Flat Gain
V+ = 5 V
100 K
+
OPA365
_
100 K
GND
VOUT
V– = GND
C1 = 0.22 µ
C2 = IopF
VIN
R1 = 470 W
R2 = 51 K
Figure 8-10. Bandpass Filter 1.5 kHz to 160 kHz and 40-db Flat Gain Schematic
8.2.2.1 Design Requirements
Use the following design parameters for this application:
• Supply voltage: 2.2 V to 5 V
• Input signal: 0 V to 25 mV
• Input signal frequency: 0 MHz to 1 MHz
8.2.2.2 Detailed Design Procedure
Some applications need bandpass filter–that is, radar or audio signal precessing. The cross over frequencies
and flat gain can be adjusted by changing the resistors and capacitors value according to applications.
The circuit is designed for 5-V supply and 20-mV input signal. With a flat gain of 100 dB or 40 dB, the peak
output signal is 2 V. The reference signal is at half way of 5 V, which is 2.5 V.
The transfer function or gain =
A zero at =
A pole at =
A pole at =
Vout
R2C1S
=Vin
(1 + R1C1S) (1 + R2C2S)
(1)
1
= 14.2 Hz
2p R2C1
(2)
1
= 1.54 KHz
2p R1C1
(3)
1
= 156 KHz
2p R 2 C2
(4)
Flat Gain of 100 or 40 dB between 1.54 kHz and 156 kHz
(5)
20 db/decade below 1.54 KHz
(6)
–20 dB/decade above 156 kHz
(7)
Bandpass between 1.54 kHz and 156 kHz
(8)
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8.2.2.3 Application Curves
Figure 8-11. Gain Is –3 dB Below the Flat Gain at
1.5 kHz
Figure 8-12. Gain Is –3 dB Above the Flat Gain at
160 kHz
9 Power Supply Recommendations
The OPAx365-Q1 family of devices is specified for operation from 2.2 V to 5.5 V (±1.1 V to ±2.75 V); many
specifications apply from –40°C to 125°C. The Section 6.6 presents parameters that can exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 7 V can permanently damage the device (see Section 6.1).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement, see Section 10.1.
20
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10 Layout
10.1 Layout Guidelines
The OPA365-Q1 is a wideband amplifier. To realize the full operational performance of the device, good highfrequency printed-circuit-board (PCB) layout practices are required. Low-loss 0.1-µF bypass capacitors must be
connected between each supply pin and ground as close to the device as possible. The bypass capacitor traces
should be designed for minimum inductance.
10.2 Layout Example
RIN
+
VIN
VOUT
RG
RF
(Schematic Representation)
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
VS+
RF
NC
NC
±IN
V+
+IN
OUT
V±
NC
RG
GND
VIN
GND
RIN
Only needed for
dual-supply
operation
GND
VS±
(or GND for single supply)
Use low-ESR, ceramic
bypass capacitor
VOUT
Ground (GND) plane on another layer
Figure 10-1. Layout Recommendation
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
Texas Instruments, ADS1258 16-Channel, 24-Bit Analog-to-Digital Converter data sheet
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA2365AQDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
O2365Q
OPA365AQDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
OTNQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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