PCM1716

® PCM 49% 171 FPO 6 PCM1716 24-Bit, 96kHz Sampling CMOS Delta-Sigma Stereo Audio DIGITAL-TO-ANALOG CONVERTER TM FEATURES q ENHANCED MULTI-LEVEL DELTA-SIGMA DAC q SAMPLING FREQUENCY (fs): 16kHz - 96kHz q INPUT AUDIO DATA WORD: 16-, 20-, 24-Bit q HIGH PERFORMANCE: THD+N: –96dB Dynamic Range: 106dB SNR: 106dB Analog Output Range: 0.62 x VCC (Vp-p) q 8x OVERSAMPLING DIGITAL FILTER: Stop Band Attenuation: –82dB Passband Ripple: ±0.002dB Slow Roll Off q MULTI FUNCTIONS: Digital De-emphasis L/R Independent Digital Attenuation Soft Mute Zero Detect Mute Zero Flag Chip Select Reversible Output Phase q +5V SINGLE SUPPLY OPERATION q SMALL 28-LEAD SSOP PACKAGE BCKIN LRCIN DIN Serial Input I/F DESCRIPTION The PCM1716 is designed for Mid to High grade Digital Audio applications which achieve 96kHz sampling rates with 24-bit audio data. PCM1716 uses a newly developed, enhanced multi-level delta-sigma modulator architecture that improves audio dynamic performance and reduces jitter sensitivity in actual applications. The internal digital filter operates at 8x over sampling at a 96kHz sampling rate, with two kinds of roll-off performances that can be selected: sharp roll-off, or slow roll-off, as required for specific applications. PCM1716 is suitable for Mid to High grade audio applications such as CD, DVD-Audio, and Music Instruments, since the device has superior audio dynamic performance, 24-bit resolution and 96kHz sampling. AGND2L VCC2L VCC2R AGND2L DAC 8X Oversampling Digital Filter with Function Controller Enhanced Multi-level Delta-Sigma Modulator DAC Low-pass Filter VOUTL EXTL ML/IIS MC/DM1 MD/DM0 CS/IWO MODE MUTE RST Crystal/OSC Mode Control I/F Low-pass Filter VOUTR EXTR ZERO SCK BPZ-Cont. Open Drain Power Supply XTI XTO CLKO VCC1 AGND1 VDD DGND International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1997 Burr-Brown Corporation PDS-1415C Printed in U.S.A. August, 1998 SPECIFICATIONS All specifications at +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, and 24-bit input data, SYSCLK = 384fS, unless otherwise noted. PCM1716 PARAMETER RESOLUTION DATA FORMAT Audio Data Interface Format Data Bit Length Audio Data Format Sampling Frequency (fS) System Clock Frequency(1) DIGITAL INPUT/OUTPUT LOGIC LEVEL Input Logic Level VIH VIL Output Logic Level (CLKO) VOH VOL CLKO PERFORMANCE(2) Output Rise Time Output Fall Time Output Duty Cycle DYNAMIC PERFORMANCE(3) (24-Bit Data) THD+N VO = 0dB VO = –60dB Dynamic Range Signal-to-Noise Ratio(4) Channel Separation DYNAMIC PERFORMANCE(3) (16-Bit Data) THD+N VO = 0dB Dynamic Range DC ACCURACY Gain Error Gain Mismatch: Channel-to-Channel Bipolar Zero Error ANALOG OUTPUT Output Voltage Center Voltage Load Impedance DIGITAL FILTER PERFORMANCE Filter Characteristics 1 (Sharp Roll-Off) Passband Stopband Passband Ripple Stopband Attenuation Filter Characteristics 2 (Slow Roll-Off) Passband Stopband Passband Ripple Stopband Attenuation Delay Time De-emphasis Error INTERNAL ANALOG FILTER –3dB Bandwidth Passband Response POWER SUPPLY REQUIREMENTS Voltage Range Supply Current: ICC +IDD Power Dissipation TEMPERATURE RANGE Operation Storage CONDITIONS MIN TYP 24 Standard/I2S 16/20/24 Selectable MSB First, 2’s Comp 16 256/384/512/768fS 2.0 0.8 IOH = 2mA IOL = 4mA 20 ~ 80% VDD, 10pF 80 ~ 20% VDD, 10pF 10pF Load fS = 44.1kHz fS = 96kHz fS = 44.1kHz fS =44.1kHz EIAJ A-weighted fS = 96kHz A-weighted fS =44.1kHz EIAJ A-weighted fS = 96kHz A-weighted fS = 44.1kHz fS = 96kHz fS = 44.1kHz fS = 96kHz fS = 44.1kHz EIAJ A-weighted fS = 96kHz A-weighted 98 98 96 4.5 0.5 5.5 4 37 –97 –94 –42 106 103 106 103 102 101 –94 –92 98 97 ±1.0 ±1.0 ±30 0.62 VCC 0.5 VCC 5 ±3.0 ±3.0 ±60 –90 V V V V ns ns % dB dB dB dB dB dB dB dB dB dB dB dB dB % of FSR % of FSR mV Vp-p V kΩ 96 kHz MAX UNITS Bits VO = 0.5VCC at Bipolar Zero Full Scale (0dB) AC Load ±0.002dB –3dB 0.546fS Stop Band = 0.546fS Stop Band = 0.567fS ±0.002dB –3dB 0.732fS Stopband = 0.732fS –82 30/fS –75 –82 0.454fS 0.490fS ±0.002 dB dB dB 0.274fS 0.454fS ±0.002 ±0.1 dB dB sec dB kHz dB 5.5 45 225 VDC mA mA mW mW °C °C f = 20kHz VDD, VCC fS = 44.1kHz fS = 96kHz fS = 44.1kHz fS = 96kHz 4.5 100 –0.16 5 32 45 160 225 –25 –55 +85 +100 NOTES: (1) Refer section of system clock. (2) External buffer is recommended. (3) Dynamic performance specs are tested with 20kHz low pass filter and THD+N specs are tested with 30kHz LPF, 400Hz HPF, Average Mode. (4) SNR is tested at internally infinity zero detection off. ® PCM1716 2 PIN CONFIGURATION PIN ASSIGNMENTS PIN 1 NAME LRCIN DIN BCKIN CLKO XTI XTO DGND VDD VCC2R AGND2R EXTR NC VOUTR AGND1 VCC1 VOUTL NC EXTL AGND2L VCC2L ZERO RST CS/IWO MODE MUTE MD/DM0 MC/DM1 ML/I2S I/O IN IN IN OUT IN OUT — — — — OUT — OUT — — OUT — OUT — — OUT IN IN IN IN IN IN IN DESCRIPTION Left and Right Clock Input. This clock is equal to the sampling rate - fS.(1) Serial Audio Data Input(1) Bit Clock Input for Serial Audio Data.(1) Buffered Output of Oscillator. Equivalent to System Clock. Oscillator Input (External Clock Input) Oscillator Output Digital Ground Digital Power +5V Analog Power +5V Analog Ground Rch, Common Pin of Analog Output Amp No Connection Rch, Analog Voltage Output of Audio Signal Analog Ground Analog Power +5V Lch, Analog Voltage Output of Audio Signal No Connection Lch, Common Pin of Analog Output Amp Analog Ground Analog Power +5V Zero Data Flag Reset. When this pin is low, the DF and modulators are held in reset.(2) Chip Select/Input Format Selection. When this pin is low, the Mode Control is effective.(3) Mode Control Select. (H: Software, L: Hardware)(2) Mute Control Mode Control, DATA/De-emphasis Selection 1(2) Mode Control, BCK/De-emphasis Selection 2(2) Mode Control, WDCK/Input Format Selection(2) LRCIN DIN BCKIN CLKO XTI XTO DGND VDD VCC2R 1 2 3 4 5 6 7 PCM1716E 8 9 28 ML/IIS 27 MC/DM1 26 MD/DM0 25 MUTE 24 MODE 23 CS/IWO 22 RST 21 ZERO 20 VCC2L 19 18 17 16 15 AGND2L EXTL NC VOUTL VCC1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 AGND2R 10 EXTR 11 NC 12 VOUTR 13 AGND1 14 PACKAGE INFORMATION PRODUCT PCM1716E PACKAGE 28-Pin SSOP PACKAGE DRAWING NUMBER(1) 324 24 25 26 27 28 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. NOTES: (1) Pins 1, 2, 3; Schmitt Trigger input. (2) Pins 22, 24, 25, 26, 27, 28; Schmitt Trigger input with pull-up resister. (3) Pin 23; Schmitt Trigger input with pull-down resister. ABSOLUTE MAXIMUM RATINGS Power Supply Voltage ...................................................................... +6.5V +VCC to +VDD Difference ................................................................... ±0.1V Input Logic Voltage .................................................. –0.3V to (VDD + 0.3V) Input Current (except power supply) ............................................... ±10mA Power Dissipation .......................................................................... 400mW Operating Temperature Range ......................................... –25°C to +85°C Storage Temperature ...................................................... –55°C to +125°C Lead Temperature (soldering, 5s) ................................................. +260°C ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 PCM1716 TYPICAL PERFORMANCE CURVES All specifications at +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, and 24-bit input data, SYSCLK = 384fS, unless otherwise noted. THD+N vs SAMPLING FREQUENCY (VCC = VDD = 5V, 24-Bit) 88 10 THD+N vs LEVEL (fS = 44.1kHz) –20 –30 91 THD+N at F/S (dB) THD+N (%) 1 16-Bit 0.1 –40 –50 –60 –70 THD+N (dB) 94 256fs 97 0.010 100 384fs 0.001 32 44.1 48 96 –60 –50 24-Bit –80 –90 –100 103 Sampling Frequency fS (kHz) –40 –30 Amplitude (dB) –20 –10 0 110 DYNAMIC RANGE vs SAMPLING FREQUENCY (VCC = VDD = 5V, 24-Bit) 110 SNR vs SAMPLING FREQUENCY (VCC = VDD = 5V, 24-Bit) Dynamic Range (A-weighted) (dB) 106 256/384fS 104 SNR (A-weighted) (dB) 108 108 106 256/384fS 104 102 102 100 32 44.1 48 96 Sampling Frequency fS (kHz) 100 32 44.1 48 96 Sampling Frequency fS (kHz) –60 –70 –80 –60dB OUTPUT SPECTRUM (f = 1kHz, fS = 44.1kHz, 16-Bit Data) –60 –70 –80 –60dB OUTPUT SPECTRUM (f = 1kHz, fS = 44.1kHz, 24-Bit Data) Amplitude (dB) –100 –110 –120 –130 –140 –150 20 2 4 6 8 10 12 14 16 18 20 Frequency (Hz) Amplitude (dB) –90 –90 –100 –110 –120 –130 –140 –150 20 2 4 6 8 10 12 14 16 18 20 Frequency (Hz) ® PCM1716 4 TYPICAL PERFORMANCE CURVES (CONT) OVERALL FREQUENCY CHARACTERISTIC (Sharp Roll-Off) 0 –20 –40 Amplitude (dB) PASSBAND RIPPLE CHARACTERISTIC (Sharp Roll-Off) 0.003 0.002 Amplitude (dB) –60 –80 –100 –120 0.001 0 –0.001 –0.002 –140 –160 –0.003 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.1 0.2 0.3 0.4 0.5 Frequency (x fS) Frequency (x fS) OVERALL FREQUENCY CHARACTERISTIC (Slow Roll-Off) 0 –20 Amplitude (dB) Amplitude (dB) 0 –2 –4 FREQUENCY CHARACTERISTIC (Slow Roll-Off) –40 –60 –80 –100 –120 –140 0 0.5 1 1.5 2 2.5 3 3.5 4 –6 –8 –10 –12 –14 –16 –18 –20 0 0.1 0.2 0.3 Frequency (x fS) 0.4 0.5 0.6 Frequency (x fS) 0 –2 –4 –6 –8 –10 0 DE-EMPHASIS FREQUENCY RESPONSE (fS = 32kHz) 0.5 0.3 0.1 –0.1 –0.3 –0.5 0 2 DE-EMPHASIS ERROR (fS = 32kHz) Level (dB) 2 4 6 8 10 12 14 Level (dB) 4 6 8 10 12 14 Frequency (kHz) DE-EMPHASIS FREQUENCY RESPONSE (fS = 44.1kHz) Frequency (kHz) DE-EMPHASIS ERROR (fS = 44.1kHz) 0 –2 –4 –6 –8 –10 0 0.5 0.3 0.1 –0.1 –0.3 –0.5 0 2 Level (dB) 2 4 6 8 10 12 14 16 18 20 Level (dB) 4 6 8 10 12 14 16 18 20 Frequency (kHz) DE-EMPHASIS FREQUENCY RESPONSE (fS = 48kHz) Frequency (kHz) DE-EMPHASIS ERR0R (fS = 48kHz) 0 –2 –4 –6 –8 –10 0 0.5 0.3 0.1 –0.1 –0.3 –0.5 0 2 4 Level (dB) 2 4 6 8 10 12 14 16 18 20 22 Level (dB) 6 8 10 12 14 16 18 20 22 ® Frequency (kHz) Frequency (kHz) 5 PCM1716 SYSTEM CLOCK The system clock for PCM1716 must be either 256fS, 384fS, 512fS or 768fS, where fS is the audio sampling frequency (typically 32kHz, 44.1kHz, 48kHz, or 96kHz). But 768fS at 96kHz is not accepted. The system clock can be either a crystal oscillator placed between XTI (pin 5) and XTO (pin 6), or an external clock input to XTI. If an external system clock is used, XTO is open (floating). Figure 1 illustrates the typical system clock connections. PCM1716 has a system clock detection circuit which automatically senses if the system clock is operating at 256fS ~ 768fS. The system clock should be synchronized with LRCIN (pin 1) clock. LRCIN (left-right clock) operates at the sampling frequency fS. In the event these clocks are not synchronized, PCM1716 can compensate for the phase difference internally. If the phase difference between left-right and system clocks is greater than 6-bit clocks (BCKIN), the synchronization is performed internally. While the synchronization is processing, the analog output is forced to a DC level at bipolar zero. The synchronization typically occurs in less than 1 cycle of LRCIN. Typical input system clock frequencies to the PCM1716 are shown in Table I, also, external input clock timing requirements are shown in Figure 2. tSCKH “H” XTI “L” tSCKL System Clock Pulse Width High tSCKIH : 7ns MIN System Clock Pulse Width Low tSCKIL : 7ns MIN 2.0V 0.8V FIGURE 2. XTI Clock Timing. DATA INTERFACE FORMATS Digital audio data is interfaced to PCM1716 on pins 1, 2, and 3, LRCIN (left-right clock), DIN (data input) and BCKIN (bit clock). PCM1716 can accept both standard, I2S, and left justified data formats. Figure 3 illustrates acceptable input data formats. Figure 4 shows required timing specification for digital audio data. Reset Externl Clock Input 4 System Clock (256/384/ 512/768fS) CLKO 5 XTI 6 XTO PCM1716 PCM1716 has both internal power-on reset circuit and the RST pin (pin 22) which accepts an external forced reset by RST = LOW. For internal power on reset, initialize (reset) is done automatically at power on VDD >2.2V (typ). During internal reset = LOW, the output of the DAC is invalid and the analog outputs are forced to VCC /2. Figure 5 illustrates the timing of the internal power on reset. PCM1716 accepts an external forced reset when RST = L. When RST = L, the output of the DAC is invalid and the analog outputs are forced to VCC /2 after internal initialization (1024 system clocks count after RST = H.) Figure 6 illustrates the timing of the RST pin. Zero Out (pin 21) If the input data is continuously zero for 65536 cycles of BCK, an internal FET is switched to “ON”. The drain of the internal FET is the zero-pin, it will enable “wired-or” with external circuit. This zero detect function is available in both software mode and hardware mode. Crystal Resonator Oscillation System Clock Buffer Out 4 Buffer C1 C2 C1 C2 : 10pF ~ 30pF XTAL 5 XTI CLKO 6 XTO PCM1716 FIGURE 1. System Clock Connection. SYSTEM CLOCK FREQUENCY - MHz SAMPLING RATE FREQUENCY (fS) - LRCIN 32kHz 44.1kHz 48kHz 96kHz 256fS 8.1920 11.2896 12.2880 24.5760 384fS 12.2880 16.9340 18.4320 36.8640(1) 512fS 16.3840 22.5792 24.5760 49.1520(1) 768fS 24.5760 33.8688(1) 36.8640(1) — NOTE: (1) The Internal Crystal oscillator frequency cannot be larger than 24.576MHz. TABLE I. Typical System Clock Frequency. ® PCM1716 6 1/fS L_ch LRCIN (pin 1) BCKIN (pin 3) (1) 16-Bit Right Justified DIN (pin 2) 14 15 16 1 2 3 MSB 1 2 3 MSB 1 2 3 MSB 1 2 3 MSB 22 LSB 1/fS LRCIN (pin 1) BCKIN (pin 3) (5) 16-Bit I2S DIN (pin 2) 1 2 3 MSB 1 2 3 MSB 14 LSB 22 LSB 23 24 1 2 15 16 1 2 3 MSB 3 MSB 14 LSB 22 LSB 23 24 1 2 15 16 1 2 L_ch R_ch 23 24 14 LSB 18 LSB 22 LSB 1 2 3 MSB 23 24 1 2 19 20 1 2 3 MSB 3 MSB 22 LSB 23 24 15 16 1 2 3 MSB 14 LSB 18 LSB 22 LSB 23 24 19 20 15 16 R_ch (2) 20-Bit Right Justified DIN (pin 2) 18 19 20 (3) 24-Bit Right Justified DIN (pin 2) 23 24 (4) 24-Bit Left Justified DIN (pin 2) (6) 24-Bit I2S DIN (pin 2) FIGURE 3. Audio Data Input Formats. LRCKIN tBCH BCKIN tBCY DIN tDS tDH tBL tBCL tLB 1.4V 1.4V 1.4V BCKIN Pulse Cycle Time BCKIN Pulse Width High BCKIN Pulse Width Low : tBCY : tBCH : tBCL : 100ns (min) : 50ns (min) : 50ns (min) : 30ns (min) : 30ns (min) : 30ns (min) : 30ns (min) BCKIN Rising Edge to LRCIN Edge : tBL LRCIN Edge to BCKIN Rising Edge : tLB DIN Set-up Time DIN Hold Time : tDS : tDH FIGURE 4. Audio Data Input Timing Specification. ® 7 PCM1716 VCC = VDD Reset Reset Removal Internal Reset 1024 system (= XTI) clocks XTI Clock FIGURE 5. Internal Power-On Reset Timing. RST tRST(1) Reset Reset Removal Internal Reset 1024 system (XTI) clocks XTI Clock NOTE: (1) tRST = 20ns min. FIGURE 6. External Forced Reset Timing. FUNCTIONAL DESCRIPTION PCM1716 has several built-in functions including digital attenuation, digital de-emphasis, input data format selection, and others. These functions are software controlled. PCM1716 can be operated in two different modes, software mode or hardware mode. Software mode is a three-wire interface using pin 28 (ML), 27 (MC), and 26 (MD). PCM1716 can also be operated in hardware mode, where static control signals are used on pin 28 (115, pin 27 (DM1), pin 26 (DM0) and pin 23 (IWO). This basic operation mode as software or hardware can be selected by pin 24 (MODE) as shown in Table II. MODE (pin 24) = H MODE (pin 24) = L Software Mode Hardware Mode FUNCTION Input Data Format Selection Input Data Bit Selection Input LRCIN Polarity Selection De-emphasis Control Mute Attenuation Infinity Zero Mute Control DAC Operation Control Slow Roll-Off Selection Output Phase Selection CLKO Output Selection SOFTWARE (Mode = H) O O O O O O O O O O O HARDWARE (Mode = L) O O X O O X X X X X X NOTE: O = Selectable, X: Not Selectable. TABLE III. Mode Control, Selectable Functions. HARDWARE MODE (MODE = L) In hardware mode, the following function can be selected. De-emphasis control De-emphasis control can be selected by DM1 (pin 27) and DM0 (pin 26) TABLE II. Mode Control. Table III indicates which functions are selectable within the users chosen mode. All of the functions shown are selectable within the software mode, but only de-emphasis control, soft mute and input data format may be selected when using PCM1716 in the hardware mode. ® PCM1716 8 DM1 (Pin 27) L L H H DM0 (Pin 26) L H L H DE-EMPHASIS OFF 48kHz 44.1kHz 32kHz FUNCTION Input Audio Data Format Selection Standard Format Left Justified I2S Format Input Audio Data Bit Selection 16-Bit 20-Bit 24-Bit Input LRCIN Polarity Selection Lch/Rch = High/Low Lch/Rch = Low/High De-emphasis Control Soft Mute Control DEFAULT MODE Standard Format TABLE IV. De-emphasis Control. Input Audio Data Format Input data format can be selected by I2S (pin 28) and IWO (pin 23) I2S (Pin 28) IWO (Pin 23) L L H H L H L H DATA FORMAT 16-Bit Data Word, Normal, Right Justified 20-Bit Data Word, Normal, Right Justified 16-Bit Data Word, I2S Format 24-Bit Data Word, I2S Format 16-Bit Lch/Rch = High/Low OFF OFF 0dB, Individual Not Operated Operated Attenuation Control Lch, Rch Individually Lch, Rch Common Infinite Zero Mute Control DAC Operation Control Sampling Rate Selection for De-emphasis Standard Frequency 44.1kHz 48kHz 32kHz Slow Roll-Off Selection Output Phase Selection TABLE V. Data Format Control. SOFT MUTE Soft Mute function can be controlled by MUTE (pin 25) MUTE (Pin 25) L H SOFT MUTE Mute ON Mute OFF (Normal Operation) 44.1kHz Not Selected (Sharp Roll-Off) Not Inverted Input Frequency CLK0 Output Selection TABLE VI. Selectable Functions and Default. PROGRAM REGISTER BIT MAPPING PCM1716’s special functions are controlled using four program registers which are 16 bits long. These registers are all loaded using MD. After the 16 data bits are clocked in, ML is used to latch in the data to the appropriate register. Table VII shows the complete mapping of the four registers and Figure 7 illustrates the serial interface timing. SOFTWARE MODE (MODE = H) PCM1716’s special functions at software mode is shown in Table VI. These functions are controlled using a ML, MC, MD serial control signal. MAPPING OF PROGRAM REGISTERS B15 MODE0 MODE1 MODE2 MODE3 res res res res B14 res res res res B13 res res res res B12 res res res res B11 res res res res B10 A1 A1 A1 A1 B9 A0 A0 A0 A0 B8 LDL LDR res IZD B7 AL7 AR7 res SF1 B6 AL6 AR6 res SF0 B5 AL5 AR5 res CK0 B4 AL4 AR4 IW1 REV B3 AL3 AR3 IW0 SR0 B2 AL2 AR2 OPE ATC B1 AL1 AR1 DEM LRP B0 AL0 AR0 MUT I2S ML (pin 28) MC (pin 27) MD (pin 26) B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 FIGURE 7. Three-Wire Serial Interface. ® 9 PCM1716 REGISTER NAME Register 0 BIT NAME AL (7:0) LDL A (1:0) res AR (7:0) LDR A (1:0) res MUT DEM OPE IW (1:0) res A (1:0) res I2S LRP ATC SRO REV CKO SF (1:0) IZD A (1:0) res REGISTER 2 (A1 = 1, A0 = 0) DESCRIPTION DAC Attenuation Data for Lch Attenuation Data Load Control for Lch Register Address Reserved, should be “L” DAC Attenuation Data for Rch Attenuation Data Load Control for Rch Register Address Reserved, should be “L” Left and Right DACs Soft Mute Control De-emphasis Control Left and Right DACs Operation Control Input Audio Data Bit and Format Select Reserved Register Address Reserved, should be “L” Audio Data Format Select Polarity of LRCIN Select Attenuator Control Slow Roll-Off Select Output Phase Select CLKO Output Select Sampling Rate Select Internal Zero Detection Circuit Control Register Address Reserved, should be “L” B15 B14 B13 B12 B11 B10 B9 B8 res res res res res A1 A0 res B7 B6 B5 B4 B3 B2 B1 B0 res res res IW1 IWO OPE DEM MUTE Register 1 Register 2 is used to control soft mute, de-emphasis, operation enable, input resolution, and input audio data bit and format. MUT (B0) MUT = L MUT = H Soft Mute OFF Soft Mute ON Register 2 Register 3 DEM (B1) DEM = L DEM = H De-emphasis OFF De-emphasis ON OPE (B2) OPE = L OPE = H Normal Operation DAC Operation OFF TABLE VII. Register Functions REGISTER 0 (A1 = 0, A0 = 0) B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0 when OPE (B2) is “HIGH”, the output of the DAC will be forced to bipolar zero, irrespective of any input data. IWO (B3), IW1 (B4) and I2S (B0) of Register 3 These resisters, IWO, IW1, I2S determine the input data word and input data format as shown below. Register 0 is used to control left channel attenuation. Bits 0 - 7 (AL0 - AL7) are used to determine the attenuation level. The level of attenuation is given by: ATT = 0.5 x (data-255) (dB) FFh = –0dB FEh = –0.5dB : : 01h = –127.5dB 00h = – ∞ (= Mute) ATTENUATION DATA LOAD CONTROL Bit 8 (LDL) is used to control the loading of attenuation data in B0:B7. When LDL is set to 0, attenuation data will be loaded into AL0:AL7, but it will not affect the attenuation level until LDL is set to 1. LDR in Register 1 has the same function for right channel attenuation. REGISTER 1 (A1 = 0, A0 = 1) B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 IW1 0 0 1 1 0 0 1 1 IW0 0 1 0 1 0 1 0 1 I2S 0 0 0 0 1 1 1 1 Audio Interface 16-Bit Standard (Right-Justified) 20-Bit Standard (Right-Justified) 24-Bit Standard (Right-Justified) 24-Bit Left-Justified (MSB First) 16-Bit I2S 24-Bit I2S Reserved Reserved REGISTER 3 (A1 = 1, A0 = 1) B15 B14 B13 B12 B11 B10 B9 B8 res res res res res A1 A0 IZD B7 B6 B5 B4 B3 B2 B1 B0 SF1 SF0 CKO REV SRO ATC LRP I2S REGISTER 3 (A1 = 1, A0 = 1) Register 3 is used to control input data format and polarity, attenuation channel control, system clock frequency, sampling frequency, infinite zero detection, output phase, CLKO output, and slow roll-off. Bit 8 is used to control the infinite zero detection function (IZD). When IZD is “LOW”, the zero detect circuit is off. Under this condition, no automatic muting will occur if the input is continuously zero. When IZD is “HIGH”, the zero detect feature is enabled. If the input data is continuously zero for 65, 536 cycles of BCKIN, the output will be immediately Register 1 is used to control right channel attenuation. As in Register 1, bits 0 - 7 (AR0 - AR7) control the level of attenuation. ® PCM1716 10 forced to a bipolar zero state (VCC / 2). The zero detection feature is used to avoid noise which may occur when the input is DC. When the output is forced to bipolar zero, there may be an audible click. PCM1716 allows the zero detect feature to be disabled so the user can implement an external muting circuit. IZD (B8) B8 = L B8 = H Zero Detect Mute OFF Zero Detect Mute ON SRO (B3) is roll-off performance of digital filter selection. SRO = L SRO = H Sharp Roll-Off Slow Roll-Off ATC (B2) is used as an attenuation control. When bit 3 is set HIGH, the attenuation data on Register 0 is used for both channels, and the data in Register 1 is ignored. When bit 3 is LOW, each channel has separate attenuation data. ATC = L Ch Individual ATT Control Common ATT Control Bits 6 (SF0) and 7 (SF1) are used to select the sampling frequency for De-emphasis. SF1 0 0 1 1 SF0 0 1 0 1 Sampling Rate Reserved 48kHz 44.1kHz 32kHz ATC = H CKO (B5) is output frequency control at CLKO pin, can be selected as Buffer (1/1) or half rate of input frequency (1/2). CKO = L CKO = H Buffer Out of XTi Clock Half (1/2) Frequency Out of XTi Clock Bits 0 (I2S) and 1 (LRP) are used to control the input data format. A “LOW” on bit 0 sets the format to (MSB-first, right-justified Japanese format) and a “HIGH” sets the format to I2S (Philips serial data protocol). Bit 1 (LRP) is used to select the polarity of LRCIN (sample rate clock). When bit 1 is “LOW”, left channel data is assumed when LRCIN is in a “HIGH” phase and right channel data is assumed when LRCIN is in a “LOW” phase. When bit 1 is “HIGH”, the polarity assumption is reversed. LRP = L L L R R H/Lch L/Lch REF (B4) is output analog signal phase control. REV = L REV = H Normal Output Inverted Output LRP = H tMLL ML tMCH MC tMCY LSB tMCL tMLH tMHH 1.4V tMLS 1.4V MD tMDS tMDH 1.4V tCSML tMLCS 1.4V CS MC Pulse Cycle Time MC Pulse Width LOW MC Pulse Width HIGH MD Hold Time MD Set-up Time ML Low Level Time ML High Level Time ML Hold Time ML Set-up Time CS Low to ML Low Time(2) ML High to CS High Time(2) : tMCY : tMCL : tMCH : tMDH : tMDS : tMLL : tMHH : tMLH : tMLS : tCSML : tMLCS : 100ns (min) : 40ns (min) : 40ns (min) : 40ns (min) : 40ns (min) : 40ns (min) + 1SYSCLK(1) (min) : 40ns (min) + 1SYSCLK(1) (min) : 40ns (min) : 40ns (min) : 10ns (min) : 10ns (min) NOTE: (1) System Clock Cycle. (2) CS Should be changed during ML = H. FIGURE 8. Program Register Input Timing. ® 11 PCM1716 THEORY OF OPERATION The delta-sigma section of PCM1716 is based on a 8-level amplitude quantizer and a 4th-order noise shaper. This section converts the oversampled input data to 8-level deltasigma format. This newly developed, “Enhanced Multi-level Delta-Sigma” architecture achieves high-grade audio dynamic performance and sound quality. A block diagram of the 8-level delta-sigma modulator is shown in Figure 9. This 8-level delta-sigma modulator has the advantage of stability and clock jitter sensitivity over the typical one-bit (2 level) delta-sigma modulator. The combined oversampling rate of the delta-sigma modulator and the internal 8-times interpolation filter is 64fS for all system clock ratios (256/384/512/768fS). The theoretical quantization noise performance of the 8-level delta-sigma modulator is shown in Figure 10. This enhanced multi-level delta-sigma architecture also has advantages for input clock jitter sensitivity due to the multilevel quantizer, simulated jitter sensitivity is shown in Figure 11. – + + Z–1 + Z–1 + Z–1 + Z–1 + 8-Level Quantizer FIGURE 9. 8-Level Delta-Sigma Modulator. CLOCK JITTER 0 –20 Dynamic Range (dB) –40 Amplitude (dB) 125 120 115 110 105 100 95 90 85 80 –60 –80 –100 –120 –140 –160 –180 0 1 2 3 4 5 6 7 8 Frequency (fS) 0 100 200 300 Jitter (ps) 400 500 600 FIGURE 10. Quantization Noise Spectrum. FIGURE 11. Jitter Sensitivity. ® PCM1716 12 APPLICATION CONSIDERATIONS DELAY TIME There is a finite delay time in delta-sigma converters. In A/D converters, this is commonly referred to as latency. For a delta-sigma D/A converter, delay time is determined by the order number of the FIR filter stage, and the chosen sampling rate. The following equation expresses the delay time of PCM1716: TD = 30 x 1/fS For fS = 44.1kHz, TD = 30/44.1kHz = 680µs Applications using data from a disc or tape source, such as CD audio, DVD audio, Video CD, DAT, Minidisc, etc., generally are not affected by delay time. For some professional applications such as broadcast audio for studios, it is important for total delay time to be less than 2ms. OUTPUT FILTERING For testing purposes all dynamic tests are done on the PCM1716 using a 20kHz low pass filter. This filter limits the measured bandwidth for THD+N, etc. to 20kHz. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the specifications. The low pass filter removes out of band noise. Although it is not audible, it may affect dynamic specification numbers. The performance of the internal low pass filter from DC to 40kHz is shown in Figure 12. The higher frequency roll-off of the filter is shown in Figure 13. If the user’s application has the PCM1716 driving a wideband amplifier, it is recommended to use an external low pass filter. BYPASSING POWER SUPPLIES The power supplies should be bypassed as close as possible to the unit. Refer to Figure 15 for optimal values of bypass capacitors. POWER SUPPLY CONNECTIONS PCM1716 has three power supply connections: digital (VDD), and analog (VCC). Each connection also has a separate ground. If the power supplies turn on at different times, there is a possibility of a latch-up condition. To avoid this condition, it is recommended to have a common connection between the digital and analog power supplies. If separate supplies are used without a common connection, the delta between the two supplies during ramp-up time must be less than 0.1V. An application circuit to avoid a latch-up condition is shown in Figure 14. Digital Power Supply Analog Power Supply VDD DGND VCC AGND FIGURE 14. Latch-Up Prevention Circuit. 1 20 0 0.5 Level (dB) Level (dB) 1 10 100 1k 10k 100k –20 –40 –60 –0.5 –80 –1 Log Frequency (Hz) –100 1 10 100 1k 10k 100k 1M 10M Log Frequency (Hz) 0 FIGURE 12. Low Pass Filter Response. FIGURE 13. Low Pass Filter Response. ® 13 PCM1716 PCM1716E 1 PCM Audio Data Input XTI Buffer Out or 1/2 Divided Out SYSTEM CLOCK (256/384/512/768fS) to DGND of D. Source C2 2 3 4 5 6 7 8 9 C4 LRCIN DIN BCKIN CLKO XTI XTO DGND VDD VCC2R ML/IIS 28 MC/DM1 27 MD/DM0 26 MUTE 25 MODE 24 CS/IWO 23 RST 22 ZERO 21 VCC2L 20 AGND2L 19 EXTL 18 NC 17 VOUTL 16 VCC1 15 C1 + C5 10µF Mode Control External Reset 10kΩ C3 10 AGND2R + 11 EXTR 12 NC 13 VOUTR 14 AGND1 C6 10µF +5V VCC C1, C2 : 10µF + 0.1µF Ceramic C3, C4 : 1µF ~ 10µF Post Low-Pass Filter Post Low-Pass Filter Analog Mute Analog Mute External Mute Control Rch Audio Out Lch Audio Out FIGURE 15. Typical Circuit Connection Diagram. ® PCM1716 14