49%
171
FPO
9E
®
PCM1719
PCM
Stereo Audio
DIGITAL-TO-ANALOG CONVERTER
TM
FEATURES
DESCRIPTION
● ACCEPTS 16- OR 18-BIT INPUT DATA
PCM1719 is a complete, low cost stereo audio digitalto-analog converter (DAC) including a digital interpolation filter, 3rd-order delta-sigma DAC, an analog
low-pass filter and output amplifier. PCM1719 also
has an on-chip stereo headphone amplifier.
● COMPLETE STEREO DAC:
8X Oversampling Digital Filter
Multi-Level Delta-Sigma DAC
Analog Low Pass Filter
PCM1719 can accept either 16-, or 18-bit input data.
The audio data input format can be either MSB-first,
right-justified or I2S. The system clock can be 256fS or
384fS. PCM1719 is fabricated on a highly advanced
0.6µs CMOS process, which delivers high performance at very low power dissipation.
● ON-CHIP HEADPHONE AMPLIFIER
● HIGH PERFORMANCE:
–88dB THD+N
96dB Dynamic Range
100dB SNR
● SELECTABLE FUNCTIONS:
Digital De-emphasis
Digital Attenuation (256 Steps)
Soft Mute
Multiple Output Formats
PCM1719 is ideal for applications which require headphone drivers such as CD-ROM drives, digital audio
workstations, portable CD players, and digital musical
instruments.
● SYSTEM CLOCK: 256fS or 384fS
● SINGLE +5V POWER SUPPLY
● SMALL 28-PIN SSOP PACKAGE
BCKIN
LRCIN
Serial
Input
I/F
DIN
ML
MC
MD
RSTB
Multi-level
Delta-Sigma
Modulator
8X Oversampling
Digital Filter
with Multi-Function
Control
VOUTL
Low-pass
Filter
DAC
COM
Multi-level
Delta-Sigma
Modulator
Mode
Control
I/F
VOUTR
Low-pass
Filter
DAC
ZERO
BPZ-Cont.
Reset
Open Drain
XTI
XTO
CLKO
PINL
Clock
and
OSC
Manager
Headphone Amp
PCM1719
POUTL
Bias
Mute
Headphone Amp
Power Supply
PCOM
PMUTE
POUTR
PINLR
VCC AGND VDD DGND PGND PVCC
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1996 Burr-Brown Corporation
SBAS056
PDS-1343A
Printed in U.S.A., November, 1996
SPECIFICATIONS
All specifications at +25°C, +VDD = +VCC = PVCC = +5V, fS = 44.1kHz, SYSCLK = 384fS, 16-bit data, unless otherwise noted.
PCM1719E
PARAMETER
CONDITIONS
RESOLUTION
MIN
TYP
16
DATA FORMAT
Audio Data Format
Data Bit Length
Sampling Frequency (fS)
System Clock Frequency
DIGITAL INPUT/OUTPUT
Logic Family
Input Logic Level(2), (3)
VIH
VIL
Input Logic Current
IIH
IIL
IIH
IIL
IIH
IIL
IIH
IIL
Output Logic Level
VOH
VOL
VOL
DYNAMIC PERFORMANCE(1)
VOUTL, VOUTR: Line Output(5)
THD+N at VO = 0dB
at VO = –60dB
Dynamic Range
Signal-to-Noise Ratio
Channel Separation
Level Linearity Error
POUTL, POUTR: Headphone Output(6)
THD+N at VO = 0dB
Frequency Response
Output Noise Level
Channel Separation
Analog Mute Attenuation Level
DC PERFORMANCE
VOUTL, VOUTR: Line Output(5)
Gain Error
Gain Mismatch Channel-to-Channel
Bipolar Zero Error
Analog Output Range
Center Voltage
AC Load Impedance
POUTL, POUTR: Headphone Output(6)
Voltage Gain
Voltage Gain Error
Input Offset Voltage
Gain Mismatch Channel-to-Channel
Maximum Output Current
Maximum Output Voltage
Output Power
AC Load Impedance
MAX
UNITS
18
Bits
Normal/I2S Selectable
16/18 Bits, Selectable
32
44.1
48
8.192/12.288
11.2896/16.9344
12.288/18.432
256fS/384fS
kHz
MHz
TTL Compatible
2
VIH = 2.0V
VIL = 0.0V
VIH = 2.0V
VIL = 0.0V
VIH = 2.0V
VIL = 0.0V
IOH = –5mA
IOL = 5mA
IOL = 5mA
0.8
VDC
VDC
0.8
–0.8
–100
–120
15
–15
–60
–100
µA
µA
µA
µA
µA
µA
µA
µA
1.0
1.0
VDC
VDC
VDC
3.8
fOUT = 991Hz
fOUT = 991Hz
EIAJ, A-weighted
EIAJ, A-weighted
fOUT = 991Hz
fOUT = 991Hz, –90dB
RL = 64Ω
90
92
90
fOUT = 20Hz to 20kHz
EIAJ, A-weighted, RG = 0Ω
87
80
–88
–34
96
100
97
±0.5
–80
dB
dB
dB
dB
dB
dB
–68
±0.1
25
90
85
–60
±0.2
30
dB
dB
µVrms
dB
dB
±1
±1
±30
3.1
VCC/2
50% of VCC
±5
±5
% of FSR
% of FSR
mV
Vp-p
V
VDC
kΩ
dB
dB
mV
dB
mArms
Vrms
mW
Ω
RL = 64Ω
VOUT = VCC/2
5
Load = 64Ω
G = –2.8dB
Load = 64Ω
Load = 64Ω
–2.8
±0.1
±30
±0.1
12.5
0.8
10
64
±0.2
±0.2
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
PCM1719
2
SPECIFICATIONS(CONT)
All specifications at +25°C, +VDD = +VCC = PVCC = +5V, fS = 44.1kHz, SYSCLK = 384fS, 16-bit data, unless otherwise noted.
PCM1719E
PARAMETER
FILTER PERFORMANCE
Digital Filter
Passband
Stopband
Passband Ripple
Stopband Attenuation
De-emphasis Error
Delay Time
ANALOG FILTER: Line Outputs
Frequency Response
POWER SUPPLY REQUIREMENTS
Voltage Range
Supply Current(7)
ICC + IDD
IPCC (Full Scale Input)
Power Dissipation
PD
PPD
CONDITIONS
MIN
TYP
MAX
UNITS
0.445
11.125/fS
fS
fS
dB
dB
dB
sec
–0.16
dB
0.555
±0.17
fS = 32kHz to 48kHz
–35
–0.2
f = 20Hz to 20kHz
VDD, VCC, PVCC
VDD = VCC = 5.0V
PVCC = 5.0V
5.0
18
18
20
+5.5
25
25
25
VDC
mA
mA
mA
VCC, VDD = 5.0
PVCC = 5.0
90
90
125
125
mW
mW
+85
+100
°C
°C
TEMPERATURE RANGE
Operation
Storage
+4.5
+0.55
–25
–55
NOTES: (1) Dynamic performance specs are tested with external 20kHz low pass filter and THD-B specs are test with 30kHz LPF, 400Jz HPF, Average Mode,
Shibasoku #725 THD Meter. (2) RSTB pin, MD pin, MC pin, and ML pin include an internal pull-up resistor. (3) RSTB pin, MD pin, MC pin, and ML pin include
internal Schmitt trigger circuits. (4) ZERO pin is an open drain output. (5) Line output should be connected by a coupling capacitor. (6) Headphone output should
be connected by a coupling capacitor. (7) Supply current and power dissipation are measured at CLKO pin = no load, XTO pin = no load.
ABSOLUTE MAXIMUM RATINGS
PACKAGE INFORMATION
Power Supply Voltage
+VDD ..................................................................................................................................... +6.5V
+VCC ..................................................................................................................................... +6.5V
+PV CC ................................................................................................................................. +6.5V
–VDD to +VCC∆ .......................................................................................... 0.1V
+VDD to +PVCC∆ ....................................................................................... 0.1V
+VDD to +PVCC∆ ....................................................................................... 0.1V
Input Logic Voltage ................................................... –0.6V to (VDD + 06V)
Power Dissipation .......................................................................... 200mW
Operating Temperature Range ......................................... –25°C to +85°C
Storge Temperature ........................................................ –55°C to +125°C
Lead Temperature (soldering, 5s) .................................................. +260°C
Junction Temperature, θJA ................................................................................ +130°C/W
PRODUCT
PACKAGE
PACKAGE DRAWING
NUMBER(1)
PCM1719E
28-Pin SSOP
324
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
®
3
PCM1719
PIN CONFIGURATION
PIN ASSIGNMENTS
TOP VIEW
PIN
SSOP
XTI
1
28
NAME
TYPE
1
XTI
IN
2
DGND
PWR
Digital Ground.
3
VDD
PWR
+5V Digital Power Supply.
4(1)
XTO
FUNCTION
Crystal Oscillator Input.
LRCIN
IN
5
DIN
IN
Left/Right Word Clock. Frequency is equal to fS.
Serial Audio Data Input.
Bit Clock for Loading in Audio Data.
DGND
2
27
CLKO
6
BCKIN
IN
VDD
3
26
ML
7
ZERO
OUT
LRCIN
4
25
MC
DIN
5
24
MD
BCKIN
6
23
RSTB
ZERO
7
22
NC
NC
8
21
COM
9
13
Right-Channel Headphone Amplifier Output.
20
VOUTL
POUTR
OUT
VOUTR
14
PAGND
PWR
Headphone Amplifier Ground.
AGND 10
19
VCC
15
PVCC
PWR
+5V Headphone Amplifier Power Supply.
16
POUTL
OUT
PCM1719
PINR 11
18
PINL
PCOM 12
17
PMUTE
POUTR 13
16
POUTL
PAGND 14
15
PVCC
Zero Data Flag. This pin is “LOW” when the input
data is continuously zero for 65, 536 periods of
BCKIN.
No Connection.
8
NC
—
9
VOUTR
OUT
Right-Channel Analog Line Output.
10
AGND
PWR
Analog Ground.
11
PINR
IN
Input for Headphone Amplifier, Right-Channel.
12
PCOM
PWR
Headphone Amplifier Common. Bypass with
100µF.
17(1) PMUTE
IN
Left-Channel Headphone Amplifier Output.
Mute Control for Headphone Amplifier.
18
PINL
IN
19
VCC
PWR
20
VOUTL
OUT
Left-Channel Analog Line Output.
21
COM
PWR
Line Out Common. Bypass with 10µF.
22
Input for Headphone Amplifier, Left-Channel.
+5V Analog Power Supply.
NC
—
23(1)
RSTB
IN
No Connection.
External Reset Control.
24(1)
MD
IN
Data for Serial Control.
25(1)
MC
IN
Clock for Serial Control.
26(1)
ML
IN
Latch for Serial Control.
27
CLKO
OUT
System Clock (256fS or 384fS) Output.
28
XTO
OUT
Crystal Oscillator Output.
NOTE: (1) With internal pull-up.
®
PCM1719
4
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VCC = VDD = PVCC = +5V, RL = 32Ω + 32Ω, and f = 1kHz, 384fS, unless otherwise noted.
ANALOG PERFORMANCE
TOTAL THD+N vs TEMPERATURE
TOTAL THD+N vs SUPPLY VOLTAGE
2.0
0.04
0.03
1.5
0.02
1.0
0dB
0.01
0.5
0
–25
0
+25
+50
+75 +85
2.5
–60dB
0.03
1.5
0.02
1.0
0dB
0.01
0
+100
0
4.0
4.5
5.0
5.5
6.0
Supply Voltage (VCC)
INDIVIDUAL THD+N vs INPUT LEVEL
(Minimum Load)
TOTAL THD+N vs INPUT LEVEL
10
10
1
1
THD+N (%)
THD+N (%)
0.5
0
Temperature (°C)
0.1
0dB = FS
0.01
0.001
–70
2.0
THD+N at –60dB (%)
THD+N at 0dB (%)
0.05
THD+N at 0dB (%)
–60dB
0.04
2.5
THD+N at –60dB (%)
0.05
DAC
0.1
0dB = FS
Headphone Amp
0.01
–60
–50
–40
–30
–20
–10
0.001
–70
0
Input Level (dB)
–60
–50
–40
–30
–20
–10
0
Input Level (dB)
®
5
PCM1719
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VCC = VDD = PVCC = +5V, RL = 64Ω, fSYS = 384fS, and 16-bit input data, unless otherwise noted.
DIGITAL FILTER
OVERALL FREQUENCY CHARACTERISTIC
PASSBAND RIPPLE CHARACTERISTIC
0
–20
–0.2
–40
–0.4
dB
dB
0
–60
–0.6
–80
–0.8
–100
–1
0 0.4536fS
1.3605fS
2.2675fS
3.1745fS
4.0815fS
0
0.1134fS
5k
10k
15k
20k
25k
0
3628
15k
20k
25k
0
4999.8375
15k
20k
19999.35
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
0
25k
Frequency (Hz)
5442
10884
Frequency (Hz)
®
PCM1719
14999.5125
DE-EMPHASIS ERROR (48kHz)
Error (dB)
Level (dB)
DE-EMPHASIS FREQUENCY RESPONSE (48kHz)
10k
9999.675
Frequency (Hz)
0
–2
–4
–6
–8
–10
–12
5k
14512
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
Frequency (Hz)
0
10884
DE-EMPHASIS ERROR (44.1kHz)
Error (dB)
Level (dB)
DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz)
10k
7256
Frequency (Hz)
0
–2
–4
–6
–8
–10
–12
5k
0.4535fS
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
Frequency (Hz)
0
0.3402fS
DE-EMPHASIS ERROR (3kHz)
Error (dB)
Level (dB)
DE-EMPHASIS FREQUENCY RESPONSE (3kHz)
0
–2
–4
–6
–8
–10
–12
0
0.2268fS
Frequency (Hz)
Frequency (Hz)
6
16326
21768
SYSTEM CLOCK
The system clock of PCM1719 must be either 256fS or
384fS, where fS is the audio sampling frequency, such as
32kHz, 44.1kHz, and 48kHz. The system clock is used to
operate the digital filter and the multi-level delta-sigma
modulator. The system clock can be either a crystal oscillator placed across XTI (pin 1) and XTO (pin28), or an
external clock input to the XTI pin directly. In this case, the
XTO pin should be open (floating). Figure 1 illustrates the
internal clock circuit and typical connection.
The PCM1719 has a system clock detection circuit which
automatically detects the system clock of either 256fS or
384fS. The system clock should be synchronized with the
LRCIN (pin 4) clock (sampling frequency), but the PCM1719
allows for a phase difference between LRCIN and the
system clock. If the phase difference between LRCIN and
system clock is larger than ±6 bit clocks (BCKIN), the
synchronization of the system clock and LRCIN is done
automatically. The analog outputs are forced to VCC/2 during the syunchronization operation. Table I shows the system clock frequency input to the PCM1719.
SAMPLING RATE
FREQUENCY (LRCIN)
32kHz
SYSTEM CLOCK
FREQUENCY (MHz)
256fS
384fS
8.1920
12.2880
44.1kHz
11.2896
16.9340
48kHz
12.2880
18.4320
TABLE I. System Clock Frequencies vs Sampling Rate.
INFINITE ZERO FLAG FUNCTION
When the audio input data (at both channels) is continuously
zero (BPZ code) for 65, 536 cycles of bit clock (BCKIN),
ZERO (pin 7) goes to a “LOW” level. When the audio input
data is non-zero, the ZERO pin goes to a high-impedance
state immediately. This pin is open-drain.
CLKO
CLKO
Internal System Clock
C1
X’tal
XTI
Internal System Clock
External Clock
XTI
C2
XTO
C1, C2 = 10 to 20pF
XTO
PCM1719
PCM1719
CRYSTAL OSCILLATOR CONNECTION
EXTERNAL CLOCK INPUT
XTO pin =Floating
FIGURE 1. Internal Clock Circuit Diagram and Oscillator Connection.
®
7
PCM1719
1/fS, fS = 32, 44.1, 48kHz
L_ch
R_ch
LRCIN (pin 4)
BCKIN (pin 6)
AUDIO DATA WORD = 16-BIT
DIN (pin 5)
14 15 16
1
2
14
3
MSB
AUDIO DATA WORD = 18-BIT
16 17 18
1
2
MSB
1
2
14
3
MSB
LSB
16
3
15 16
17 18
1
LSB
2
15 16
LSB
16
3
MSB
17 18
LSB
FIGURE 2. Data Input Timing of Normal Format ( MSB-first, right-justified); Lch = “H”, Rch = “L”.
1/fS, fS = 32, 44.1, 48kHz
L_ch
LRCIN (pin 4)
R_ch
BCKIN (pin 6)
AUDIO DATA WORD = 16-BIT
DIN (pin 5)
1
2
MSB
AUDIO DATA WORD = 18-BIT
DIN (pin 5)
3
1
2
14
15 16
1
2
MSB
LSB
3
MSB
3
16
17 18
1
LSB
2
14
15 16
1
2
1
2
LSB
16
3
MSB
17 18
LSB
FIGURE 3. Data Input Timing of I2S Data Format (Philips format); Lch = “L”, Rch = “H”.
REGISTER CONTROL (Bits 9, 10)
PCM AUDIO INTERFACE
PCM audio data of the PCM1719 is accepted via LRCIN
(pin 4), DIN (pin 5) and BCKIN (pin 6). The PCM1719E
accepts both normal and I2S data input formats. The normal
data format is MSB-first, Two’s Complement and rightjustified. The I2S format is compatible with Philips’ serial
data protocol. In these formats, the serial data is 16- or 18bit input selectable. Figures 2 and 3 illustrate the input audio
data timing and format.
REGISTER
B9 (A0)
B10 (A1)
0
1
2
3
0
1
0
1
0
0
1
1
Control data timing is shown in Figure 7. ML is used to latch
the data from the control registers. After each register’s
contents are checked in, ML should be taken “LOW” to
latch in the data. A “res” in the register indicates that
location is reserved for factory use. When loading the
registers, the “res” bits should be set “LOW”.
OPERATIONAL CONTROL
The Software Mode uses a three-wire interface on pins 24,
25 and 26. Pin 25 (MC) is used to clock in the serial control
data, pin 26 (ML) is used to latch the serial control data, and
pin 24 (MD) is used to load in the serial control register.
There are four distinct registers, with bits 9 and 10 (of 16)
determining which register is in use.
REGISTER 0
B15 B14 B13 B12 B11 B10 B9 B8
B7 B6 B5 B4 B3 B2 B1 B0
res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
Register 0 is used to control left channel attenuation. Bits
0-7 (AL0-AL7) are used to determine the attenuation level.
The level of attenuation is given by:
ATT = [20log10 (ATT_DATA/255)] dB
®
PCM1719
8
ATTENUATION DATA LOAD CONTROL, LCH
Bit 8 (LDL) is used to simultaneously set analog outputs of
Lch and Rch. An output level is controlled by AL[0:7]
attenuation data when this bit is set to 1. When set to 0, an
output level is not controlled and remained at the previous
attenuation level. A LDR bit in Register 1 has an equivalent
function as the LDL. When one of LDL or LDR is set to 1,
the output level of the left and right channel is simultaneously controlled. The attenuation level is given by:
Bits 3 (OPE) and 4 (IZD) are used to control the infinite zero
detection features. Tables II through IV illustrate the relationship between IZD, OPE, and RSTB (reset control):
DATA INPUT
DAC OUTPUT
Zero
Forced to BPZ(1)
Other
Normal
IZD = 1
IZD = 0
Zero
Zero(2)
Other
Normal
TABLE II. Infinite Zero Detection (IZD) Function.
ATT = 20log (y/256) (dB), where y = x, when 0 ≤ x ≤ 254
y = x + 1, when x = 255
DATA INPUT
DAC OUTPUT
SOFTWARE MODE
INPUT
Enabled
OPE = 1
X is the user-determined step number, an integer value
between 0 and 255.
OPE = 0
Example:
let x = 255
let x = 254
let x = 1
let x = 0
Zero
Forced to BPZ(1)
Other
Forced to BPZ(1)
Enabled
Zero
Controlled by IZD
Enabled
Other
Normal
Enabled
TABLE III. Output Enable (OPE) Function.
255 + 1
ATT = 20 log
= 0dB
256
DATA INPUT
DAC OUTPUT
SOFTWARE
MODE
INPUT
Enabled
RSTB = “HIGH”
254
ATT = 20 log
= –0. 068dB
256
RSTB = “LOW”
Zero
Controlled by OPE and IZD
Other
Controlled by OPE and IZD
Enabled
Zero
Forced to BPZ(1)
Disabled
Other
Forced to BPZ(1)
Disabled
1
= –48.16dB
ATT = 20 log
256
TABLE IV. Reset (RSTB) Function.
0
= –∞
ATT = 20 log
256
OPE controls the operation of the DAC: when OPE is
“LOW”, the DAC will convert all non-zero input data. If the
input data is continuously zero for 65,536 cycles of BCKIN,
the output will only be forced to zero only if IZD is “HIGH”.
When OPE is “HIGH”, the output of the DAC will be forced
to bipolar zero, irrespective of any input data.
NOTE: (1) ∆∑ is disconnected from output amplifier. (2) ∆∑ is connected to
output amplifier.
REGISTER 1
Register 1 is used to control right channel attenuation. As
in Register 1, bits 0-7 (AR0-AR7) control the level of
attenuation.
B15 B14 B13 B12 B11 B10 B9 B8
res res res res res
IZD controls the operation of the zero detect feature: when
IZD is “LOW”, the zero detect circuit is off. Under this
condition, no automatic muting will occur if the input is
continuously zero. When IZD is “HIGH”, the zero detect
feature is enabled. If the input data is continuously zero for
65,536 cycles of BCKIN, the output will be immediately
forced to a bipolar zero state (VCC/2). The zero detection
feature is used to avoid noise which may occur when the
input is DC. When the output is forced to bipolar zero, there
may be an audible click. PCM1719 allows the zero detect
feature to be disabled so the user can implement an external
muting circuit.
B7 B6 B5 B4 B3 B2 B1 B0
A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
REGISTER 2
B15 B14 B13 B12 B11 B10 B9 B8
res res res res res A1
B7
B6 B5
B4
B3
B2
B1
B0
A0 res res res res IZD OPE DM1 DM0 MUTE
Register 2 is used to control soft mute, digital de-emphasis,
disable, and infinite zero detect. Bit 0 is used for soft mute;
a HIGH level on bit 0 will cause the output to be muted.
Bits 1 and 2 are used to control digital de-emphasis as
shown below:
REGISTER 3
B15 B14 B13 B12 B11 B10 B9 B8
res res res res res A1
BIT 1 (DM0)
BIT 2 (DM1)
0
0
De-emphasis disabled
1
0
De-emphasis enabled at 48kHz
0
1
De-emphasis enabled at 44.1kHz
1
1
De-emphasis enabled at 32kHz
B7
B6 B5
B4
B3
A0 res PL3 PL2 PL1 PL0 ATC
B2
B1
IW LRP
B0
IIS
DE-EMPHASIS
Register 3 is used to select the I/O data formats. Bit 0 (IIS)
is used to control the input data format. If the input data
source is normal (16- or 18-bit, MSB first, right-justified),
set bit 0 “LOW”. If the input format is I2S, set bit 0 “HIGH”.
®
9
PCM1719
Bit 2 is used to select the input word length. When bit 2 is
LOW, the input word length is set for 16 bits; when bit 2 is
HIGH, the input word length is set for 18 bits.
50% of VDD
LRCIN
tBCH
tBCL
Bit 3 is used as an attenuation control. When bit 3 is set
HIGH, the attenuation data on Register 0 is used for both
channels, and the data in Register 1 is ignored. When bit 3
is LOW, each channel has separate attenuation data.
tLB
50% of VDD
BCKIN
tBL
tBCY
Bits 4 through 7 are used to determine the output format, as
shown in Table V:
50% of VDD
DIN
tDH
tDS
BCKIN Pulsewidth (High Level)
BCKIN Pulsewidth (Low Level)
BCKIN Pulse Cycle Time
BCKIN Rising Edge ➝ LRCIN Edge
LRCIN Edge ➝ BCKIN Rising Edge
DIN Setup Time
DIN Hold Time
tBCH
tBCL
tBCY
tBL
tLB
tDS
tDH
50ns (min)
50ns (min)
100ns (min)
30ns (min)
30ns (min)
30ns (min)
30ns (min)
FIGURE 4. Data Input Timing.
Bit 1 is used to select the polarity of LRCIN (sample rate
clock). When bit 1 is LOW, a HIGH state on LRCIN is used
for the left channel, and a LOW state on LRCIN is used for
the right channel. When bit 1 is HIGH the polarity of LRCIN
is reversed.
PL0
PL1
PL2
PL3
Lch OUTPUT
Rch OUTPUT
NOTE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MUTE
MUTE
MUTE
MUTE
R
R
R
R
L
L
L
L
(L + R)/2
(L + R)/2
(L + R)/2
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
R
L
(L + R)/2
MUTE
TABLE V. PCM1719 Output Mode Control.
ML (pin 18)
MC (pin 17)
MD (pin 16)
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
tMLS
tMLH
50% of VDD
ML
tMCH
tMCY
tMCL
tMLL
MC
50% of VDD
MD
50% of VDD
tMDS
tMDH
MC Pulse Cycle
MC Pulsewidth “L”
MC Pulse Cycle “H”
MD Setup Time
MD Hold Time
ML Setup Time
ML Hold Time
ML Pulsewidth “L”
tMCY
tMCL
tMCH
tMDS
tMDH
tMLS
tMLH
tMLL
100ns (min)
50ns (min)
50ns (min)
30ns (min)
30ns (min)
30ns (min)
30ns (min)
30ns + 1SYSCLK (min)
FIGURE 5. Control Data Timing in Software Mode Control.
50% of VDD
RSTB
tRST
RSTB Pulsewidth
FIGURE 6. External Reset Timing.
®
PCM1719
10
20ns (min)
REVERSE
STEREO
MONO
0.1µF to 10µF
Bypass Capacitor
10pF to 22pF
2
3
DGND
VDD
+5.0V
Analog Power
Supply
28 XTO
CLKO 27
XTAL
1
XTI
0.1µF to 10µF Bypass Capacitor
10pF to 22pF
AGND 10
COM 21
System Clock
(256fS/384fS)
PCM
Audio
Data
Processer
(DSP)
Function
Control
Processor
(MPU)
4
LRCIN
5
DIN
6
BCKIN
ZERO
7
VOUTR
9
PCM1719
PINR 11
PINL 18
24 MD
25 MC
VOUTL 20
26 ML
PCOM 12
Reset
Mute
VDD
VCC 19
23 RSTB
POUTR 13
17 PMUTE
POUTL 16
PVCC
PAGND
15
14
+
10µF
10µF
+
4.7kΩ
Post Low Pass
Filter(1)
10µF
+
Line Out
10kΩ
10µF
+
10kΩ
10µF
+
Post Low Pass
Filter(1)
100µF
+
32Ω
470µF
+
32Ω
470µF
+
Headphone Out
NOTE: (1) Either passive or active, depending on application.
0.1µF to 10µF
Bypass Capacitor
FIGURE 7. Typical Circuit Connection.
TYPICAL APPLICATION CIRCUIT
Bypassing and decoupling capacitors should be placed as
close as possible to the device pin. The capacitance between PCOM (pin 12) and/or COM (pin 21) to ground can
be reduced to 1µF, but this may decrease performance of
the PCM1719’s internal analog low-pass filter. The 10µF
capacitor shown between COM and analog ground is used
to set the pole for the PCM1719’s internal low-pass filter.
It is also important to limit the measurement bandwidth of
the PCM1719 to 20kHz during performance evaluation. By
definition, delta-sigma DACs have a large amount of energy beyond the audio band. Including this energy in
THD+N measurements will not demonstrate the true inband performance of PCM1719.
Figure 7 shows the typical application circuit. In this circuit,
VDD, VCC, and PVCC are connected to a common analog
power supply. It is possible to use separate analog and
digital power supplies for PCM1719. If separate supplies are
used, the difference voltage between the supplies must be
less than ±0.1V. PCM1719’s headphone amplifier allows for
high current flow from the outputs to ground. To keep the
high load current from affecting the DAC’s performance,
the headphone jack ground should be connected to a lowimpedance ground plane. Interference from the headphone
amplifier can also be minimized by using a separate power
supply for PVCC, but avoid power supply deltas greater than
±0.1V.
®
11
PCM1719
POWER SUPPLY
CONNECTIONS
A block diagram of the 5-level delta-sigma modulator is
shown in Figure 9. This 5-level delta-sigma modulator has
the advantage of stability and clock jitter sensitivity over the
typical one-bit (2 level) delta-sigma modulator.
PCM1719 has two power supply connections: digital (VDD)
and analog (VCC). Each connection also has a separate
ground. If the power supplies turn on at different times, there
is a possibility of a latch-up condition. To avoid this condition, it is recommended to have a common connection
between the digital and analog power supplies. If separate
supplies are used without a common connection, the delta
between the two supplies during ramp-up time must be less
than 0.6V.
The combined oversampling rate of the delta-sigma modulator and the internal 8-times interpolation filter is 48fS for
a 384fS system clock, and 64fS for a 256fS system clock. The
theoretical quantization noise performance of the 5-level
delta-sigma modulator is shown in Figure 10.
An application circuit to avoid a latch-up condition is shown
in Figure 8.
Digital
Power Supply
Analog
Power Supply
3rd ORDER ∆Σ MODULATOR
20
0
VCC
DGND
AGND
–20
Gain (–dB)
VDD
–40
–60
–80
–100
FIGURE 8. Latch-up Prevention Circuit.
–120
–140
THEORY OF OPERATION
–160
0
The delta-sigma section of PCM1719 is based on a 5-level
amplitude quantizer and a 3rd-order noise shaper. This
section converts the oversampled input data to 5-level deltasigma format.
+
+
In
8fS
18-Bit
5
10
FIGURE 10. Quantization Noise Spectrum.
+
Z–1
+
+
–
+
Z–1
–
+
+
5-level Quantizer
+
4
3
Out
48fS (384fS)
64fS (256fS)
2
1
0
FIGURE 9. 5-Level ∆Σ Modulator Block Diagram.
®
PCM1719
15
Frequency (kHz)
12
Z–1
20
25
APPLICATION
CONSIDERATIONS
The performance of the internal low pass filter from DC to
24kHz is shown in Figure 11. The higher frequency rolloff
of the filter is shown in Figure 12. If the user’s application
has the PCM1719 driving a wideband amplifier, it is recommended to use an external low pass filter. A simple 3rdorder filter is shown in Figure 13. For some applications, a
passive RC filter or 2nd-order filter may be adequate.
DELAY TIME
There is a finite delay time in delta-sigma converters. In A/D
converters, this is commonly referred to as latency. For a
delta-sigma D/A converter, delay time is determined by the
order number of the FIR filter stage, and the chosen sampling
rate. The following equation expresses the delay time of
PCM1719:
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(20Hz~24kHz, Expanded Scale)
1.0
TD = 11.125 x 1/fS
0.5
For fS = 44.1kHz, TD = 11.125/44.1kHz = 502.8µs
dB
Applications using data from a disc or tape source, such as
CD audio, CD-Interactive, Video CD, DAT, Minidisc, etc.,
generally are not affected by delay time. For some professional applications such as broadcast audio for studios, it is
important for total delay time to be less than 2ms.
0
–0.5
–1.0
INTERNAL RESET
20
When power is first applied to PCM1719, an automatic reset
function occurs after 1,024 cycles of XTI clock. Refer to
Table I for default conditions. During the first 1,024 cycles
of XTI clock, PCM1719 cannot be programmed (Software
Control). Data can be loaded into the control registers during
this time, and after 1,204 cycles of XTI clock, a “LOW” on
ML (pin 18) will initiate programming.
100
1k
Frequency (Hz)
10k
24k
FIGURE 11. Low Pass Filter Frequency Response.
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(10Hz~10MHz)
dB
OUTPUT FILTERING
For testing purposes all dynamic tests are done on the
PCM1719 using a 20kHz low pass filter. This filter limits
the measured bandwidth for THD+N, etc. to 20kHz. Failure
to use such a filter will result in higher THD+N and lower
SNR and Dynamic Range readings than are found in the
specifications. The low pass filter removes out-of-band
noise. Although it is not audible, it may affect dynamic
specification numbers.
10
5
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
FIGURE 12. Low Pass Filter Frequency Response.
GAIN vs FREQUENCY
6
90
+
VSIN
10kΩ
10kΩ
680pF
OPA604
10kΩ
–14
0
–34
–90
–54
–180
Phase (°)
1500pF
Gain (dB)
Gain
Phase
100pF
–
–74
–270
–94
–360
100
1k
10k
Frequency (Hz)
100k
1M
FIGURE 13. 3rd-Order LPF.
®
13
PCM1719
Test Disk
Shibasoku #725
Through
Lch
CD
Player
DEMPCM1719
DAI
Digital
PGA
THD
Meter
0dB/60dB
30KHz LPF on
External
LPF
Rch
For test of S/N ratio and Dynamic Range, A-filter ON.
FIGURE 14. Test Block Diagram.
TEST CONDITIONS
Figure 14 illustrates the actual test conditions applied to
PCM1719 in production. The external filter is necessary in
the production environment for the removal of noise resulting from the relatively long physical distance between the
unit and the test analyzer. In most actual applications, the
3rd-order filter shown in Figure 13 is adequate. Under
normal conditions, THD+N typical performance is –70dB
with a 30kHz low pass filter (shown here on the THD
meter), improving to –89dB when the external 20kHz 11thorder filter is used.
2
1
14.4ps
0
–1
48fs
2
FIGURE 16. Simulation Method for Clock Jitter.
JITTER SENSITIVITY
HEADPHONE AMPLIFIER
Delta-sigma DACs are by nature very sensitive to jitter on the
master clock. Phase noise on the clock will result in an
increase in noise, ultimately degrading dynamic range. It is
difficult to quantify the effect of jitter due to problems in
synthesizing low levels of jitter. One of the reasons deltasigma DACs are prone to jitter sensitivity is the large quantization noise when the modulator can only achieve two discrete output levels (0 or 1). The multi-level delta-sigma DAC
has improved theoretical SNR because of multiple output
states. This reduces sensitivity to jitter. Figure 15 contrasts
jitter sensitivity between a one-bit PWM type DAC and multilevel delta-sigma DAC. The data was derived using a simulator, where clock jitter could be completely synthesized.
PCM1719 has an integrated headphone amplifier which can
directly drive a 32Ω load, such as headphones. The amplifier
is configured in a gain of –2.8dB (inverting), and the
maximum output current is 12.5mA (rms). The maximum
output voltage is 0.8Vrms into a 64Ω load (stereo 32Ω
headphones), based on the typical DAC full scale voltage
output of 3.1V (p-p). PINL and PINR should be AC-coupled
such that the input impedance for the headphone amplifier is
55kΩ typical, and the noninverting input is biased to VCC/2.
The headphone amplifier has no internal current limiting
circuit. It is recommended to used an external current limiting resistor to avoid damage caused by overloading the
output, and avoid shorting POUTL and POUTR to ground. The
minimum output load of 64Ω includes any current limiting
resistor. If the input impedance of the headphone is 32Ω, a
current limiting resistor of 32Ω should be used. Figure 17
110
100
0
Multi-level
95
–10
90
–20
85
80
75
THD+N (dB)
Dynamic Range (dB)
105
PWM
70
65
60
0
100
200
300
400
500
600
Clock Jitter (ps)
–30
VDD: 5V
DAC Input: BPZ
VIN = 3.1Vp-p (0dB)
f = 1kHz
20kHz Bandwidth Limitation
RP = 32Ω
Test
Point
RP
POUT
–40
Current Limit
Resistor
RL = RP + RH
RH
Headphone
Resistor
–50
–60
RL = 40Ω
–70
48Ω
–80
64Ω
–90
–60
FIGURE 15. Simulation Results of Clock Jitter Sensitivity.
–50
–40
–30
–20
–10
0
Input Signal (dB)
FIGURE 17. THD+N vs Input Signal, Output Load.
®
PCM1719
14
10
illustrates THD+N versus input signal and output load. The
PCM1719 headphone amplifier specification for THD+N is
done with a 64Ω load at 12.5mA (rms) maximum output
current. Although PCM1719 is capable of driving loads as
low as 15Ω, the output waveform will be saturated under
such a condition. The recommended application circuit employs a 32Ω load with a 32Ω current limiting resistor.
with the center tap of the pot AC-coupled to the headphone
amplifier’s inputs. Refer to Figure 7, the typical connection
diagram, for an illustration of this circuit.
ANALOG MUTE FUNCTION
The headphone amplifier’s output can be muted to –80dB.
When PMUTE is taken “LOW”, the headphone outputs are
muted. For normal operation, PMUTE should be held
“HIGH” or left open.
VOLUME CONTROL
PCM1719 allows the user to attentuate the volume by using
a variable resistor. In the actual application, a 10kΩ pot is
connected between the line (DAC) outputs and analog ground,
®
15
PCM1719
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
PCM1719E
ACTIVE
SSOP
DB
28
47
PCM1719E/2K
ACTIVE
SSOP
DB
28
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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