PCM1719E

® PCM 49% 171 FPO 9E PCM1719 Stereo Audio DIGITAL-TO-ANALOG CONVERTER TM FEATURES q ACCEPTS 16- OR 18-BIT INPUT DATA q COMPLETE STEREO DAC: 8X Oversampling Digital Filter Multi-Level Delta-Sigma DAC Analog Low Pass Filter q ON-CHIP HEADPHONE AMPLIFIER q HIGH PERFORMANCE: –88dB THD+N 96dB Dynamic Range 100dB SNR q SELECTABLE FUNCTIONS: Digital De-emphasis Digital Attenuation (256 Steps) Soft Mute Multiple Output Formats q SYSTEM CLOCK: 256fS or 384fS q SINGLE +5V POWER SUPPLY q SMALL 28-PIN SSOP PACKAGE DESCRIPTION PCM1719 is a complete, low cost stereo audio digitalto-analog converter (DAC) including a digital interpolation filter, 3rd-order delta-sigma DAC, an analog low-pass filter and output amplifier. PCM1719 also has an on-chip stereo headphone amplifier. PCM1719 can accept either 16-, or 18-bit input data. The audio data input format can be either MSB-first, right-justified or I2S. The system clock can be 256fS or 384fS. PCM1719 is fabricated on a highly advanced 0.6µs CMOS process, which delivers high performance at very low power dissipation. PCM1719 is ideal for applications which require headphone drivers such as CD-ROM drives, digital audio workstations, portable CD players, and digital musical instruments. BCKIN LRCIN DIN Serial Input I/F Multi-level Delta-Sigma Modulator 8X Oversampling Digital Filter with Multi-Function Control DAC Low-pass Filter VOUTL COM Multi-level Delta-Sigma Modulator Low-pass Filter VOUTR ML MC MD RSTB XTI Mode Control I/F Reset DAC ZERO BPZ-Cont. Open Drain PINL XTO CLKO Clock and OSC Manager PCM1719 Headphone Amp Bias Mute POUTL PCOM PMUTE POUTR PINLR Power Supply Headphone Amp VCC AGND VDD DGND PGND PVCC International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1996 Burr-Brown Corporation PDS-1343A Printed in U.S.A., November, 1996 SPECIFICATIONS All specifications at +25°C, +VDD = +VCC = PVCC = +5V, fS = 44.1kHz, SYSCLK = 384fS, 16-bit data, unless otherwise noted. PCM1719E PARAMETER RESOLUTION DATA FORMAT Audio Data Format Data Bit Length Sampling Frequency (fS) System Clock Frequency DIGITAL INPUT/OUTPUT Logic Family Input Logic Level(2), (3) VIH VIL Input Logic Current IIH IIL IIH IIL IIH IIL IIH IIL Output Logic Level VOH VOL VOL DYNAMIC PERFORMANCE(1) VOUTL, VOUTR: Line Output(5) THD+N at VO = 0dB at VO = –60dB Dynamic Range Signal-to-Noise Ratio Channel Separation Level Linearity Error POUTL, POUTR: Headphone Output(6) THD+N at VO = 0dB Frequency Response Output Noise Level Channel Separation Analog Mute Attenuation Level DC PERFORMANCE VOUTL, VOUTR: Line Output(5) Gain Error Gain Mismatch Channel-to-Channel Bipolar Zero Error Analog Output Range Center Voltage AC Load Impedance POUTL, POUTR: Headphone Output(6) Voltage Gain Voltage Gain Error Input Offset Voltage Gain Mismatch Channel-to-Channel Maximum Output Current Maximum Output Voltage Output Power AC Load Impedance CONDITIONS MIN 16 TYP MAX 18 UNITS Bits 256fS/384fS Normal/I2S Selectable 16/18 Bits, Selectable 32 44.1 48 8.192/12.288 11.2896/16.9344 12.288/18.432 TTL Compatible 2 0.8 0.8 –0.8 –100 –120 15 –15 –60 –100 3.8 1.0 1.0 kHz MHz VDC VDC µA µA µA µA µA µA µA µA VDC VDC VDC VIH = 2.0V VIL = 0.0V VIH = 2.0V VIL = 0.0V VIH = 2.0V VIL = 0.0V IOH = –5mA IOL = 5mA IOL = 5mA fOUT = 991Hz fOUT = 991Hz EIAJ, A-weighted EIAJ, A-weighted fOUT = 991Hz fOUT = 991Hz, –90dB RL = 64Ω fOUT = 20Hz to 20kHz EIAJ, A-weighted, RG = 0Ω 90 92 90 –88 –34 96 100 97 ±0.5 –68 ±0.1 25 90 85 –80 dB dB dB dB dB dB dB dB µVrms dB dB –60 ±0.2 30 87 80 RL = 64Ω VOUT = VCC/2 ±1 ±1 ±30 3.1 VCC/2 50% of VCC 5 –2.8 ±0.1 ±30 ±0.1 12.5 0.8 10 64 ±5 ±5 Load = 64Ω G = –2.8dB Load = 64Ω Load = 64Ω ±0.2 ±0.2 % of FSR % of FSR mV Vp-p V VDC kΩ dB dB mV dB mArms Vrms mW Ω The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® PCM1719 2 SPECIFICATIONS(CONT) All specifications at +25°C, +VDD = +VCC = PVCC = +5V, fS = 44.1kHz, SYSCLK = 384fS, 16-bit data, unless otherwise noted. PCM1719E PARAMETER FILTER PERFORMANCE Digital Filter Passband Stopband Passband Ripple Stopband Attenuation De-emphasis Error Delay Time ANALOG FILTER: Line Outputs Frequency Response POWER SUPPLY REQUIREMENTS Voltage Range Supply Current(7) ICC + IDD IPCC (Full Scale Input) Power Dissipation PD PPD TEMPERATURE RANGE Operation Storage CONDITIONS MIN TYP MAX UNITS 0.445 0.555 ±0.17 fS = 32kHz to 48kHz –35 –0.2 11.125/fS f = 20Hz to 20kHz VDD, VCC, PVCC VDD = VCC = 5.0V PVCC = 5.0V VCC, VDD = 5.0 PVCC = 5.0 –25 –55 +4.5 –0.16 5.0 18 18 20 90 90 +5.5 25 25 25 125 125 +85 +100 +0.55 fS fS dB dB dB sec dB VDC mA mA mA mW mW °C °C NOTES: (1) Dynamic performance specs are tested with external 20kHz low pass filter and THD-B specs are test with 30kHz LPF, 400Jz HPF, Average Mode, Shibasoku #725 THD Meter. (2) RSTB pin, MD pin, MC pin, and ML pin include an internal pull-up resistor. (3) RSTB pin, MD pin, MC pin, and ML pin include internal Schmitt trigger circuits. (4) ZERO pin is an open drain output. (5) Line output should be connected by a coupling capacitor. (6) Headphone output should be connected by a coupling capacitor. (7) Supply current and power dissipation are measured at CLKO pin = no load, XTO pin = no load. ABSOLUTE MAXIMUM RATINGS Power Supply Voltage +VDD ..................................................................................................................................... +6.5V +VCC ..................................................................................................................................... +6.5V +PV CC ................................................................................................................................. +6.5V –VDD to +VCC∆ .......................................................................................... 0.1V +VDD to +PVCC∆ ....................................................................................... 0.1V +VDD to +PVCC∆ ....................................................................................... 0.1V Input Logic Voltage ................................................... –0.6V to (VDD + 06V) Power Dissipation .......................................................................... 200mW Operating Temperature Range ......................................... –25°C to +85°C Storge Temperature ........................................................ –55°C to +125°C Lead Temperature (soldering, 5s) .................................................. +260°C Junction Temperature, θJA ................................................................................ +130°C/W PACKAGE INFORMATION PRODUCT PCM1719E PACKAGE 28-Pin SSOP PACKAGE DRAWING NUMBER(1) 324 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ® 3 PCM1719 PIN CONFIGURATION TOP VIEW SSOP PIN ASSIGNMENTS PIN 1 2 3 4(1) 5 6 7 NAME XTI DGND VDD LRCIN DIN BCKIN ZERO TYPE IN PWR PWR IN IN IN OUT FUNCTION Crystal Oscillator Input. Digital Ground. +5V Digital Power Supply. Left/Right Word Clock. Frequency is equal to fS. Serial Audio Data Input. Bit Clock for Loading in Audio Data. Zero Data Flag. This pin is “LOW” when the input data is continuously zero for 65, 536 periods of BCKIN. No Connection. Right-Channel Analog Line Output. Analog Ground. Input for Headphone Amplifier, Right-Channel. Headphone Amplifier Common. Bypass with 100µF. Right-Channel Headphone Amplifier Output. Headphone Amplifier Ground. +5V Headphone Amplifier Power Supply. Left-Channel Headphone Amplifier Output. Mute Control for Headphone Amplifier. Input for Headphone Amplifier, Left-Channel. +5V Analog Power Supply. Left-Channel Analog Line Output. Line Out Common. Bypass with 10µF. No Connection. External Reset Control. Data for Serial Control. Clock for Serial Control. Latch for Serial Control. System Clock (256fS or 384fS) Output. Crystal Oscillator Output. XTI DGND VDD LRCIN DIN BCKIN ZERO NC VOUTR 1 2 3 4 5 6 7 8 9 PCM1719 28 27 26 25 24 23 22 21 20 19 18 17 16 15 XTO CLKO ML MC 8 MD RSTB NC COM 13 VOUTL VCC PINL PMUTE POUTL PVCC 14 15 16 18 19 20 21 22 23(1) 24(1) 25(1) 26(1) 27 28 9 10 11 12 NC VOUTR AGND PINR PCOM POUTR PAGND PVCC POUTL PINL VCC VOUTL COM NC RSTB MD MC ML CLKO XTO — OUT PWR IN PWR OUT PWR PWR OUT IN IN PWR OUT PWR — IN IN IN IN OUT OUT AGND 10 PINR 11 PCOM 12 POUTR 13 PAGND 14 17(1) PMUTE NOTE: (1) With internal pull-up. ® PCM1719 4 TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = VDD = PVCC = +5V, RL = 32Ω + 32Ω, and f = 1kHz, 384fS, unless otherwise noted. ANALOG PERFORMANCE TOTAL THD+N vs TEMPERATURE 0.05 –60dB 2.5 TOTAL THD+N vs SUPPLY VOLTAGE 0.05 –60dB 2.5 0.04 THD+N at 0dB (%) 2.0 THD+N at –60dB (%) THD+N at 0dB (%) 0.04 2.0 THD+N at –60dB (%) ® 0.03 1.5 0.03 1.5 0.02 0dB 0.01 1.0 0.02 0dB 1.0 0.5 0.01 0.5 0 –25 0 +25 +50 +75 +85 0 +100 0 4.0 4.5 5.0 Supply Voltage (VCC) 5.5 6.0 0 Temperature (°C) TOTAL THD+N vs INPUT LEVEL 10 10 INDIVIDUAL THD+N vs INPUT LEVEL (Minimum Load) 1 THD+N (%) 1 DAC 0.1 0dB = FS 0.01 THD+N (%) 0.1 0dB = FS Headphone Amp 0.01 0.001 –70 –60 –50 –40 –30 –20 –10 0 0.001 –70 –60 –50 –40 –30 –20 –10 0 Input Level (dB) Input Level (dB) 5 PCM1719 TYPICAL PERFORMANCE CURVES At TA = +25° C, VCC = VDD = PVCC = +5V, RL = 64Ω, fSYS = 384fS, and 16-bit input data, unless otherwise noted. DIGITAL FILTER OVERALL FREQUENCY CHARACTERISTIC 0 0 PASSBAND RIPPLE CHARACTERISTIC –20 –0.2 –40 dB –0.4 –60 dB –0.6 –80 –0.8 –100 0 0.4536fS 1.3605fS 2.2675fS 3.1745fS 4.0815fS Frequency (Hz) –1 0 0.1134fS 0.2268fS Frequency (Hz) 0.3402fS 0.4535fS DE-EMPHASIS FREQUENCY RESPONSE (3kHz) 0 –2 –4 –6 –8 –10 –12 0 5k 10k 15k 20k 25k Frequency (Hz) DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz) 0 –2 –4 –6 –8 –10 –12 0 5k 10k 15k 20k 25k Frequency (Hz) DE-EMPHASIS FREQUENCY RESPONSE (48kHz) 0 –2 –4 –6 –8 –10 –12 0 5k 10k 15k 20k 25k Frequency (Hz) 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 0 Level (dB) DE-EMPHASIS ERROR (3kHz) 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 0 3628 7256 Frequency (Hz) DE-EMPHASIS ERROR (44.1kHz) 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 0 4999.8375 9999.675 Frequency (Hz) DE-EMPHASIS ERROR (48kHz) Error (dB) Error (dB) Error (dB) Level (dB) 10884 14512 Level (dB) 14999.5125 19999.35 5442 10884 Frequency (Hz) 16326 21768 ® PCM1719 6 SYSTEM CLOCK The system clock of PCM1719 must be either 256fS or 384fS, where fS is the audio sampling frequency, such as 32kHz, 44.1kHz, and 48kHz. The system clock is used to operate the digital filter and the multi-level delta-sigma modulator. The system clock can be either a crystal oscillator placed across XTI (pin 1) and XTO (pin28), or an external clock input to the XTI pin directly. In this case, the XTO pin should be open (floating). Figure 1 illustrates the internal clock circuit and typical connection. The PCM1719 has a system clock detection circuit which automatically detects the system clock of either 256fS or 384fS. The system clock should be synchronized with the LRCIN (pin 4) clock (sampling frequency), but the PCM1719 allows for a phase difference between LRCIN and the system clock. If the phase difference between LRCIN and system clock is larger than ±6 bit clocks (BCKIN), the synchronization of the system clock and LRCIN is done automatically. The analog outputs are forced to VCC/2 during the syunchronization operation. Table I shows the system clock frequency input to the PCM1719. SAMPLING RATE FREQUENCY (LRCIN) SYSTEM CLOCK FREQUENCY (MHz) 256fS 32kHz 44.1kHz 48kHz 8.1920 11.2896 12.2880 384fS 12.2880 16.9340 18.4320 TABLE I. System Clock Frequencies vs Sampling Rate. INFINITE ZERO FLAG FUNCTION When the audio input data (at both channels) is continuously zero (BPZ code) for 65, 536 cycles of bit clock (BCKIN), ZERO (pin 7) goes to a “LOW” level. When the audio input data is non-zero, the ZERO pin goes to a high-impedance state immediately. This pin is open-drain. CLKO CLKO Internal System Clock Internal System Clock C1 X’tal XTI External Clock XTI C2 XTO C1, C2 = 10 to 20pF PCM1719 XTO PCM1719 EXTERNAL CLOCK INPUT XTO pin =Floating CRYSTAL OSCILLATOR CONNECTION FIGURE 1. Internal Clock Circuit Diagram and Oscillator Connection. ® 7 PCM1719 1/fS, fS = 32, 44.1, 48kHz L_ch LRCIN (pin 4) BCKIN (pin 6) AUDIO DATA WORD = 16-BIT DIN (pin 5) 14 15 16 1 2 3 MSB 1 2 3 MSB 14 LSB 16 LSB 17 18 1 2 3 MSB 15 16 1 2 3 MSB 14 LSB 16 LSB 17 18 15 16 R_ch AUDIO DATA WORD = 18-BIT 16 17 18 FIGURE 2. Data Input Timing of Normal Format ( MSB-first, right-justified); Lch = “H”, Rch = “L”. 1/fS, fS = 32, 44.1, 48kHz LRCIN (pin 4) BCKIN (pin 6) AUDIO DATA WORD = 16-BIT DIN (pin 5) 1 2 3 MSB 1 2 3 MSB 14 LSB 16 LSB 17 18 1 2 15 16 1 2 3 MSB 3 MSB 14 LSB 16 LSB 17 18 1 2 15 16 1 2 L_ch R_ch AUDIO DATA WORD = 18-BIT DIN (pin 5) FIGURE 3. Data Input Timing of I2S Data Format (Philips format); Lch = “L”, Rch = “H”. PCM AUDIO INTERFACE PCM audio data of the PCM1719 is accepted via LRCIN (pin 4), DIN (pin 5) and BCKIN (pin 6). The PCM1719E accepts both normal and I2S data input formats. The normal data format is MSB-first, Two’s Complement and rightjustified. The I2S format is compatible with Philips’ serial data protocol. In these formats, the serial data is 16- or 18bit input selectable. Figures 2 and 3 illustrate the input audio data timing and format. REGISTER CONTROL (Bits 9, 10) REGISTER 0 1 2 3 B9 (A0) 0 1 0 1 B10 (A1) 0 0 1 1 OPERATIONAL CONTROL The Software Mode uses a three-wire interface on pins 24, 25 and 26. Pin 25 (MC) is used to clock in the serial control data, pin 26 (ML) is used to latch the serial control data, and pin 24 (MD) is used to load in the serial control register. There are four distinct registers, with bits 9 and 10 (of 16) determining which register is in use. Control data timing is shown in Figure 7. ML is used to latch the data from the control registers. After each register’s contents are checked in, ML should be taken “LOW” to latch in the data. A “res” in the register indicates that location is reserved for factory use. When loading the registers, the “res” bits should be set “LOW”. REGISTER 0 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0 Register 0 is used to control left channel attenuation. Bits 0-7 (AL0-AL7) are used to determine the attenuation level. The level of attenuation is given by: ATT = [20log10 (ATT_DATA/255)] dB ® PCM1719 8 ATTENUATION DATA LOAD CONTROL, LCH Bit 8 (LDL) is used to simultaneously set analog outputs of Lch and Rch. An output level is controlled by AL[0:7] attenuation data when this bit is set to 1. When set to 0, an output level is not controlled and remained at the previous attenuation level. A LDR bit in Register 1 has an equivalent function as the LDL. When one of LDL or LDR is set to 1, the output level of the left and right channel is simultaneously controlled. The attenuation level is given by: ATT = 20log (y/256) (dB), where y = x, when 0 ≤ x ≤ 254 y = x + 1, when x = 255 X is the user-determined step number, an integer value between 0 and 255. Example: let x = 255 Bits 3 (OPE) and 4 (IZD) are used to control the infinite zero detection features. Tables II through IV illustrate the relationship between IZD, OPE, and RSTB (reset control): DATA INPUT IZD = 1 IZD = 0 Zero Other Zero Other DAC OUTPUT Forced to BPZ(1) Normal Zero(2) Normal TABLE II. Infinite Zero Detection (IZD) Function. DATA INPUT OPE = 1 OPE = 0 Zero Other Zero Other DAC OUTPUT Forced to BPZ(1) Forced to BPZ(1) Controlled by IZD Normal SOFTWARE MODE INPUT Enabled Enabled Enabled Enabled TABLE III. Output Enable (OPE) Function. 255 + 1  ATT = 20 log  = 0dB  256  254  ATT = 20 log  = –0. 068dB  256  RSTB = “HIGH” RSTB = “LOW” DATA INPUT Zero Other Zero Other DAC OUTPUT Controlled by OPE and IZD Controlled by OPE and IZD Forced to BPZ(1) Forced to BPZ(1) SOFTWARE MODE INPUT Enabled Enabled Disabled Disabled let x = 254 let x = 1 1 = –48.16dB ATT = 20 log   256  0 = –∞ ATT = 20 log   256  TABLE IV. Reset (RSTB) Function. NOTE: (1) ∆∑ is disconnected from output amplifier. (2) ∆∑ is connected to output amplifier. let x = 0 REGISTER 1 Register 1 is used to control right channel attenuation. As in Register 1, bits 0-7 (AR0-AR7) control the level of attenuation. B15 B14 B13 B12 B11 B10 B9 B8 res res res res res B7 B6 B5 B4 B3 B2 B1 B0 A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 OPE controls the operation of the DAC: when OPE is “LOW”, the DAC will convert all non-zero input data. If the input data is continuously zero for 65,536 cycles of BCKIN, the output will only be forced to zero only if IZD is “HIGH”. When OPE is “HIGH”, the output of the DAC will be forced to bipolar zero, irrespective of any input data. IZD controls the operation of the zero detect feature: when IZD is “LOW”, the zero detect circuit is off. Under this condition, no automatic muting will occur if the input is continuously zero. When IZD is “HIGH”, the zero detect feature is enabled. If the input data is continuously zero for 65,536 cycles of BCKIN, the output will be immediately forced to a bipolar zero state (VCC/2). The zero detection feature is used to avoid noise which may occur when the input is DC. When the output is forced to bipolar zero, there may be an audible click. PCM1719 allows the zero detect feature to be disabled so the user can implement an external muting circuit. REGISTER 3 B15 B14 B13 B12 B11 B10 B9 B8 res res res res res A1 B7 B6 B5 B4 B3 B2 B1 B0 IIS A0 res PL3 PL2 PL1 PL0 ATC IW LRP REGISTER 2 B15 B14 B13 B12 B11 B10 B9 B8 res res res res res A1 B7 B6 B5 B4 B3 B2 B1 B0 A0 res res res res IZD OPE DM1 DM0 MUTE Register 2 is used to control soft mute, digital de-emphasis, disable, and infinite zero detect. Bit 0 is used for soft mute; a HIGH level on bit 0 will cause the output to be muted. Bits 1 and 2 are used to control digital de-emphasis as shown below: BIT 1 (DM0) 0 1 0 1 BIT 2 (DM1) 0 0 1 1 DE-EMPHASIS De-emphasis disabled De-emphasis enabled at 48kHz De-emphasis enabled at 44.1kHz De-emphasis enabled at 32kHz Register 3 is used to select the I/O data formats. Bit 0 (IIS) is used to control the input data format. If the input data source is normal (16- or 18-bit, MSB first, right-justified), set bit 0 “LOW”. If the input format is I2S, set bit 0 “HIGH”. ® 9 PCM1719 LRCIN tBCH tBCL tLB 50% of VDD Bit 2 is used to select the input word length. When bit 2 is LOW, the input word length is set for 16 bits; when bit 2 is HIGH, the input word length is set for 18 bits. Bit 3 is used as an attenuation control. When bit 3 is set HIGH, the attenuation data on Register 0 is used for both channels, and the data in Register 1 is ignored. When bit 3 is LOW, each channel has separate attenuation data. Bits 4 through 7 are used to determine the output format, as shown in Table V: PL0 PL1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PL2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PL3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Lch OUTPUT MUTE MUTE MUTE MUTE R R R R L L L L (L + R)/2 (L + R)/2 (L + R)/2 (L + R)/2 Rch OUTPUT MUTE R L (L + R)/2 MUTE R L (L + R)/2 MUTE R L (L + R)/2 MUTE R L (L + R)/2 NOTE MUTE 50% of VDD BCKIN tBCY DIN tDH tDS 50% of VDD tBL BCKIN Pulsewidth (High Level) BCKIN Pulsewidth (Low Level) BCKIN Pulse Cycle Time BCKIN Rising Edge ¨ LRCIN Edge LRCIN Edge ¨ BCKIN Rising Edge DIN Setup Time DIN Hold Time tBCH tBCL tBCY tBL tLB tDS tDH 50ns (min) 50ns (min) 100ns (min) 30ns (min) 30ns (min) 30ns (min) 30ns (min) FIGURE 4. Data Input Timing. Bit 1 is used to select the polarity of LRCIN (sample rate clock). When bit 1 is LOW, a HIGH state on LRCIN is used for the left channel, and a LOW state on LRCIN is used for the right channel. When bit 1 is HIGH the polarity of LRCIN is reversed. 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 REVERSE STEREO MONO TABLE V. PCM1719 Output Mode Control. ML (pin 18) MC (pin 17) MD (pin 16) B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 tMLS ML tMCH MC tMCL tMCY tMLL 50% of VDD tMLH 50% of VDD MD tMDS tMDH tMCY tMCL tMCH tMDS tMDH tMLS tMLH tMLL 100ns (min) 50ns (min) 50ns (min) 30ns (min) 30ns (min) 30ns (min) 30ns (min) 30ns + 1SYSCLK (min) 50% of VDD MC Pulse Cycle MC Pulsewidth “L” MC Pulse Cycle “H” MD Setup Time MD Hold Time ML Setup Time ML Hold Time ML Pulsewidth “L” FIGURE 5. Control Data Timing in Software Mode Control. RSTB tRST 50% of VDD RSTB Pulsewidth 20ns (min) FIGURE 6. External Reset Timing. ® PCM1719 10 0.1µF to 10µF Bypass Capacitor +5.0V Analog Power Supply 2 10pF to 22pF DGND 28 XTO XTAL 1 10pF to 22pF XTI 3 VDD CLKO 27 VDD 0.1µF to 10µF Bypass Capacitor AGND 10 COM 21 ZERO 7 10µF + 10µF + 10µF + 10µF + 100µF + 32Ω 470µF + 470µF + Headphone Out Post Low Pass Filter(1) + 10µF 4.7kΩ VCC 19 System Clock (256fS/384fS) PCM Audio Data Processer (DSP) 4 5 6 LRCIN DIN BCKIN PCM1719 VOUTR 9 Post Low Pass Filter(1) Line Out PINR 11 24 MD 25 MC 26 ML PCOM 12 PINL 18 VOUTL 20 10kΩ 10kΩ Function Control Processor (MPU) Reset Mute 23 RSTB 17 PMUTE PVCC 15 POUTR 13 32Ω POUTL 16 PAGND 14 NOTE: (1) Either passive or active, depending on application. 0.1µF to 10µF Bypass Capacitor FIGURE 7. Typical Circuit Connection. TYPICAL APPLICATION CIRCUIT Figure 7 shows the typical application circuit. In this circuit, VDD, VCC, and PVCC are connected to a common analog power supply. It is possible to use separate analog and digital power supplies for PCM1719. If separate supplies are used, the difference voltage between the supplies must be less than ± 0.1V. PCM1719’s headphone amplifier allows for high current flow from the outputs to ground. To keep the high load current from affecting the DAC’s performance, the headphone jack ground should be connected to a lowimpedance ground plane. Interference from the headphone amplifier can also be minimized by using a separate power supply for PVCC, but avoid power supply deltas greater than ±0.1V. Bypassing and decoupling capacitors should be placed as close as possible to the device pin. The capacitance between PCOM (pin 12) and/or COM (pin 21) to ground can be reduced to 1µF, but this may decrease performance of the PCM1719’s internal analog low-pass filter. The 10µF capacitor shown between COM and analog ground is used to set the pole for the PCM1719’s internal low-pass filter. It is also important to limit the measurement bandwidth of the PCM1719 to 20kHz during performance evaluation. By definition, delta-sigma DACs have a large amount of energy beyond the audio band. Including this energy in THD+N measurements will not demonstrate the true inband performance of PCM1719. ® 11 PCM1719 POWER SUPPLY CONNECTIONS PCM1719 has two power supply connections: digital (VDD) and analog (VCC). Each connection also has a separate ground. If the power supplies turn on at different times, there is a possibility of a latch-up condition. To avoid this condition, it is recommended to have a common connection between the digital and analog power supplies. If separate supplies are used without a common connection, the delta between the two supplies during ramp-up time must be less than 0.6V. An application circuit to avoid a latch-up condition is shown in Figure 8. A block diagram of the 5-level delta-sigma modulator is shown in Figure 9. This 5-level delta-sigma modulator has the advantage of stability and clock jitter sensitivity over the typical one-bit (2 level) delta-sigma modulator. The combined oversampling rate of the delta-sigma modulator and the internal 8-times interpolation filter is 48fS for a 384fS system clock, and 64fS for a 256fS system clock. The theoretical quantization noise performance of the 5-level delta-sigma modulator is shown in Figure 10. Digital Power Supply Analog Power Supply 3rd ORDER ∆Σ MODULATOR 20 0 VDD DGND VCC AGND Gain (–dB) –20 –40 –60 –80 –100 –120 –140 FIGURE 8. Latch-up Prevention Circuit. THEORY OF OPERATION The delta-sigma section of PCM1719 is based on a 5-level amplitude quantizer and a 3rd-order noise shaper. This section converts the oversampled input data to 5-level deltasigma format. –160 0 5 10 15 20 25 Frequency (kHz) FIGURE 10. Quantization Noise Spectrum. + In 8fS 18-Bit + – Z–1 + + Z–1 – + + Z–1 + + 5-level Quantizer + 4 3 Out 48fS (384fS) 64fS (256fS) 2 1 0 FIGURE 9. 5-Level ∆Σ Modulator Block Diagram. ® PCM1719 12 APPLICATION CONSIDERATIONS DELAY TIME There is a finite delay time in delta-sigma converters. In A/D converters, this is commonly referred to as latency. For a delta-sigma D/A converter, delay time is determined by the order number of the FIR filter stage, and the chosen sampling rate. The following equation expresses the delay time of PCM1719: TD = 11.125 x 1/fS For fS = 44.1kHz, TD = 11.125/44.1kHz = 502.8µs Applications using data from a disc or tape source, such as CD audio, CD-Interactive, Video CD, DAT, Minidisc, etc., generally are not affected by delay time. For some professional applications such as broadcast audio for studios, it is important for total delay time to be less than 2ms. INTERNAL RESET When power is first applied to PCM1719, an automatic reset function occurs after 1,024 cycles of XTI clock. Refer to Table I for default conditions. During the first 1,024 cycles of XTI clock, PCM1719 cannot be programmed (Software Control). Data can be loaded into the control registers during this time, and after 1,204 cycles of XTI clock, a “LOW” on ML (pin 18) will initiate programming. OUTPUT FILTERING For testing purposes all dynamic tests are done on the PCM1719 using a 20kHz low pass filter. This filter limits the measured bandwidth for THD+N, etc. to 20kHz. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the specifications. The low pass filter removes out-of-band noise. Although it is not audible, it may affect dynamic specification numbers. The performance of the internal low pass filter from DC to 24kHz is shown in Figure 11. The higher frequency rolloff of the filter is shown in Figure 12. If the user’s application has the PCM1719 driving a wideband amplifier, it is recommended to use an external low pass filter. A simple 3rdorder filter is shown in Figure 13. For some applications, a passive RC filter or 2nd-order filter may be adequate. INTERNAL ANALOG FILTER FREQUENCY RESPONSE (20Hz~24kHz, Expanded Scale) 1.0 0.5 dB 0 –0.5 –1.0 20 100 1k Frequency (Hz) 10k 24k FIGURE 11. Low Pass Filter Frequency Response. INTERNAL ANALOG FILTER FREQUENCY RESPONSE (10Hz~10MHz) 10 5 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 10 100 1k 10k 100k 1M 10M Frequency (Hz) FIGURE 12. Low Pass Filter Frequency Response. dB GAIN vs FREQUENCY 6 Gain –14 1500pF + VSIN – –74 –270 10kΩ 10kΩ 680pF 10kΩ 100pF 0 90 –54 Phase –180 –94 100 1k 10k Frequency (Hz) 100k 1M –360 FIGURE 13. 3rd-Order LPF. ® 13 PCM1719 Phase (°) OPA604 Gain (dB) –34 –90 Test Disk Lch CD Player DAI DEMPCM1719 Rch Through Shibasoku #725 Digital PGA External LPF 0dB/60dB THD Meter 30KHz LPF on For test of S/N ratio and Dynamic Range, A-filter ON. FIGURE 14. Test Block Diagram. TEST CONDITIONS Figure 14 illustrates the actual test conditions applied to PCM1719 in production. The external filter is necessary in the production environment for the removal of noise resulting from the relatively long physical distance between the unit and the test analyzer. In most actual applications, the 3rd-order filter shown in Figure 13 is adequate. Under normal conditions, THD+N typical performance is –70dB with a 30kHz low pass filter (shown here on the THD meter), improving to –89dB when the external 20kHz 11thorder filter is used. JITTER SENSITIVITY Delta-sigma DACs are by nature very sensitive to jitter on the master clock. Phase noise on the clock will result in an increase in noise, ultimately degrading dynamic range. It is difficult to quantify the effect of jitter due to problems in synthesizing low levels of jitter. One of the reasons deltasigma DACs are prone to jitter sensitivity is the large quantization noise when the modulator can only achieve two discrete output levels (0 or 1). The multi-level delta-sigma DAC has improved theoretical SNR because of multiple output states. This reduces sensitivity to jitter. Figure 15 contrasts jitter sensitivity between a one-bit PWM type DAC and multilevel delta-sigma DAC. The data was derived using a simulator, where clock jitter could be completely synthesized. 2 1 14.4ps 0 –1 48fs 2 FIGURE 16. Simulation Method for Clock Jitter. HEADPHONE AMPLIFIER PCM1719 has an integrated headphone amplifier which can directly drive a 32Ω load, such as headphones. The amplifier is configured in a gain of –2.8dB (inverting), and the maximum output current is 12.5mA (rms). The maximum output voltage is 0.8Vrms into a 64Ω load (stereo 32Ω headphones), based on the typical DAC full scale voltage output of 3.1V (p-p). PINL and PINR should be AC-coupled such that the input impedance for the headphone amplifier is 55kΩ typical, and the noninverting input is biased to VCC/2. The headphone amplifier has no internal current limiting circuit. It is recommended to used an external current limiting resistor to avoid damage caused by overloading the output, and avoid shorting POUTL and POUTR to ground. The minimum output load of 64Ω includes any current limiting resistor. If the input impedance of the headphone is 32Ω, a current limiting resistor of 32Ω should be used. Figure 17 0 –10 –20 THD+N (dB) 110 105 Dynamic Range (dB) 100 95 90 85 80 75 70 65 60 0 100 200 300 Clock Jitter (ps) 400 500 600 PWM Multi-level –30 –40 –50 –60 –70 –80 –90 VDD: 5V DAC Input: BPZ VIN = 3.1Vp-p (0dB) f = 1kHz 20kHz Bandwidth Limitation RP = 32Ω Test Point POUT RP Current Limit Resistor RH Headphone Resistor RL = RP + RH RL = 40Ω 48Ω 64Ω –60 –50 –40 –30 –20 –10 0 10 FIGURE 15. Simulation Results of Clock Jitter Sensitivity. ® Input Signal (dB) FIGURE 17. THD+N vs Input Signal, Output Load. PCM1719 14 illustrates THD+N versus input signal and output load. The PCM1719 headphone amplifier specification for THD+N is done with a 64Ω load at 12.5mA (rms) maximum output current. Although PCM1719 is capable of driving loads as low as 15Ω, the output waveform will be saturated under such a condition. The recommended application circuit employs a 32Ω load with a 32Ω current limiting resistor. VOLUME CONTROL PCM1719 allows the user to attentuate the volume by using a variable resistor. In the actual application, a 10kΩ pot is connected between the line (DAC) outputs and analog ground, with the center tap of the pot AC-coupled to the headphone amplifier’s inputs. Refer to Figure 7, the typical connection diagram, for an illustration of this circuit. ANALOG MUTE FUNCTION The headphone amplifier’s output can be muted to –80dB. When PMUTE is taken “LOW”, the headphone outputs are muted. For normal operation, PMUTE should be held “HIGH” or left open. ® 15 PCM1719