PCM3002EG

Burr Brown Products from Texas Instruments PCM3002 PCM3003 SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 16/20-BIT SINGLE-ENDED ANALOG INPUT/OUTPUT STEREO AUDIO CODECS FEATURES • • • • • Monolithic 20-Bit ∆Σ ADC and DAC 16/20-Bit Input/Output Data Software Control: PCM3002 Hardware Control: PCM3003 Stereo ADC: – Single-Ended Voltage Input – Antialiasing Filter – 64× Oversampling – High Performance • THD+N: –86 dB • SNR: 90 dB • Dynamic Range: 90 dB Stereo DAC: – Single-Ended Voltage Output – Analog Low-Pass Filter – 64× Oversampling – High Performance • THD+N: –86 dB • SNR: 94 dB • Dynamic Range: 94 dB Special Features (PCM3002, PCM3003) – Digital De-Emphasis: 32 kHz, 44.1 kHz, 48 kHz – Power Down: ADC/DAC Independent Special Features (PCM3002) – Digital Attenuation (256 Steps) – Soft Mute – Digital Loopback – Four Alternative Audio Data Formats Sampling Rate: 4 kHz to 48 kHz • • • • • Single 3-V Power Supply Small Package: SSOP-24 APPLICATIONS DVC Applications DSC Applications Portable/Mobile Audio Applications DESCRIPTION The PCM3002 and PCM3003 are low-cost, single-chip stereo audio codecs (analog-to-digital and digital-to-analog converters) with single-ended analog voltage input and output. The ADCs and DACs employ delta-sigma modulation with 64-times oversampling. The ADCs include a digital decimation filter, and the DACs include an 8-times oversampling digital interpolation filter. The DACs also include digital attenuation, de-emphasis, infinite zero detection, and soft mute to form a complete subsystem. The PCM3002 and PCM3003 operate with left-justified (ADC) and right-justified (DAC) formats, while the PCM3002 also supports other formats, including the I2S data format. The PCM3002 and PCM3003 provide a power-down mode that operates on the ADCs and DACs independently. The PCM3002 and PCM3003 are fabricated using a highly advanced CMOS process, and are available in a 24-pin SSOP package. The PCM3002 and PCM3003 are suitable for a wide variety of cost-sensitive consumer applications where good performance is required. The PCM3002 programmable functions are controlled by software. The PCM3003 functions, which are controlled by hardware, include de-emphasis, power-down, and audio data format selections. • • • • Lch In Analog Front-End Rch In Delta-Sigma Modulator Digital Decimation Filter * Digital Out Serial Interface and Mode Control Digital In Lch Out Rch Out Low-Pass Filter and Output Buffer * PCM3002 Only Multilevel Delta-Sigma Modulator Digital Interpolation Filter Mode Control System Clock B0006-01 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. System Two, Audio Precision are trademarks of Audio Precision, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2004, Texas Instruments Incorporated PCM3002 PCM3003 SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ELECTRICAL CHARACTERISTICS All specifications at TA = 25°C, VDD = VCC = 3 V, fS = 44.1 kHz, SYSCLK = 384 fS, and 16-bit data, unless otherwise noted PARAMETER DIGITAL INPUT/OUTPUT Input Logic VIH (1) (2) (3) VIL (1) (2) (3) IIN (2) IIN (1) (3) VOH (4) VOL (4) CONDITIONS PCM3002E/3003E MIN TYP MAX UNITS Input logic level Input logic current 0.7 VDD 0.3 VDD ±1 100 IOUT = –1 mA VDD – 0.3 0.3 0.3 4 (6) 256 fS 1.024 1.536 2.048 384 fS 512 fS 44.1 11.2896 16.9344 22.5792 20 48 12.288 18.432 24.576 VDC µA Output Logic Output logic level IOUT = 1 mA IOUT = 1 mA Sampling frequency System clock frequency ADC CHARACTERISTICS Resolution DC Accuracy Gain mismatch, channelto-channel Gain error Gain drift Bipolar zero error Bipolar zero drift Dynamic Performance (8) THD+N Dynamic range Signal-to-noise ratio Channel separation (1) (2) (3) (4) (5) (6) (7) (8) 2 VIN = –0.5 dB VIN = –60 dB A-weighted A-weighted 86 86 84 –86 –28 90 90 88 –80 dB dB dB dB High-pass filter bypassed (7) High-pass filter bypassed (7) ±1 ±2 ±20 ±1.7 ±20 ±3 ±5 % of FSR % of FSR ppm of FSR/°C % of FSR ppm of FSR/°C Bits VDC VOL (5) CLOCK FREQUENCY fs kHz MHz Pins 7, 8, 17 and 18: RST, ML, MD, and MC for the PCM3002; PDAD, PDDA, DEM1, and DEM0 for PCM3003 (Schmitt-trigger input with 100-kΩ typical internal pulldown resistor) Pins 9, 10, 11, 15: SYSCLK, LRCIN, BCKIN, DIN (Schmitt-trigger input) Pin 16: 20BIT for PCM3003 (Schmitt-trigger input, 100-kΩ typical internal pulldown resistor) Pin 12: DOUT Pin 16: ZFLG for PCM3002 (open-drain output) See Application Bulletin SBAA033 for information relating to operation at lower sampling frequencies. High-pass filter for offset cancel fIN = 1 kHz, using the System Two™ audio measurement system by Audio Precision™ in rms mode with 20-kHz LPF, 400-Hz HPF used for performance calculation. PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = VCC = 3 V, fS = 44.1 kHz, SYSCLK = 384 fS, and 16-bit data, unless otherwise noted PARAMETER Digital Filter Performance Pass band Stop band Pass-band ripple Stop-band attenuation Delay time HPF frequency response Analog Input Voltage range Center voltage Input impedance Antialiasing filter frequency response DAC CHARACTERISTICS Resolution DC Accuracy Gain mismatch, channelto-channel Gain error Gain drift Bipolar zero error Bipolar zero drift Dynamic Performance (9) THD+N Dynamic range Signal-to-noise ratio Channel separation Digital Filter Performance Pass band Stop band Pass-band ripple Stop-band attenuation Delay time Analog Output Voltage range Center voltage Load impedance LPF frequency response (9) AC coupling f = 20 kHz 10 –0.16 0.6 VCC 0.5 VCC Vp-p VDC kΩ dB –35 11.1/fS 0.555 fS ±0.17 0.445 fS Hz Hz dB dB s VOUT = 0 dB (full scale) VOUT = –60 dB EIAJ, A-weighted EIAJ, A-weighted 88 88 86 –86 –32 94 94 91 –80 dB dB dB dB ±1 ±1 ±20 ±2.5 ±20 ±3 ±5 % of FSR % of FSR ppm of FSR/°C % of FSR ppm of FSR/°C 20 Bits –3 dB 0.6 VCC 0.5 VCC 30 150 Vp-p VDC kΩ kHz –3 dB –65 17.4/fS 0.019 fS 0.583 fS ±0.05 0.454 fS Hz Hz dB dB s mHz CONDITIONS PCM3002E/3003E MIN TYP MAX UNITS fOUT = 1 kHz, using the System Two audio measurement system by Audio Precision in rms mode with 20-kHz LPF, 400-Hz HPF used for performance calculation. 3 PCM3002 PCM3003 SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = VCC = 3 V, fS = 44.1 kHz, SYSCLK = 384 fS, and 16-bit data, unless otherwise noted PARAMETER POWER SUPPLY REQUIREMENTS VCC, VDD Supply voltage Supply current –25°C to 85°C 0° C to 70°C (10) Operation, VCC = VDD = 3 V Power down, VCC = VDD = 3 V Operation, VCC = VDD = 3 V Power dissipation TEMPERATURE RANGE TA Tstg θJA Operation Storage Thermal resistance –25 –55 100 85 125 °C °C °C/W Power down (11), VCC = VDD = 3V 2.7 2.4 3 3 18 50 54 150 72 3.6 3.6 24 VDC VDC mA µA mW µW CONDITIONS PCM3002E/3003E MIN TYP MAX UNITS (10) Applies for voltages between 2.4 V and 2.7 V for 0°C to 70°C and 256 fS/512 fS operation (384 fS not available) (11) SYSCLK, BCKIN, and LRCIN are stopped. PACKAGE/ORDERING INFORMATION PRODUCT PCM3002E PCM3003E PACKAGE TYPE 24-pin SSOP 24-pin SSOP PACKAGE CODE DB DB PACKAGE MARKING PCM3002E PCM3003E ORDERING NUMBER PCM3002E PCM3002E/2K PCM3003E PCM3003E/2K TRANSPORT MEDIA Rails Tape and reel Rails Tape and reel QUANTITY 58 2000 58 2000 ABSOLUTE MAXIMUM RATINGS Supply voltage VDD, VCC1, VCC2 Supply voltage differences GND voltage differences Digital input voltage Analog input voltage Power dissipation Input current (any pins except supplies) Operating temperature Storage temperature Lead temperature, soldering Package temperature (IR reflow, peak) –0.3 V to 6.5 V ±0.1 V ±0.1 V –0.3 V to VDD + 0.3 V, < 6.5 V –0.3 V to VCC1, VCC2 + 0.3 V, < 6.5 V 300 mW ±10 mA –25°C to 85°C –55°C to 125°C 260°C, 5 s 235°C 4 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range MIN Analog supply voltage, VCC1, VCC2 Digital supply voltage, VDD Analog input voltage, full scale (–0 dB) Digital input logic family Digital input clock frequency Analog output load resistance Analog output load capacitance Digital output load capacitance Operating free-air temperature, TA PCM3002 (TOP VIEW) NOM 3 3 1.8 CMOS MAX 3.6 3.6 UNIT V V Vp-p 2.7 2.7 VCC = 3 V System clock Sampling clock 8.192 32 10 24.576 48 30 10 MHz kHz kΩ pF pF –25 PCM3003 (TOP VIEW) 24 23 22 21 20 19 18 17 16 15 14 13 85 °C VCC1 VCC1 VINR VREF1 VREF2 VINL RST ML SYSCLK LRCIN BCKIN DOUT 1 2 3 4 5 6 7 8 9 10 11 12 VCC2 AGND1 AGND2 VCOM VOUTR VOUTL MC MD ZFLG DIN VDD DGND VCC1 VCC1 VINR VREF1 VREF2 VINL PDAD PDDA SYSCLK LRCIN BCKIN DOUT 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC2 AGND1 AGND2 VCOM VOUTR VOUTL DEM0 DEM1 20BIT DIN VDD DGND P0004-02 PIN ASSIGNMENTS—PCM3002 NAME AGND1 AGND2 BCKIN DGND DIN DOUT LRCIN MC MD ML RST SYSCLK VCC1 VCC2 VCOM VDD (1) (2) PIN 23 22 11 13 15 12 10 18 17 8 7 9 1, 2 24 21 14 I/O – – I – I O I I I I I I – – – – ADC analog ground DAC analog ground Bit clock input (1) Digital ground Data input (1) Data output Sample rate clock input (fs) (1) Bit clock for mode control (1) (2) Serial data for mode control (1) (2) Strobe pulse for mode control (1) (2) Reset, active LOW (1) (2) System clock input (1) ADC analog power supply DAC analog power supply ADC/DAC common Digital power supply DESCRIPTION Schmitt-trigger input With 100-kΩ typical internal pulldown resistor 5 PCM3002 PCM3003 SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 www.ti.com PIN ASSIGNMENTS—PCM3002 (continued) NAME VINL VINR VOUTL VOUTR VREF1 VREF2 ZFLG (3) Open-drain output PIN 6 3 19 20 4 5 16 I/O I I O O – – O ADC analog input, Lch ADC analog input, Rch DAC analog output, Lch DAC analog output, Rch ADC reference 1 ADC reference 2 Zero flag output, active LOW (3) DESCRIPTION PIN ASSIGNMENTS—PCM3003 NAME AGND1 AGND2 BCKIN DEM0 DEM1 DGND DIN DOUT LRCIN PDAD PDDA SYSCLK VCC1 VCC2 VCOM VDD VINL VINR VOUTL VOUTR VREF1 VREF2 20BIT (1) (2) PIN 23 22 11 18 17 13 15 12 10 7 8 9 1, 2 24 21 14 6 3 19 20 4 5 16 I/O – – I I I – I O I I I I – – – – I I O O – – I ADC analog ground DAC analog ground Bit clock input (1) De-emphasis control 0 (1) (2) De-emphasis control 1 (1) (2) Digital ground Data input (1) Data output Sample rate clock input (fs) (1) ADC power down, active LOW (1) (2) DAC power down, active LOW (1) (2) System clock input (1) ADC analog power supply DAC analog power supply ADC/DAC common Digital power supply ADC analog input, Lch ADC analog input, Rch DAC analog output, Lch DAC analog output, Rch ADC reference 1 ADC reference 2 20-bit format select(1)(2) DESCRIPTION Schmitt-trigger input With 100-kΩ typical internal pulldown resistor 6 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, and fSIGNAL = 1 kHz, unless otherwise noted ADC SECTION THD+N vs TEMPERATURE THD+N − Total Harm. Dist. + Noise at −0.5 dB − % THD+N − Total Harm. Dist. + Noise at −60 dB − % 0.010 5 94 DYNAMIC RANGE and SNR vs TEMPERATURE 94 0.008 −60 dB 4 92 Dynamic Range − dB Dynamic Range 92 0.006 −0.5 dB 3 90 SNR 90 0.004 2 88 88 0.002 −25 0 25 50 75 1 100 G001 86 −25 0 25 50 75 86 100 G002 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 1. THD+N vs SUPPLY VOLTAGE THD+N − Total Harm. Dist. + Noise at −0.5 dB − % THD+N − Total Harm. Dist. + Noise at −60 dB − % 0.010 5 94 Figure 2. DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE 94 0.008 4 92 Dynamic Range − dB Dynamic Range 92 0.006 3 90 SNR 90 0.004 −0.5 dB 2 88 88 0.002 2.1 2.4 2.7 3.0 3.3 3.6 1 3.9 G003 86 2.1 2.4 2.7 3.0 3.3 3.6 86 3.9 G004 VCC − Supply Voltage − V VCC − Supply Voltage − V Figure 3. Figure 4. NOTE: All characteristics at supply voltages from 2.4 V to 2.7 V are measured at SYSCLK = 256 fS. SNR − Signal-to-Noise Ratio − dB −60 dB SNR − Signal-to-Noise Ratio − dB 7 PCM3002 PCM3003 SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 www.ti.com TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, and fSIGNAL = 1 kHz, unless otherwise noted THD+N vs SAMPLING FREQUENCY THD+N − Total Harm. Dist. + Noise at −0.5 dB − % THD+N − Total Harm. Dist. + Noise at −60 dB − % 0.010 5 94 DYNAMIC RANGE and SNR vs SAMPLING FREQUENCY 94 0.008 4 92 Dynamic Range − dB Dynamic Range 92 0.006 3 90 SNR 88 90 0.004 −0.5 dB 2 88 0.002 32 44.1 48 fS − Sampling Frequency − kHz 1 86 32 44.1 48 fS − Sampling Frequency − kHz 86 G005 G006 Figure 5. Figure 6. DAC SECTION THD+N vs TEMPERATURE THD+N − Total Harm. Dist. + Noise at −60 dB − % 0.010 THD+N − Total Harm. Dist. + Noise at FS − % 4 98 DYNAMIC RANGE and SNR vs TEMPERATURE 98 0.008 −60 dB 3 96 Dynamic Range − dB Dynamic Range 96 0.006 2 94 94 SNR 92 92 0.004 FS 1 0.002 −25 0 25 50 75 0 100 G007 90 −25 0 25 50 75 90 100 G008 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 7. Figure 8. 8 SNR − Signal-to-Noise Ratio − dB SNR − Signal-to-Noise Ratio − dB −60 dB PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, and fSIGNAL = 1 kHz, unless otherwise noted THD+N vs SUPPLY VOLTAGE THD+N − Total Harm. Dist. + Noise at −60 dB − % 0.010 THD+N − Total Harm. Dist. + Noise at FS − % 4 98 DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE 98 0.008 −60 dB 3 96 Dynamic Range − dB Dynamic Range 94 96 0.006 2 94 FS 0.004 1 SNR 92 92 0.002 2.1 2.4 2.7 3.0 3.3 3.6 0 3.9 G009 90 2.1 2.4 2.7 3.0 3.3 3.6 90 3.9 G010 VCC − Supply Voltage − V VCC − Supply Voltage − V Figure 9. Figure 10. NOTE: All characteristics at supply voltages from 2.4 V to 2.7 V are measured at SYSCLK = 256 fS. THD+N vs SAMPLING FREQUENCY and SYSTEM CLOCK THD+N − Total Harm. Dist. + Noise at −60 dB − % 0.010 THD+N − Total Harm. Dist. + Noise at FS − % 4 98 DYNAMIC RANGE and SNR vs SAMPLING FREQUENCY and SYSTEM CLOCK 98 256 fS, 512 fS 96 Dynamic Range − dB SNR 0.008 −60 dB 3 384 fS 256 fS, 512 fS 96 0.006 384 fS 2 FS 256 fS, 512 fS 94 Dynamic Range 94 0.004 1 92 384 fS 92 0.002 32 44.1 48 fS − Sampling Frequency − kHz 0 90 32 44.1 48 fS − Sampling Frequency − kHz 90 G011 G012 Figure 11. Figure 12. SNR − Signal-to-Noise Ratio − dB SNR − Signal-to-Noise Ratio − dB 9 PCM3002 PCM3003 SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 www.ti.com TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, and fSIGNAL = 1 kHz, unless otherwise noted OUTPUT SPECTRUM ADCs OUTPUT SPECTRUM (–0.5 dB, N = 8192) 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 0 5 10 15 20 25 G013 OUTPUT SPECTRUM (–60 dB, N = 8192) 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 0 5 10 15 20 25 G015 f − Frequency − kHz f − Frequency − kHz Figure 13. THD+N vs SIGNAL LEVEL 100 THD+N − Total Harmonic Distortion + Noise − % Figure 14. 10 1 0.1 0.01 0.001 −96 −84 −72 −60 −48 −36 −24 −12 0 G017 Signal Level − dB Figure 15. 10 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, and fSIGNAL = 1 kHz, unless otherwise noted DACs OUTPUT SPECTRUM (0 dB, N = 8192) 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 0 5 10 15 20 25 G014 OUTPUT SPECTRUM (–60 dB, N = 8192) 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 0 5 10 15 20 25 G016 f − Frequency − kHz f − Frequency − kHz Figure 16. THD+N vs SIGNAL LEVEL 100 THD+N − Total Harmonic Distortion + Noise − % Figure 17. 10 1 0.1 0.01 0.001 −96 −84 −72 −60 −48 −36 −24 −12 0 G018 Signal Level − dB Figure 18. 11 PCM3002 PCM3003 SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 www.ti.com TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, DIN = BPZ, and VIN = BPZ, unless otherwise noted SUPPLY CURRENT ICC + IDD vs SUPPLY VOLTAGE 25 2.5 25 ICC + IDD vs TEMPERATURE 2.5 ICC + IDD: Power Down and Off − mA 20 ADC and DAC ICC + IDD − mA 15 ADC 10 DAC 5 Power Down and Off 0 2.1 2.4 2.7 3.0 3.3 3.6 2.0 20 ADC and DAC 2.0 1.5 15 ADC 10 DAC 5 1.5 1.0 1.0 0.5 0.5 Power Down and Off 0 3.9 G020 0 −50 −25 0 25 50 75 0 100 G019 VCC − Supply Voltage − V TA − Free-Air Temperature − °C Figure 19. Figure 20. All characteristics at supply voltages from 2.4 V to 2.7 V are measured at SYSCLK = 256 fS. ICC + IDD vs SAMPLING FREQUENCY 20 ADC and DAC 19 512 fS ICC + IDD − mA 18 256 fS 17 16 15 32 44.1 48 G021 fS − Sampling Frequency − kHz Figure 21. 12 ICC + IDD: Power Down and Off − mA ICC + IDD − mA PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, and fSYSCLK = 384 fS, unless otherwise noted DECIMATION FILTER OVERALL CHARACTERISTICS 0 0 STOP-BAND ATTENUATION CHARACTERISTICS −20 −50 Amplitude − dB Amplitude − dB 0 8 16 24 32 G022 −40 −100 −60 −150 −80 −200 Normalized Frequency [× fS Hz] −100 0.0 0.2 0.4 0.6 0.8 1.0 G023 Normalized Frequency [× fS Hz] Figure 22. PASS-BAND RIPPLE CHARACTERISTICS 0.2 0 −1 0.0 −2 −3 Amplitude − dB −4 −5 −6 −7 −8 −9 −1.0 0.0 Figure 23. TRANSITION BAND CHARACTERISTICS Amplitude − dB −0.2 −0.4 −0.6 −0.8 0.1 0.2 0.3 0.4 0.5 G024 −4.13 dB at 0.5 fS −10 0.45 0.47 0.49 0.51 0.53 0.55 G025 Normalized Frequency [× fS Hz] Normalized Frequency [× fS Hz] Figure 24. Figure 25. 13 PCM3002 PCM3003 SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 www.ti.com TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs) (continued) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, and fSYSCLK = 384 fS, unless otherwise noted HIGH-PASS FILTER HIGH-PASS FILTER RESPONSE 0 −10 −20 −30 Amplitude − dB −40 −50 −60 −70 −80 −90 −100 0.0 −1.0 0.1 0.2 0.3 0.4 0.5 G026 HIGH-PASS FILTER RESPONSE 0.2 0.0 Amplitude − dB −0.2 −0.4 −0.6 −0.8 0 1 2 3 4 G027 Normalized Frequency [× fS/1000 Hz] Normalized Frequency [× fS/1000 Hz] Figure 26. Figure 27. ANTIALIASING FILTER ANTIALIASING FILTER OVERALL FREQUENCY RESPONSE 0 0.2 ANTIALIASING FILTER PASS-BAND FREQUENCY RESPONSE −10 0.0 Amplitude − dB −20 Amplitude − dB 1 10 100 1k 10k 100k 1M 10M G028 −0.2 −0.4 −30 −0.6 −40 −0.8 −50 f − Frequency − Hz −1.0 1 10 100 1k 10k 100k G029 f − Frequency − Hz Figure 28. Figure 29. 14 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, and fSYSCLK = 384 fS, unless otherwise noted DIGITAL FILTER OVERALL FREQUENCY CHARACTERISTICS (fS = 44.1 kHz) 0 0.00 PASS-BAND RIPPLE CHARACTERISTICS (fS = 44.1 kHz) −20 −0.20 Level − dB −60 Level − dB 0 25k 50k 75k 100k 125k 150k 175k G030 −40 −0.40 −0.60 −80 −0.80 −100 f − Frequency − Hz −1.00 0 5k 10k f − Frequency − Hz G031 15k 20k Figure 30. Figure 31. DE-EMPHASIS FILTER DE-EMPHASIS FREQUENCY RESPONSE (32 kHz) 0 0.6 DE-EMPHASIS ERROR (32 kHz) −2 0.4 −4 Level − dB Error − dB 0 5k 10k 15k 20k 25k G032 0.2 −6 0.0 −8 −0.2 −10 −0.4 −12 f − Frequency − Hz −0.6 0 3628 7256 f − Frequency − Hz G033 10884 14512 Figure 32. Figure 33. 15 PCM3002 PCM3003 SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 www.ti.com TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, and fSYSCLK = 384 fS, unless otherwise noted DE-EMPHASIS FREQUENCY RESPONSE (44.1 kHz) 0 0.6 DE-EMPHASIS ERROR (44.1 kHz) −2 0.4 −4 Level − dB Error − dB 0 5k 10k 15k 20k 25k G034 0.2 −6 0.0 −8 −0.2 −10 −0.4 −12 f − Frequency − Hz −0.6 0 4999.8375 9999.675 14999.5125 19999.35 G035 f − Frequency − Hz Figure 34. DE-EMPHASIS FREQUENCY RESPONSE (48 kHz) 0 0.6 Figure 35. DE-EMPHASIS ERROR (48 kHz) −2 0.4 −4 Level − dB Error − dB 0 5k 10k 15k 20k 25k G036 0.2 −6 0.0 −8 −0.2 −10 −0.4 −12 f − Frequency − Hz −0.6 0 5442 10884 f − Frequency − Hz G037 16326 21768 Figure 36. Figure 37. 16 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, and fSYSCLK = 384 fS, unless otherwise noted ANALOG LOW-PASS FILTER INTERNAL ANALOG FILTER FREQUENCY RESPONSE (1 Hz–10 MHz) 20 INTERNAL ANALOG FILTER FREQUENCY RESPONSE (1 Hz–100 kHz) 0.15 0 0.10 −20 Level − dB Level − dB 1 10 100 1k 10k 100k 1M 10M G038 0.05 −40 0.00 −60 −0.05 −80 −0.10 −100 f − Frequency − Hz −0.15 1 10 100 1k 10k 100k G039 f − Frequency − Hz Figure 38. Figure 39. 17 PCM3002 PCM3003 SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 www.ti.com BLOCK DIAGRAM (+) VINL Analog Front-End Circuit (−) Delta-Sigma Modulator Decimation and High-Pass Filter LRCIN VREF1 VCOM VREF2 BCKIN Reference ADC Serial Data Interface DIN (−) VINR Analog Front-End Circuit Delta-Sigma Modulator Decimation and High-Pass Filter DOUT (+) MC(1)/DEM0(2) VOUTL Analog Low-Pass Filter Multilevel Delta-Sigma Modulator Interpolation Filter 8× Oversampling Mode Control Interface MD(1)/DEM1(2) ML(1) 20BIT(2) DAC Analog Low-Pass Filter Multilevel Delta-Sigma Modulator Interpolation Filter 8× Oversampling VOUTR Reset and Power Down PDDA(2) RST(1)/PDAD(2) Power Supply Clock Zero Detect(1) AGND2 VCC2 AGND1 VCC1 DGND VDD SYSCLK ZFLG(1) B0004-03 (1) (2) MC, MD, ML, RST, and ZFLG are for PCM3002 only. DEM0, DEM1, 20BIT, PDAD, and PDDA are for PCM3003 only. 18 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 1.0 µF + 3 VINR 30 kΩ − − + + (−) (+) 21 4.7 µF + 4 4.7 µF + 5 4.7 µF + VCOM Delta-Sigma Modulator VREF1 VREF2 VREF S0011-03 Figure 40. Analog Front-End (Single-Channel) PCM AUDIO INTERFACE The four-wire digital audio interface for the PCM3002/3003 comprises LRCIN (pin 10), BCKIN (pin 11), DIN (pin 15), and DOUT (pin 12). The PCM3002 can be used with any of the four input/output data formats (formats 0–3), while the PCM3003 can only be used with selected input/output formats (formats 0–1). For the PCM3002, these formats are selected through program register 3 in the software mode. For the PCM3003, data formats are selected by the 20BIT input (pin 16). Figure 41, Figure 42, and Figure 43 illustrate audio data input/output formats and timing. The PCM3002/3003 can accept 32, 48, or 64 bit clocks (BCKIN) in one clock of LRCIN. Only the 16-bit data format can be selected when 32-bit clocks/LRCIN are applied. 19 PCM3002 PCM3003 SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 www.ti.com FORMAT 0: PCM3002/3003 DAC: 16-Bit, MSB-First, Right-Justified LRCIN BCKIN DIN 16 1 2 3 14 15 16 LSB 1 2 3 14 15 16 LSB Left-Channel Right-Channel MSB MSB ADC: 16-Bit, MSB-First, Left-Justified LRCIN BCKIN DOUT 1 2 3 14 15 16 LSB 1 2 3 14 15 16 LSB 1 Left-Channel Right-Channel MSB MSB FORMAT 1: PCM3002/3003 DAC: 20-Bit, MSB-First, Right-Justified LRCIN BCKIN DIN 20 1 2 3 18 19 20 LSB 1 2 3 18 19 20 LSB Left-Channel Right-Channel MSB MSB ADC: 20-Bit, MSB-First, Left-Justified LRCIN BCKIN DOUT 1 2 3 18 19 20 LSB 1 2 3 18 19 20 LSB T0016-04 Left-Channel Right-Channel 1 MSB MSB Figure 41. Audio Data Input/Output Format 20 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 FORMAT 2: PCM3002 Only DAC: 20-Bit, MSB-First, Left-Justified LRCIN BCKIN DIN 1 2 3 18 19 20 LSB 1 2 3 18 19 20 LSB 1 Left-Channel Right-Channel MSB MSB ADC: 20-Bit, MSB-First, Left-Justified LRCIN BCKIN DOUT 1 2 3 18 19 20 LSB 1 2 3 18 19 20 LSB 1 Left-Channel Right-Channel MSB MSB FORMAT 3: PCM3002 Only DAC: 20-Bit, MSB-First, I2S LRCIN BCKIN DIN 1 2 3 18 19 20 LSB 1 2 3 18 19 20 LSB Left-Channel Right-Channel MSB MSB ADC: 20-Bit, MSB-First, I2S LRCIN BCKIN DOUT 1 2 3 18 19 20 LSB 1 2 3 18 19 20 LSB T0016-05 Left-Channel Right-Channel MSB MSB Figure 42. Audio Data Input/Output Format (PCM3002) 21 PCM3002 PCM3003 SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 www.ti.com t(LRP) LRCIN t(BCL) t(BCH) t(BL) 0.5 VDD t(BCY) t(DIS) t(DIH) t(LB) 0.5 VDD BCKIN DIN t(BDO) t(LDO) 0.5 VDD DOUT 0.5 VDD T0021−01 BCKIN pulse cycle time BCKIN pulse duration, HIGH BCKIN pulse duration, LOW BCKIN rising edge to LRCIN edge LRCIN edge to BCKIN rising edge LRCIN pulse duration DIN setup time DIN hold time DOUT delay time to BCKIN falling edge DOUT delay time to LRCIN edge Rising time of all signals Falling time of all signals t(BCY) t(BCH) t(BCL) t(BL) t(LB) t(LRP) t(DIS) t(DIH) t(BDO) t(LDO) t(RISE) t(FALL) 300 ns (min) 120 ns (min) 120 ns (min) 40 ns (min) 40 ns (min) t(BCY) (min) 40 ns (min) 40 ns (min) 40 ns (max) 40 ns (max) 20 ns (max) 20 ns (max) Figure 43. Audio Data Input/Output Timing SYSTEM CLOCK The system clock for the PCM3002/3003 must be either 256 fS, 384 fS, or 512 fS, where fS is the audio sampling frequency. The system clock should be provided at the SYSCLK input (pin 9). The PCM3002/3003 also has a system-clock detection circuit that automatically senses if the system clock is operating at 256 fS, 384 fS, or 512 fS. When a 384-fS or 512-fS system clock is used, the clock is divided to 256 fS automatically. The 256-fS clock is used to operate the digital filters and the delta-sigma modulators. Table 1 lists the relationship of typical sampling frequencies and system clock frequencies; Figure 44 illustrates the system clock timing. Table 1. System Clock Frequencies SAMPLING RATE FREQUENCY (kHz) 256 fs 32 44.1 48 8.1920 11.2896 12.2880 SYSTEM CLOCK FREQUENCY (MHz) 384 fs 12.2880 16.9344 18.4320 512 fs 16.3840 22.5792 24.5760 22 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 t(SCKH) H SYSCLK L t(SCKL) 1/256 fS, 1/384 fS, or 1/512 fS T0005-05 0.7 VDD 0.3 VDD Figure 44. System Clock Timing System clock pulse duration, HIGH System clock pulse duration, LOW t(SCKH) t(SCKL) 12 ns (min) 12 ns (min) POWER-ON RESET Both the PCM3002 and PCM3003 have internal power-on reset circuitry. Power-on reset occurs when the system clock (SYSCLK) is active and VDD > 2.2 V. For the PCM3003, the SYSCLK must complete a minimum of three complete cycles prior to VDD > 2.2 V to ensure proper reset operation. The initialization sequence requires 1024 SYSCLK cycles for completion, as shown in Figure 45. Figure 46 shows the state of the DAC and ADC outputs during and after the reset sequence. 2.4 V 2.2 V 2.0 V VDD Reset Internal Reset Reset Removal 3 Clocks Minimum 1024 System Clock Periods System Clock T0014-03 Figure 45. Internal Power-On Reset Timing 23 PCM3002 PCM3003 SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 www.ti.com Reset Removal or Power Down Off Internal Reset or Power Down Reset Power Down t(DACDLY1) (16384/fS) DAC VOUT GND VCOM (0.5 VCC) t(ADCDLY1) (18432/fS) ADC DOUT Zero Data Zero Data Normal Data(1) T0019-02 Ready/Operation (1) The HPF transient response (exponentially attenuated signal from ±0.2% dc of FSR with 200-ms time constant) appears initially. Figure 46. DAC Output and ADC Output for Reset and Power Down EXTERNAL RESET The PCM3002 includes a reset input, RST (pin 7), while the PCM3003 uses both PDAD (pin 7) and PDDA (pin 8) for external reset control. As shown in Figure 47, the external reset signal must drive RST or PDAD and PDDA low for a minimum of 40 nanoseconds while SYSCLK is active in order to initiate the reset sequence. Initialization starts on the rising edge of RST or PDAD and PDDA, and requires 1024 SYSCLK cycles for completion. Figure 46 shows the state of the DAC and ADC outputs during and after the reset sequence. RST or PDAD and PDDA RST Pulse Duration t(RST) = 40 ns (min) t(RST) Reset Internal Reset 1024 System Clock Periods System Clock T0015-02 Reset Removal Figure 47. External Forced-Reset Timing SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM The PCM3002/3003 operates with LRCIN synchronized to the system clock. The PCM3002/3003 does not require any specific phase relationship between LRCIN and the system clock, but there must be synchronization of LRCIN and the system clock. If the synchronization between the system clock and LRCIN changes more than 6 bit clocks (BCKIN) during one sample (LRCIN) period because of phase jitter on LRCIN, internal operation of the DAC stops within 1/fS, and the analog output is forced to bipolar zero (0.5 VCC) until the system clock is resynchronized to LRCIN followed by t(DACDLY2) delay time. Internal operation of the ADC also stops within 1/fS, and the digital output codes are set to bipolar zero until resynchronization occurs followed by t(ADCDLY2) delay time. If LRCIN is synchronized within 5 or fewer bit clocks to the system clock, operation is normal. Figure 48 illustrates the effects on the output when synchronization is lost. Before the outputs are forced to bipolar zero ( 10 kΩ, depending on system performance requirements MC, MD, ML, ZFLG, RST, and 10-kΩ pullup resistor are for the PCM3002. DEM0, DEM1, 20BIT, PDAD, PDDA are for the PCM3003. Figure 51. Typical Connection Diagram for PCM3002/3003 33 PCM3002 PCM3003 SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 www.ti.com THEORY OF OPERATION ADC SECTION The PCM3002/3003 ADC consists of two reference circuits, a stereo single-to-differential converter, a fully differential fifth-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface circuit. The block diagram in this data sheet illustrates the architecture of the ADC section, Figure 40 shows the single-to-differential converter, and Figure 52 illustrates the architecture of the fifth-order delta-sigma modulator and transfer functions. An internal reference circuit with three external capacitors provides all reference voltages required by the ADC, which defines the full-scale range for the converter. The internal single-to-differential voltage converter saves the space and extra parts needed for the external circuitry required by many delta-sigma converters. The internal full-differential signal processing architecture provides a wide dynamic range and excellent power supply rejection performance. The input signal is sampled at a 64× oversampling rate, eliminating the need for a sample-and-hold circuit, and simplifying antialias filtering requirements. The fifth-order delta-sigma noise shaper consists of five integrators which use a switched-capacitor topology, a comparator, and a feedback loop consisting of a one-bit DAC. The delta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain. The high order of the modulator enables it to randomize the modulator outputs, reducing idle tone levels. The 64-fS, one-bit data stream from the modulator is converted to 1-fS, 16/20-bit data words by the decimation filter, which also acts as a low-pass filter to remove the shaped quantization noise. The dc components are removed by a high-pass filter function contained within the decimation filter. DAC SECTION The delta-sigma DAC section of the PCM3002/3003 is based on a 5-level amplitude quantizer and a third-order noise shaper. This section converts the oversampled input data to a 5-level delta-sigma format. A block diagram of the 5-level delta-sigma modulator is shown in Figure 53. This 5-level delta-sigma modulator has the advantage of improved stability and reduced clock-jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator. The combined oversampling rate of the delta-sigma modulator and the internal 8× interpolation filter is 64 fS for a 256-fS system clock. The theoretical quantization noise performance of the 5-level delta-sigma modulator is shown in Figure 54. Analog In X(z) + − 1st SW-CAP Integrator + − 2nd SW-CAP Integrator 3rd SW-CAP Integrator + − 4th SW-CAP Integrator 5th SW-CAP Integrator Qn(z) + + + + + + + + Digital Out Y(z) H(z) Comparator 1-Bit DAC Y(z) = STF(z) * X(z) + NTF(z) * Qn(z) Signal Transfer Function STF(z) = H(z) / [1 + H(z)] Noise Transfer Function NTF(z) = 1 / [1 + H(z)] B0005-01 Figure 52. Simplified Fifth-Order Delta-Sigma Modulator 34 PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 THEORY OF OPERATION (continued) In 8 fS 21-Bit + + − Z−1 + + − Z−1 + + Z−1 + 5-Level Quantizer + + 4 3 Out 64 fS 2 1 0 B0008-01 Figure 53. Five-Level Delta-Sigma Modulator Block Diagram 0 −10 −20 −30 −40 −50 Gain − dB −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 0 5 10 15 20 25 30 G040 f − Frequency − kHz Figure 54. Quantization Noise Spectrum 35 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2007 PACKAGING INFORMATION Orderable Device PCM3002E PCM3002E/2K PCM3002E/2KG4 PCM3002EG PCM3002EG/2K PCM3002EG/2KE6 PCM3002EG4 PCM3002EGE6 PCM3003E PCM3003E/2K PCM3003E/2KG4 PCM3003EG4 (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type SSOP SSOP SSOP SSOP SSOP SSOP SSOP SSOP SSOP SSOP SSOP SSOP Package Drawing DB DB DB DB DB DB DB DB DB DB DB DB Pins Package Eco Plan (2) Qty 24 24 24 24 24 24 24 24 24 24 24 24 58 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU SNBI CU SNBI CU SNBI CU NIPDAU CU SNBI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-1-260C-UNLIM Level-2-260C-1 YEAR Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 58 2000 2000 58 58 58 Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS & no Sb/Br) Pb-Free (RoHS) Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 58 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2007 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) 28 PINS SHOWN 0,65 28 0,38 0,22 15 0,15 M PLASTIC SMALL-OUTLINE 0,25 0,09 5,60 5,00 8,20 7,40 Gage Plane 1 A 14 0°– 8° 0,25 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** DIM A MAX 14 16 20 24 28 30 38 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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