PCM3052ARTFRG4

Burr Brown Products from Texas Instruments PCM3052A SLES160 – NOVEMBER 2005 24-BIT, 96-kHz STEREO AUDIO CODEC WITH MICROPHONE AMPLIFIER, BIAS, MUXTIPLEXER, AND PGA FEATURES • Microphone Amplifier and Bias – Monaural Microphone Amplifier: 34-dB Gain at Differential Input – Microphone Bias: 1 mA at 3.75 V Multiplexer and PGA – Multiplex of Stereo Single-Ended Line Inputs and Monaural Microphone Amplifier – 0.1 Vrms to 1.5 Vrms Full-Scale Input Range – 22-kΩ Input Resistance at 0.1-Vrms Input – 20 dB to –4 dB/range, 1 dB/step PGA Reference Output: ±10 mA at 2.5 V 24-Bit Delta-Sigma ADC and DAC Stereo ADC: – Full-Scale Input: 3 Vp-p – Antialiasing Filter Included – 1/64 Decimation Filter: • Pass-Band Ripple: ±0.05 dB • Stop-Band Attenuation: –65 dB – On-Chip High-Pass Filter: 0.91 Hz at fS = 48 kHz – High Performance: • THD+N: –94 dB (Typical) • SNR: 101 dB (Typical) • Dynamic Range: 101 dB (Typical) Stereo DAC: – Single-Ended Voltage Output: 4 Vp-p – Analog Low-Pass Filter Included – ×8 Oversampling Digital Filter: • Pass-Band Ripple: ±0.03 dB • Stop-Band Attenuation: –50 dB – High Performance: • THD+N: –97 dB (Typical) • SNR: 105 dB (Typical) • Dynamic Range: 104 dB (Typical) S/PDIF Output for DAC Digital Input A • • • • • • • • • • • Multiple Functions With I2C Interface: – Digital De-Emphasis: 32-, 44.1-, 48-kHz – Zipper-Noise-Free Digital Attenuation and Soft Mute for DAC – HPF Bypass Control for ADC – S/PDIF Output Control – Power Down: ADC/DAC Independently External Power-Down Pin: – ADC/DAC Simultaneously Audio Data Format: 24-Bit I2S Only Sampling Rate: – 16–96 kHz for Both ADC and DAC System Clock: 256 fS Only Dual Power Supplies: – 5 V for Analog and 3.3 V for Digital Package: VQFN-32 DESCRIPTION The PCM3052A is a low-cost, single-chip, 24-bit stereo audio codec (ADC and DAC) with single-ended analog voltage input and output. It also has an analog front end consisting of a 34-dB microphone amplifier, microphone bias generator, 2 stereo multiplexers, and a wide-range PGA. Analogto-digital converters (ADCs) employ delta-sigma modulation with 64-times oversampling. On the other hand, digital-to-analog converters (DACs) employ modulation with 64- and 128-times oversampling. ADCs include a digital decimation filter with a high-pass filter, and DACs include an 8-times oversampling digital interpolation filter. The PCM3052A has many functions which are controlled using the I2C interface: DAC digital de-emphasis, digital attenuation, soft mute etc. The PCM3052A also has an S/PDIF output pin for the DAC digital input. The power-down mode, which works on ADCs and DACs simultaneously, is provided by an external pin. The PCM3052A is suitable for a wide variety of cost-sensitive PC audio (recorder and player) applications where good performance is required. The PCM3052A is fabricated using a highly advanced CMOS process and is available in a small 32-pin VQFN package. • • Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. System Two, Audio Precision are trademarks of Audio Precision, Inc. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated PCM3052A www.ti.com SLES160 – NOVEMBER 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) PCM3052A Supply voltage Supply voltage differences Ground voltage differences Digital input voltage Analog input voltage VCC1, VCC2, VCC3 VDD VCC1, VCC2, VCC3 AGND1, AGND2, AGND3, DGND PDWN, DIN, SCKI, SDA, SCL, ADR, I2CEN DOUT, LRCK, BCK, DOUTS VINL, VINR, VREF1, VREF2, REFO, ATEST, L/M, VOUTR, VOUTL, VCOM, MINP, MINM, MBIAS –0.3 V to 6.5 V –0.3 V to 4 V ±0.1 V ±0.1 V –0.3 V to 6.5 V – 0.3 V to (VDD + 0.3 V) < 4 V –0.3 V to (VCC + 0.3 V) < 6.5 V ±10 mA –40°C to 125°C –55°C to 150°C 150°C 260°C, 5 s 260°C Input current (any pins except supplies) Ambient temperature under bias Storage temperature Junction temperature Lead temperature (soldering) Package temperature (reflow, peak) (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN VDD VCC Digital supply voltage Analog supply voltage Digital input logic family System clock Sampling clock Line input, full scale, PGA = 0 dB Microphone input, full scale, PGA = 0 dB 5 50 3.75 250 –40 85 4 16 3 30 20 3 4.5 NOM 3.3 5 TTL compatible 25 96 MHz kHz Vp-p mVp-p pF kΩ pF kΩ Ω °C MAX 3.6 5.5 UNIT V V Digital input clock frequency Analog input voltage Digital output load capacitance Line output load resistance Line output load capacitance Microphone bias output load resistance Reference output load resistance TA Operating free-air temperature 2 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 ELECTRICAL CHARACTERISTICS All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted PARAMETER DIGITAL INPUT/OUTPUT – DATA FORMAT Audio data interface format Audio data bit length Audio data format fS Sampling frequency, ADC Sampling frequency, DAC System clock frequency INPUT LOGIC VIH (1) VIL (1) TEST CONDITIONS MIN TYP I2S 24 MAX UNIT Bits 96 96 25 VDD 0.8 5.5 0.8 ±10 ±10 kHz kHz MHz MSB-first, 2s complement 16 16 256 fS 4 2 2 VIN = VDD VIN = 0 V VIN = VDD VIN = 0 V IOUT = –4 mA 2.8 0.5 4.5 0.5 1 40 5 6 20 59 –77 0.75 VCC1 – 0.15 0.75 VCC1 + 0.15 1 48 100 Hz–20 kHz, with 10-µF decoupling 0.5 VCC1 – 0.15 1.8 15 65 48 48 Input logic level Input logic level Input logic current Input logic current VDC VDC µA µA VIH (2) (3) VIL(2) (3) IIH(2) IIL (2) IIH(1)(3) IIL(1) (3) VOH (4) VOL (4) (5) VOH (6) VOL (6) 100 ±10 OUTPUT LOGIC IOUT = 4 mA IOUT = –0.3 mA IOUT = 0.3 mA Input level Gain Input resistance Frequency response SNR THD+N MICROPHONE BIAS GENERATOR Output voltage Output source current Output impedance Output noise voltage REFERENCE OUTPUT Output voltage Output source/sink current Output impedance Output noise voltage 100 Hz–20 kHz, with 10-µF decoupling 6 1.8 IOUT = ±10 mA 0.5 VCC1 0.5 VCC1 + 0.15 10 V mA Ω µVrms IOUT = –1 mA 0.75 VCC1 V mA Ω µVrms Single-ended Single-ended Single-ended –3 dB 1-kHz, 100-mVrms output 1-kHz, 1-Vrms output VDC VDC Output logic level MICROPHONE AMPLIFIER mVrms dB kΩ kHz dB dB (1) (2) (3) (4) (5) (6) Pins 10, 11: LRCK, BCK (Schmitt-trigger input with 50-kΩ typical internal pulldown resistor) Pins 12, 17, 18, 19, 21: DIN, SCKI, SDA, SCL, I2CEN (Schmitt-trigger input, 5-V tolerant) Pins 9, 20 : PDWN, ADR (Schmitt-trigger input with 50-kΩ typical internal pulldown resistor, 5-V tolerant). Pins 13, 14: DOUT, DOUTS Pin 18: SDA (Open-drain LOW output) Pin 3: L/M 3 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted PARAMETER AFE MULTIPLEXER Input channel Input range for full scale Input Impedance Antialiasing filter frequency response Input center voltage (VREF1) AFE PGA Gain range Gain step Monotonicity ADC CHARACTERISTICS Resolution Full-scale input voltage DC Accuracy Gain mismatch, channe-to-channel Gain error Bipolar-zero error Dynamic Performance (7) TEST CONDITIONS MIN TYP 2 MAX UNIT CH VINL, VINR VINL, VINR –3 dB, PGA gain = 0 dB 0.1 22 1 143 300 0.5 VCC1 1.5 Vrms kΩ kHz V –4 0 1 Ensured 24 20 dB dB Bits Vp-p ±2 ±4 % of FSR % of FSR % of FSR –88 dB VINL, VINR at PGA gain = 0 dB Full scale input, VINL, VINR Full scale input, VINL, VINR HPF bypass, VINL, VINR fS = 48 kHz, VIN = –0.5 dB 0.6 VCC1 ±1 ±2 ±2 –94 –89 –38 –38 95 95 92 92 101 101 101 101 98 99 98 99 0.454 fS 0.583 fS ±0.05 THD+N Total harmonic distortion + noise fS = 96 kHz, VIN = –0.5 dB fS = 48 kHz, VIN = –60 dB fS = 96 kHz, VIN = –60 dB fS = 48 kHz, A-weighted fS = 96 kHz, A-weighted fS = 48 kHz, A-weighted fS = 96 kHz, A-weighted fS = 48 kHz fS = 96 kHz fS = 48 kHz fS = 96 kHz ±0.05 dB Dynamic range S/N Signal-to-noise ratio Channel separation (between L-ch and R-ch of line-in) Channel separation (between microphone and line-in) Digital Filter Performance Pass band Stop band Pass-band ripple Stop-band attenuation Delay time HPF frequency response DAC CHARACTERISTICS Resolution DC Accuracy Gain mismatch, channel-to-channel Gain error Bipolar zero error dB dB dB dB Hz Hz dB dB s MHz Bits 0.583 fS –3 dB –65 17.4/fS 0.019 fS 24 ±1 ±2 ±1 ±2 ±6 % of FSR % of FSR % of FSR (7) 4 fIN = 1 kHz, using System Two™ audio measurement system by Audio Precision™ in the RMS mode with 20-kHz LPF and 400-Hz HPF in the calculation, at PGA gain = 0 dB, for VINL and VINR. PCM3052A www.ti.com SLES160 – NOVEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted PARAMETER Dynamic Performance (8) TEST CONDITIONS fS = 48 kHz, VOUT = 0 dB MIN TYP –97 –99 –42 –43 MAX –90 UNIT THD+N Total harmonic distortion + noise fS = 96 kHz, VOUT = 0 dB fS = 48 kHz, VOUT = –60 dB fS = 96 kHz, VOUT = –60 dB fS = 48 kHz, EIAJ, A-weighted fS = 96 kHz, EIAJ, A-weighted fS = 48 kHz, EIAJ, A-weighted fS = 96 kHz, EIAJ, A-weighted fS = 48 kHz fS = 96 kHz 97 99 98 dB Dynamic range S/N Signal-to-noise ratio Channel separation Analog Output Output voltage Center voltage Load impedance LPF frequency response Digital Filter Performance Pass band Stop band Pass-band ripple Stop-band attenuation Delay time De-emphasis error POWER SUPPLY REQUIREMENTS VCC1 VCC2 VCC3 VDD 104 106 105 106 103 104 0.8 VCC2 0.5 VCC2 dB dB dB Vp-p V kΩ AC coupling f = 20 kHz f = 40 kHz ±0.03 dB 5 –0.03 –0.20 0.454 fS 0.546 fS ±0.03 dB Hz Hz dB dB s dB 0.546 fS –50 20/fS ±0.1 Voltage range 4.25 3 fS = 48 kHz fS = 96 kHz 5 3.3 39 41 5.5 3.6 50 VDC ICC (9) Supply current IDD mA µA Full power down fS = 48 kHz fS = 96 kHz (10) 300 10 19 90 228 268 180 63 1.8 300 15 mA µA Full power down (10) Operation, fS = 48 kHz Operation, fS = 96 kHz Power dissipation ADC operation at fS = 48 kHz/DAC power down ADC power down/DAC operation at fS = 48 kHz Full power down (10) mW (8) fOUT = 1 kHz, using System Two audio measurement system by Audio Precision in the RMS mode with 20-kHz LPF and 400-Hz HPF. (9) ICC = ICC1 + ICC2 + ICC3 (10) Halt SCKI, BCK, LRCK. 5 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted PARAMETER TEMPERATURE RANGE Operation temperature θJA Thermal resistance –40 100 85 °C °C/W TEST CONDITIONS MIN TYP MAX UNIT DEVICE INFORMATION BLOCK DIAGRAM VINL Single-Ended MUX and PGA Delta-Sigma Modulator BCLK Decimation Filter with HPF Audio Data Interface LRCK DOUT DOUTS VREF1 VREF2 REFO Reference and Buffer VINR Single-Ended MUX and PGA DIN Delta-Sigma Modulator PDWN L/M ATEST MBIAS MINM MINP Mic Bias Mic Amp Clock and Timing Generator, Power Control SCKI VOUTL Analog LPF and Buffer Amp Multilevel Delta-Sigma Modulator ×8 Oversampling Interpolation Filter Mode Control Interface I2CEN ADR SCL SDA VCOM Analog LPF and Buffer Amp Multilevel Delta-Sigma Modulator VOUTR Power Supply AGND3 VCC3 AGND2 VCC2 AGND1 VCC1 DGND VDD B0085-01 6 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 DEVICE INFORMATION (continued) PIN ASSIGNMENTS RTF PACKAGE (TOP VIEW) VOUTR AGND2 VCC2 I2CEN VOUTL 25 24 23 22 21 20 19 18 VCOM MBIAS MINM MINP AGND3 VCC3 REFO 17 SCKI ADR SDA SCL 26 27 28 29 30 31 32 16 15 14 13 12 11 10 VDD DGND DOUTS DOUT DIN BCK LRCK 1 2 3 4 5 6 7 8 AGND1 ATEST PDWN L/M VREF1 VREF2 VINR VINL VCC1 9 P0036-01 TERMINAL FUNCTIONS TERMINAL NAME ADR AGND1 AGND2 AGND3 ATEST DGND BCK DIN DOUT DOUTS I2CEN L/M LRCK MBIAS MINM MINP PDWN REFO (1) (2) (3) NO. 20 8 22 30 1 15 11 12 13 14 21 3 10 27 28 29 9 32 I I O O I O I O I I I O O I/O I DESCRIPTION Mode control address select input ADC analog ground DAC analog ground Microphone amplifier and bias analog ground Analog test, must be open Digital ground Audio data bit clock input Audio data digital input (3) (2) (1) Audio data digital output S/PDIF data digital output Mode control enable/disable input, active HIGH ADC line/microphone select indicator Audio data latch enable input (2) (3) Microphone bias output/decoupling, 0.75 VCC1 Microphone amplifier input to ADC, inverting Microphone amplifier input to ADC, non-inverting ADC and DAC power down control input, active LOW (1) Reference output / decoupling, 0.5 VCC1 Schimtt-trigger input with 50-kΩ typical internal pulldown resistor, 5-V tolerant Schimtt-trigger input with 50-kΩ typical internal pulldown resistor Schimtt-trigger input, 5-V tolerant 7 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 DEVICE INFORMATION (continued) TERMINAL FUNCTIONS (continued) TERMINAL NAME SCKI SCL SDA VCC1 VCC2 VCC3 VCOM VDD VINL VINR VOUTL VOUTR VREF1 VREF2 (4) NO. 17 19 18 7 23 31 26 16 2 6 25 24 4 5 I I O O I/O I I I/O DESCRIPTION System clock input, 256 fS (3) Mode control clock input (3) (4) Mode control data input/output ADC analog power supply, 5 V DAC analog power supply, 5 V Microphone amplifier and bias analog power supply, 5 V DAC common voltage decoupling, 0.5 VCC2 Digital power supply, 3.3 V Line input to ADC, L-channel Line input to ADC, R-channel Analog output from DAC, L-channel Analog output from DAC, R-channel ADC reference 1 voltage output, 0.5 VCC1 ADC reference 2 voltage decoupling, VCC1 Schimtt-trigger input/open-drain LOW output, 5-V tolerant TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (ADC SECTION) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256fS, 24-bit data, unless otherwise noted. DIGITAL FILTER OVERALL CHARACTERISTICS 0 0 STOP-BAND ATTENUATION CHARACTERISTICS −20 −50 Amplitude − dB Amplitude − dB 0 8 16 24 32 G001 −40 −100 −60 −150 −80 −200 Normalized Frequency [×fS] −100 0.0 0.2 0.4 0.6 0.8 1.0 G002 Normalized Frequency [×fS] Figure 1. Figure 2. 8 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (ADC SECTION) (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256fS, 24-bit data, unless otherwise noted. PASS-BAND RIPPLE CHARACTERISTICS 0.2 0 −1 0.0 −2 −3 Amplitude − dB −4 −5 −6 −7 −8 −9 −1.0 0.0 −10 0.45 −4.13 dB at 0.5 fS TRANSITION BAND CHARACTERISTICS Amplitude − dB −0.2 −0.4 −0.6 −0.8 0.1 0.2 0.3 0.4 0.5 G003 0.47 0.49 0.51 0.53 0.55 G004 Normalized Frequency [×fS] Normalized Frequency [×fS] Figure 3. HIGH-PASS FILTER STOP-BAND CHARACTERISTICS 0 −10 −20 −30 Amplitude − dB −40 −50 −60 −70 −80 −90 −100 0.0 −1.0 0.1 0.2 0.3 0.4 0.5 G005 Figure 4. HIGH-PASS FILTER PASS-BAND CHARACTERISTICS 0.2 0.0 Amplitude − dB −0.2 −0.4 −0.6 −0.8 0 1 2 3 4 G006 Normalized Frequency [×fS/1000] Normalized Frequency [×fS/1000] Figure 5. Figure 6. 9 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (ADC SECTION) (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256fS, 24-bit data, unless otherwise noted. ANALOG FILTER (Line Input, PGA Gain = 0 dB) ANTIALIASING FILTER STOP-BAND CHARACTERISTICS 0 ANTIALIASING FILTER PASS-BAND CHARACTERISTICS 0.0 −10 f−3dB = 300 kHz Amplitude − dB −20 Amplitude − dB 1 10 100 f − Frequency − kHz G007 −0.2 −0.4 −30 −0.6 −40 −0.8 −50 1k 10k −1.0 0.1 1 10 f − Frequency − kHz 100 1k G008 Figure 7. Figure 8. 10 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (DAC SECTION) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256fS, 24-bit data, unless otherwise noted. DIGITAL FILTER FREQUENCY RESPONSE, STOP BAND (Sharp Rolloff) 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 0 1 2 Frequency [×fS] 3 4 G009 FREQUENCY RESPONSE, PASS BAND (Sharp Rolloff) 0.2 0.0 Amplitude − dB −0.2 −0.4 −0.6 −0.8 −1.0 0.0 0.1 0.2 0.3 0.4 0.5 G010 Frequency [×fS] Figure 9. DE-EMPHASIS (fS = 32 kHz) 0 −1 −2 −3 Level − dB Error − dB −4 −5 −6 −7 −8 −9 −10 0 2 4 6 8 10 12 14 G011 Figure 10. DE-EMPHASIS ERROR (fS = 32 kHz) 0.5 0.4 0.3 0.2 0.1 0.0 −0.1 −0.2 −0.3 −0.4 −0.5 0 2 4 6 8 10 12 14 G012 f − Frequency − kHz f − Frequency − kHz Figure 11. Figure 12. 11 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (DAC SECTION) (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256fS, 24-bit data, unless otherwise noted. DE-EMPHASIS (fS = 44.1 kHz) 0 −1 −2 −3 Level − dB Error − dB −4 −5 −6 −7 −8 −9 −10 0 2 4 6 8 10 12 14 16 18 20 G013 DE-EMPHASIS ERROR (fS = 44.1 kHz) 0.5 0.4 0.3 0.2 0.1 0.0 −0.1 −0.2 −0.3 −0.4 −0.5 0 2 4 6 8 10 12 14 16 18 20 G014 f − Frequency − kHz f − Frequency − kHz Figure 13. DE-EMPHASIS (fS = 48 kHz) 0 −1 −2 −3 Level − dB Error − dB −4 −5 −6 −7 −8 −9 −10 0 2 4 6 8 10 12 14 16 18 20 22 G015 Figure 14. DE-EMPHASIS ERROR (fS = 48 kHz) 0.5 0.4 0.3 0.2 0.1 0.0 −0.1 −0.2 −0.3 −0.4 −0.5 0 2 4 6 8 10 12 14 16 18 20 22 G016 f − Frequency − kHz f − Frequency − kHz Figure 15. Figure 16. 12 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (DAC SECTION) (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256fS, 24-bit data, unless otherwise noted. ANALOG FILTER STOP-BAND CHARACTERISTICS (1 kHz–10 MHz) 0 0.0 PASS-BAND CHARACTERISTICS (100 Hz–1 MHz) −10 f−3dB = 300 kHz Amplitude − dB −20 Amplitude − dB 1 10 100 f − Frequency − kHz G017 −0.2 −0.4 −30 −0.6 −40 −0.8 −50 1k 10k −1.0 0.1 1 10 f − Frequency − kHz 100 1k G018 Figure 17. Figure 18. 13 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES (ADC SECTION) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted. LINE INPUT (at PGA Gain = 0 dB) THD+N vs TEMPERATURE THD+N − Total Harmonic Distortion + Noise at −0.5 dB − dB −85 110 DYNAMIC RANGE AND SNR vs TEMPERATURE Dynamic Range and SNR − dB −90 105 Dynamic Range 100 SNR −95 −100 −40 −15 10 35 60 85 G019 95 −40 −15 10 35 60 85 G020 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 19. THD+N vs SUPPLY VOLTAGE THD+N − Total Harmonic Distortion + Noise at −0.5 dB − dB −85 110 Figure 20. DYNAMIC RANGE AND SNR vs SUPPLY VOLTAGE Dynamic Range and SNR − dB −90 105 Dynamic Range 100 SNR −95 −100 4.25 4.50 4.75 5.00 5.25 5.50 G021 95 4.25 4.50 4.75 5.00 5.25 5.50 G022 VCC − Supply Voltage − V VCC − Supply Voltage − V Figure 21. Figure 22. 14 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES (ADC SECTION) (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted. THD+N vs SAMPLING FREQUENCY THD+N − Total Harmonic Distortion + Noise at −0.5 dB − dB −85 110 DYNAMIC RANGE AND SNR vs SAMPLING FREQUENCY Dynamic Range and SNR − dB −90 105 Dynamic Range 100 SNR −95 −100 32 95 48 64 80 96 G023 32 48 64 80 96 G024 fS − Sampling Frequency − kHz fS − Sampling Frequency − kHz Figure 23. Figure 24. 15 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES (DAC SECTION) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted. THD+N vs TEMPERATURE THD+N − Total Harmonic Distortion + Noise at 0 dB − dB −90 110 DYNAMIC RANGE AND SNR vs TEMPERATURE −95 Dynamic Range and SNR − dB SNR 105 Dynamic Range −100 100 −105 −40 −15 10 35 60 85 G025 95 −40 −15 10 35 60 85 G026 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 25. THD+N vs SUPPLY VOLTAGE THD+N − Total Harmonic Distortion + Noise at 0 dB − dB −90 110 Figure 26. DYNAMIC RANGE AND SNR vs TEMPERATURE −95 Dynamic Range and SNR − dB 105 SNR Dynamic Range −100 100 −105 4.25 4.50 4.75 5.00 5.25 5.50 G027 95 4.25 4.50 4.75 5.00 5.25 5.50 G028 VCC − Supply Voltage − V VCC − Supply Voltage − V Figure 27. Figure 28. 16 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES (DAC SECTION) (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted. THD+N vs SAMPLING FREQUENCY THD+N − Total Harmonic Distortion + Noise at 0 dB − dB −90 110 DYNAMIC RANGE AND SNR vs SAMPLING FREQUENCY Dynamic Range and SNR − dB SNR 105 Dynamic Range −95 −100 100 −105 32 95 48 64 80 96 G029 32 48 64 80 96 G030 fS − Sampling Frequency − kHz fS − Sampling Frequency − kHz Figure 29. Figure 30. 17 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted. ADC OUTPUT SPECTRUM (Line Input, at PGA Gain = 0 dB) OUTPUT SPECTRUM (–0.5 dB, N = 8192) 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 0 5 10 f − Frequency − kHz G031 OUTPUT SPECTRUM (–60 dB, N = 8192) 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 15 20 0 5 10 f − Frequency − kHz 15 20 G032 Figure 31. Figure 32. DAC OUTPUT SPECTRUM OUTPUT SPECTRUM (0 dB, N = 8192) 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 0 5 10 f − Frequency − kHz G033 OUTPUT SPECTRUM (–60 dB, N = 8192) 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 15 20 0 5 10 f − Frequency − kHz 15 20 G034 Figure 33. Figure 34. 18 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted. SUPPLY CURRENT SUPPLY CURRENT vs TEMPERATURE 45 40 35 Supply Current − mA 30 25 20 15 10 5 0 −40 IDD ICC1 + ICC2 + ICC3 Supply Current − mA 45 40 35 30 25 20 15 10 5 0 −15 10 35 60 85 G035 SUPPLY CURRENT vs SAMPLING FREQUENCY, ADC AND DAC OPERATING ICC1 + ICC2 + ICC3 IDD 32 48 64 80 96 G036 TA − Free-Air Temperature − °C fS − Sampling Frequency − kHz Figure 35. SUPPLY CURRENT vs SUPPLY VOLTAGE 45 40 35 Supply Current − mA 30 25 20 15 10 5 0 3.0 IDD Supply Current − mA 45 40 35 30 25 20 15 10 5 0 4.25 Figure 36. SUPPLY CURRENT vs SUPPLY VOLTAGE ICC1 + ICC2 + ICC3 3.3 VDD − Supply Voltage − V 3.6 G037 4.50 4.75 5.00 5.25 5.50 G038 VCC − Supply Voltage − V Figure 37. Figure 38. 19 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 THEORY OF OPERATION ADC SECTION The ADC block consists of a reference circuit, two channels of single-ended to differential converter, a fifth-order delta-sigma modulator with fully differential architecture, a decimation filter with high-pass filter, and a serial interface circuit which is also used as the serial interface for the DAC input signal as shown in the block diagram. Figure 39 is the block diagram of the fifth-order delta-sigma modulator and transfer function. An on-chip reference circuit with two external capacitors provides all reference voltages that are needed in the ADC section, and defines the full-scale voltage range of both channels. An on-chip, single-ended to differential signal converter saves the design, space, and extra parts cost of an external signal converter. Full differential architecture provides a wide dynamic range and excellent power supply rejection performance. The input signal is sampled at ×64 oversampling rate and an on-chip antialiasing filter eliminates the need for an external sample-hold amplifier. A fifth-order delta-sigma noise shaper, which consists of five integrators using the switched-capacitor technique and a comparator, shapes the quantization noise generated outside of audio signal band by the comparator and 1-bit DAC. The high-order delta-sigma modulation randomizes the modulator outputs and reduces idle-tone level. The 64 fS, 1-bit stream from the delta-sigma modulator is converted to a 1-fS, 24-bit digital signal by removing high-frequency noise components with the decimation filter. The dc component of the signal is removed by the HPF, and the HPF output is converted to a time-multiplexed serial signal through the serial interface. Analog In X(z) + − 1st SW-CAP Integrator + − 2nd SW-CAP Integrator 3rd SW-CAP Integrator + − 4th SW-CAP Integrator 5th SW-CAP Integrator Qn(z) + + + + + + + + Digital Out Y(z) H(z) Comparator 1-Bit DAC Y(z) = STF(z) * X(z) + NTF(z) * Qn(z) Signal Transfer Function STF(z) = H(z) / [1 + H(z)] Noise Transfer Function NTF(z) = 1 / [1 + H(z)] B0005-02 Figure 39. Block Diagram of Fifth-Order Delta-Sigma Modulator DAC SECTION The DAC section is based on the delta-sigma modulator, which consists of an 8-level amplitude quantizer and a fourth-order noise shaper. This section converts the oversampled input data to 8-level delta-sigma format. A block diagram of the 8-level delta-sigma modulator is shown in Figure 40. This 8-level delta-sigma modulator has the advantage of stability and clock jitter over the typical one-bit (2-level) delta-sigma modulator. The combined oversampling rate of the delta-sigma modulator and the internal 8× interpolation filter is 64 fS for all system clocks. The theoretical quantization-noise performance of the 8-level delta-sigma modulator is shown in Figure 41. 20 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 THEORY OF OPERATION (continued) − + IN 8 fS + + − Z–1 + + Z–1 + + Z–1 + + Z–1 + 8-Level Quantizer OUT 64 fS ++ + B0008-03 Figure 40. 8-Level Delta-Sigma Modulator Block Diagram 0 −20 −40 Amplitude − dB −60 −80 −100 −120 −140 −160 −180 0 1 2 3 4 5 6 7 8 G039 125 120 115 110 105 100 95 90 0 100 200 300 400 500 600 G040 fS − Sampling Frequency − kHz Dynamic Range − dB Jitter − psP−P Figure 41. Quantization Noise Spectrum Figure 42. Clock Jitter 21 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 THEORY OF OPERATION (continued) SYSTEM CLOCK The system clock for the PCM3052A must be 256 fS, where fS is the audio sampling rate, 16 kHz to 96 kHz. Table 1 lists typical system clock frequencies, and Figure 43 illustrates the system clock timing. Table 1. Typical System Clock SAMPLING RATE FREQUENCY (fS) – LRCK 16 kHz 32 kHz 44.1 kHz 48 kHz 96 kHz tw(SCKH) 2V System Clock 0.8 V tw(SCKL) 1/256 fS T0005−10 SYSTEM CLOCK FREQUENCY – MHz 256 fS 4.096 8.192 11.2896 12.288 24.576 PARAMETER tw(SCKH) tw(SCKL) System clock pulse duration, HIGH System clock pulse duration, LOW MIN 16 16 MAX UNIT ns ns Figure 43. System Clock Timing POWER SUPPLY ON, EXTERNAL RESET, AND POWER DOWN The PCM3052A has both an internal power-on-reset circuit and an external reset circuit. The sequences for both resets are shown as follows. Figure 44 is the timing chart of the internal power-on reset. Two power-on-reset circuits are implemented, one each for for VCC1 and VDD. Initialization (reset) is performed automatically at the time when VCC1 and VDD exceed 3.9 V (typical) and 2.2 V (typical), respectively. Internal reset is released after 1024 SCKI from power-on-reset release, and the PCM3052A begins normal operation. VOUTL and VOUTR from the DAC are forced to the VCOM (= 0.5 VCC2) level as VCC2 rises. When synchronization between SCKI, BCK, and LRCK is maintained, VOUTL and VOUTR go into the fade-in sequence. Then VOUTL and VOUTR provide outputs corresponding to DIN after t(DACDLY1) = 2100/fS from power-on-reset release. On the other hand, DOUT from the ADC provides an output corresponding to VINL and VINR after t(ADCDLY1) = 4500/fS from power-on-reset release. If synchronization is not maintained, the internal reset is not released, and operation is kept in the power-down mode. After resynchronization, the DAC goes into the fade-in sequence, and the ADC goes into normal operation after internal initialization. DOUTS can provide S/PDIF data after the power-on-reset release if the SPDIF bit is HIGH (see serial control port for mode control section). Figure 45 shows timing chart for external reset. The PDWN pin (pin 9) initiates external forced reset when PDWN = LOW, and it provides the power-down mode, which is the lowest power-dissipation state in the PCM3052A. When PDWN transitions from HIGH to LOW while SCKI, BCK, and LRCK are synchronized, VOUTL and VOUTR are faded out and forced into VCOM (= 0.5 VCC2) level after tDACDLY1 = 2100/fS. At the same time as the internal reset becomes LOW, DOUT becomes ZERO, the PCM3052A enters the power-down mode. To return to normal operation, set PDWN to HIGH. Then the power-on reset sequence, Figure 44, is performed. 22 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 DOUTS is driven LOW immediately after PDWN is asserted and recovers about 40/fS following PDWN release. Notes: 1. Large pop noises can be generated on VOUTL and VOUTR if the power supply is turned off during normal operation. 2. To switch PDWN during fade-in or fade-out causes an immediate change between fade-in and fade-out. 3. Changing mode controls during normal operation can degrade analog performance. It is recommended that mode controls be changed through the serial control port, and that changing or stopping the clock, switching the power supply off, etc., be done in the power-down mode. VCC1, VDD (VCC1 = 5 V, VDD = 3.3 V Typ) 0V (VCC1 = 3.9 V, VDD = 2.2 V Typ) LRCK, BCK, SCKI Synchronous Clocks PDWN 1024 SCKI Internal Reset Power Down Normal Operation t(DACDLY1), 2100 /fS About 40/fS VOUTL, VOUTR VCOM (0.5 VCC2) t(ADCDLY1), 4500 /fS DOUT ZERO DOUTS Disable Enable if S/PDIF Bit = HIGH T0097-01 Figure 44. DAC Output and ADC Output for Power-On Reset 23 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 VCC1, VCC2, VCC3, VDD (VCC1 − VCC3 = 5 V, VDD = 3.3 V Typ) 0V LRCK, BCK, SCKI Synchronous Clocks Synchronous Clocks PDWN 1024 SCKI Internal Reset Normal Operation Power Down Normal Operation t(DACDLY1), 2100 /fS t(DACDLY1), 2100 /fS VOUTL, VOUTR VCOM (0.5 VCC2) 0.5 VCC2 t(ADCDLY1), 4500 /fS DOUT ZERO About 40/fS DOUTS LOW T0098-01 Figure 45. DAC Output and ADC Output for External Reset (PDWN Pin) 24 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 PCM AUDIO INTERFACE Digital audio data is interfaced to the PCM3052A on LRCK (pin 10), BCK (pin 11), DIN (pin 12), DOUT (pin 13), and DOUTS (pin 14). The PCM3052A can accept 24-bit I2S format only. In case of AC-3 type output data for DOUTS, bits 17 to 24 of DIN must be held LOW. See the Digital Audio Interface Transmitter (DIT) section of this data sheet. Table 2. Audio Data Format DATA FORMAT 24-bit, MSB-first, I2S The PCM3052A accepts only 64 clocks of BCK during one clock of LRCK. Figure 46 and Figure 47 illustrate audio data input/output format and timing. LRCK Left-Channel Right-Channel BCK DIN 1 2 3 22 23 24 LSB 1 2 3 22 23 24 LSB MSB DOUT 1 2 3 MSB 1 2 3 22 23 24 LSB 22 23 24 LSB Sub-Frame T0016-15 MSB DOUTS Sub-Frame MSB Sub-Frame Figure 46. Audio Data Input/Output Format 25 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 t(LRP) LRCK t(BCL) t(BCH) t(BL) 1.4 V t(BCY) t(DIS) t(DIH) t(LB) 1.4 V BCK DIN t(BDO) t(LDO) 1.4 V DOUT 0.5 VDD T0021−03 PARAMETER tBCY tBCH tBCL tBL tLB tLRP tDIS tDIH tBDO tLDO tR tF BCK pulse cycle time BCK pulse duration, HIGH BCK pulse duration, LOW BCK rising edge to LRCK edge LRCK edge to BCK rising edge LRCK pulse duration DIN setup time to BCK rising edge DIN hold time to BCK rising edge DOUT delay time from BCK falling edge DOUT delay time from LRCK edge Rising time of all signals Falling time of all signals MIN 160 70 70 20 20 4.2 20 20 MAX UNIT ns ns ns ns ns µs ns ns 20 20 10 10 ns ns ns ns NOTE: Load capacitance at DOUT is 20 pF. Rising and falling time is measured from 10% to 90% of IN/OUT signal swing. Figure 47. Audio Data Input/Output Timing 26 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM The PCM3052A operates with LRCK and BCK synchronized to the system clock in slave mode. The PCM3052A does not need specific phase relationship among LRCK, BCK, and the system clock, but does require the synchronization of LRCK, BCK, and the system clock. If the relationship between system clock and LRCK changes more than ±6 BCKs during one sample period due to LRCK jitter, etc., internal operation of DAC halts within 6/fS, and the analog output is forced to 0.5 VCC2 until re-synchronization of the system clock to LRCK and BCK has completed and then the time of t(DACDLY2) has elapsed. DOUTS is also held LOW during the same period. Internal operation of the ADC also halts within 6/fS, and digital output is forced into ZERO code until re-synchronization of the system clock to LRCK and BCK has completed and then the time of t(ADCDLY2) has elapsed. In case of changes less than ±5 BCKs, re-synchronization does not occur and the previously described analog/digital output control and discontinuity does not occur. Figure 48 illustrates the DAC analog output, ADC digital output, and DOUTS output for loss of synchronization. During undefined data, the PCM3052A can generate some noise in audio signal. Also, the transition of normal to undefined data and undefined or zero data to normal creates a discontinuity of data on analog and digital outputs, which could generate some noise in audio signal. Synchronization Lost Resynchronization State of Synchronization Synchronous Asynchronous t(DACDLY2) (32/fS) Undefined Data Synchronous Within 6/fS VCOM (0.5 VCC2) t(ADCDLY2) (32/fS) Normal Data DAC VOUT Normal Data ADC DOUT Normal Data Undefined Data Zero Data Normal Data DOUTS Normal Data Undefined Data Low Normal Data T0020-07 Figure 48. DAC Output and ADC Output for Loss of Synchronization MICROPHONE AMPLIFIER AND MICROPHONE BIAS GENERATOR The PCM3052A has a built-in, high-performance differential-input microphone amplifier with 34-dB gain, 5-kΩ (minimum) input resistance, and 59-dB SNR at 100-mVrms output. Bandwidth is 20 kHz for –3-dB attenuation. The PCM3052A also has a low-noise microphone bias generator with 0.75-VCC1 and 1-mA current-source capability for electret microphones. Output impedance is 48 Ω for external noise reduction. The output of the microphone amplifier and the line input are connected as inputs to the multiplexer. The serial control port can be used to control which input the multiplexer selects (see Figure 50). 27 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 REFERENCE OUTPUT The PCM3052A has a reference output pin (RFFO, pin 32) to supply reference voltage (0.5 VCC1) to external components. The pin has 10-mA sink/source capability with 6-Ω output impedance. −1 mA (0.75 VCC1) + MBIAS 48 Ω MINM − Electret Microphone MINP REF (0.5 VCC1) + + 10 mA S0124-01 34 dB + MUX REFO 6Ω Figure 49. Microphone Amplifier, Microphone Bias Generator, and Reference Output LINE AND MICROPHONE INPUT SELECT INDICATOR The PCM3052A employs an indicator pin (L/M, pin 3) to show which analog input is selected, line or microphone. Table 3. Line and Microphone Select Indicator L/M LOW HIGH LINE/MIC SELECT INDICATOR Microphone Line 28 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 MULTIPLEXER AND PGA The PCM3052A has built-in analog front-end circuit which is shown in Figure 50. Multiplexer input and PGA gain are selected by mode control via the serial port, as shown in the Serial Control Port for Mode Control section. The full-scale input voltage range is 0.1 Vrms to 1.5 Vrms, and it can be adjusted to an adequate level for following the ADC sections. VINL and VINR input resistance is maintained above 22 kΩ for all PGA gains. The input resistance value for each gain can be calculated by Equation 1. 286 R IN(kW, typical) + (PGA Gain 20) 1 ) 10 (1) R VINL R L-ch PGA (−4 dB to 20 dB) −1 LIN+ LIN− R VINR R PGA (−4 dB to 20 dB) R-ch −1 RIN+ RIN− 2-ch MUX Mic Amp S0125-01 Figure 50. Multiplexer and PGA ANALOG OUTPUTS FROM DAC The PCM3052A has two independent output channels, VOUTL and VOUTR. These are unbalanced outputs, each capable of driving 4 Vp-p (typical) into a 5-kΩ ac-coupled load. The internal output amplifiers for VOUTL and VOUTR are biased to the dc common-mode (or bipolar zero) voltage, equal to 0.5 VCC2 The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy present at the DAC outputs due to the noise-shaping characteristics of the PCM3052A delta-sigma modulators. The frequency response of this filter is shown in the typical performance curves. By itself, this filter is not adequate to attenuate the out-of-band noise to an acceptable level for many applications. An external low-pass filter is required to provide sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the PCM1742 data sheet (SBAS176). VCOM OUTPUT FOR DAC One unbuffered common-mode voltage output pin, VCOM (pin 26), is brought out for decoupling purposes. This pin is nominally biased to a dc voltage level equal to 0.5 VCC2. This pin can be used to bias external circuits. Output resistance of this pin is 21 kΩ (typical). DIGITAL AUDIO INTERFACE TRANSMITTER (DIT) The PCM3052A employs S/PDIF output from DOUTS (pin 14). The data (I2S format only) from DAC digital data input (DIN, pin 12) is encoded to S/PDIF format with preambles according to IEC958. S/PDIF output is controlled through the serial control port. The output data type (linear PCM or AC-3) can be also selected through the serial control port. For the output data type of AC-3, the word length is limited to 16 bits in the PCM3052A. Therefore, bits 17 to 24 in the I2S format data must be set to LOW. 29 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 Each bit after the audio sample word is assigned in the PCM3052A as follows. Validity bit: User data: Channel status [0]: Channel status [1]: Channel status [2]: Channel status [3:5]: Channel status [6:7]: Channel status [8:15]: Channel status [16:19]: Channel status [20:23]: Channel status [24:27]: Channel status [28:29]: Channel status [30:31]: Channel status [32:35]: Channel status [36:191]: Parity bit: Writable through serial control port Fixed to 0 Fixed to 0 (consumer use) Writable through serial control port (audio sample word type) Writable through serial control port (copyright flag) Writable through serial control port (additional format information) Fixed to 00 (mode 0) Writable through serial control port (category code) Fixed to 0000 (source number) Fixed to 0000 (channel number) Writable through serial control port (sampling frequency) Writable through serial control port (clock accuracy) Fixed to 00 Writable through serial control port (word length) Fixed to all 0s Even parity for preceding data from preamble to channel status bit S/PDIF output timing is shown in Figure 51. The S/PDIF block starts with a preamble after 32/fS from the frame where S/PDIF output control bit becomes HIGH. The behavior of DOUTS for power-on reset, external reset, and loss of synchronization is shown in Figure 44, Figure 45, and Figure 48, respectively. Frame Frame Frame Frame DIN (I2S Format) L-ch R-ch L-ch R-ch L-ch R-ch S/PDIF Output Control Bit Disable Enable 32/fS DOUTS PA SW Frame LOW V U C Pa P A SW V U C Pa P A P: Preamble A: Aux SW: Audio Sample Word V: Validity Bit U: User Bits C: Channel Status Pa: Parity Bit T0099-01 Figure 51. S/PDIF Output Timing 30 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 SERIAL CONTROL PORT FOR MODE CONTROL The several built-in functions of the PCM3052A can be controlled through the I2C format serial-control port, SDA (pin 18) and SCL (pin 19). The PCM3052A supports the I2C serial bus and the data transmission protocol for standard mode as a slave device. This protocol is explained in I2C specification 2.0. Serial control is available even during the power-down state and without a system clock, except when the MRST bit = 0 or I2CEN (pin 21) = LOW. Slave Address MSB 1 0 0 0 1 1 ADR LSB R/W The PCM3052A has seven bits for its own slave address. The first six bits (MSBs) of the slave address are factory preset to 100011. The next bit of the address byte is the device select bit which can be user-defined by ADR (pin 20). A maximum of two PCM3052As can be connected on the same bus at one time. Each PCM3052A responds when it receives its own slave address. Packet Protocol A master device must control packet protocol, which consists of start condition, slave address with read/write bit, data if write or acknowledgement if read, and stop condition. The PCM3052A supports slave receiver function. SDA SCL St 1−7 Slave Address 8 R/W 9 ACK 1−8 DATA 9 ACK 1−8 DATA 9 ACK 9 ACK Sp Start Condition Write Operation Transmitter Data Type R/W: Read Operation if 1; Otherwise, Write Operation ACK: Acknowledgement of a Byte if 0 DATA: 8 Bits (Byte) NACK: Not Acknowledgement of a bite if 1 M Slave Address M W S ACK M DATA S ACK M DATA S ACK S ACK Stop Condition M St M Sp M: Master Device S: Slave Device St: Start Condition W: Write Sp: Stop Condition T0049-04 Figure 52. Basic I2C Framework 31 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 Write Operation The PCM3052A supports receiver function. A master can write to any PCM3052A registers using single or multiple accesses. The master sends a PCM3052A slave address with a write bit, a register address, and the data. If multiple access is required, the address is that of the starting register, followed by the data to be transferred. When the data are received properly, the index register is incremented by 1 automatically. When the index register reaches 50h, the next value is 41h. When undefined registers are accessed, the PCM3052A does not send an acknowledgement. Figure 53 is a diagram of the write operation. The register address and the write data are 8 bits and MSB-first format. Transmitter Data Type M St M Slave Address M W S ACK M Reg Address S ACK M Write Data 1 S ACK M Write Data 2 S ACK S ACK M Sp M: Master Device S: Slave Device St: Start Condition ACK: Acknowledge W: Write Sp: Stop Condition R0002-03 Figure 53. Framework for Write Operation Serial Control Enable/Disable The PCM3052A supports I2C serial control enable/disable function by I2CEN (pin 21) to avoid an unstable start condition. When the I2CEN pin transitions from LOW to HIGH, both SDA (pin 18) and SCL (pin 19) must be HIGH stable and the ADR (pin 20) must be also stable. While I2CEN = LOW, the write operation is disabled. A timing chart of I2CEN is shown in Figure 54. I2CEN Disable Enable 0 µs (min) 1 µs (min) SDA/SCL Don’t Care HIGH Fixed ADR Don’t Care HIGH or LOW T0100-01 Figure 54. I2CEN Timing Chart 32 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TIMING DIAGRAM Start t(D-HD) t(BUF) t(D-SU) t(SDA-R) Repeated Start t(SDA-F) t(P-SU) Stop SDA t(SCL-R) t(LOW) SCL t(RS-HD) t(S-HD) t(SCL-F) t(HI) t(RS-SU) T0050-01 PARAMETER f(SCL) t(BUF) t(LOW) t(HI) tRS-SU t(S-HD) t(RS-HD) t(D-SU) t(D-HD) t(SCL-R) t(SCL-R1) t(SCL-F) t(SDA-R) t(SDA-F) t(P-SU) CB VNH SCL clock frequency Bus free time between STOP and START condition Low period of the SCL clock High period of the SCL clock Setup time for START/repeated START condition Hold time for START/repeated START condition Data setup time Data hold time Rise time of SCL signal Rise time of SCL signal after a repeated START condition and after an acknowledge bit Fall time of SCL signal Rise time of SDA signal Fall time of SDA signal Setup time for STOP condition Capacitive load for SDA and SCL line Noise margin at high level for each connected device (including hysteresis) CONDITIONS Standard mode Standard mode Standard mode Standard mode Standard mode Standard mode Standard mode Standard mode Standard mode Standard mode Standard mode Standard mode Standard mode Standard mode Standard mode MIN 4.7 4.7 4 4.7 4 250 0 20 + 0.1 CB 20 + 0.1 CB 20 + 0.1 CB 20 + 0.1 CB 20 + 0.1 CB 4 MAX 100 UNIT kHz µs µs µs µs µs ns 900 1000 1000 1000 1000 1000 400 ns ns ns ns ns ns µs pF V 0.2 VDD Figure 55. Control Interface Timing MODE CONTROL REGISTERS User-Programmable Mode Controls The PCM3052A has several user programmable functions which are accessed via control registers. The registers are programmed using the I2C serial control port, which was previously discussed in this data sheet. Table 4 lists the available mode control functions, along with their reset default conditions and associated register addresses. The register map is shown in Table 5. 33 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 Table 4. User-Programmable Mode Controls FUNCTION Digital attenuation control, 0 dB to –63 dB in 0.5-dB steps (DAC) Mode control register reset (ADC and DAC) System reset (ADC and DAC) ADC power-save control (ADC) DAC Power Save Control (DAC) Soft-mute control (DAC) Oversampling rate control (DAC) De-emphasis function control (DAC) De-emphasis sampling rate selection (DAC) Digital filter rolloff control (DAC) Output phase select (DAC) Multiplexer input channel control (ADC) PGA gain control (ADC) HPF bypass control (ADC) DAC output control (DAC) Additional format information (DIT) Copyright flag (DIT) Audio sample word type (DIT) DIT output control (DIT) Category code (DIT) Clock accuracy (DIT) Sampling frequency (DIT) Validity bit for L-channel (DIT) Validity bit for R-channel (DIT) S/PDIF output control (DIT) Word Length (DIT) RESET DEFAULT 0 dB, no attenuation Normal operation Normal operation Normal operation Normal operation Mute disabled 64-fS oversampling De-emphasis disabled 48 kHz Sharp rolloff Normal LINE IN –4 dB HPF enabled Disabled Two audio channels without pre-emphasis Asserted PCM Disable General Level II 44.1kHz Valid Valid Disabled 24 bits REGISTER 65 and 66 67 67 67 67 68 68 69 69 70 71 72 72 75 77 77 77 77 77 78 79 79 80 80 80 80 BIT(S) AT1[7:0], AT2[7:0] MRST SRST ADPSV DAPSV MUT[2:1] OVR1 DM12 DMF[1:0] FLT0 DREV AML PG[4:0] BYP DACMSK AFI[5:3] COPY AUDIO DITMSK CAT[15:8] CLK[29:28] SF[27:24] VALIDL VALIDR SPDIF WL[35:32] Table 5. Register Map REGISTER ADDRESS IDX (B8–B14) 41h 42h 43h 44h 45h 46h 47h 48h 4Bh 4Dh 4Eh 4Fh 50h REGISTER 65 66 67 68 69 70 71 72 75 77 78 79 80 B15 0 0 0 0 0 0 0 0 0 0 0 0 0 B14 1 1 1 1 1 1 1 1 1 1 1 1 1 B13 0 0 0 0 0 0 0 0 0 0 0 0 0 B12 0 0 0 0 0 0 0 0 0 0 0 0 1 B11 0 0 0 0 0 0 0 1 1 1 1 1 0 B10 0 0 0 1 1 1 1 0 0 1 1 1 0 B9 0 1 1 0 0 1 1 0 1 0 1 1 0 B8 1 0 1 0 1 0 1 0 1 1 0 1 0 B7 AT17 AT27 MRST RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) DACMSK CAT15 RSV (1) VALIDL B6 AT16 AT26 SRST OVR1 DMF1 RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) CAT14 RSV (1) VALIDR B5 AT15 AT25 ADPSV RSV (1) DMF0 FLT0 RSV (1) AML RSV (1) AFI5 CAT13 CLK29 SPDIF B4 AT14 AT24 DAPSV RSV (1) DM12 RSV (1) RSV (1) PG4 RSV (1) AFI4 CAT12 CLK28 RSV (1) DATA B3 AT13 AT23 RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) PG3 BYP AFI3 CAT11 SF27 WL35 B2 AT12 AT22 RSV (1) RSV (1) RSV (1) 1 RSV (1) PG2 1 COPY CAT10 SF26 WL34 B1 AT11 AT21 RSV (1) MUT2 RSV (1) RSV (1) RSV (1) PG1 RSV (1) AUDIO CAT9 SF25 WL33 B0 AT10 AT20 RSV (1) MUT1 RSV (1) RSV (1) DREV PG0 RSV (1) DITMSK CAT8 SF24 WL32 (1) RSV means reserved for test operation or future extension, and these bits should be set 0 during regular operation. Do not write any values in other addresses than those listed in the table. 34 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 REGISTER DEFINITIONS B15 REGISTER 65 REGISTER 66 0 0 B14 1 1 B13 0 0 B12 0 0 B11 0 0 B10 0 0 B9 0 1 B8 1 0 B7 AT17 AT27 B6 AT16 AT26 B5 AT15 AT25 B4 AT14 AT24 B3 AT13 AT23 B2 AT12 AT22 B1 AT11 AT21 B0 AT10 AT20 ATx[7:0]: Digital Attenuation Level Setting (DAC) Where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR (x = 2). Default value: 1111 1111b ATX[7:0] 1111 1111b 1111 1110b 1111 1101b : 1000 0011b 1000 0010b 1000 0001b 1000 0000b : 0000 0000b DECIMAL VALUE 255 254 253 : 131 130 129 128 : 0 ATTENUATION LEVEL SETTING 0 dB, No Attenuation. (default) –0.5 dB –1.0 dB : –62.0 dB –62.5 dB –63.0 dB Mute : Mute Each DAC channel (VOUTL and VOUTR) includes a digital attenuation function. The attenuation level can be set from 0 dB to –63 dB in 0.5-dB steps, and also can be set to infinite attenuation (mute). The attenuation level change from current value to target value is performed by incrementing or decrementing by one small step size for every 1/fS time interval during 2048/fS. The small step size is determined automatically so that it can provide a transition in attenuation level with a characteristic S-shaped curve from the current value to the target value. While the attenuation level change sequence is in progress for 2048/fS, processing of the attenuation level change for any new command is ignored, and the new command is overwritten into command buffer. The last command for an attenuation level change is performed after present attenuation level change sequence is finished. The attenuation data for each channel can be set individually. The attenuation level can be calculated using the following formula: Attenuation level (dB) = 0.5 × (ATx[7:0]DEC – 255) where ATx[7:0]DEC = 0 through 255. For ATx[7:0]DEC = 0 through 128, attenuation is set to infinite attenuation. The preceding table shows attenuation levels for various settings. B15 REGISTER 67 0 B14 1 B13 0 B12 0 B11 0 B10 0 B9 1 B8 1 B7 B6 B5 B4 B3 RSV B2 RSV B1 RSV B0 RSV MRST SRST ADPSV DAPSV MRST: Mode Control Register Reset (ADC and DAC) Default value: 1 MRST = 0 MRST = 1 Set default value Normal operation (default) The MRST bit controls mode control register reset. Pop-noise may be generated. SRST: System Reset (ADC and DAC) Default value: 1 35 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 SRST = 0 SRST = 1 Re-synchronization Normal operation (default) The SRST bit controls system reset. The PCM3052A does not go into power-down state. The mode control register is not reset by this control. Also pop-noise may be generated. ADPSV: ADC Power-Save Control (ADC) Default value: 0 ADPSV = 0 ADPSV = 1 Normal operation (default) Power-save mode The ADPSV bit controls ADC power-save mode. In power-save mode, ADC goes into power-down state, the data in ADC are reset, and DOUT is forced into ZERO immediately. I2C control is enabled. DAPSV: DAC Power-Save Control (DAC) Default value: 0 DAPSV = 0 DAPSV = 1 Normal operation (default) Power-save mode The DAPSV bit controls the DAC power-save mode. In the power-save mode, the DAC output is faded out and DAC goes into the power-down state. I2C control is enabled. A waiting time of more than 2100/fS from power-save-mode assertion is required for the release of the power-save mode. DIT function is available if SPDIF bit = 1, even though DAPSV = 1. B15 REGISTER 68 0 B14 1 B13 0 B12 0 B11 0 B10 1 B9 0 B8 0 B7 RSV B6 OVR1 B5 RSV B4 RSV B3 RSV B2 RSV B1 MUT2 B0 MUT1 OVR1: Oversampling Rate Control (DAC) Default value: 0 OVR1 = 0 OVR1 = 1 64× oversampling (default) 128× oversampling The OVR1 bit is used to control the oversampling rate of the delta-sigma D/A converters. To write over this register during normal operation may generate noise. MUTx: Soft-Mute Control (DAC) where, x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR (x = 2). Default value: 0 MUTx = 0 MUTx = 1 Mute disabled (default) Mute enabled The mute bits, MUT1 and MUT2, are used to enable or disable the soft-mute function for the corresponding DAC outputs, VOUTL and VOUTR. The soft-mute function is incorporated into the digital attenuators. When mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, the digital attenuator for the corresponding output is decreased from the current setting to infinite attenuation, one attenuator step (0.5 dB) for every 8/fS seconds. This provides pop-free muting of the DAC output. By setting MUTx = 0, the attenuator is increased one step for every 8/fS seconds to the previously programmed attenuation level. 36 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 B15 REGISTER 69 0 B14 1 B13 0 B12 0 B11 0 B10 1 B9 0 B8 1 B7 RSV B6 DMF1 B5 DMF0 B4 DM12 B3 RSV B2 RSV B1 RSV B0 RSV DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function (DAC) Default value: 01 DMF[1:0] 00 01 10 11 DE-EMPHASIS SAMPLING RATE SELECTION 44.1 kHz 48 kHz (default) 32 kHz Reserved The DMF[1:0] bits are used to select the sampling frequency used for the digital de-emphasis function when it is enabled. DM12: Digital De-Emphasis Function Control (DAC) Default value: 0 DM12 = 0 DM12 = 1 De-emphasis disabled (default) De-emphasis enabled The DM12 bit is used to enable or disable the digital de-emphasis function. See the plots shown in the Typical Performance Curves section of this data sheet. B15 REGISTER 70 0 B14 1 B13 0 B12 0 B11 0 B10 1 B9 1 B8 0 B7 RSV B6 RSV B5 FLT0 B4 RSV B3 RSV B2 1 B1 RSV B0 RSV FLT0: Digital Filter Rolloff Control (DAC) Default value: 0 FLT0 = 0 FLT0 = 1 Sharp rolloff (default) Slow rolloff The FLT0 bit allows the user to select the digital filter rolloff that is best suited to their application. Two filter rolloff selections are available: Sharp and Slow. The filter responses for these selections are shown in the Typical Performance Curves section of this data sheet. B15 REGISTER 71 0 B14 1 B13 0 B12 0 B11 0 B10 1 B9 1 B8 1 B7 RSV B6 RSV B5 RSV B4 RSV B3 RSV B2 RSV B1 RSV B0 DREV DREV: Output Phase Select (DAC) Default value: 0 DREV = 0 DREV = 1 Normal output (default) Inverted output The DREV bit is used to control the output analog signal phase control. 37 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 B15 REGISTER 72 0 B14 1 B13 0 B12 0 B11 1 B10 0 B9 0 B8 0 B7 RSV B6 RSV B5 AML B4 PG4 B3 PG3 B2 PG2 B1 PG1 B0 PG0 AML: Multiplexer Input Channel Selection (ADC) Default value: 0 AML 0 1 MULTIPLEXER INPUT CHANNEL SELECTION Line (default) Microphone The AML bit selects the input channel of multiplexer. PG[4:0]: PGA Gain Selection (ADC) Default value: 0 0100 (–4 dB) PG[4:0] 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000 PGA Gain Selection Digital mute Digital mute Digital mute 20 dB 19 dB 18 dB 17 dB 16 dB 15 dB 14 dB 13 dB 12 dB 11 dB 10 dB 9 dB 8 dB PG[4:0] 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 PGA Gain Selection 7 dB 6 dB 5 dB 4 dB 3 dB 2 dB 1 dB 0 dB – 1 dB –2 dB –3 dB –4 dB (default) Digital mute Digital mute Digital mute Digital mute The PG[4:0] bits control the gain of PGA for adjusting the signal level for ADC. B15 REGISTER 75 0 B14 1 B13 0 B12 0 B11 1 B10 0 B9 1 B8 1 B7 RSV B6 RSV B5 RSV B4 RSV B3 BYP B2 1 B1 RSV B0 RSV BYP: HPF Bypass Control (ADC) Default value: 0 BYP = 0 BYP = 1 Normal output, HPF enable (default) Bypass output, HPF disable The BYP bit controls HPF function; dc components of input and dc offset are converted in bypass mode. 38 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 B15 REGISTER 77 0 B14 1 B13 0 B12 0 B11 1 B10 1 B9 0 B8 1 B7 DACMSK B6 RSV B5 AFI5 B4 AFI4 B3 AFI3 B2 B1 B0 DITMSK COPY AUDIO DACMSK: DAC Output Control (DAC) Default value: 0 DACMSK = 0 DACMSK = 1 Mask disable (default) Mask DIN to BPZ level The DACMSK bit is used to mask DIN to BPZ level. The analog outputs from DAC is forced to BPZ level immediately. Larger noise may be generated by this control. AFI[5:3]: Additional Format Information (DIT) Default value: 000 (2 audio channels without pre-emphasis) The AFI[5:3] bits control bits[5:3] of channel status bits in compliance with IEC958. COPY: Copyright Flag (DIT) Default value: 0 (Asserted) The COPY bit controls bit[2] of channel status bits in compliance with IEC958. AUDIO: Audio Sample Word Type (DIT) Default value: 0 (PCM) The AUDIO bit controls bit[1] of channel status bits in compliance with IEC958. DITMSK: DIT Output Control (DIT) Default value: 0 DITMSK = 0 DITMSK = 1 Mask disable (default) Force DOUTS to encoded ZERO status The DITMSK bit forces only aux and audio sample words on DOUTS to encoded ZERO status. As for validity and channel status bits, the values in the register are output. 39 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 B15 REGISTER 78 0 B14 1 B13 0 B12 0 B11 1 B10 1 B9 1 B8 0 B7 CAT15 B6 CAT14 B5 CAT13 B4 CAT12 B3 CAT11 B2 CAT10 B1 CAT9 B0 CAT8 CAT[15:8]: Category Code (DIT) Default value: 0000 0000 (general) The CAT[15:8] bits control bits[15:8] of channel status bits in compliance with IEC958. B15 REGISTER 79 0 B14 1 B13 0 B12 0 B11 1 B10 1 B9 1 B8 1 B7 RSV B6 RSV B5 CLK29 B4 CLK28 B3 SF27 B2 SF26 B1 SF25 B0 SF24 CLK[29:28]: Clock Accuracy (DIT) Default value: 00 (level II) The CLK[29:28] bits control bits[29:28] of channel status bits in compliance with IEC958. SF[27:24]: Sampling Frequency (DIT) Default value: 0000 (44.1 kHz) The SF[27:24] bits control bits[27:24] of channel status bits in compliance with IEC958. B15 REGISTER 80 0 B14 1 B13 0 B12 1 B11 0 B10 0 B9 0 B8 • 0 B7 B6 B5 B4 RSV B3 WL35 B2 WL34 B1 WL33 B0 WL32 VALIDL VALIDR SPDIF VALIDL: Validity Bit for L-channel (DIT) Default value: 0 (valid) The VALIDL bit controls the validity bit for L-channel in compliance with IEC958. VALIDR: Validity Bit for R-channel (DIT) Default value: 0 (valid) The VALIDR bit controls validity bit for R-channel in compliance with IEC958. SPDIF: S/PDIF Output Control (DIT) Default value: 0 SPDIF = 0 SPDIF = 1 DOUTS disabled (default) DOUTS enabled The SPDIF bit controls output from DOUTS pin. In case of default, DOUTS always becomes LOW status. WL[35:32]: Word Length (DIT) Default value: 0001 (24 bits) The WL[35:32] bits control bits[35:32] of channel status bits and the actual data word length of audio sample word including auxiliary 4-bits from DOUTS pin in compliance with IEC958. If the WL[35:32] bits indicate 16 bits, the actual data word length of audio sample word is limited to 16 bits even though data input on DIN pin is 24-bits, for example. 40 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL CIRCUIT CONNECTION Figure 56 illustrates typical circuit connection. Line Out GND 5V Control 3.3 V Post LPF + + VOUTL C13 VOUTR C14 + C2 AGND2 I2CEN SCKI 17 VCC2 ADR 25 24 23 22 21 20 19 18 SDA SCL C7 C15 + + R1 C9 C10 VCOM MBIAS MINM MINP AGND3 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 PCM3052A 16 15 14 13 12 11 10 VDD DGND DOUTS DOUT DIN BCK LRCK + C4 System Clock and Audio Interface R2 C3 + C8 + VCC3 REFO ATEST C11 + C5 C6 + C1 + + + C12 Mic In Line In S0126-01 NOTE: C1– C4: 0.1-µF ceramic and 10-µF electrolytic capacitors typical, depending on power supply quality and pattern layout. C5– C8: 0.1-µF ceramic and 10-µF electrolytic capacitors are recommended. C9, C10: 1-µF non-polar electrolytic capacitors are recommended, which give 27-Hz cutoff frequency. C11, C12: 0.22-µF electrolytic capacitors are recommended, which give 5-Hz cutoff frequency at PGA gain = 0 dB. C13, C14: 2.2-µF electrolytic capacitors are typical. C15: 10-µF electrolytic capacitor is recommended. R1, R2: 1-kΩ typical is recommended. Figure 56. Typical Application Diagram AGND1 PDWN VINL L/M VREF1 VREF2 VCC1 VINR 41 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 DESIGN AND LAYOUT CONSIDERATIONS IN APPLICATION Power Supply Pins (VCC1, VCC2, VCC3, VDD) The digital and analog power supply lines to the PCM3052A should be bypassed to the corresponding ground pins with 0.1-µF ceramic and 10-µF electrolytic capacitors as close to the pins as possible to maximize the dynamic performance of the ADC and DAC. Although the PCM3052A has four power lines to maximize the potential of dynamic performance, using one common 5-V power supply for VCC1, VCC2, and VCC3. A 3.3-V power supply for VDD, which is generated from the 5-V power supply for VCC1, VCC2, and VCC3, is recommended to avoid unexpected power supply trouble like latch-up or power supply sequencing problems. Grounding (AGND1, AGND2, AGND3, DGND) To maximize the dynamic performance of the PCM3052A, the analog and digital grounds are not connected internally. These points should have low impedance to avoid digital noise and signal components feeding back into the analog ground. They should be connected directly to each other under the parts to reduce the potential of noise problems. VINL, VINR Pins A 0.22-µF electrolytic capacitor is recommended as an ac-coupling capacitor, which gives a 5-Hz cutoff frequency at PGA gain = 0 dB. If higher full-scale input voltage is required, it can be adjusted by adding only one series resistor to VINX pins. VREF1, VREF2, VCOM Pins Both 0.1-µF ceramic and 10-µF electrolytic capacitors are recommended from VREF1 and VREF2 to AGND1, and from VCOM to AGND2, to ensure low source impedance of the ADC and DAC references. These capacitors should be located as close as possible to the VREF1, VREF2, and VCOM pins to reduce dynamic errors on the ADC and DAC references. MBIAS Pin A 10-µF electrolytic capacitor is recommended between MBIAS and AGND3 to ensure low noise on MBIAS. REFO Pin Both 0.1-µF ceramic and 10-µF electrolytic capacitors are recommended between REFO and AGND1 to ensure low noise on REFO. MINM, MINP Pins A 1-µF non-polar electrolytic capacitor which gives a 27-Hz cutoff frequency, is recommended as coupling capacitor. System Clock The quality of SCKI can influence dynamic performance, as the PCM3052A (both of DAC and ADC) operates based on SCKI. Therefore, it might be necessary to consider the jitter, duty, rise and fall time, etc. of the system clock. External Mute Control For power-down ON/OFF control without click noise which is generated by DAC output dc level changes, the external mute control is generally required. The control sequence, which is described as External Mute ON, CODEC Power Down ON, SCKI stop and resume if necessary, CODEC Power Down OFF, and External Mute OFF, is recommended. 42 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION Orderable Device PCM3052ARTF PCM3052ARTFG4 PCM3052ARTFR PCM3052ARTFRG4 (1) Status (1) ACTIVE ACTIVE ACTIVE ACTIVE Package Type QFN QFN QFN QFN Package Drawing RTF RTF RTF RTF Pins Package Eco Plan (2) Qty 32 32 32 32 250 250 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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