PCM3052ARTFG4

          PCM3052A SLES160 – NOVEMBER 2005 24-BIT, 96-kHz STEREO AUDIO CODEC WITH MICROPHONE AMPLIFIER, BIAS, MUXTIPLEXER, AND PGA FEATURES • • • • • • • Microphone Amplifier and Bias – Monaural Microphone Amplifier: 34-dB Gain at Differential Input – Microphone Bias: 1 mA at 3.75 V Multiplexer and PGA – Multiplex of Stereo Single-Ended Line Inputs and Monaural Microphone Amplifier – 0.1 Vrms to 1.5 Vrms Full-Scale Input Range – 22-kΩ Input Resistance at 0.1-Vrms Input – 20 dB to –4 dB/range, 1 dB/step PGA Reference Output: ±10 mA at 2.5 V 24-Bit Delta-Sigma ADC and DAC Stereo ADC: – Full-Scale Input: 3 Vp-p – Antialiasing Filter Included – 1/64 Decimation Filter: • Pass-Band Ripple: ±0.05 dB • Stop-Band Attenuation: –65 dB – On-Chip High-Pass Filter: 0.91 Hz at fS = 48 kHz – High Performance: • THD+N: –94 dB (Typical) • SNR: 101 dB (Typical) • Dynamic Range: 101 dB (Typical) Stereo DAC: – Single-Ended Voltage Output: 4 Vp-p – Analog Low-Pass Filter Included – ×8 Oversampling Digital Filter: • Pass-Band Ripple: ±0.03 dB • Stop-Band Attenuation: –50 dB – High Performance: • THD+N: –97 dB (Typical) • SNR: 105 dB (Typical) • Dynamic Range: 104 dB (Typical) S/PDIF Output for DAC Digital Input A • • • • • • • Multiple Functions With I2C Interface: – Digital De-Emphasis: 32-, 44.1-, 48-kHz – Zipper-Noise-Free Digital Attenuation and Soft Mute for DAC – HPF Bypass Control for ADC – S/PDIF Output Control – Power Down: ADC/DAC Independently External Power-Down Pin: – ADC/DAC Simultaneously Audio Data Format: 24-Bit I2S Only Sampling Rate: – 16–96 kHz for Both ADC and DAC System Clock: 256 fS Only Dual Power Supplies: – 5 V for Analog and 3.3 V for Digital Package: VQFN-32 DESCRIPTION The PCM3052A is a low-cost, single-chip, 24-bit stereo audio codec (ADC and DAC) with single-ended analog voltage input and output. It also has an analog front end consisting of a 34-dB microphone amplifier, microphone bias generator, 2 stereo multiplexers, and a wide-range PGA. Analogto-digital converters (ADCs) employ delta-sigma modulation with 64-times oversampling. On the other hand, digital-to-analog converters (DACs) employ modulation with 64- and 128-times oversampling. ADCs include a digital decimation filter with a high-pass filter, and DACs include an 8-times oversampling digital interpolation filter. The PCM3052A has many functions which are controlled using the I2C interface: DAC digital de-emphasis, digital attenuation, soft mute etc. The PCM3052A also has an S/PDIF output pin for the DAC digital input. The power-down mode, which works on ADCs and DACs simultaneously, is provided by an external pin. The PCM3052A is suitable for a wide variety of cost-sensitive PC audio (recorder and player) applications where good performance is required. The PCM3052A is fabricated using a highly advanced CMOS process and is available in a small 32-pin VQFN package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. System Two, Audio Precision are trademarks of Audio Precision, Inc. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated PCM3052A www.ti.com SLES160 – NOVEMBER 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) PCM3052A Supply voltage VCC1, VCC2, VCC3 VDD –0.3 V to 4 V Supply voltage differences VCC1, VCC2, VCC3 Ground voltage differences AGND1, AGND2, AGND3, DGND Digital input voltage Analog input voltage –0.3 V to 6.5 V ±0.1 V ±0.1 V PDWN, DIN, SCKI, SDA, SCL, ADR, I2CEN –0.3 V to 6.5 V DOUT, LRCK, BCK, DOUTS – 0.3 V to (VDD + 0.3 V) < 4 V VINL, VINR, VREF1, VREF2, REFO, ATEST, L/M, VOUTR, VOUTL, VCOM, MINP, MINM, MBIAS –0.3 V to (VCC + 0.3 V) < 6.5 V ±10 mA Input current (any pins except supplies) Ambient temperature under bias –40°C to 125°C Storage temperature –55°C to 150°C Junction temperature 150°C Lead temperature (soldering) 260°C, 5 s Package temperature (reflow, peak) (1) 260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VDD Digital supply voltage VCC Analog supply voltage MIN NOM MAX 3 3.3 3.6 V 4.5 5 5.5 V 4 25 MHz 16 96 kHz Digital input logic family Digital input clock frequency Analog input voltage TTL compatible System clock Sampling clock Line input, full scale, PGA = 0 dB Microphone input, full scale, PGA = 0 dB Digital output load capacitance Line output load resistance 2 3 Vp-p 30 mVp-p 20 5 Line output load capacitance TA UNIT pF kΩ 50 pF Microphone bias output load resistance 3.75 kΩ Reference output load resistance 250 Ω Operating free-air temperature –40 85 °C PCM3052A www.ti.com SLES160 – NOVEMBER 2005 ELECTRICAL CHARACTERISTICS All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT – DATA FORMAT Audio data interface format I2S Audio data bit length 24 Audio data format fS Bits MSB-first, 2s complement Sampling frequency, ADC 16 48 96 kHz Sampling frequency, DAC 16 48 96 kHz 4 25 MHz 2 VDD System clock frequency 256 fS INPUT LOGIC VIH (1) VIL (1) VIH (2) (3) VIL(2) (3) IIH(2) (2) IIL IIH(1)(3) IIL(1) (3) Input logic level 0.8 2 Input logic level Input logic current Input logic current 5.5 0.8 VIN = VDD ±10 VIN = 0 V ±10 VIN = VDD 65 100 ±10 VIN = 0 V VDC VDC µA µA OUTPUT LOGIC VOH (4) IOUT = –4 mA VOL (4) (5) IOUT = 4 mA VOH (6) Output logic level VOL (6) IOUT = –0.3 mA 2.8 0.5 4.5 IOUT = 0.3 mA 0.5 VDC VDC MICROPHONE AMPLIFIER Input level Single-ended Gain Single-ended Input resistance Single-ended Frequency response –3 dB SNR 1-kHz, 100-mVrms output THD+N 1-kHz, 1-Vrms output 1 5 15 mVrms 40 dB 6 kΩ 20 kHz 59 dB –77 dB MICROPHONE BIAS GENERATOR Output voltage IOUT = –1 mA 0.75 VCC1 – 0.15 0.75 VCC1 Output source current 1 Output impedance Output noise voltage 0.75 VCC1 + 0.15 100 Hz–20 kHz, with 10-µF decoupling V mA 48 Ω 1.8 µVrms REFERENCE OUTPUT Output voltage IOUT = ±10 mA 0.5 VCC1 – 0.15 0.5 VCC1 Output source/sink current 10 Output impedance Output noise voltage (1) (2) (3) (4) (5) (6) 0.5 VCC1 + 0.15 6 100 Hz–20 kHz, with 10-µF decoupling 1.8 V mA Ω µVrms Pins 10, 11: LRCK, BCK (Schmitt-trigger input with 50-kΩ typical internal pulldown resistor) Pins 12, 17, 18, 19, 21: DIN, SCKI, SDA, SCL, I2CEN (Schmitt-trigger input, 5-V tolerant) Pins 9, 20 : PDWN, ADR (Schmitt-trigger input with 50-kΩ typical internal pulldown resistor, 5-V tolerant). Pins 13, 14: DOUT, DOUTS Pin 18: SDA (Open-drain LOW output) Pin 3: L/M 3 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.5 Vrms AFE MULTIPLEXER Input channel 2 CH Input range for full scale VINL, VINR 0.1 1 Input Impedance VINL, VINR 22 143 kΩ Antialiasing filter frequency response –3 dB, PGA gain = 0 dB 300 kHz Input center voltage (VREF1) 0.5 VCC1 V AFE PGA Gain range –4 Gain step 0 20 1 Monotonicity dB dB Ensured ADC CHARACTERISTICS Resolution Full-scale input voltage VINL, VINR at PGA gain = 0 dB 24 Bits 0.6 VCC1 Vp-p DC Accuracy Gain mismatch, channe-to-channel Full scale input, VINL, VINR ±1 ±2 % of FSR Gain error Full scale input, VINL, VINR ±2 ±4 % of FSR Bipolar-zero error HPF bypass, VINL, VINR ±2 Dynamic Performance THD+N Total harmonic distortion + noise fS = 48 kHz, VIN = –0.5 dB –94 fS = 96 kHz, VIN = –0.5 dB –89 fS = 48 kHz, VIN = –60 dB –38 fS = 96 kHz, VIN = –60 dB Dynamic range S/N % of FSR (7) Signal-to-noise ratio fS = 48 kHz, A-weighted fS = 48 kHz Channel separation (between microphone and line-in) fS = 48 kHz 101 dB 101 95 fS = 96 kHz, A-weighted Channel separation (between L-ch and R-ch of line-in) dB –38 95 fS = 96 kHz, A-weighted fS = 48 kHz, A-weighted –88 101 dB 101 92 fS = 96 kHz 98 dB 99 92 fS = 96 kHz 98 dB 99 Digital Filter Performance Pass band ±0.05 dB Stop band 0.454 fS 0.583 fS Hz ±0.05 Pass-band ripple Stop-band attenuation 0.583 fS Delay time HPF frequency response –3 dB Hz –65 dB dB 17.4/fS s 0.019 fS MHz 24 Bits DAC CHARACTERISTICS Resolution DC Accuracy (7) 4 Gain mismatch, channel-to-channel ±1 ±2 % of FSR Gain error ±2 ±6 % of FSR Bipolar zero error ±1 % of FSR fIN = 1 kHz, using System Two™ audio measurement system by Audio Precision™ in the RMS mode with 20-kHz LPF and 400-Hz HPF in the calculation, at PGA gain = 0 dB, for VINL and VINR. PCM3052A www.ti.com SLES160 – NOVEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted PARAMETER Dynamic Performance THD+N Total harmonic distortion + noise Dynamic range S/N TEST CONDITIONS MIN TYP MAX fS = 48 kHz, VOUT = 0 dB –97 –90 fS = 96 kHz, VOUT = 0 dB –99 fS = 48 kHz, VOUT = –60 dB –42 fS = 96 kHz, VOUT = –60 dB –43 UNIT (8) Signal-to-noise ratio Channel separation fS = 48 kHz, EIAJ, A-weighted 98 fS = 96 kHz, EIAJ, A-weighted fS = 48 kHz, EIAJ, A-weighted 104 dB 106 99 fS = 96 kHz, EIAJ, A-weighted fS = 48 kHz dB 105 dB 106 97 fS = 96 kHz 103 dB 104 Analog Output Output voltage 0.8 VCC2 Center voltage 0.5 VCC2 Load impedance LPF frequency response AC coupling Vp-p V 5 kΩ f = 20 kHz –0.03 f = 40 kHz –0.20 dB Digital Filter Performance Pass band ±0.03 dB 0.454 fS Stop band 0.546 fS Hz ±0.03 Pass-band ripple Stop-band attenuation 0.546 fS Hz –50 dB dB Delay time 20/fS s De-emphasis error ±0.1 dB POWER SUPPLY REQUIREMENTS VCC1 VCC2 VCC3 Voltage range VDD ICC (9) Supply current IDD Power dissipation 4.25 5 5.5 3 3.3 3.6 fS = 48 kHz 39 50 fS = 96 kHz 41 Full power down (10) 10 fS = 96 kHz 19 Full power down (10) 90 Operation, fS = 48 kHz 228 Operation, fS = 96 kHz 268 ADC operation at fS = 48 kHz/DAC power down 180 ADC power down/DAC operation at fS = 48 kHz 63 Full power down (10) 1.8 mA µA 300 fS = 48 kHz VDC 15 mA µA 300 mW (8) fOUT = 1 kHz, using System Two audio measurement system by Audio Precision in the RMS mode with 20-kHz LPF and 400-Hz HPF. (9) ICC = ICC1 + ICC2 + ICC3 (10) Halt SCKI, BCK, LRCK. 5 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEMPERATURE RANGE Operation temperature θJA –40 Thermal resistance 85 °C °C/W 100 DEVICE INFORMATION BLOCK DIAGRAM VINL VREF1 VREF2 REFO VINR Single-Ended MUX and PGA Delta-Sigma Modulator BCLK Decimation Filter with HPF Reference and Buffer Audio Data Interface LRCK DOUT DOUTS Single-Ended MUX and PGA DIN Delta-Sigma Modulator PDWN L/M Clock and Timing Generator, Power Control ATEST MBIAS MINM SCKI Mic Bias Mic Amp MINP VOUTL Analog LPF and Buffer Amp Multilevel Delta-Sigma Modulator VCOM VOUTR I2CEN ×8 Oversampling Interpolation Filter Analog LPF and Buffer Amp Mode Control Interface ADR SCL SDA Multilevel Delta-Sigma Modulator Power Supply AGND3 VCC3 AGND2 VCC2 AGND1 VCC1 DGND VDD B0085-01 6 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 DEVICE INFORMATION (continued) PIN ASSIGNMENTS VOUTL VOUTR VCC2 AGND2 I2CEN ADR SCL SDA SCKI 25 24 23 22 21 20 19 18 17 RTF PACKAGE (TOP VIEW) 12 DIN VCC3 31 11 BCK REFO 32 10 LRCK 9 30 PDWN AGND3 AGND1 DOUT 8 13 7 29 VCC1 MINP 6 DOUTS VINR 14 5 28 VREF2 MINM 4 DGND VREF1 15 3 27 L/M MBIAS 2 VDD VINL 16 1 26 ATEST VCOM P0036-01 TERMINAL FUNCTIONS TERMINAL NAME ADR NO. 20 I/O I DESCRIPTION Mode control address select input (1) AGND1 8 ADC analog ground AGND2 22 DAC analog ground AGND3 30 Microphone amplifier and bias analog ground ATEST 1 DGND 15 BCK 11 I Audio data bit clock input DIN 12 I Audio data digital input DOUT 13 O Audio data digital output DOUTS 14 O S/PDIF data digital output I2CEN 21 I Mode control enable/disable input, active HIGH L/M 3 O ADC line/microphone select indicator LRCK 10 I Audio data latch enable input MBIAS 27 O Microphone bias output/decoupling, 0.75 VCC1 MINM 28 I Microphone amplifier input to ADC, inverting MINP 29 I Microphone amplifier input to ADC, non-inverting PDWN 9 I ADC and DAC power down control input, active LOW (1) REFO 32 O Reference output / decoupling, 0.5 VCC1 (1) (2) (3) O Analog test, must be open Digital ground (2) (3) (3) (2) Schimtt-trigger input with 50-kΩ typical internal pulldown resistor, 5-V tolerant Schimtt-trigger input with 50-kΩ typical internal pulldown resistor Schimtt-trigger input, 5-V tolerant 7 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 DEVICE INFORMATION (continued) TERMINAL FUNCTIONS (continued) TERMINAL NAME I/O NO. DESCRIPTION SCKI 17 I System clock input, 256 fS (3) SCL 19 I Mode control clock input SDA 18 I/O VCC1 7 ADC analog power supply, 5 V VCC2 23 DAC analog power supply, 5 V VCC3 31 Microphone amplifier and bias analog power supply, 5 V VCOM 26 DAC common voltage decoupling, 0.5 VCC2 VDD 16 Digital power supply, 3.3 V VINL 2 I Line input to ADC, L-channel VINR 6 I Line input to ADC, R-channel VOUTL 25 O Analog output from DAC, L-channel VOUTR 24 O Analog output from DAC, R-channel VREF1 4 ADC reference 1 voltage output, 0.5 VCC1 VREF2 5 ADC reference 2 voltage decoupling, VCC1 (4) (3) Mode control data input/output (4) Schimtt-trigger input/open-drain LOW output, 5-V tolerant TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (ADC SECTION) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256fS, 24-bit data, unless otherwise noted. DIGITAL FILTER OVERALL CHARACTERISTICS STOP-BAND ATTENUATION CHARACTERISTICS 0 0 −20 Amplitude − dB Amplitude − dB −50 −100 −40 −60 −150 −80 −200 0 8 16 24 Normalized Frequency [×fS] Figure 1. 8 32 G001 −100 0.0 0.2 0.4 0.6 0.8 Normalized Frequency [×fS] Figure 2. 1.0 G002 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (ADC SECTION) (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256fS, 24-bit data, unless otherwise noted. PASS-BAND RIPPLE CHARACTERISTICS TRANSITION BAND CHARACTERISTICS 0.2 0 −1 −2 −3 −0.2 Amplitude − dB Amplitude − dB 0.0 −0.4 −0.6 −4 −4.13 dB at 0.5 fS −5 −6 −7 −8 −0.8 −9 −1.0 0.0 0.1 0.2 0.3 0.4 Normalized Frequency [×fS] −10 0.45 0.5 0.47 0.49 0.51 0.53 0.55 Normalized Frequency [×fS] G003 Figure 3. G004 Figure 4. HIGH-PASS FILTER STOP-BAND CHARACTERISTICS HIGH-PASS FILTER PASS-BAND CHARACTERISTICS 0 0.2 −10 0.0 −20 Amplitude − dB Amplitude − dB −30 −40 −50 −60 −70 −80 −0.2 −0.4 −0.6 −0.8 −90 −100 0.0 −1.0 0.1 0.2 0.3 0.4 Normalized Frequency [×fS/1000] Figure 5. 0.5 0 1 2 3 Normalized Frequency [×fS/1000] G005 4 G006 Figure 6. 9 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (ADC SECTION) (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256fS, 24-bit data, unless otherwise noted. ANALOG FILTER (Line Input, PGA Gain = 0 dB) ANTIALIASING FILTER STOP-BAND CHARACTERISTICS ANTIALIASING FILTER PASS-BAND CHARACTERISTICS 0 0.0 −10 −0.2 Amplitude − dB Amplitude − dB f−3dB = 300 kHz −20 −30 −40 −0.4 −0.6 −0.8 −50 1 10 100 1k 10k f − Frequency − kHz −1.0 0.1 1 10 G007 Figure 7. 10 100 1k f − Frequency − kHz G008 Figure 8. PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (DAC SECTION) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256fS, 24-bit data, unless otherwise noted. DIGITAL FILTER FREQUENCY RESPONSE, STOP BAND (Sharp Rolloff) FREQUENCY RESPONSE, PASS BAND (Sharp Rolloff) 0.2 0 −20 0.0 Amplitude − dB Amplitude − dB −40 −60 −80 −0.2 −0.4 −0.6 −100 −0.8 −120 −140 0 1 2 3 −1.0 0.0 4 Frequency [×fS] 0.1 0.2 0.4 0.5 Frequency [×fS] G009 Figure 9. G010 Figure 10. DE-EMPHASIS (fS = 32 kHz) DE-EMPHASIS ERROR (fS = 32 kHz) 0 0.5 −1 0.4 −2 0.3 −3 0.2 −4 0.1 Error − dB Level − dB 0.3 −5 −6 0.0 −0.1 −7 −0.2 −8 −0.3 −9 −0.4 −10 −0.5 0 2 4 6 8 10 12 14 0 f − Frequency − kHz 2 4 6 8 G011 Figure 11. 10 12 14 f − Frequency − kHz G012 Figure 12. 11 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (DAC SECTION) (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256fS, 24-bit data, unless otherwise noted. DE-EMPHASIS ERROR (fS = 44.1 kHz) 0.5 −1 0.4 −2 0.3 −3 0.2 −4 0.1 Error − dB Level − dB DE-EMPHASIS (fS = 44.1 kHz) 0 −5 −6 0.0 −0.1 −7 −0.2 −8 −0.3 −9 −0.4 −10 −0.5 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 f − Frequency − kHz 8 10 12 14 16 18 G013 G014 Figure 13. Figure 14. DE-EMPHASIS ERROR (fS = 48 kHz) 0 0.5 −1 0.4 −2 0.3 −3 0.2 −4 0.1 Error − dB Level − dB DE-EMPHASIS (fS = 48 kHz) −5 −6 0.0 −0.1 −7 −0.2 −8 −0.3 −9 −0.4 −10 −0.5 0 2 4 6 8 10 12 14 16 18 20 22 f − Frequency − kHz 0 2 4 6 8 10 12 Figure 15. 14 16 18 20 22 f − Frequency − kHz G015 12 20 f − Frequency − kHz G016 Figure 16. PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (DAC SECTION) (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256fS, 24-bit data, unless otherwise noted. ANALOG FILTER STOP-BAND CHARACTERISTICS (1 kHz–10 MHz) PASS-BAND CHARACTERISTICS (100 Hz–1 MHz) 0 0.0 −10 −0.2 Amplitude − dB Amplitude − dB f−3dB = 300 kHz −20 −30 −40 −0.4 −0.6 −0.8 −50 1 10 100 1k 10k f − Frequency − kHz −1.0 0.1 1 10 G017 Figure 17. 100 1k f − Frequency − kHz G018 Figure 18. 13 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES (ADC SECTION) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted. LINE INPUT (at PGA Gain = 0 dB) 110 Dynamic Range and SNR − dB −85 −90 −95 −100 −40 −15 10 35 60 TA − Free-Air Temperature − °C Dynamic Range 100 SNR 95 −40 85 −15 10 35 60 TA − Free-Air Temperature − °C G019 Figure 20. THD+N vs SUPPLY VOLTAGE DYNAMIC RANGE AND SNR vs SUPPLY VOLTAGE 85 G020 110 −85 −90 −95 −100 4.25 105 Figure 19. 4.50 4.75 5.00 VCC − Supply Voltage − V Figure 21. 14 DYNAMIC RANGE AND SNR vs TEMPERATURE Dynamic Range and SNR − dB THD+N − Total Harmonic Distortion + Noise at −0.5 dB − dB THD+N − Total Harmonic Distortion + Noise at −0.5 dB − dB THD+N vs TEMPERATURE 5.25 5.50 105 Dynamic Range 100 95 4.25 SNR 4.50 4.75 5.00 VCC − Supply Voltage − V G021 Figure 22. 5.25 5.50 G022 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES (ADC SECTION) (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted. DYNAMIC RANGE AND SNR vs SAMPLING FREQUENCY 110 −85 Dynamic Range and SNR − dB THD+N − Total Harmonic Distortion + Noise at −0.5 dB − dB THD+N vs SAMPLING FREQUENCY −90 −95 −100 32 105 Dynamic Range SNR 100 95 48 64 80 fS − Sampling Frequency − kHz Figure 23. 96 32 48 64 80 fS − Sampling Frequency − kHz G023 96 G024 Figure 24. 15 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES (DAC SECTION) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted. −90 Dynamic Range and SNR − dB 110 −95 −100 −105 −40 −15 10 35 60 TA − Free-Air Temperature − °C 105 Dynamic Range 100 95 −40 85 −15 10 35 60 TA − Free-Air Temperature − °C G025 Figure 26. THD+N vs SUPPLY VOLTAGE DYNAMIC RANGE AND SNR vs TEMPERATURE −90 85 G026 110 −95 −100 −105 4.25 SNR Figure 25. 4.50 4.75 5.00 VCC − Supply Voltage − V Figure 27. 16 DYNAMIC RANGE AND SNR vs TEMPERATURE Dynamic Range and SNR − dB THD+N − Total Harmonic Distortion + Noise at 0 dB − dB THD+N − Total Harmonic Distortion + Noise at 0 dB − dB THD+N vs TEMPERATURE 5.25 5.50 G027 105 SNR Dynamic Range 100 95 4.25 4.50 4.75 5.00 VCC − Supply Voltage − V Figure 28. 5.25 5.50 G028 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES (DAC SECTION) (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted. DYNAMIC RANGE AND SNR vs SAMPLING FREQUENCY −90 110 Dynamic Range and SNR − dB THD+N − Total Harmonic Distortion + Noise at 0 dB − dB THD+N vs SAMPLING FREQUENCY −95 −100 −105 32 SNR 105 Dynamic Range 100 95 48 64 80 fS − Sampling Frequency − kHz Figure 29. 96 G029 32 48 64 80 fS − Sampling Frequency − kHz 96 G030 Figure 30. 17 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted. ADC OUTPUT SPECTRUM (Line Input, at PGA Gain = 0 dB) OUTPUT SPECTRUM (–60 dB, N = 8192) 0 0 −20 −20 −40 −40 Amplitude − dB Amplitude − dB OUTPUT SPECTRUM (–0.5 dB, N = 8192) −60 −80 −60 −80 −100 −100 −120 −120 −140 −140 0 5 10 15 20 0 5 f − Frequency − kHz 10 15 20 f − Frequency − kHz G031 G032 Figure 31. Figure 32. DAC OUTPUT SPECTRUM OUTPUT SPECTRUM (–60 dB, N = 8192) 0 0 −20 −20 −40 −40 Amplitude − dB Amplitude − dB OUTPUT SPECTRUM (0 dB, N = 8192) −60 −80 −60 −80 −100 −100 −120 −120 −140 −140 0 5 10 15 20 f − Frequency − kHz 0 5 10 G033 Figure 33. 18 15 20 f − Frequency − kHz G034 Figure 34. PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted. SUPPLY CURRENT SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs SAMPLING FREQUENCY, ADC AND DAC OPERATING 45 45 40 30 25 20 15 IDD 10 25 20 0 −15 10 35 60 85 32 G035 64 80 Figure 35. Figure 36. SUPPLY CURRENT vs SUPPLY VOLTAGE SUPPLY CURRENT vs SUPPLY VOLTAGE 40 40 35 35 Supply Current − mA 45 30 25 20 15 IDD 96 G036 ICC1 + ICC2 + ICC3 30 25 20 15 10 5 0 3.0 48 fS − Sampling Frequency − kHz 45 10 IDD 15 5 TA − Free-Air Temperature − °C Supply Current − mA 30 10 5 0 −40 ICC1 + ICC2 + ICC3 35 Supply Current − mA Supply Current − mA 35 40 ICC1 + ICC2 + ICC3 5 3.3 VDD − Supply Voltage − V Figure 37. 3.6 G037 0 4.25 4.50 4.75 5.00 VCC − Supply Voltage − V 5.25 5.50 G038 Figure 38. 19 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 THEORY OF OPERATION ADC SECTION The ADC block consists of a reference circuit, two channels of single-ended to differential converter, a fifth-order delta-sigma modulator with fully differential architecture, a decimation filter with high-pass filter, and a serial interface circuit which is also used as the serial interface for the DAC input signal as shown in the block diagram. Figure 39 is the block diagram of the fifth-order delta-sigma modulator and transfer function. An on-chip reference circuit with two external capacitors provides all reference voltages that are needed in the ADC section, and defines the full-scale voltage range of both channels. An on-chip, single-ended to differential signal converter saves the design, space, and extra parts cost of an external signal converter. Full differential architecture provides a wide dynamic range and excellent power supply rejection performance. The input signal is sampled at ×64 oversampling rate and an on-chip antialiasing filter eliminates the need for an external sample-hold amplifier. A fifth-order delta-sigma noise shaper, which consists of five integrators using the switched-capacitor technique and a comparator, shapes the quantization noise generated outside of audio signal band by the comparator and 1-bit DAC. The high-order delta-sigma modulation randomizes the modulator outputs and reduces idle-tone level. The 64 fS, 1-bit stream from the delta-sigma modulator is converted to a 1-fS, 24-bit digital signal by removing high-frequency noise components with the decimation filter. The dc component of the signal is removed by the HPF, and the HPF output is converted to a time-multiplexed serial signal through the serial interface. Analog In X(z) + − 1st SW-CAP Integrator + − 2nd SW-CAP Integrator + 3rd SW-CAP Integrator + + + + − 4th SW-CAP Integrator + 5th SW-CAP Integrator + H(z) + Qn(z) Digital Out Y(z) + Comparator 1-Bit DAC Y(z) = STF(z) * X(z) + NTF(z) * Qn(z) Signal Transfer Function STF(z) = H(z) / [1 + H(z)] Noise Transfer Function NTF(z) = 1 / [1 + H(z)] B0005-02 Figure 39. Block Diagram of Fifth-Order Delta-Sigma Modulator DAC SECTION The DAC section is based on the delta-sigma modulator, which consists of an 8-level amplitude quantizer and a fourth-order noise shaper. This section converts the oversampled input data to 8-level delta-sigma format. A block diagram of the 8-level delta-sigma modulator is shown in Figure 40. This 8-level delta-sigma modulator has the advantage of stability and clock jitter over the typical one-bit (2-level) delta-sigma modulator. The combined oversampling rate of the delta-sigma modulator and the internal 8× interpolation filter is 64 fS for all system clocks. The theoretical quantization-noise performance of the 8-level delta-sigma modulator is shown in Figure 41. 20 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 THEORY OF OPERATION (continued) − + IN 8 fS + + + Z–1 − + + + Z–1 + + + + + Z–1 Z–1 + 8-Level Quantizer OUT 64 fS B0008-03 Figure 40. 8-Level Delta-Sigma Modulator Block Diagram 0 125 −20 120 Dynamic Range − dB Amplitude − dB −40 −60 −80 −100 −120 115 110 105 100 −140 95 −160 −180 90 0 1 2 3 4 5 6 7 fS − Sampling Frequency − kHz Figure 41. Quantization Noise Spectrum 8 0 G039 100 200 300 400 Jitter − psP−P 500 600 G040 Figure 42. Clock Jitter 21 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 THEORY OF OPERATION (continued) SYSTEM CLOCK The system clock for the PCM3052A must be 256 fS, where fS is the audio sampling rate, 16 kHz to 96 kHz. Table 1 lists typical system clock frequencies, and Figure 43 illustrates the system clock timing. Table 1. Typical System Clock SAMPLING RATE FREQUENCY (fS) – LRCK SYSTEM CLOCK FREQUENCY – MHz 16 kHz 4.096 256 fS 32 kHz 8.192 44.1 kHz 11.2896 48 kHz 12.288 96 kHz 24.576 tw(SCKH) 2V System Clock 0.8 V tw(SCKL) 1/256 fS T0005−10 PARAMETER MIN MAX UNIT tw(SCKH) System clock pulse duration, HIGH 16 ns tw(SCKL) System clock pulse duration, LOW 16 ns Figure 43. System Clock Timing POWER SUPPLY ON, EXTERNAL RESET, AND POWER DOWN The PCM3052A has both an internal power-on-reset circuit and an external reset circuit. The sequences for both resets are shown as follows. Figure 44 is the timing chart of the internal power-on reset. Two power-on-reset circuits are implemented, one each for for VCC1 and VDD. Initialization (reset) is performed automatically at the time when VCC1 and VDD exceed 3.9 V (typical) and 2.2 V (typical), respectively. Internal reset is released after 1024 SCKI from power-on-reset release, and the PCM3052A begins normal operation. VOUTL and VOUTR from the DAC are forced to the VCOM (= 0.5 VCC2) level as VCC2 rises. When synchronization between SCKI, BCK, and LRCK is maintained, VOUTL and VOUTR go into the fade-in sequence. Then VOUTL and VOUTR provide outputs corresponding to DIN after t(DACDLY1) = 2100/fS from power-on-reset release. On the other hand, DOUT from the ADC provides an output corresponding to VINL and VINR after t(ADCDLY1) = 4500/fS from power-on-reset release. If synchronization is not maintained, the internal reset is not released, and operation is kept in the power-down mode. After resynchronization, the DAC goes into the fade-in sequence, and the ADC goes into normal operation after internal initialization. DOUTS can provide S/PDIF data after the power-on-reset release if the SPDIF bit is HIGH (see serial control port for mode control section). Figure 45 shows timing chart for external reset. The PDWN pin (pin 9) initiates external forced reset when PDWN = LOW, and it provides the power-down mode, which is the lowest power-dissipation state in the PCM3052A. When PDWN transitions from HIGH to LOW while SCKI, BCK, and LRCK are synchronized, VOUTL and VOUTR are faded out and forced into VCOM (= 0.5 VCC2) level after tDACDLY1 = 2100/fS. At the same time as the internal reset becomes LOW, DOUT becomes ZERO, the PCM3052A enters the power-down mode. To return to normal operation, set PDWN to HIGH. Then the power-on reset sequence, Figure 44, is performed. 22 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 DOUTS is driven LOW immediately after PDWN is asserted and recovers about 40/fS following PDWN release. Notes: 1. Large pop noises can be generated on VOUTL and VOUTR if the power supply is turned off during normal operation. 2. To switch PDWN during fade-in or fade-out causes an immediate change between fade-in and fade-out. 3. Changing mode controls during normal operation can degrade analog performance. It is recommended that mode controls be changed through the serial control port, and that changing or stopping the clock, switching the power supply off, etc., be done in the power-down mode. VCC1, VDD (VCC1 = 5 V, VDD = 3.3 V Typ) 0V (VCC1 = 3.9 V, VDD = 2.2 V Typ) LRCK, BCK, SCKI Synchronous Clocks PDWN 1024 SCKI Internal Reset Power Down Normal Operation t(DACDLY1), 2100 /fS About 40/fS VOUTL, VOUTR VCOM (0.5 VCC2) t(ADCDLY1), 4500 /fS DOUT DOUTS ZERO Disable Enable if S/PDIF Bit = HIGH T0097-01 Figure 44. DAC Output and ADC Output for Power-On Reset 23 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 VCC1, VCC2, VCC3, VDD LRCK, BCK, SCKI (VCC1 − VCC3 = 5 V, VDD = 3.3 V Typ) 0V Synchronous Clocks Synchronous Clocks PDWN 1024 SCKI Internal Reset Normal Operation Power Down t(DACDLY1), 2100 /fS VOUTL, VOUTR Normal Operation t(DACDLY1), 2100 /fS VCOM (0.5 VCC2) 0.5 VCC2 t(ADCDLY1), 4500 /fS ZERO DOUT About 40/fS DOUTS LOW T0098-01 Figure 45. DAC Output and ADC Output for External Reset (PDWN Pin) 24 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 PCM AUDIO INTERFACE Digital audio data is interfaced to the PCM3052A on LRCK (pin 10), BCK (pin 11), DIN (pin 12), DOUT (pin 13), and DOUTS (pin 14). The PCM3052A can accept 24-bit I2S format only. In case of AC-3 type output data for DOUTS, bits 17 to 24 of DIN must be held LOW. See the Digital Audio Interface Transmitter (DIT) section of this data sheet. Table 2. Audio Data Format DATA FORMAT 24-bit, MSB-first, I2S The PCM3052A accepts only 64 clocks of BCK during one clock of LRCK. Figure 46 and Figure 47 illustrate audio data input/output format and timing. Left-Channel LRCK Right-Channel BCK DIN 1 2 3 MSB DOUT 1 2 LSB 3 MSB DOUTS 22 23 24 Sub-Frame 22 23 24 LSB 1 2 3 MSB 1 2 22 23 24 LSB 3 MSB Sub-Frame 22 23 24 LSB Sub-Frame T0016-15 Figure 46. Audio Data Input/Output Format 25 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 t(LRP) 1.4 V LRCK t(BCL) t(LB) t(BCH) t(BL) 1.4 V BCK t(BCY) t(DIS) t(DIH) 1.4 V DIN t(BDO) t(LDO) 0.5 VDD DOUT T0021−03 PARAMETER tBCY BCK pulse cycle time tBCH MIN MAX UNIT 160 ns BCK pulse duration, HIGH 70 ns tBCL BCK pulse duration, LOW 70 ns tBL BCK rising edge to LRCK edge 20 ns tLB LRCK edge to BCK rising edge 20 ns tLRP LRCK pulse duration 4.2 µs tDIS DIN setup time to BCK rising edge 20 ns tDIH DIN hold time to BCK rising edge 20 tBDO DOUT delay time from BCK falling edge 20 ns tLDO DOUT delay time from LRCK edge 20 ns tR Rising time of all signals 10 ns tF Falling time of all signals 10 ns NOTE: Load capacitance at DOUT is 20 pF. Rising and falling time is measured from 10% to 90% of IN/OUT signal swing. Figure 47. Audio Data Input/Output Timing 26 ns PCM3052A www.ti.com SLES160 – NOVEMBER 2005 SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM The PCM3052A operates with LRCK and BCK synchronized to the system clock in slave mode. The PCM3052A does not need specific phase relationship among LRCK, BCK, and the system clock, but does require the synchronization of LRCK, BCK, and the system clock. If the relationship between system clock and LRCK changes more than ±6 BCKs during one sample period due to LRCK jitter, etc., internal operation of DAC halts within 6/fS, and the analog output is forced to 0.5 VCC2 until re-synchronization of the system clock to LRCK and BCK has completed and then the time of t(DACDLY2) has elapsed. DOUTS is also held LOW during the same period. Internal operation of the ADC also halts within 6/fS, and digital output is forced into ZERO code until re-synchronization of the system clock to LRCK and BCK has completed and then the time of t(ADCDLY2) has elapsed. In case of changes less than ±5 BCKs, re-synchronization does not occur and the previously described analog/digital output control and discontinuity does not occur. Figure 48 illustrates the DAC analog output, ADC digital output, and DOUTS output for loss of synchronization. During undefined data, the PCM3052A can generate some noise in audio signal. Also, the transition of normal to undefined data and undefined or zero data to normal creates a discontinuity of data on analog and digital outputs, which could generate some noise in audio signal. Synchronization Lost State of Synchronization Synchronous Asynchronous Normal Data Synchronous t(DACDLY2) (32/fS) Within 6/fS DAC VOUT Resynchronization Undefined Data VCOM Normal Data (0.5 VCC2) t(ADCDLY2) (32/fS) ADC DOUT Normal Data Undefined Data DOUTS Normal Data Undefined Data Zero Data Low Normal Data Normal Data T0020-07 Figure 48. DAC Output and ADC Output for Loss of Synchronization MICROPHONE AMPLIFIER AND MICROPHONE BIAS GENERATOR The PCM3052A has a built-in, high-performance differential-input microphone amplifier with 34-dB gain, 5-kΩ (minimum) input resistance, and 59-dB SNR at 100-mVrms output. Bandwidth is 20 kHz for –3-dB attenuation. The PCM3052A also has a low-noise microphone bias generator with 0.75-VCC1 and 1-mA current-source capability for electret microphones. Output impedance is 48 Ω for external noise reduction. The output of the microphone amplifier and the line input are connected as inputs to the multiplexer. The serial control port can be used to control which input the multiplexer selects (see Figure 50). 27 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 REFERENCE OUTPUT The PCM3052A has a reference output pin (RFFO, pin 32) to supply reference voltage (0.5 VCC1) to external components. The pin has 10-mA sink/source capability with 6-Ω output impedance. −1 mA (0.75 VCC1) MBIAS 48 Ω + MINM − Electret Microphone MUX 34 dB + MINP REF (0.5 VCC1) REFO 6Ω +
10 mA S0124-01 Figure 49. Microphone Amplifier, Microphone Bias Generator, and Reference Output LINE AND MICROPHONE INPUT SELECT INDICATOR The PCM3052A employs an indicator pin (L/M, pin 3) to show which analog input is selected, line or microphone. Table 3. Line and Microphone Select Indicator 28 L/M LINE/MIC SELECT INDICATOR LOW Microphone HIGH Line PCM3052A www.ti.com SLES160 – NOVEMBER 2005 MULTIPLEXER AND PGA The PCM3052A has built-in analog front-end circuit which is shown in Figure 50. Multiplexer input and PGA gain are selected by mode control via the serial port, as shown in the Serial Control Port for Mode Control section. The full-scale input voltage range is 0.1 Vrms to 1.5 Vrms, and it can be adjusted to an adequate level for following the ADC sections. VINL and VINR input resistance is maintained above 22 kΩ for all PGA gains. The input resistance value for each gain can be calculated by Equation 1. 286 R IN(k
, typical)  (PGA Gain20) 1
10 (1) PGA (−4 dB to 20 dB) R VINL L-ch R −1 LIN+ LIN− PGA (−4 dB to 20 dB) R VINR R-ch R −1 RIN+ RIN− 2-ch MUX Mic Amp S0125-01 Figure 50. Multiplexer and PGA ANALOG OUTPUTS FROM DAC The PCM3052A has two independent output channels, VOUTL and VOUTR. These are unbalanced outputs, each capable of driving 4 Vp-p (typical) into a 5-kΩ ac-coupled load. The internal output amplifiers for VOUTL and VOUTR are biased to the dc common-mode (or bipolar zero) voltage, equal to 0.5 VCC2 The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy present at the DAC outputs due to the noise-shaping characteristics of the PCM3052A delta-sigma modulators. The frequency response of this filter is shown in the typical performance curves. By itself, this filter is not adequate to attenuate the out-of-band noise to an acceptable level for many applications. An external low-pass filter is required to provide sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the PCM1742 data sheet (SBAS176). VCOM OUTPUT FOR DAC One unbuffered common-mode voltage output pin, VCOM (pin 26), is brought out for decoupling purposes. This pin is nominally biased to a dc voltage level equal to 0.5 VCC2. This pin can be used to bias external circuits. Output resistance of this pin is 21 kΩ (typical). DIGITAL AUDIO INTERFACE TRANSMITTER (DIT) The PCM3052A employs S/PDIF output from DOUTS (pin 14). The data (I2S format only) from DAC digital data input (DIN, pin 12) is encoded to S/PDIF format with preambles according to IEC958. S/PDIF output is controlled through the serial control port. The output data type (linear PCM or AC-3) can be also selected through the serial control port. For the output data type of AC-3, the word length is limited to 16 bits in the PCM3052A. Therefore, bits 17 to 24 in the I2S format data must be set to LOW. 29 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 Each bit after the audio sample word is assigned in the PCM3052A as follows. Validity bit: Writable through serial control port User data: Fixed to 0 Channel status [0]: Fixed to 0 (consumer use) Channel status [1]: Writable through serial control port (audio sample word type) Channel status [2]: Writable through serial control port (copyright flag) Channel status [3:5]: Writable through serial control port (additional format information) Channel status [6:7]: Fixed to 00 (mode 0) Channel status [8:15]: Writable through serial control port (category code) Channel status [16:19]: Fixed to 0000 (source number) Channel status [20:23]: Fixed to 0000 (channel number) Channel status [24:27]: Writable through serial control port (sampling frequency) Channel status [28:29]: Writable through serial control port (clock accuracy) Channel status [30:31]: Fixed to 00 Channel status [32:35]: Writable through serial control port (word length) Channel status [36:191]: Fixed to all 0s Parity bit: Even parity for preceding data from preamble to channel status bit S/PDIF output timing is shown in Figure 51. The S/PDIF block starts with a preamble after 32/fS from the frame where S/PDIF output control bit becomes HIGH. The behavior of DOUTS for power-on reset, external reset, and loss of synchronization is shown in Figure 44, Figure 45, and Figure 48, respectively. Frame DIN (I2S Format) S/PDIF Output Control Bit L-ch Frame R-ch L-ch Disable Frame Frame R-ch L-ch Enable 32/fS DOUTS Frame P A LOW P: Preamble A: Aux R-ch SW: Audio Sample Word V: Validity Bit U: User Bits C: Channel Status SW V U C Pa P A SW V U C Pa P A Pa: Parity Bit T0099-01 Figure 51. S/PDIF Output Timing 30 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 SERIAL CONTROL PORT FOR MODE CONTROL The several built-in functions of the PCM3052A can be controlled through the I2C format serial-control port, SDA (pin 18) and SCL (pin 19). The PCM3052A supports the I2C serial bus and the data transmission protocol for standard mode as a slave device. This protocol is explained in I2C specification 2.0. Serial control is available even during the power-down state and without a system clock, except when the MRST bit = 0 or I2CEN (pin 21) = LOW. Slave Address MSB LSB 1 0 0 0 1 1 ADR R/W The PCM3052A has seven bits for its own slave address. The first six bits (MSBs) of the slave address are factory preset to 100011. The next bit of the address byte is the device select bit which can be user-defined by ADR (pin 20). A maximum of two PCM3052As can be connected on the same bus at one time. Each PCM3052A responds when it receives its own slave address. Packet Protocol A master device must control packet protocol, which consists of start condition, slave address with read/write bit, data if write or acknowledgement if read, and stop condition. The PCM3052A supports slave receiver function. SDA SCL St 1−7 8 9 1−8 9 1−8 9 9 Slave Address R/W ACK DATA ACK DATA ACK ACK R/W: Read Operation if 1; Otherwise, Write Operation ACK: Acknowledgement of a Byte if 0 DATA: 8 Bits (Byte) NACK: Not Acknowledgement of a bite if 1 Start Condition Write Operation Sp Stop Condition Transmitter M M M S M S M S S M Data Type St Slave Address W ACK DATA ACK DATA ACK ACK Sp M: Master Device S: Slave Device St: Start Condition W: Write Sp: Stop Condition T0049-04 Figure 52. Basic I2C Framework 31 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 Write Operation The PCM3052A supports receiver function. A master can write to any PCM3052A registers using single or multiple accesses. The master sends a PCM3052A slave address with a write bit, a register address, and the data. If multiple access is required, the address is that of the starting register, followed by the data to be transferred. When the data are received properly, the index register is incremented by 1 automatically. When the index register reaches 50h, the next value is 41h. When undefined registers are accessed, the PCM3052A does not send an acknowledgement. Figure 53 is a diagram of the write operation. The register address and the write data are 8 bits and MSB-first format. Transmitter M M M S M S M S M S S M Data Type St Slave Address W ACK Reg Address ACK Write Data 1 ACK Write Data 2 ACK ACK Sp M: Master Device S: Slave Device St: Start Condition ACK: Acknowledge W: Write Sp: Stop Condition R0002-03 Figure 53. Framework for Write Operation Serial Control Enable/Disable The PCM3052A supports I2C serial control enable/disable function by I2CEN (pin 21) to avoid an unstable start condition. When the I2CEN pin transitions from LOW to HIGH, both SDA (pin 18) and SCL (pin 19) must be HIGH stable and the ADR (pin 20) must be also stable. While I2CEN = LOW, the write operation is disabled. A timing chart of I2CEN is shown in Figure 54. I2CEN Disable Enable 0 µs (min) 1 µs (min) SDA/SCL Don’t Care ADR Don’t Care HIGH Fixed HIGH or LOW T0100-01 Figure 54. I2CEN Timing Chart 32 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TIMING DIAGRAM Start Repeated Start Stop t(D-HD) t(BUF) t(D-SU) t(SDA-R) t(SDA-F) t(P-SU) SDA t(SCL-R) t(RS-HD) t(LOW) SCL t(S-HD) t(HI) t(RS-SU) t(SCL-F) T0050-01 PARAMETER CONDITIONS MIN MAX UNIT 100 kHz f(SCL) SCL clock frequency Standard mode t(BUF) Bus free time between STOP and START condition Standard mode 4.7 µs t(LOW) Low period of the SCL clock Standard mode 4.7 µs t(HI) High period of the SCL clock Standard mode 4 µs tRS-SU Setup time for START/repeated START condition Standard mode 4.7 µs t(S-HD) t(RS-HD) Hold time for START/repeated START condition Standard mode 4 µs t(D-SU) Data setup time Standard mode 250 t(D-HD) Data hold time Standard mode 0 900 ns t(SCL-R) Rise time of SCL signal Standard mode 20 + 0.1 CB 1000 ns t(SCL-R1) Rise time of SCL signal after a repeated START condition and after an acknowledge bit Standard mode 20 + 0.1 CB 1000 ns t(SCL-F) Fall time of SCL signal Standard mode 20 + 0.1 CB 1000 ns t(SDA-R) Rise time of SDA signal Standard mode 20 + 0.1 CB 1000 ns t(SDA-F) Fall time of SDA signal Standard mode 20 + 0.1 CB 1000 ns t(P-SU) Setup time for STOP condition Standard mode 4 CB Capacitive load for SDA and SCL line 400 pF VNH Noise margin at high level for each connected device (including hysteresis) Standard mode 0.2 VDD ns µs V Figure 55. Control Interface Timing MODE CONTROL REGISTERS User-Programmable Mode Controls The PCM3052A has several user programmable functions which are accessed via control registers. The registers are programmed using the I2C serial control port, which was previously discussed in this data sheet. Table 4 lists the available mode control functions, along with their reset default conditions and associated register addresses. The register map is shown in Table 5. 33 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 Table 4. User-Programmable Mode Controls FUNCTION RESET DEFAULT REGISTER BIT(S) 0 dB, no attenuation 65 and 66 AT1[7:0], AT2[7:0] Mode control register reset (ADC and DAC) Normal operation 67 MRST System reset (ADC and DAC) Normal operation 67 SRST ADC power-save control (ADC) Normal operation 67 ADPSV DAC Power Save Control (DAC) Normal operation 67 DAPSV Mute disabled 68 MUT[2:1] OVR1 Digital attenuation control, 0 dB to –63 dB in 0.5-dB steps (DAC) Soft-mute control (DAC) Oversampling rate control (DAC) 64-fS oversampling 68 De-emphasis disabled 69 DM12 48 kHz 69 DMF[1:0] Sharp rolloff 70 FLT0 Output phase select (DAC) Normal 71 DREV Multiplexer input channel control (ADC) LINE IN 72 AML –4 dB 72 PG[4:0] HPF bypass control (ADC) HPF enabled 75 BYP DAC output control (DAC) Disabled 77 DACMSK Two audio channels without pre-emphasis 77 AFI[5:3] Asserted 77 COPY PCM 77 AUDIO DIT output control (DIT) Disable 77 DITMSK Category code (DIT) General 78 CAT[15:8] Clock accuracy (DIT) Level II 79 CLK[29:28] Sampling frequency (DIT) 44.1kHz 79 SF[27:24] Valid 80 VALIDL VALIDR De-emphasis function control (DAC) De-emphasis sampling rate selection (DAC) Digital filter rolloff control (DAC) PGA gain control (ADC) Additional format information (DIT) Copyright flag (DIT) Audio sample word type (DIT) Validity bit for L-channel (DIT) Validity bit for R-channel (DIT) S/PDIF output control (DIT) Valid 80 Disabled 80 SPDIF 24 bits 80 WL[35:32] Word Length (DIT) Table 5. Register Map REGISTER ADDRESS DATA IDX (B8–B14) REGISTER B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 41h 65 0 1 0 0 0 0 0 1 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10 42h 66 0 1 0 0 0 0 1 0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20 RSV (1) RSV (1) RSV (1) 43h (1) 34 67 0 1 0 0 0 0 1 1 MRST SRST ADPSV DAPSV RSV (1) RSV (1) RSV (1) RSV (1) 44h 68 0 1 0 0 0 1 0 0 RSV (1) OVR1 RSV (1) MUT2 MUT1 45h 69 0 1 0 0 0 1 0 1 RSV (1) DMF1 DMF0 DM12 RSV (1) RSV (1) RSV (1) RSV (1) 46h 70 0 1 0 0 0 1 1 0 RSV (1) RSV (1) FLT0 RSV (1) RSV (1) 1 RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) DREV 47h 71 0 1 0 0 0 1 1 1 RSV (1) 48h 72 0 1 0 0 1 0 0 0 RSV (1) RSV (1) AML PG4 PG3 PG2 PG1 PG0 4Bh 75 0 1 0 0 1 0 1 1 RSV (1) RSV (1) RSV (1) RSV (1) BYP 1 RSV (1) RSV (1) 4Dh 77 0 1 0 0 1 1 0 1 DACMSK RSV (1) AFI5 AFI4 AFI3 COPY AUDIO DITMSK 4Eh 78 0 1 0 0 1 1 1 0 CAT15 CAT14 CAT13 CAT12 CAT11 CAT10 CAT9 CAT8 4Fh 79 0 1 0 0 1 1 1 1 RSV (1) RSV (1) CLK29 CLK28 SF27 SF26 SF25 SF24 50h 80 0 1 0 1 0 0 0 0 VALIDL VALIDR SPDIF RSV (1) WL35 WL34 WL33 WL32 RSV means reserved for test operation or future extension, and these bits should be set 0 during regular operation. Do not write any values in other addresses than those listed in the table. PCM3052A www.ti.com SLES160 – NOVEMBER 2005 REGISTER DEFINITIONS B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 65 0 1 0 0 0 0 0 1 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10 REGISTER 66 0 1 0 0 0 0 1 0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20 ATx[7:0]: Digital Attenuation Level Setting (DAC) Where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR (x = 2). Default value: 1111 1111b ATX[7:0] DECIMAL VALUE 1111 1111b 255 0 dB, No Attenuation. (default) ATTENUATION LEVEL SETTING 1111 1110b 254 –0.5 dB 1111 1101b 253 –1.0 dB : : 1000 0011b 131 –62.0 dB 1000 0010b 130 –62.5 dB 1000 0001b 129 –63.0 dB 1000 0000b 128 Mute : : : : 0000 0000b 0 Mute Each DAC channel (VOUTL and VOUTR) includes a digital attenuation function. The attenuation level can be set from 0 dB to –63 dB in 0.5-dB steps, and also can be set to infinite attenuation (mute). The attenuation level change from current value to target value is performed by incrementing or decrementing by one small step size for every 1/fS time interval during 2048/fS. The small step size is determined automatically so that it can provide a transition in attenuation level with a characteristic S-shaped curve from the current value to the target value. While the attenuation level change sequence is in progress for 2048/fS, processing of the attenuation level change for any new command is ignored, and the new command is overwritten into command buffer. The last command for an attenuation level change is performed after present attenuation level change sequence is finished. The attenuation data for each channel can be set individually. The attenuation level can be calculated using the following formula: Attenuation level (dB) = 0.5 × (ATx[7:0]DEC – 255) where ATx[7:0]DEC = 0 through 255. For ATx[7:0]DEC = 0 through 128, attenuation is set to infinite attenuation. The preceding table shows attenuation levels for various settings. REGISTER 67 B15 B14 B13 B12 B11 B10 B9 B8 0 1 0 0 0 0 1 1 B7 B6 B5 B4 MRST SRST ADPSV DAPSV B3 B2 B1 B0 RSV RSV RSV RSV MRST: Mode Control Register Reset (ADC and DAC) Default value: 1 MRST = 0 Set default value MRST = 1 Normal operation (default) The MRST bit controls mode control register reset. Pop-noise may be generated. SRST: System Reset (ADC and DAC) Default value: 1 35 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 SRST = 0 Re-synchronization SRST = 1 Normal operation (default) The SRST bit controls system reset. The PCM3052A does not go into power-down state. The mode control register is not reset by this control. Also pop-noise may be generated. ADPSV: ADC Power-Save Control (ADC) Default value: 0 ADPSV = 0 Normal operation (default) ADPSV = 1 Power-save mode The ADPSV bit controls ADC power-save mode. In power-save mode, ADC goes into power-down state, the data in ADC are reset, and DOUT is forced into ZERO immediately. I2C control is enabled. DAPSV: DAC Power-Save Control (DAC) Default value: 0 DAPSV = 0 Normal operation (default) DAPSV = 1 Power-save mode The DAPSV bit controls the DAC power-save mode. In the power-save mode, the DAC output is faded out and DAC goes into the power-down state. I2C control is enabled. A waiting time of more than 2100/fS from power-save-mode assertion is required for the release of the power-save mode. DIT function is available if SPDIF bit = 1, even though DAPSV = 1. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 1 0 0 0 1 0 0 RSV OVR1 RSV RSV RSV RSV MUT2 MUT1 REGISTER 68 OVR1: Oversampling Rate Control (DAC) Default value: 0 OVR1 = 0 64× oversampling (default) OVR1 = 1 128× oversampling The OVR1 bit is used to control the oversampling rate of the delta-sigma D/A converters. To write over this register during normal operation may generate noise. MUTx: Soft-Mute Control (DAC) where, x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR (x = 2). Default value: 0 MUTx = 0 Mute disabled (default) MUTx = 1 Mute enabled The mute bits, MUT1 and MUT2, are used to enable or disable the soft-mute function for the corresponding DAC outputs, VOUTL and VOUTR. The soft-mute function is incorporated into the digital attenuators. When mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1, the digital attenuator for the corresponding output is decreased from the current setting to infinite attenuation, one attenuator step (0.5 dB) for every 8/fS seconds. This provides pop-free muting of the DAC output. By setting MUTx = 0, the attenuator is increased one step for every 8/fS seconds to the previously programmed attenuation level. 36 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 1 0 0 0 1 0 1 RSV DMF1 DMF0 DM12 RSV RSV RSV RSV REGISTER 69 DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function (DAC) Default value: 01 DMF[1:0] DE-EMPHASIS SAMPLING RATE SELECTION 00 44.1 kHz 01 48 kHz (default) 10 32 kHz 11 Reserved The DMF[1:0] bits are used to select the sampling frequency used for the digital de-emphasis function when it is enabled. DM12: Digital De-Emphasis Function Control (DAC) Default value: 0 DM12 = 0 De-emphasis disabled (default) DM12 = 1 De-emphasis enabled The DM12 bit is used to enable or disable the digital de-emphasis function. See the plots shown in the Typical Performance Curves section of this data sheet. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 1 0 0 0 1 1 0 RSV RSV FLT0 RSV RSV 1 RSV RSV REGISTER 70 FLT0: Digital Filter Rolloff Control (DAC) Default value: 0 FLT0 = 0 Sharp rolloff (default) FLT0 = 1 Slow rolloff The FLT0 bit allows the user to select the digital filter rolloff that is best suited to their application. Two filter rolloff selections are available: Sharp and Slow. The filter responses for these selections are shown in the Typical Performance Curves section of this data sheet. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 1 0 0 0 1 1 1 RSV RSV RSV RSV RSV RSV RSV DREV REGISTER 71 DREV: Output Phase Select (DAC) Default value: 0 DREV = 0 Normal output (default) DREV = 1 Inverted output The DREV bit is used to control the output analog signal phase control. 37 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 1 0 0 1 0 0 0 RSV RSV AML PG4 PG3 PG2 PG1 PG0 REGISTER 72 AML: Multiplexer Input Channel Selection (ADC) Default value: 0 AML MULTIPLEXER INPUT CHANNEL SELECTION 0 Line (default) 1 Microphone The AML bit selects the input channel of multiplexer. PG[4:0]: PGA Gain Selection (ADC) Default value: 0 0100 (–4 dB) PG[4:0] PGA Gain Selection PG[4:0] PGA Gain Selection 11111 Digital mute 01111 7 dB 11110 Digital mute 01110 6 dB 11101 Digital mute 01101 5 dB 11100 20 dB 01100 4 dB 11011 19 dB 01011 3 dB 11010 18 dB 01010 2 dB 11001 17 dB 01001 1 dB 11000 16 dB 01000 0 dB 10111 15 dB 00111 – 1 dB 10110 14 dB 00110 –2 dB 10101 13 dB 00101 –3 dB 10100 12 dB 00100 –4 dB (default) 10011 11 dB 00011 Digital mute 10010 10 dB 00010 Digital mute 10001 9 dB 00001 Digital mute 10000 8 dB 00000 Digital mute The PG[4:0] bits control the gain of PGA for adjusting the signal level for ADC. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 1 0 0 1 0 1 1 RSV RSV RSV RSV BYP 1 RSV RSV REGISTER 75 BYP: HPF Bypass Control (ADC) Default value: 0 BYP = 0 Normal output, HPF enable (default) BYP = 1 Bypass output, HPF disable The BYP bit controls HPF function; dc components of input and dc offset are converted in bypass mode. 38 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 0 1 0 0 1 1 0 1 DACMSK RSV AFI5 AFI4 AFI3 REGISTER 77 B2 B1 COPY AUDIO B0 DITMSK DACMSK: DAC Output Control (DAC) Default value: 0 DACMSK = 0 Mask disable (default) DACMSK = 1 Mask DIN to BPZ level The DACMSK bit is used to mask DIN to BPZ level. The analog outputs from DAC is forced to BPZ level immediately. Larger noise may be generated by this control. AFI[5:3]: Additional Format Information (DIT) Default value: 000 (2 audio channels without pre-emphasis) The AFI[5:3] bits control bits[5:3] of channel status bits in compliance with IEC958. COPY: Copyright Flag (DIT) Default value: 0 (Asserted) The COPY bit controls bit[2] of channel status bits in compliance with IEC958. AUDIO: Audio Sample Word Type (DIT) Default value: 0 (PCM) The AUDIO bit controls bit[1] of channel status bits in compliance with IEC958. DITMSK: DIT Output Control (DIT) Default value: 0 DITMSK = 0 Mask disable (default) DITMSK = 1 Force DOUTS to encoded ZERO status The DITMSK bit forces only aux and audio sample words on DOUTS to encoded ZERO status. As for validity and channel status bits, the values in the register are output. 39 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 1 0 0 1 1 1 0 CAT15 CAT14 CAT13 CAT12 CAT11 CAT10 CAT9 CAT8 REGISTER 78 CAT[15:8]: Category Code (DIT) Default value: 0000 0000 (general) The CAT[15:8] bits control bits[15:8] of channel status bits in compliance with IEC958. REGISTER 79 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 1 0 0 1 1 1 1 RSV RSV CLK29 CLK28 SF27 SF26 SF25 SF24 CLK[29:28]: Clock Accuracy (DIT) Default value: 00 (level II) The CLK[29:28] bits control bits[29:28] of channel status bits in compliance with IEC958. SF[27:24]: Sampling Frequency (DIT) Default value: 0000 (44.1 kHz) The SF[27:24] bits control bits[27:24] of channel status bits in compliance with IEC958. B15 B14 B13 B12 B11 B10 B9 0 1 0 1 0 0 0 REGISTER 80 B8 • 0 B7 B6 B5 VALIDL VALIDR SPDIF B4 B3 B2 B1 B0 RSV WL35 WL34 WL33 WL32 VALIDL: Validity Bit for L-channel (DIT) Default value: 0 (valid) The VALIDL bit controls the validity bit for L-channel in compliance with IEC958. VALIDR: Validity Bit for R-channel (DIT) Default value: 0 (valid) The VALIDR bit controls validity bit for R-channel in compliance with IEC958. SPDIF: S/PDIF Output Control (DIT) Default value: 0 SPDIF = 0 DOUTS disabled (default) SPDIF = 1 DOUTS enabled The SPDIF bit controls output from DOUTS pin. In case of default, DOUTS always becomes LOW status. WL[35:32]: Word Length (DIT) Default value: 0001 (24 bits) The WL[35:32] bits control bits[35:32] of channel status bits and the actual data word length of audio sample word including auxiliary 4-bits from DOUTS pin in compliance with IEC958. If the WL[35:32] bits indicate 16 bits, the actual data word length of audio sample word is limited to 16 bits even though data input on DIN pin is 24-bits, for example. 40 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL CIRCUIT CONNECTION Figure 56 illustrates typical circuit connection. Line Out GND Control 5V 3.3 V Post LPF + C7 C15 + + VCOM R1 MBIAS C9 C10 R2 MINM MINP AGND3 C3 + VCC3 C8 REFO + SCKI 17 SDA 18 19 SCL ADR 20 21 22 I2CEN AGND2 C2 VCC2 24 25 VOUTL VOUTR C13 23 + C14 26 16 27 15 28 14 PCM3052A 29 13 30 12 31 11 32 10 VDD DGND DOUTS + C4 System Clock and Audio Interface DOUT DIN BCK LRCK + C12 C1 8 9 PDWN AGND1 7 6 VINR + VCC1 5 4 C6 + C5 Mic In VREF2 VREF1 3 2 C11 L/M VINL ATEST 1 + + + Line In S0126-01 NOTE: C1– C4: 0.1-µF ceramic and 10-µF electrolytic capacitors typical, depending on power supply quality and pattern layout. C5– C8: 0.1-µF ceramic and 10-µF electrolytic capacitors are recommended. C9, C10: 1-µF non-polar electrolytic capacitors are recommended, which give 27-Hz cutoff frequency. C11, C12: 0.22-µF electrolytic capacitors are recommended, which give 5-Hz cutoff frequency at PGA gain = 0 dB. C13, C14: 2.2-µF electrolytic capacitors are typical. C15: 10-µF electrolytic capacitor is recommended. R1, R2: 1-kΩ typical is recommended. Figure 56. Typical Application Diagram 41 PCM3052A www.ti.com SLES160 – NOVEMBER 2005 DESIGN AND LAYOUT CONSIDERATIONS IN APPLICATION Power Supply Pins (VCC1, VCC2, VCC3, VDD) The digital and analog power supply lines to the PCM3052A should be bypassed to the corresponding ground pins with 0.1-µF ceramic and 10-µF electrolytic capacitors as close to the pins as possible to maximize the dynamic performance of the ADC and DAC. Although the PCM3052A has four power lines to maximize the potential of dynamic performance, using one common 5-V power supply for VCC1, VCC2, and VCC3. A 3.3-V power supply for VDD, which is generated from the 5-V power supply for VCC1, VCC2, and VCC3, is recommended to avoid unexpected power supply trouble like latch-up or power supply sequencing problems. Grounding (AGND1, AGND2, AGND3, DGND) To maximize the dynamic performance of the PCM3052A, the analog and digital grounds are not connected internally. These points should have low impedance to avoid digital noise and signal components feeding back into the analog ground. They should be connected directly to each other under the parts to reduce the potential of noise problems. VINL, VINR Pins A 0.22-µF electrolytic capacitor is recommended as an ac-coupling capacitor, which gives a 5-Hz cutoff frequency at PGA gain = 0 dB. If higher full-scale input voltage is required, it can be adjusted by adding only one series resistor to VINX pins. VREF1, VREF2, VCOM Pins Both 0.1-µF ceramic and 10-µF electrolytic capacitors are recommended from VREF1 and VREF2 to AGND1, and from VCOM to AGND2, to ensure low source impedance of the ADC and DAC references. These capacitors should be located as close as possible to the VREF1, VREF2, and VCOM pins to reduce dynamic errors on the ADC and DAC references. MBIAS Pin A 10-µF electrolytic capacitor is recommended between MBIAS and AGND3 to ensure low noise on MBIAS. REFO Pin Both 0.1-µF ceramic and 10-µF electrolytic capacitors are recommended between REFO and AGND1 to ensure low noise on REFO. MINM, MINP Pins A 1-µF non-polar electrolytic capacitor which gives a 27-Hz cutoff frequency, is recommended as coupling capacitor. System Clock The quality of SCKI can influence dynamic performance, as the PCM3052A (both of DAC and ADC) operates based on SCKI. Therefore, it might be necessary to consider the jitter, duty, rise and fall time, etc. of the system clock. External Mute Control For power-down ON/OFF control without click noise which is generated by DAC output dc level changes, the external mute control is generally required. The control sequence, which is described as External Mute ON, CODEC Power Down ON, SCKI stop and resume if necessary, CODEC Power Down OFF, and External Mute OFF, is recommended. 42 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) PCM3052ARTF ACTIVE VQFN RTF 32 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PCM3052A PCM3052ARTFR ACTIVE VQFN RTF 32 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 PCM3052A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of