User's Guide
SLDU011B – May 2015 – Revised August 2018
PGAxxxEVM-034 User Guide
The PGAxxxEVM-034 supplies a platform to test the PGA900, PGA300, and PGA305 in the QFN
package. The EVM is shipped as either the PGA900EVM-034, the PGA300EVM-034, or the
PGA305EVM-034, with the name identifying the signal conditioner included in the EVM package. The
PGAxxxEVM-034 supplies an interchangeable platform all of these devices can use.
1
2
3
4
5
6
7
Contents
Introduction ................................................................................................................... 2
Default Configuration ........................................................................................................ 3
Inputs and Output Configurations ......................................................................................... 4
3.1
Pressure Input ....................................................................................................... 4
3.2
Temperature Input .................................................................................................. 4
3.3
Output ................................................................................................................ 4
3.4
Voltage Mode........................................................................................................ 5
3.5
Current Mode ........................................................................................................ 6
3.6
OWI and SPI/I2C/SWD in 4-mA to 20-mA Current Loop ...................................................... 7
OWI .......................................................................................................................... 10
4.1
Activation Pulse.................................................................................................... 11
4.2
Data Sent Through OWI .......................................................................................... 12
XDS200 and USB2ANY Connectors .................................................................................... 13
Power Supplies in the PGAxxxEVM-034 ................................................................................ 16
Schematics .................................................................................................................. 17
List of Figures
1
PGAxxxEVM-034 ............................................................................................................ 2
2
Pressure Stimulus in the PGAxxxEVM-034 .............................................................................. 4
3
PGA900 in Voltage Mode Configuration .................................................................................. 5
4
PGAxxxEVM-034 in Current Mode ........................................................................................ 6
5
Additional Loop Current in 4-mA to 20-mA Mode When Using SPI/I2C/SWD as Digital Interface
6
Additional Loop Current in 4-mA to 20-mA Mode When Using OWI as Digital Interface .......................... 9
7
OWI Block Diagram ........................................................................................................ 10
8
OWI Activation Pulse for the PGA900 Generated by the PGAxxxEVM-034 in Voltage Mode ................... 11
9
OWI Data at 320 bps; Oscilloscope Probe is Connected at TP20 in the PGAxxxEVM-034 ..................... 12
10
XDS200 Emulator Connection to the PGAxxxEVM-034 .............................................................. 13
11
USB2ANY Connection to the PGAxxxEVM-034 ....................................................................... 14
12
USB2ANY ................................................................................................................... 14
13
USB2ANY Pinout ........................................................................................................... 15
14
Power Distribution in PGAxxxEVM-034 ................................................................................. 16
15
PGAxxxEVM-034 Main Schematic ....................................................................................... 17
16
Input and Output Schematic .............................................................................................. 18
17
USB2ANY Schematic ...................................................................................................... 19
18
OWI Activation Pulse and Data Schematic ............................................................................. 20
19
OWI Power Amplifier Schematic ......................................................................................... 21
20
Power Supplies Schematic................................................................................................ 22
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1
Introduction
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Trademarks
All trademarks are the property of their respective owners.
1
Introduction
Figure 1 shows the PGAxxxEVM-034 and labels the primary sections.
Figure 1. PGAxxxEVM-034
The PGAxxxEVM-034 is divided into six sections:
1. Interface boards and external power:
a. USB2ANY connector
b. XDS200 connector (single wire debugger)
c. Banana connectors to power up EVM
2. Power:
a. 7.5-V, 5-V, and 3.3-V regulators
3. Mode selection:
a. 4- to 20-mA loop (current mode)
b. Voltage mode
4. OWI circuitry
5. Resistive bridge
6. Application components
The application components section only lists the required components for real-life applications using the
PGA900/PGA300/PGA305 device. In this case, the application is configured for current mode.
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Default Configuration
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NOTE: The PGA900, PGA300, and PGA305 have different features and pin functions, and some
circuitry and communication features found on the PGAxxxEVM-034 are only applicable to
the PGA900. Each device also has its own unique Graphical User Interface (GUI) that
communicates with the included USB2ANY board.
2
Default Configuration
The EVM requires a 10- to 30-V input applied to J20 and J21. Clamp the power supply current to 100 mA.
The shipped EVM is configured for voltage mode as shown in Table 1.
Table 1. Jumper Settings for PGAxxxEVM-034 in Voltage Mode
Jumper
Setting
Function
J12
Closed
PGAxxx powered up from OWI circuitry (VDD = 5 V)
J1, J2, J3
Closed
Connect resistive bridge to PGA900
J6, J7, J8
Closed
Voltage mode with a 100-nF load
J24, J25, J26, J27, J28, J30 Closed
SPI/I2C/UART enabled (only applicable to PGA900)
J16
Closed
Connect ASIC_GND to IRETURN
J14
Pins 1-2 closed
Connect VDD cap to ASIC_GND
J19
Pins 2-3 closed
Connect USBGND to IRETURN
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Inputs and Output Configurations
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3
Inputs and Output Configurations
3.1
Pressure Input
The PGAxxxEVM-034 has a resistive bridge where one leg of the bridge can be changed using a digital
potentiometer. The changing leg has two digital potentiometers connected in parallel in series with a 4.7kΩ resistor. J1 must be closed to connect the bridge voltage from the PGAxxx device to the resistive
bridge. The J2 and J3 must also be closed to connect the bridge outputs to the PGAxxx. An RC filter is in
series with each of the input pins in the PGAxxx with a cutoff frequency of approximately 106 Hz. Figure 2
shows the pressure stimulus circuit in the PGAxxxEVM-034.
PGA900
J1
VBRGP
4.7 NŸ
4.99 NŸ
J2
RC filter
VINPP
RC filter
VINPN
J3
4.99 NŸ
4.99 NŸ
VBRGN
Figure 2. Pressure Stimulus in the PGAxxxEVM-034
3.2
Temperature Input
The PGAxxxEVM-034 does not have on-board stimulus for the temperature inputs of the PGAxxx, but the
TP27 and TP29 on the far-right side of the board can be used to apply external signals.
3.3
Output
The PGAxxxEVM-034 can be configured for voltage or current mode (4-mA to 20-mA loop). Each mode
requires different jumper settings as shown in the following sections.
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Inputs and Output Configurations
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3.4
Voltage Mode
The PGAxxxEVM-034 is by default configured in voltage mode with a 100-nF load. A compensation
capacitor and an isolation resistor are necessary for stability. Figure 3 shows the PGAxxx schematic for
voltage mode and Table 1 shows all the jumpers necessary to configure the board in this mode. If the
capacitive load is different from 100 nF, then the isolation resistor and compensation capacitor values
must be changed. Refer to the application note PGA900 as a Capacitive Load Driver (SLDA020) for more
information.
VOUT
110 Ÿ
560 pF
100 nF
PGA900
COMP
FBN
AVSS
DVSS
GND
FBP
Figure 3. PGA900 in Voltage Mode Configuration
NOTE: If the designer wants the VDD to be higher than 5 V in voltage mode, open J12 and close
J13. VDD will be equal to the power applied to the PGAxxxEVM-034.
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Inputs and Output Configurations
3.5
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Current Mode
When in current mode, the PGAxxxEVM-034 must be properly configured to separate the different
negative references for all the voltage levels present in the board. Figure 4 shows the primary connections
for current mode. The two scenarios in current mode are:
• Current mode using OWI
• Current mode using SPI/I2C/SWD (only applicable to the PGA900 or the PGA305 in I2C mode)
PGA900EVM
J12
OWI
PWR
J13
VDD
VOUT
J20
PGA900
J21
150 Ÿ
COMP
FBN
10 Ÿ
AVSS
DVSS
GND
FBP
USB2ANY
PC
J16
ASICGND
IRETURN
J16: Open for current mode
J16: Closed for
x Voltage mode
x SPI/I2C/SWD communication
IRETURN
J19: USBGND to IRETURN for OWI in current mode
J19: USBGND to ASICGND for SPI/I2C/SWD in current mode
J19
ASICGND
USBGND
Figure 4. PGAxxxEVM-034 in Current Mode
NOTE: When in current mode, the input voltage to the EVM (J20 and J21) should be at least 20 V.
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3.6
2
OWI and SPI/I C/SWD in 4-mA to 20-mA Current Loop
Remember that when in current mode, there are two different scenarios depending on whether OWI or
SPI/I2C/SWD will be used as the type of communication for the PGA900. The PGA300 only allows
communication through OWI, so always follow the settings found on Table 3 when using the PGA300 in
current mode. Table 2 shows the jumper settings necessary for each of these scenarios. Refer to Figure 4
for the locations of the jumpers. The PGA305 allows communication through OWI or through I2C. When
using OWI communication with the PGA305 device in current mode, refer to the same settings used for
the PGA300 listed earlier. For I2C communication with the PGA305 in current mode, use the same
settings as those used for I2C communication with the PGA900 in current mode.
Table 2. Jumper Settings for PGA900EVM-034 in Current Mode Using SPI/I2C/SWD
Jumper
Setting
J16
Open
J19
Pins 1-2 closed
J13
Closed
J6
Open
J9
Closed
Connect COMP to ASIC_GND
J4
Closed
Short out resistor at VOUT
J8
Open
J5
Closed
J7
Open
J10
Closed
J14
Pins 1-2 closed
Function
Disconnect ASIC_GND from IRETURN
Connect USBGND to ASICGND
Connect PGA900 VDD pin to EVM input voltage
Disconnect 180 pF between COMP and VOUT
Disconnect FBN from VOUT
Connect VOUT to BJT
Lift 100-nF Voltage-mode load Capacitor at base of BJT
Connect FBP to IRETURN through 10-Ω resistor
100-nF capacitor from VDD to FBP and from DACCAP to FBP
J12
Open
J25, J27
Closed
Disconnect PGA900 VDD pin from OWI signal from EVM
If I2C is desired
J24, J26, J28, J30
Closed
If SPI/UART is desired
Table 3. Jumper Settings for PGAxxxEVM-034 in Current Mode Using OWI
Jumper
Setting
J16
Open
J19
Pins 2-3 closed
J13
Open
Disconnect PGA900 VDD pin from EVM input voltage
J6
Open
Disconnect 560 pF between COMP and VOUT
J9
Closed
Connect COMP to ASIC_GND
J4
Closed
Short out resistor at VOUT
J8
Open
J5
Closed
J7
Open
Function
Disconnect ASIC_GND from IRETURN
Connect USBGND to IRETURN
Disconnect FBN from VOUT
Connect VOUT to BJT
Lift 100-nF Voltage-mode load Capacitor at base of BJT
J10
Closed
J14
Pins 1-2 closed
Connect FBP to IRETURN through 10-Ω resistor
J12
Closed
J25, J27
Open
Disconnect I2C pins between USB2ANY and PGA900
J24, J26, J28, J30
Open
Disconnect SPI/UART pins between USB2ANY and PGA900
100-nF capacitor from VDD to FBP and from DACCAP to FBP
Connect VDD in PGA900 to OWI signal from EVM
The PGA300 and PGA305 are prepared for OWI communication and do not require additional device
configuration.
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For the PGA900, OWI in current mode can only be used with appropriate firmware programmed in the
device. The firmware should:
1. Enable the OWI interrupt and service it when the activation sequence on VDD is received by the
device.
2. Set the deglitch time to the 1-ms default time (OWI_DGL_CNT_SEL = 0).
3. Disconnect the DAC output from the loop by setting bit 0 of AMUX_CTRL to 0.
4. Enable the OWI transceiver and reset M0 by writing 0x03 to MICRO_INTERFACE_CONTROL register.
When in 4-mA to 20-mA loop configuration, there is additional current from ASIC_GND (GND of PGA900)
to IRETURN (return path for the loop current) that is caused by the voltage difference created by the 40-Ω
resistor inside the PGA900 and the 10-Ω (R9) EVM resistor. This additional current is due to the U11
(when in SPI/I2C/SWD communication) and U1 (digital potentiometer in the resistive bridge). Figure 5 and
Figure 6 show this additional current. As a result, the designer should lift J22 and J23 to isolate U1 and
should use OWI when using the PGAxxxEVM-034 if they want accurate calibration (firmware required) in
4-mA to 20-mA mode.
PGA900EVM
J13
PGA900
VDD
VBRGP
VOUT
U1
PWR
OWI
VINPN
J20
VINPP
150 Ÿ
OWI-Rx
OWI-Tx
VBRGN
J21
U11
J19
COMP
ADDITIONAL
CURRENT
10 Ÿ
40 Ÿ
AVSS
DVSS
GND
LOOP CURRENT
FBP
ADDITIONAL
CURRENT
J19: USBGND to ASICGND for SPI/I2C/SWD in current mode
J16
J16: Open
ASICGND
IRETURN
Figure 5. Additional Loop Current in 4-mA to 20-mA Mode When Using SPI/I2C/SWD as Digital Interface
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PGA900EVM
J12
PGA900
VDD
VBRGP
VOUT
U1
PWR
OWI
VINPN
J20
VINPP
150 Ÿ
OWI-Rx
OWI-Tx
VBRGN
J21
U11
J19
COMP
ADDITIONAL
CURRENT
10 Ÿ
40 Ÿ
AVSS
DVSS
GND
LOOP CURRENT
J19: USBGND to IRETURN for OWI in current mode
FBP
J16
J16: Open
ASICGND
IRETURN
Figure 6. Additional Loop Current in 4-mA to 20-mA Mode When Using OWI as Digital Interface
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OWI
4
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OWI
The OWI circuitry in the PGAxxxEVM-034 allows the designer to communicate with the PGA900, PGA300,
and PGA305 through voltage level translation and current sensing circuitry. The OWI circuitry is based on
a summing amplifier using the OPA454. This is because the current mode application where the GND
reference for the PGA900 (ASIC_GND) is at a higher potential than the reference for the OWI circuitry
(IRETURN). This is due to the internal 40-Ω resistor and the 10-Ω (R9) EVM resistor connected to FBP.
However, this resistor could be a higher value, and as expected, the potential difference will be larger and
is current-dependent. The summing amplifier principle compensates for these voltage differences so that
the OWI logic levels (with respect to the ASIC_GND) always remain the same, regardless of current. The
OWI circuitry, shown in Figure 7, consists of four primary blocks:
1. OWI write: UART data and activation pulses level translated to OWI voltage logic levels.
2. Offset voltage: Constant offset voltage selected by the user to compensate for constant drops from
components such as diodes. This is only necessary when operating the device in current mode. In
voltage mode, the offset voltage should be set to 0 V.
3. Current compensating voltage: This additional voltage is only necessary when operating the device in
current mode to compensate for the voltage difference between the PGA900 ground and the OWI
circuitry ground due to the loop current. In voltage mode, the gain of the OPA734 should be set to unity
gain.
4. OWI read: Current to voltage and voltage level translation to UART voltage logic levels.
6.81 NŸ
10 NŸ
OWI READ
UART-Rx
OPA454
USB2ANY
20
UART-Tx
10
VDD
10.2k
+
OWI WRITE
100 nF
4 ± 5 V for Communication
5 ± 7.5 V for Activation
12.4 NŸ
OPA734
PGA900
+
INA138
16.2 NŸ
1 NŸ
Offset Voltage
Current Compensating Voltage
Figure 7. OWI Block Diagram
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OWI
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4.1
Activation Pulse
The activation pulse generated by the PGAxxxEVM-034 generates the OWI interrupt necessary to activate
the OWI (with the proper firmware developed by the user). Figure 8 shows the activation pulse from the
PGAxxxEVM-034.
• In the PGA900 and PGA305 GUIs, to use this activation pulse, select the “Through Pulse” option from
the “OWI Activation Mode” menu and then click “OWI”. The duration of the activation pulse varies due
to software delays, but the minimum requirement of 1 or 10 ms is always met. If the pulse is not
necessary, OWI can also be enabled through I2C. To select this option, select “Through I2C” from the
“OWI Activation Mode” menu, and then click “OWI”.
• In the PGA300 GUI, the activation pulse is sent as soon as the designer presses "Activate OWI". The
pulse is sent as defined in the PGA300 data sheet (SLDS204).
Figure 8. OWI Activation Pulse for the PGA900 Generated by the PGAxxxEVM-034 in Voltage Mode
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OWI
4.2
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Data Sent Through OWI
Data through OWI can be sent to the PGA900/PGA300/PGA305 at rates between 320 to 9600 bps.
Figure 9 shows data sent at 320 bps.
Figure 9. OWI Data at 320 bps; Oscilloscope Probe is Connected at TP20 in the PGAxxxEVM-034
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XDS200 and USB2ANY Connectors
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5
XDS200 and USB2ANY Connectors
The XDS200 is used for the single-wire debugging (SWD) feature of the PGA900. The designer must use
a small breakout board (part of the XDS200 kit) to connect to J17 in the PGA900EVM-034. No external
connections are necessary. Figure 10 shows the proper connection for the XDS200 emulator.
Figure 10. XDS200 Emulator Connection to the PGAxxxEVM-034
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XDS200 and USB2ANY Connectors
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The USB2ANY is used for the different communication protocols supplied by the
PGA900/PGA300/PGA305. The USB2ANY connects to J18 in the PGAxxxEVM-034 as shown in
Figure 11. The USB2ANY hardware is based on the TI MSP430F5529, 16-bit microcontroller with
integrated USB 2.0. The PCB is a two-layer, single-sided board with minimal component count. There are
two versions of the USB2ANY, shown in Figure 12, one enclosed and one open. The functionality is the
same for both.
Figure 11. USB2ANY Connection to the PGAxxxEVM-034
Figure 12. USB2ANY
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Figure 13 shows the pinout of the USB2ANY. The ribbon cable can only be connected one way to the USB2ANY due to a latch present in the
cable. A USB cable is included to connect the device to the PC. No external supply is necessary.
Figure 13. USB2ANY Pinout
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Power Supplies in the PGAxxxEVM-034
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Power Supplies in the PGAxxxEVM-034
The PGAxxxEVM-034 requires an input voltage between 10 V to 30 V to properly operate. Figure 14
shows the different power options in the PGAxxxEVM-034.
J13
To PGA900 VDD
J11
To PGA900 VDD
J15
To PGA900 VP_OTP
J20
10 to 30 V
7.5-V Regulator
3.3-V Regulator
5-V Regulator
J21
Figure 14. Power Distribution in PGAxxxEVM-034
NOTE: J15 must be closed during OTP programming. This is only applicable for the PGA900. The
PGA300 has no OTP functionality.
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Schematics
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7
Schematics
Figure 15 through Figure 20 show the PGAxxxEVM-034 schematics.
TP11
TP10
TP12
PIN 29 TP13
PIN 33
PIN 34
TP15
PIN 31
TP14
PIN 28
PIN 30
PIN 35
PIN 36
TP16
Q5
BSS169H6327XTSA1
J11
OWI
VPWR
J12
PIN 1
28
29
TP17
30
31
33
34
35
36
37
ASIC_GND
VPWR
32 DVSS
ASIC_GND
VDD SELECTION
XU1
790-41036-101T
TP18
TP19
J13
PWR
TP20
TP23
DVDD
1
27
PIN 27
2
26
PIN 26
3
25
PIN 25
4
24
PIN 24
5
23
6
22
INT-
7
21
INT+
8
20
PIN 20
9
19
PIN 19
TP22
TP21
TP24
TP25
PIN 4
INT+
INTINP+
INPBRG+
BRG-
PWR
C21
1000pF
DACCAP
TP26
C23
0.1µF
PIN 7
OUT
TP30
AVDD
1
2
3
PWR
9
AVDD
3
DVDD
2
DVDD_MEM
21
INTINP-
6
1
4
7
19
20
24
25
26
12
11
OUT
COMP
17
16
FB+
FB-
INT+
22
18
BRG+
BRG-
AVSS
DVSS
INP+
NU
NU
NU
NU
NU
NU
NU
NU
COMP
FBFB+
COMP
18
16
17
15
BRG+
REFCAP
14
13
COMP
BRG-
12
PIN 31
PIN 30
INP+
TP34
TP35
TP37 TP38
TP39
TP41 TP42 TP40
8
ASIC_GND
C24
0.1µF
ASIC_GND
23
32
10
PAD
37
NU
NU
NU
NU
NU
NU
NU
NU
NU
28
29
30
31
33
34
35
36
27
DACCAP
FBFB+
TP31
INT+
INTINP+
INPBRG+
BRG-
INP-
TP36
13
GND
REFCAP
11
10
GND
ASIC_GND
15
14
PIN 31
PIN 30
ASIC_GND
TP29
TP33
U17
5
TP27
TP32
FB-
J14
TP28
C22
0.1µF
FB+
FB+
ASIC_GND
AVSS
DECOUPLING CAPS
J15
V7P5
J16 J16 -
OPEN FOR 4-20 mA LOOP
CLOSED FOR VOLTAGE OUTPUT
SPI/I2C COMMUNICATION
PIN 1
DVDD
AVDD
J16
C25
0.1µF
C26
0.1µF
ASIC_GND IRETURN
PGA300ARHHR
ASIC_GND
Figure 15. PGAxxxEVM-034 Main Schematic
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Schematics
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J1
RESISTIVE BRIDGE
J22
BRG+
V5
U1
1
C1
0.1µF
2
11
3
VDD
A1
6
W1
4
B1
5
AD0
PIN 33
PIN 36
7
9
J2
AD1
ASIC_GND
A3
WP
W3
ASIC_GND
R2
4.99k
R1
4.70k
SDA
B3
SCL
VSS
DGND
12
R3
14
C2
0.15µF
INP+
C3
0.01µF
DNI
10.0k
J3
13
8
10
R4
AD5252BRUZ1
R5
4.99k
INP-
10.0k
R6
4.99k
INP+
INP-
C4
0.15µF
J23
ASIC_GND
BRG-
DAC OUTPUT CONFIGURATIONS
PWR
J4
4-20 mA loop:
D4
BAS70W-7-F Close J4, J5, J9, J10 and J14 (pins
1-2)
Open J6, J7, J8 and J16
J5
OUT
2,4
TP1
R7
J6
Q1
BCP56-16
J7
110
Voltage mode:
Close J6, J7, J8, J14 (pins 2-3) and
J16
Open J4, J5, J9 and J10
J8
C6
560pF
C5
0.1µF
R8
150
J9
ASIC_GND
COMP
COMP
J10
FB-
ASIC_GND
FB-
TP2
TP3
R9
FB+
10.0
IRETURN
Figure 16. Input and Output Schematic
18
PGAxxxEVM-034 User Guide
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Schematics
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XDS200
GND TEST POINTS
AVDD
TP43
TP44
TP45
TP46
TP47
TP48
IRETURN
USBGND
USBGND
R40
10.0k
J17
1
3
5
7
9
ASIC_GND ASIC_GND IRETURN
2
4
6
8
10
PIN 31
PIN 30
ASIC_GND
USB2ANY
J18
J24
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
EFC0/GPIO12/CLOCK
TP50
GPIO6/PWM1/SPI(CS)
GPIO4/SPI(SIMO)/UART(TXD)
PIN 29
TP53
USBGND
U11
9
PIN 35
OWI_RX
PIN 34
OWI_TX
V+
NC1
COM1
2
NO1
7
NC2
IN1
COM2
4
NO2
3
GND
IN2
PIN 28
+5V_EXT
C28
0.1µF
J26
TP59
8
10
J28
TP55
GPIO2/SPI(SCLK)
GPIO0/I2C(SDA)
TP57
ADC1
GPIO8/ADC3
GPIO_OWI_VDD
GPIO10/VEREF-
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
TP49
TP51
R41
0
+3.3V_EXT
GPIO3/PWM2
GPIO1/I2C(SCL)
J25
TP52
TP54
PIN 36
SCL
SCL
TP56
ADC0
GPIO9/ADC2
TP58
J27
GPIO11/VEREF+
0
TP60
SDA
1
GPIO_OWI_ACT
GPIO7/PWM0
R42
TP61
SPI_SIMO/UART_TX_U2A
DAC0
+5V_EXT
PWM3
DAC1
TP62
GPIO_OWI_TX
PIN 33
SDA
6
SPI_SOMI/UART_RX_U2A
5
GPIO5/SPI(SOMI)/UART(RXD)
U16
GPIO_OWI_TX
SDA 3
IO1
IO2
5 SCL
GND
NC
NC
1
2
TS5A23159DGS
J30
USBGND
4
1
2
3
J19 - USBGND TO IRETURN: OWI in 4-20 mA LOOP
J19 - USBGND TO ASIC_GND: SPI/I2C/SWD in 4-20 mA LOOP
ASIC_GND
TPD2E2U06DRLR
USBGND
IRETURN
J19
Figure 17. USB2ANY Schematic
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Schematics
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OWI ACTIVATION PULSE AND DATA
OWI ACTIVATION
V7P5
Q2
BSS192PH6327FTSA1
-250V
R10
200k
V7P5
C7
0.1µF
TP4
R11
2.00k
IRETURN
U2
Q3
R12
1.00k
GPIO_OWI_ACT
IRETURN
2
4
POWER_AMP_IN
U15
3 OPA734AIDBVT
1
4
6
1
GPIO_OWI_TX
5
5
6
V7P5
V+
COM
NO
NC
IN
GND
N.C.
-VCC
BSS123
100V
8
2
R13
4.02k
3
7
IRETURN
C18
IRETURN
TS12A12511DGKR
0.1µF
IRETURN
IRETURN
OWI DATA
V5
Q4
BSS192PH6327FTSA1
-250V
R14
5.1k
R15
2.00k
TP5
C8
0.1µF
TP6
U3A
TLC352ID
8
R17
1.00k
R18
8.06k
IRETURN
2
1
V+
V-
A
4
R16
2.00k
IRETURN
3
IRETURN
OWI_TX
V3P0
R19
3.0k
IRETURN
Figure 18. OWI Activation Pulse and Data Schematic
20
PGAxxxEVM-034 User Guide
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POWER AMPLIFIER
GPIO_OWI_VDD
Only "1" when button to "Raise VDD during
calibration in voltage mode" is clicked in the
GUI
OWI
C10
R20
0
1000pF
CURRENT SENSING - UART RX
V3P3
OWI
R25
V3P3
Q6
BC847CLT1G
R21
C11
0.1µF
R22
2.00k
C9
1µF
R31
R26
6.81k
10.0k
IRETURN
VPWR
IRETURN
R28
V7P5
IRETURN
U5
VPWR
R27
C14
1.0Meg
6
1.0Meg
8
0.1µF
1
TP9
7
5
8
U4B
OPA2734AIDGST
10
V5
6
8
R37
10.0k
9
4
2
R34
16.2k
4.99k
V+
3
6
V-
R32
R33
20.0
10.0
OUT
IN+
PRE OUT
IN-
NC
BUF IN
4
10µF
3
A
3
TLC352ID
V3P3
2
1
V+
V-
R30
46.4k
R29
499k
7
R35
1.00k
R46
20.0k
C15
82pF
IRETURN
5
4
3
IRETURN
IRETURN
V+
IRETURN
VIN-
10.2k
VIN+
0.1µF
U8
IRETURN
IRETURN
1
IRETURN
U4A
2
OUT
U9
TPL0102-100RUCR
GND
INA138NA
R47
12.4k
4
11
OWI_RX
C17
8
VSS
5
LB
GND
6
4
HB
LA
WB
2
3
1
HA
GND
TP8
U6A
2
IRETURN
VPWR
R39
WA
R24
1.00k
U7
OPA454AIDDA
IRETURN
5.1k
C12
0.1µF
IRETURN
5
INA271AID
C16
270pF
POWER_AMP_IN
R23 TP7
40.2k
C13
V+
4
9
1
7
IRETURN
R36
IRETURN
8
10k
4
GPIO_OWI_VDD
3 OPA2734AIDGST
1
10
C27
SCL
SDA
A2
A1
A0
VDD
2
5
V7P5
R48
C39
0.027µF
1.00k
R38
4.99k
IRETURN
10
9
7
12
13
14
0.1µF
IRETURN
V7P5
U10
C19
4
SCL SDA
V3P3
0.1µF
V5
IRETURN
13
C40
VDD
O1
14
VL
O2
12
C20
DNI
1000pF
IRETURN
5
0.1µF
9
IRETURN
SCL
SDA
A
AD1
W
8
AD0
B
6
SCL
V3P3
IRETURN
SHDN
7
GND
SDA
VSS
1
2
3
10
11
AD5280BRUZ50
IRETURN
Figure 19. OWI Power Amplifier Schematic
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21
Schematics
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POWER SUPPLIES
7.5V Regulator
10V - 30V PGA900EVM input
D2
100V
VPWR
T1
V7P5
1N4002-T
U12
T2
VPWR
3
J20
1
IN
OUT
4
ADJ
LM317MKVURG3
SPC15363
C30
100µF
C29
0.1µF
D3
1N4002-T
100V
R43
240
C31
1µF
J21
C32
0.1µF
SPC15354
R44
1.18k
C33
10µF
IRETURN
IRETURN
IRETURN
IRETURN
IRETURN
3.3V Regulator
5V Regulator
V5
V7p5
T3
V3P3
V5 T4
U13
U14
1
C34
1µF
3
IN
EN
OUT
NC
GND
1
IN
3
EN
5
C35
0.1µF
4
R45
0
2
OUT
5
BYPASS
4
GND
2
C36
0.01µF
C37
1µF
TPS79133DBV
TPS76950QDBVRG4Q1
C38
10µF
IRETURN
IRETURN
IRETURN
IRETURN
IRETURN
IRETURN
IRETURN
Figure 20. Power Supplies Schematic
22
PGAxxxEVM-034 User Guide
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Revision History
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from A Revision (June 2016) to B Revision .................................................................................................... Page
•
Added references for PGA305EVM..................................................................................................... 1
Changes from Original (May 2015) to A Revision ........................................................................................................... Page
•
•
•
•
•
•
•
•
•
Updated Table 2 ........................................................................................................................... 7
Added Table 3 ............................................................................................................................. 7
Additional current discussion when in 4-mA to 20-mA mode........................................................................ 8
Added Figure 5 ............................................................................................................................ 8
Added Figure 6 ............................................................................................................................ 9
Added note regarding jumper for OTP voltage ...................................................................................... 16
Updated designator for J16 in Figure 15 ............................................................................................. 17
Updated designators for text in DAC Output Configurations in Figure 16 ....................................................... 18
Updated designator for J19 in Figure 17 ............................................................................................. 19
SLDU011B – May 2015 – Revised August 2018
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Revision History
23
STANDARD TERMS FOR EVALUATION MODULES
1.
Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2
Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
3
Regulatory Notices:
3.1 United States
3.1.1
Notice applicable to EVMs not FCC-Approved:
FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software
associated with the kit to determine whether to incorporate such items in a finished product and software developers to write
software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or
otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition
that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must
operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2
For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•
•
•
•
Reorient or relocate the receiving antenna.
Increase the separation between the equipment and receiver.
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1
For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1
Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page
3.3.2
Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the
instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs
(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):
1.
2.
3.
Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1.
2.
3.
電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
実験局の免許を取得後ご使用いただく。
技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
3.3.3
Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/
/www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
3.4 European Union
3.4.1
For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):
This is a class A product intended for use in environments other than domestic environments that are connected to a
low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this
product may cause radio interference in which case the user may be required to take adequate measures.
4
EVM Use Restrictions and Warnings:
4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT
LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.
4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling
or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information
related to, for example, temperatures and voltages.
4.3 Safety-Related Warnings and Restrictions:
4.3.1
User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user
guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and
customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input
and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or
property damage. If there are questions concerning performance ratings and specifications, User should contact a TI
field representative prior to connecting interface electronics including input power and intended loads. Any loads applied
outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible
permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any
load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.
During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit
components may have elevated case temperatures. These components include but are not limited to linear regulators,
switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the
information in the associated documentation. When working with the EVM, please be aware that the EVM may become
very warm.
4.3.2
EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the
dangers and application risks associated with handling electrical mechanical components, systems, and subsystems.
User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,
affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic
and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely
limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and
liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or
designees.
4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,
state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all
responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and
liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local
requirements.
5.
Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate
as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as
accurate, complete, reliable, current, or error-free.
6.
Disclaimers:
6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT
LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL
FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT
NOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS
FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE
SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.
6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BE
CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR
INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE
EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR
IMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.
7.
USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS
LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,
EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY
HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLY
WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL
THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.
8.
Limitations on Damages and Liability:
8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,
INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE
TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR
REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,
OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF
USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI
MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS
OCCURRED.
8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED
HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN
CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR
EVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE
CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.
9.
Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)
will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in
a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable
order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),
excluding any postage or packaging costs.
10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,
without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to
these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.
Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief
in any United States or foreign court.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES
Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to,
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TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
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You understand and agree that you remain responsible for using your independent analysis, evaluation and judgment in designing your
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This Notice applies to TI Resources. Additional terms apply to the use and purchase of certain types of materials, TI products and services.
These include; without limitation, TI’s standard terms for semiconductor products http://www.ti.com/sc/docs/stdterms.htm), evaluation
modules, and samples (http://www.ti.com/sc/docs/sampterms.htm).
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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