SN65DSI83TPAPRQ1

Product Folder Order Now Support & Community Tools & Software Technical Documents SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 SN65DSI83-Q1 Automotive Single-Channel MIPI® DSI to Single-Link LVDS Bridge 1 Features 3 Description • • The SN65DSI83-Q1 DSI-to-LVDS bridge features a single-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1 Gbps per lane and a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data-stream to an LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Single-Link LVDS with four data lanes per link. • • • • • • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 2: –40°C to +105°C Ambient Operating Temperature – Device HBM ESD Classification Level 3A – Device CDM ESD Classification Level C6 Implements MIPI® D-PHY Version 1.00.00 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00 Single-Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1 Gbps Per Lane Supports 18-bpp and 24-bpp DSI Video Packets with RGB666 and RGB888 Formats Maximum Resolution up to 60 fps WUXGA 1920 × 1200 at 18 bpp and 24 bpp Color With Reduced Blanking. Suitable for 60 fps 1366 × 768 / 1280 × 800 at 18 bpp and 24 bpp Output for Single-Link LVDS Supports Single Channel DSI to Single-Link LVDS Operating Mode LVDS Output Clock Range of 25 MHz to 154 MHz LVDS Pixel Clock May be Sourced from FreeRunning Continuous D-PHY Clock or External Reference Clock (REFCLK) 1.8-V Main VCC Power Supply Low Power Features Include SHUTDOWN Mode, Reduced LVDS Output Voltage Swing, Common Mode, and MIPI Ultra-Low Power State (ULPS) Support LVDS Channel SWAP, LVDS PIN Order Reverse Feature for Ease of PCB Routing Packaged in 64-pin 10-mm × 10-mm HTQFP (PAP) PowerPAD™ IC Package 2 Applications • • • • • • • The SN65DSI83-Q1 device can support up to WUXGA 1920 × 1200 at 60 frames per second, at 24 bpp with reduced blanking. The SN65DSI83-Q1 device is also suitable for applications using 60 fps 1366 × 768/1280 × 800 at 18 bpp and 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces. The SN65DSI83-Q1 device is implemented in a small outline 10-mm × 10-mm HTQFP package with a 0.5-mm pitch, and operates across a temperature range from –40°C to +105°C. Device Information(1) PART NUMBER SN65DSI83-Q1 PACKAGE BODY SIZE (NOM) HTQFP (64) 10.00 mm × 10.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. SN65DSI83-Q1 Schematic TFT LCD Display DA[3:0]P DA[3:0]N Application Processor With DSI Output DACP/N SCL/SDA Single-Channel DSI to Dual LVDS Bridge SN65SDSI83-Q1 A_Y0:3N A_Y0:3P A_CLKN/P 24-Bit TCON 1 IRQ EN Copyright © 2016, Texas Instruments Incorporated Infotainment Head Unit With Integrated Display Infotainment Head Unit With Remote Display Infotainment Rear-Seat Entertainment Hybrid Automotive Cluster Portable Navigation Device Navigation Industrial Human Machine Interface (HMI) and Displays 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 6 6.1 6.2 6.3 6.4 6.5 6.6 6 6 6 6 7 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics......................................... Parameter Measurement Information ................ 10 Detailed Description ............................................ 13 8.1 8.2 8.3 8.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Programming........................................................... 13 13 13 21 8.5 Register Maps ......................................................... 23 9 Application and Implementation ........................ 37 9.1 Application Information............................................ 37 9.2 Typical Application .................................................. 38 10 Power Supply Recommendations ..................... 43 10.1 VCC Power Supply................................................. 43 10.2 VCORE Power Supply ......................................... 43 11 Layout................................................................... 43 11.1 Layout Guidelines ................................................. 43 11.2 Layout Example .................................................... 44 12 Device and Documentation Support ................. 45 12.1 12.2 12.3 12.4 12.5 12.6 Documentation Support ........................................ Receiving Notification of Documentation Updates Community Resource............................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 45 45 45 45 45 45 13 Mechanical, Packaging, and Orderable Information ........................................................... 46 4 Revision History Changes from Original (December 2016) to Revision A Page • Deleted figure RESET and Initialization Timing Definition While VCC is High ...................................................................... 12 • Changed the paragraph following Figure 8 ......................................................................................................................... 15 • Changed Recommended Initialization Sequence To: Initialization Sequence ..................................................................... 16 • Changed Table 2 .................................................................................................................................................................. 16 • Changed item 3 in Video Stop and Restart Sequence From: Drive all DSI input lanes including DSI CLK lane to LP11. To: Drive all DSI data lanes to LP11, but keep the DSI CLK lanes in HS. ............................................................... 37 2 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 SN65DSI83-Q1 www.ti.com SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 5 Pin Configuration and Functions ADDR VCC RSVD RSVD RSVD RSVD VCC RSVD RSVD VCC RSVD RSVD GND RSVD RSVD VCC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PAP Package 64-Pin HTQFP With PowerPAD™ Top View RSVD2 1 48 VCC EN 2 47 A_Y0N VCC 3 46 A_Y0P RSVD 4 45 A_Y1N RSVD 5 44 A_Y1P RSVD 6 43 VCC RSVD 7 42 A_Y2N RSVD 8 41 A_Y2P RSVD 9 40 VCC RSVD 10 39 A_CLKN RSVD 11 38 A_CLKP RSVD 12 37 A_Y3N RSVD 13 36 A_Y3P VCC 14 35 VCC SCL 15 34 RSVD1 SDA 16 33 IRQ Thermal 32 VCC 31 VCORE 30 DA3N 29 DA3P 28 DA2N 27 DA2P 26 GND 25 DACN 24 DACP 23 GND 22 DA1N 21 DA1P 20 DA0N 19 DA0P 18 VCC REFCLK 17 Pad Not to scale See the Layout section for layout information. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 3 SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 www.ti.com Pin Functions PIN NAME NO. ADDR 64 A_CLKP 38 A_CLKN 39 A_Y0P 46 A_Y0N 47 A_Y1P 44 A_Y1N 45 A_Y2P 41 A_Y2N 42 A_Y3P 36 A_Y3N 37 DA0P 19 DA0N 20 DA1P 21 DA1N 22 DA2P 27 DA2N 28 DA3P 29 DA3N 30 DACP 24 DACN 25 EN TYPE DESCRIPTION I/O Local I2C interface target address select. See Table 3. In normal operation this pin is an input. When the ADDR pin is programmed high, it must be tied to the same 1.8-V power rails where the SN65DSI83-Q1 VCC 1.8-V power rail is connected O LVDS channel A, LVDS clock output O LVDS channel A, LVDS data output 0 O LVDS channel A, LVDS data output 1 O LVDS channel A, LVDS data output 2 O LVDS channel A, LVDS data output 3. A_Y3P and A_Y3N must be left not connected (NC) for 18-bpp panels I MIPI D-PHY channel A, data lane 0; data rate up to 1 Gbps I MIPI D-PHY channel A, data lane 1; data rate up to 1 Gbps I MIPI D-PHY channel A, data lane 2; data rate up to 1 Gbps I MIPI D-PHY channel A, data lane 3; data rate up to 1 Gbps I MIPI D-PHY channel A, clock lane; data rate up to 1 Gbps 2 I Chip enable and reset. The device is reset (shutdown) when the EN pin is low GND 23, 26, 52 G Reference ground IRQ 33 O Interrupt signal REFCLK 17 I This pin is an optional external reference clock for the LVDS pixel clock. If an external reference clock is not used, this pin must be pulled to ground with an external resistor. The source of the reference clock must be placed as close as possible with a series resistor near the source to reduce EMI 4 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 SN65DSI83-Q1 www.ti.com SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 Pin Functions (continued) PIN NAME NO. TYPE DESCRIPTION 4 5 6 7 8 9 10 11 12 RSVD 13 50 RSVD Reserved and leave them unconnected 51 53 54 56 57 59 60 61 62 RSVD1 34 I/O Reserved. This pin must be left unconnected for normal operation RSVD2 1 I Reserved. This pin must be left unconnected for normal operation SCL 15 I Local I2C interface clock SDA 16 I/O Local I2C interface data — 1.8-V power supply 3 14 18 32 35 VCC 40 43 48 49 55 58 63 VCORE 31 P 1.1-V output from the voltage regulator. This pin must have a 1-µF external capacitor to ground PowerPAD — — Reference ground Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 5 SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC MIN MAX UNIT –0.3 2.175 V CMOS input pins –0.5 2.175 V DSI input pins (DAxP, DAxN) –0.4 1.4 V Supply voltage Input voltage TA Operating free-air temperature –40 105 °C TJ Junction temperature –40 115 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE Electrostatic discharge V(ESD) (1) Human-body model (HBM), per AEC Q100-002 (1) ±4000 Charged-device model (CDM), per AEC Q100-011 ±1000 UNIT V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT 1.65 1.8 1.95 V VCC VCC power supply VPSN Supply noise on any VCC pin V(DSI) DSI input pin voltage ƒ(I2C) Local I2C input frequency ƒHS(CLK) DSI high-speed (HS) clock input frequency tsu DSI HS data to clock setup time; see Figure 1 0.15 UI (1) th DSI HS data to clock hold time; see Figure 1 0.15 UI (1) ZOD(LVDS) LVDS output differential impedance TC Case temperature (1) ƒ(noise) > 1 MHz 0.05 V –50 1350 mV 400 kHz 500 MHz 40 90 132 Ω 92.2 °C The unit interval (UI) is one half of the period of the HS clock; at 500 MHz the minimum setup and hold time is 150 ps. 6.4 Thermal Information SN65DSI83-Q1 THERMAL METRIC (1) PAP (HTQFP) UNIT 64 PINS RθJA Junction-to-ambient thermal resistance 36.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 18.2 °C/W RθJB Junction-to-board thermal resistance 20.6 °C/W ψJT Junction-to-top characterization parameter 0.8 °C/W ψJB Junction-to-board characterization parameter 20.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 2.2 °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 SN65DSI83-Q1 www.ti.com SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 6.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT VIL Low-level control signal input voltage VIH High-level control signal input voltage VOH High-level output voltage IOH = –4 mA VOL Low-level output voltage IOL = 4 mA 0.4 V ILKG Input failsafe leakage current VCC = 0; VCC(PIN) = 1.8 V ±30 μA IIH High level input current Any input terminal ±30 μA IIL Low level input current Any input terminal ±30 μA IOZ High-impedance output current CMOS output terminals ±10 μA IOS Short-circuit output current Any output driving GND short ±50 mA ICC Device active current See 77 124 mA IULPS Device standby current All data and clock lanes are in ultra-low power state (ULPS) 7.7 14 mA IRST Shutdown current EN = 0 130 µA REN EN control input resistor (1) (2) 0.3 × VCC 0.7 × VCC (2) V V 1.25 V 200 kΩ All typical values are at VCC = 1.8 V and TA = 25°C SN65DSI83-Q1: SINGLE Channel DSI to SINGLE Channel DSI, 1280 × 800 (a) Number of LVDS lanes = 3 data lanes + 1 CLK lane (b) Number of DSI lanes = 4 data lanes + 1 CLK lane (c) LVDS CLK OUT = 83 M (d) DSI CLK = 500 M (e) RGB888, LVDS 18 bpp Maximum values are at VCC = 1.95 V and TA = 85°C Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 7 SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 www.ti.com Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT MIPI DSI INTERFACE VIH-LP LP receiver input high threshold See Figure 2 VIL-LP LP receiver input low threshold See Figure 2 |VID| HS differential input voltage |VIDT| HS differential input voltage threshold VIL-ULPS LP receiver input low threshold; ultra-low power state (ULPS) VCM-HS HS common mode voltage; steady-state ΔVCMHS HS common mode peak-to-peak variation including symbol delta and interference VIH-HS HS single-ended input high voltage See Figure 2 VIL-HS HS single-ended input low voltage See Figure 2 VTERM- HS termination enable; single-ended input voltage (both Dp AND Dn apply to enable) Termination is switched simultaneous for Dn and Dp EN RDIFF- 880 mV 100 70 HS mode differential input impedance 550 mV 270 mV 50 mV 300 mV 330 mV 100 mV 460 mV –40 mV 80 450 mV 125 Ω HS LVDS OUTPUT |VOD| |VOD| Steady-state differential output voltage A_Y x P/N Steady-state differential output voltage for A_CLKP/N Δ|VOD| Change in steady-state differential output voltage between opposite binary states VOC(SS) Steady state common-mode output voltage (3) CSR 0×19.3:2=00 100 Ω near end termination 180 245 330 CSR 0×19.3:2=01 100 Ω near end termination 215 293 392 CSR 0×19.3:2=10 100 Ω near end termination 250 341 455 CSR 0×19.3:2=11 100 Ω near end termination 290 389 515 CSR 0×19.3:2=00 200 Ω near end termination 150 204 275 CSR 0×19.3:2=01 200 Ω near end termination 200 271 365 CSR 0×19.3:2=10 200 Ω near end termination 250 337 450 CSR 0×19.3:2=11 200 Ω near end termination 300 402 535 CSR 0×19.3:2=00 near end termination 140 191 262 CSR 0×19.3:2=01 100 Ω near end termination 168 229 315 CSR 0×19.3:2=10 100 Ω near end termination 195 266 365 CSR 0×19.3:2=11 100 Ω near end termination 226 303 415 CSR 0×19.3:2=00 200 Ω near end termination 117 159 220 CSR 0×19.3:2=01 200 Ω near end termination 156 211 295 CSR 0×19.3:2=10 200 Ω near end termination 195 263 362 CSR 0×19.3:2=11 200 Ω near end termination 234 314 435 Peak-to-peak common-mode output voltage RLVDS_D Pulldown resistance for disabled LVDS outputs mV RL = 100 Ω CSR 0×19.6 = 1 and CSR 0×1B.6 = 1 Figure 3 CSR 0×19.6 = 0 see Figure 3 VOC(PP) mV 35 0.75 0.9 1.13 1 1.25 1.5 see Figure 3 35 1 mV V mV kΩ IS (3) 8 Tested at VCC = 1.8V , TA = –40°C for MIN, TA = 25°C for TYP, TA = 105°C for MAX. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 SN65DSI83-Q1 www.ti.com 6.6 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT 300 ps 40 ns DSI tGS DSI LP glitch suppression pulse width LVDS tc Output clock period tw High-level output clock (CLK) pulse duration 6.49 t0 Delay time, CLK↑ to 1st serial bit position t1 Delay time, CLK↑ to 2nd serial bit position t2 Delay time, CLK↑ to 3rd serial bit position t3 Delay time, CLK↑ to 4th serial bit position t4 Delay time, CLK↑ to 5th serial bit position t5 t6 tr Differential output rise time tf Differential output fall time 4/7 tc ns –0.15 0.15 ns 1/7 tc – 0.15 1/7 tc + 0.15 ns 2/7 tc – 0.15 2/7 tc + 0.15 ns 3/7 tc – 0.15 3/7 tc + 0.15 ns 4/7 tc – 0.15 4/7 tc + 0.15 ns Delay time, CLK↑ to 6th serial bit position 5/7 tc – 0.15 5/7 tc + 0.15 ns Delay time, CLK↑ to 7th serial bit position 6/7 tc – 0.15 6/7 tc + 0.15 ns 180 500 ps tc = 6.49 ns; Input clock jitter < 25 ps (REFCLK) See Figure 4 See Figure 4 EN, ULPS, RESET ten Enable time from EN or ULPS tc(o) = 12.9 ns 1 ms tdis Disable time to standby; see tc(o) = 12.9 ns 0.1 ms treset Reset yime 10 FREFCLK REFCLK freqeuncy. Supported frequencies: 25 MHz - 154 MHz 25 154 tr, tf REFCLK rise and fall time 100 × 10–12 1×10–9 s tpj REFCLK peak-to-peak phase jitter 50 ps Duty REFCLK duty cycle ms REFCLK 40% 50% 60% 0.5% 1% 2% MHz REFCLK or DSI CLK (DACP/N) SSC_CLKIN (1) (2) SSC enabled Input CLK center spread depth (2) Modulation frequency 30 60 kHz All typical values are at VCC = 1.8 V and TA = 25°C For EMI reduction purpose, the SN65DSI83-Q1 supports the center spreading of the LVDS CLK output through the REFCLK or DSI CLK input. The center spread CLK input to the REFCLK or DSI CLK is passed through to the LVDS CLK output A_CLKP/N. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 9 SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 www.ti.com 7 Parameter Measurement Information Figure 1. DSI HS Mode Receiver Timing Definitions 1.3 V LP-RX Input HIGH VIH(LP) VIL(LP) VID LP-RX Input LOW VIH(HS) VCM(HS)max HS-RX Common Mode Range VCM(HS)min GND VIL(HS) Low Power (LP) Mode Receiver High Speed (HS) Mode Receiver Figure 2. DSI Receiver Voltage Definitions 10 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 SN65DSI83-Q1 www.ti.com SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 Parameter Measurement Information (continued) 49.9 A_YnP ±1% (2 PLCS) VOD A_YnN VOC 100 % 80% VOD(H) 0V VOD(L) 20% 0% tf tr VOC(PP) VOC(s) VOC(s) 0V Figure 3. Test Load and Voltage Definitions for LVDS Outputs CLK td(6) td(5) td(4) td(3) td(2) td(1) td(0) Yn VOD(H) 0V VOD(L) td(0) to td(6) Figure 4. SN65DSI83-Q1 LVDS Timing Definitions Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 11 SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 www.ti.com Parameter Measurement Information (continued) ULPS (LP00) State DSI lane ten tdis A_CLKP/N (LVDS_CHA_CLK) (1) See the ULPS section of the data sheet for the ULPS entry and exit sequence. (2) ULPS entry and exit protocol and timing requirements must be met according to the MIPI DPHY specification. Figure 5. ULPS Timing Definition 12 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 SN65DSI83-Q1 www.ti.com SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 8 Detailed Description 8.1 Overview The SN65DSI83-Q1 DSI to LVDS bridge device features a single-channel MIPI® D-PHY receiver front-end configuration with four lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to an LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a SingleLink LVDS with four data lanes per link. 8.2 Functional Block Diagram AVCC ERR AGND VCC ULPS LANE ERR MERGE GND LPRX DA0P DA0N 8 18 HSRX DATA LANE 0 18 LVDS SERIALIZER EOT DA1P DA1N DA2P DA2N DA3P DA3N DATA LANE 1 (Circuit same as DATA LANE 0) 8 DATA LANE 2 (Circuit same as DATA LANE 0) 8 DATA LANE 3 (Circuit same as DATA LANE 0) 8 32 DACN DSI PACKET PROCESSORS DE VS HS CHANNEL FORMATTER ULPS ULPS DACP SOT A_Y0P A_Y0N A_Y1P A_Y1N A_Y2P A_Y2N A_CLKP A_CLKN A_Y3P A_Y3N PARTIAL LPRX LPRX LVDSPLL PLL Lock HSRX HSRX CLOCK CIRCUITS PIXEL CLOCK CLK LANE PLL Lock Logic Clocks SCL CSR HS Clock Sourced M /N Pixel Clock PLL 2 LOCAL I2C CSR READ CSR WRITE SDA IRQ ADDR Clock Dividers Reset SN65DSI83-Q1 REFCLK EN RSVD1 RSVD2 8.3 Feature Description 8.3.1 Clock Configurations and Multipliers The LVDS clock may be derived from the DSI channel A clock, or from an external reference clock source. When the MIPI D-PHY channel A HS clock is used as the LVDS clock source, the D-PHY clock lane must operate in HS free-running (continuous) mode. This feature eliminates the need for an external reference clock reducing system costs. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 13 SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 www.ti.com Feature Description (continued) The reference clock source is selected by HS_CLK_SRC (CSR 0×0A.0) programmed through the local I2C interface. If an external reference clock is selected, it is multiplied by the factor in REFCLK_MULTIPLIER (CSR 0×0B.1:0) to generate the LVDS output clock. When an external reference clock is selected, it must be between 25 MHz and 154 MHz. If the DSI channel A clock is selected, it is divided by the factor in DSI_CLK_DIVIDER (CSR 0×0B.7:3) to generate the LVDS output clock. Additionally, LVDS_CLK_RANGE (CSR 0×0A.3:1) and CH_DSI_CLK_RANGE(CSR 0×12) must be set to the frequency range of the LVDS output clock and DSI Channel A input clock respectively for the internal PLL to operate correctly. After these settings are programmed, PLL_EN (CSR 0×0D.0) must be set to enable the internal PLL. 8.3.2 ULPS The SN65DSI83-Q1 device supports the MIPI defined ULPS. While the device is in the ULPS, the CSR registers are accessible via I2C interface. ULPS sequence must be issued to all active DSI CLK and, or DSI data lanes of the enabled DSI channels for the SN65DSI83-Q1 device to enter the ULPS. The following sequence must be followed to enter and exit the ULPS. 1. The host issues a ULPS entry sequence to all DSI CLK and data lanes enabled. 2. When the host is ready to exit the ULPS mode, the host issues a ULPS exit sequence to all DSI CLK and data lanes that need to be active in normal operation. 3. Wait for the PLL_LOCK bit (CSR 0×0A.7) to be set. 4. Set the SOFT_RESET bit (CSR 0×09.0). 5. Device resumes normal operation (that is, video streaming resumes on the panel). 8.3.3 LVDS Pattern Generation The SN65DSI83-Q1 device supports a pattern generation feature on LVDS channels. This feature can be used to test the LVDS output path and LVDS panels in a system platform. The pattern generation feature can be enabled by setting the CHA_TEST_PATTERN bit at address 0×3C. No DSI data is received while the pattern generation feature is enabled. There are three modes available for LVDS test pattern generation. The mode of test pattern generation is determined by register configuration, as shown in Table 1. Table 1. Video Registers ADDRESS BIT REGISTER NAME 0×20.7:0 CHA_ACTIVE_LINE_LENGTH_LOW 0×21.3:0 CHA_ACTIVE_LINE_LENGTH_HIGH 0×24.7:0 CHA_VERTICAL_DISPLAY_SIZE_LOW 0×25.3:0 CHA_VERTICAL_DISPLAY_SIZE_HIGH 0×2C.7:0 CHA_HSYNC_PULSE_WIDTH_LOW 0×2D.1:0 CHA_HSYNC_PULSE_WIDTH_HIGH 0×30.7:0 CHA_VSYNC_PULSE_WIDTH_LOW 0×31.1:0 CHA_VSYNC_PULSE_WIDTH_HIGH 0×34.7:0 CHA_HORIZONTAL_BACK_PORCH 0×36.7:0 CHA_VERTICAL_BACK_PORCH 0×38.7:0 CHA_HORIZONTAL_FRONT_PORCH 0×3A.7:0 CHA_VERTICAL_FRONT_PORCH 8.3.4 Reset Implementation When the EN pin is deasserted (low), the SN65DSI83-Q1 device is in SHUTDOWN or RESET state. In this state, CMOS inputs are ignored, the MIPI D-PHY inputs are disabled and outputs are high impedance. Transitioning the EN input from a low to a high level after the VCC supply has reached the minimum operating voltage as shown in Figure 6 is critical. This transition is achieved by a control signal to the EN input, or by an external capacitor connected between EN and GND. 14 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 SN65DSI83-Q1 www.ti.com SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 VCC 1.65 V EN tVCC ten Figure 6. Cold-Start VCC Ramp Up to EN When implementing the external capacitor, the size of the external capacitor depends on the power up ramp of the VCC supply, where a slower ramp-up results in a larger value external capacitor. Consider an approximately 200-nF capacitor as a reasonable first estimate for the size of the external capacitor. Figure 7 and Figure 8 show both EN implementations. VCC GPO EN C EN R(EN) = 200 kΩ C SN65DSI83-Q1 Controller SN65DSI83-Q1 Figure 7. External Capacitor Controlled EN Figure 8. EN Input from Active Controller When the SN65DSI83-Q1 is reset while VCC is high, the EN pin must be held low for at least 10 ms before being asserted high as described in Table 2 to be sure that the device is properly reset. The DSI CLK lane MUST be in HS and the DSI data lanes MUST be driven to LP11 while the device is in reset before the EN pin is asserted per the timing described in Table 2. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 15 SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 www.ti.com 8.3.5 Initialization Sequence Use the following initialization sequence to setup the SN65DSI83-Q1. This sequence is required for proper operation of the device. Steps 9 through 11 in the sequence are optional. Also see Figure 6. Table 2. Initialization Sequence INITIALIZATION SEQUENCE NUMBER INITIALIZATION SEQUENCE DESCRIPTION Init seq 1 Power on Init seq 2 After power is applied and stable, the DSI CLK lanes MUST be in HS state and the DSI data lanes MUST be driven to LP11 state Init seq 3 Set EN pin to Low Wait 10 ms (1) Init seq 4 Tie EN pin to High Wait 10 ms (1) Init seq 5 Initialize all CSR registers to their appropriate values based on the implementation (The SN65DSI8x is not functional until the CSR registers are initialized) Init seq 6 Set the PLL_EN bit (CSR 0x0D.0) Wait 10 ms (1) Init seq 7 Set the SOFT_RESET bit (CSR 0x09.0) Wait 10 ms (1) Init seq 8 Wait 5 ms Change DSI data lanes to HS state and start DSI video stream (1) Init seq 9 Read back all resisters and confirm they were correctly written Init seq 10 Wait 1 ms Init seq 11 (1) Write 0xFF to CSR 0xE5 to clear the error registers (1) Read CSR 0xE5. If CSR 0xE5!= 0x00, then go back to step #2 and re-initialize Minimum recommended delay. It is fine to exceed these. 8.3.6 LVDS Output Formats The SN65DSI83-Q1 device processes DSI packets and produces video data driven to the LVDS interface in an industry standard format. Single-Link LVDS is supported by the SN65DSI83-Q1 device. During conditions such as the default condition, and some video synchronization periods, where no video stream data is passing from the DSI input to the LVDS output, the SN65DSI83-Q1 device transmits zero value pixel data on the LVDS outputs while maintaining transmission of the vertical sync and horizontal sync status. Figure 9 illustrates a Single-Link LVDS 18-bpp application. Figure 10 illustrates a Single-Link 24-bpp application using Format 2, controlled by CHA_24BPP_FORMAT1 (CSR 0×18.1). In data Format 2, the two MSB per color are transferred on the Y3P/N LVDS lane. Figure 11 illustrates a 24-bpp Single-Link application using Format 1. In data Format 1, the two LSB per color are transferred on the Y3P/N LVDS lane. Figure 12 illustrates a Single-Link LVDS application where 24-bpp data is received from DSI and converted to 18 bpp data for transmission to an 18-bpp panel. This application is configured by setting CHA_24BPP_FORMAT1 (CSR 0×18.1) to 1 and CHA_24BPP_MODE (CSR 0×18.3) to 0. In this configuration, the SN65DSI83-Q1 device does not transmit the 2 LSB per color since the Y3P and Y3N LVDS lane is disabled. NOTE Figure 9, Figure 10, Figure 11, and Figure 12 only illustrate a few example applications for the SN65DSI83-Q1 device. Other applications are also supported. 16 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 SN65DSI83-Q1 www.ti.com SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 A_CLKP/N cycle ‘n-1’ cycle ‘n’ A_Y0P/N G0 R5 R4 R3 R2 R1 R0 A_Y1P/N B1 B0 G5 G4 G3 G2 G1 A_Y2P/N DE VS HS B5 B4 B3 B2 A_Y3P/N DE = Data Enable; A_Y3P/N are Output Low Figure 9. LVDS Output Data; Single-Link 18 bpp A_CLKP/N cycle ‘n-1’ cycle ‘n’ A_Y0P/N G0 R5 R4 R3 R2 R1 R0 A_Y1P/N B1 B0 G5 G4 G3 G2 G1 A_Y2P/N DE VS HS B5 B4 B3 B2 A_Y3P/N 0 B7 B6 G7 G6 R7 R6 DE = Data Enable Figure 10. LVDS Output Data (Format 2); Single-Link 24 bpp A_CLKP/N cycle ‘n-1’ cycle ‘n’ A_Y0P/N G2 R7 R6 R5 R4 R3 R2 A_Y1P/N B3 B2 G7 G6 G5 G4 G3 A_Y2P/N DE VS HS B7 B6 B5 B4 A_Y3P/N 0 B1 B0 G1 G0 R1 R0 DE = Data Enable Figure 11. LVDS Output Data (Format 1); Single-Link 24 bpp Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 17 SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 www.ti.com A_CLKP/N cycle ‘n-1’ cycle ‘n’ A_Y0P/N G2 R7 R6 R5 R4 R3 R2 A_Y1P/N B3 B2 G7 G6 G5 G4 G3 A_Y2P/N DE VS HS B7 B6 B5 B4 A_Y3P/N DE = Data Enable; A_Y3P and A_Y3N are output low; A_Y3P and A_Y3N are output low Figure 12. LVDS Output Data (Format 1); 24 bpp to Single-Link 18 bpp Conversion 8.3.7 DSI Lane Merging The SN65DSI83-Q1 supports four DSI data lanes per input channel, and may be configured to support one, two, or three DSI data lanes per channel. Unused DSI input pins on the SN65DSI83-Q1 must be left unconnected or driven to LP11 state.The bytes received from the data lanes are merged in HS mode to form packets that carry the video stream. DSI data lanes are bit and byte aligned. Figure 13 shows the lane merging function for each channel; 4-Lane, 3-Lane, and 2-Lane modes are illustrated. HS BYTES TRANSMITTED (n) IS INTEGER MULTIPLE OF 3 HS BYTES TRANSMITTED (n) IS INTEGER MULTIPLE OF 4 LANE 0 SOT BYTE 0 BYTE 4 BYTE 8 BYTE n-4 EOT LANE 0 SOT BYTE 0 BYTE 3 BYTE 6 BYTE n-3 EOT LANE 1 SOT BYTE 1 BYTE 5 BYTE 9 BYTE n-3 EOT LANE 1 SOT BYTE 1 BYTE 4 BYTE 7 BYTE n-2 EOT LANE 2 SOT BYTE 2 BYTE 6 BYTE 10 BYTE n-2 EOT LANE 2 SOT BYTE 2 BYTE 5 BYTE 8 BYTE n-1 EOT LANE 3 SOT BYTE 3 BYTE 7 BYTE 11 BYTE n-1 EOT HS BYTES TRANSMITTED (n) IS 1 LESS THAN INTEGER MULTIPLE OF 3 HS BYTES TRANSMITTED (n) IS 1 LESS THAN INTEGER MULTIPLE OF 4 LANE 0 SOT BYTE 0 BYTE 4 BYTE 8 BYTE n-3 EOT LANE 1 SOT BYTE 1 BYTE 5 BYTE 9 BYTE n-2 EOT LANE 2 SOT BYTE 2 BYTE 6 BYTE 10 BYTE n-1 EOT LANE 3 SOT BYTE 3 BYTE 7 BYTE 11 EOT LANE 0 SOT BYTE 0 BYTE 3 BYTE 6 BYTE n-2 EOT LANE 1 SOT BYTE 1 BYTE 4 BYTE 7 BYTE n-1 EOT LANE 2 SOT BYTE 2 BYTE 5 BYTE 8 EOT HS BYTES TRANSMITTED (n) IS 2 LESS THAN INTEGER MULTIPLE OF 3 HS BYTES TRANSMITTED (n) IS 2 LESS THAN INTEGER MULTIPLE OF 4 LANE 0 SOT BYTE 0 BYTE 4 BYTE 8 BYTE n-2 EOT LANE 1 SOT BYTE 1 BYTE 5 BYTE 9 BYTE n-1 EOT LANE 2 SOT BYTE 2 BYTE 6 BYTE 10 EOT LANE 3 SOT BYTE 3 BYTE 7 BYTE 11 EOT LANE 0 SOT BYTE 0 BYTE 3 BYTE 6 BYTE n-1 LANE 1 SOT BYTE 1 BYTE 4 BYTE 7 EOT LANE 2 SOT BYTE 2 BYTE 5 BYTE 8 EOT 3 DSI Data Lane Configuration HS BYTES TRANSMITTED (n) IS INTEGER MULTIPLE OF 2 HS BYTES TRANSMITTED (n) IS 3 LESS THAN INTEGER MULTIPLE OF 4 LANE 0 SOT BYTE 0 BYTE 4 BYTE 8 BYTE n-1 LANE 1 SOT BYTE 1 BYTE 5 BYTE 9 EOT LANE 2 SOT BYTE 2 BYTE 6 BYTE 10 EOT LANE 3 SOT BYTE 3 BYTE 7 BYTE 11 EOT 4 DSI Data Lane Configuration (default) EOT EOT LANE 0 SOT BYTE 0 BYTE 2 BYTE 4 BYTE n-2 EOT LANE 1 SOT BYTE 1 BYTE 3 BYTE 5 BYTE n-1 EOT HS BYTES TRANSMITTED (n) IS 1 LESS THAN INTEGER MULTIPLE OF 2 LANE 0 SOT BYTE 0 BYTE 2 BYTE 4 BYTE n-1 LANE 1 SOT BYTE 1 BYTE 3 BYTE 5 EOT EOT 2 DSI Data Lane Configuration Figure 13. SN65DSI83-Q1 DSI Lane Merging Illustration 18 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 SN65DSI83-Q1 www.ti.com SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 8.3.8 DSI Pixel Stream Packets The SN65DSI83-Q1 processes 18-bpp (RGB666) and 24-bpp (RGB888) DSI packets as shown in Figure 14, Figure 15, and Figure 16. 2 Bytes DATA TYPE (0x2E) VIRTUAL CHANNEL 1 Byte 1 Byte WORD COUNT WORD COUNT Bytes 18 bpp Loosely Packed Pixel Stream ECC CRC CHECKSUM (Variable Size Payload) Packet Payload Packet Header 1 Byte 01 2 Bytes 1 Byte 1 Byte 1 Byte 1 Byte Packet Footer 1 Byte 1 Byte 1 Byte 1 Byte 2 7 2 7 2 7 2 7 2 7 2 7 2 7 2 7 2 7 R0 R5 G0 G5 B0 B5 R0 R5 G0 G5 B0 B5 R0 R5 G0 G5 B0 B5 6-bits RED 6-bits GREEN 6-bits BLUE 6-bits RED First Pixel in Packet 6-bits GREEN 6-bits BLUE 6-bits RED 6-bits GREEN Second Pixel in Packet 6-bits BLUE Third Pixel in Packet Variable Size Payload (Three Pixels Per Nine Bytes of Payload) Figure 14. 18-bpp (Loosely Packed) DSI Packet Structure 2 Bytes DATA TYPE (0x1E) VIRTUAL CHANNEL 1 Byte 1 Byte WORD COUNT WORD COUNT Bytes 18 bpp Packed Pixel Stream ECC 0 R0 5 Packet Payload 1 Byte 6 7 0 R5 G0 6-bits RED CRC CHECKSUM (Variable Size Payload) Packet Header 1 Byte 2 Bytes 3 4 G5 B 0 6-bits GREEN First Pixel in Packet 1 Byte 7 01 2 7 B 5 R0 6-bits BLUE 1 Byte 0 5 R5 G0 6-bits RED 1 Byte 6 7 0 G5 B 0 6-bits GREEN Second Pixel in Packet 3 4 B 5 R0 6-bits BLUE Packet Footer 1 Byte 7 01 2 7 R5 G0 6-bits RED 1 Byte 0 G5 B 0 6-bits GREEN 5 1 Byte 6 7 0 B 5 R0 6-bits BLUE 3 4 7 01 R5 G0 6-bits RED Third Pixel in Packet 1 Byte 2 G5 B 0 6-bits GREEN 7 B5 6-bits BLUE Fourth Pixel in Packet Variable Size Payload (Four Pixels Per Nine Bytes of Payload) Figure 15. 18-bpp (Tightly Packed) DSI Packet Structure Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 19 SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 2 Bytes DATA TYPE (0x3E) VIRTUAL CHANNEL 1 Byte www.ti.com 1 Byte WORD COUNT WORD COUNT Bytes 24 bpp Packed Pixel Stream ECC CRC CHECKSUM (Variable Size Payload) Packet Payload Packet Header 1 Byte 1 Byte 0 7 0 R0 R7 G0 8-bits RED 2 Bytes 1 Byte 7 0 7 G 7 B0 8-bits GREEN 1 Byte B7 8-bits BLUE 1 Byte 0 7 0 R0 R7 G0 8-bits RED First Pixel in Packet Packet Footer 1 Byte 7 0 7 G 7 B0 8-bits GREEN 1 Byte B7 0 7 R0 8-bits BLUE 1 Byte R7 8-bits RED Second Pixel in Packet 1 Byte 0 7 G0 G7 B 0 0 8-bits GREEN 7 B7 8-bits BLUE Third Pixel in Packet Variable Size Payload (Three Pixels Per Nine Bytes of Payload) Figure 16. 24-bpp DSI Packet Structure 8.3.9 DSI Video Transmission Specifications The SN65DSI83-Q1 supports burst video mode and non-burst video mode with sync events or with sync pulses packet transmission as described in the DSI specification. The burst mode supports time-compressed pixel stream packets that leave added time per scan line for power savings LP mode. The SN65DSI83-Q1 requires a transition to LP mode once per frame to enable PHY synchronization with the DSI host processor; however, for a robust and low-power implementation, the transition to LP mode is recommended on every video line. Figure 17 shows the DSI video transmission applied to SN65DSI83-Q1 applications. In all applications, the LVDS output rate must be less than or equal to the DSI input rate. The first line of a video frame shall start with a VSS packet, and all other lines start with VSE or HSS. The position of the synchronization packets in time is of utmost importance since this has a direct impact on the visual performance of the display panel; that is, these packets generate the HS and VS (horizontal and vertical sync) signals on the LVDS interface after the delay programmed into CHA_SYNC_DELAY_LOW/HIGH (CSR 0×28.7:0 and 0×29.3:0). As required in the DSI specification, the SN65DSI83-Q1 requires that pixel stream packets contain an integer number of pixels (i.e. end on a pixel boundary); it is recommended to transmit an entire scan line on one pixel stream packet. When a scan line is broken in to multiple packets, inter-packet latency shall be considered such that the video pipeline (ie. pixel queue or partial line buffer) does not run empty (i.e. under-run); during scan line processing, if the pixel queue runs empty, the SNDSI83-Q1 transmits zero data (18’b0 or 24’b0) on the LVDS interface. NOTE When the HS clock is used as a source for the LVDS pixel clock, the LP mode transitions apply only to the data lanes, and the DSI clock lane remains in the HS mode during the entire video transmission. The SN65DSI83-Q1 does not support the DSI Virtual Channel capability or reverse direction (peripheral to processor) transmissions. 20 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 SN65DSI83-Q1 www.ti.com SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 One Video Frame NOP/ ... LP RGB Vertical sync / blanking t W (HS ) HS NOP/ LP DSI Channel(s) NOP/ LP NOP/ LP HSS t LINE NOP/ LP RGB ... t W(HS) (1) HS (1) t PD HS (1) t PD VS (2) VS (2) VS DE (3) DE (3) DE (3) DATA ... Active Video Line LVDS Transfer Function HSS DSI Channel A NOP/ LP Vertical sync / blanking t LINE HSS VSS t LINE NOP/ LP NOP/ LP Active Lines Vertical Blanking Period LVDS Transfer Function DSI Channel A RGB t LINE HSS NOP/ LP t LINE HSS ... t LINE HSS NOP/ LP NOP/ LP HSS NOP/ LP t LINE NOP/ LP HSS VSS DSI Channel A t LINE HSS t LINE t LINE 0x000 DATA 0x000 (2) 0x000 DATA PixelStream Data 0x000 (4) LEGEND (1) The assertion of HS is delayed (t PD) by a programmable number of pixel clocks from the last bit of VSS/HSS packet received on DSI. The HS pulse width (tW(HS) ) is also programmable. The illustration shows HS active low. (2) VS is signaled for a programmable number of lines (tLINE ) and is asserted when HS is asserted for the first line of the frame . VS is de -asserted when HS is asserted after the number of lines programmed has been reached. The illustration shows VS active low VSS DSI Sync Event Packet: V Sync Start HSS DSI Sync Event Packet: H Sync Start RGB A sequence of DSI Pixel Stream Packets and Null Packets NOP/LP DSI Null Packet , Blanking Packet , or a transition to LP Mode (3) DE is asserted when active pixel data is transmitted on LVDS , and polarity is set independent to HS/VS. The illustration shows DE active high (4) After the last pixel in an active line is output to LVDS, the LVDS data is output zero Figure 17. DSI Channel Transmission and Transfer Function 8.4 Programming 8.4.1 Local I2C Interface Overview The SN65DSI83-Q1 device local I2C interface is enabled when EN is input high, access to the CSR registers is supported during ULPS. The SCL and SDA pins are used for I2C clock and I2C data respectively. The SN65DSI83-Q1 device I2C interface conforms to the 2-wire serial interface defined by the I2C Bus Specification, Version 2.1 (January 2000) and supports fast mode transfers up to 400 kbps. The device address byte is the first byte received following the start condition from the master device. The 7-bit device address for SN65DSI83-Q1 device is factory preset to 010110X with the least significant bit being determined by the ADDR control input. Table 3 clarifies the SN65DSI83-Q1 device target address. Table 3. SN65DSI83-Q1 I2C Target Address Description (1) (2) BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (W/R) 0 1 0 1 1 0 ADDR 0/1 (1) (2) When ADDR = 1, Address cycle is 0×5A (write) and 0×5B (read) When ADDR = 0, Address cycle is 0×58 (write) and 0×59 (read) Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 21 SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 www.ti.com The following procedure is followed to write to the SN65DSI83-Q1 device I2C registers: 1. The master initiates a write operation by generating a start condition (S), followed by the SN65DSI83-Q1 device 7-bit address and a zero-value W/R bit to indicate a write cycle. 2. The SN65DSI83-Q1 device acknowledges the address cycle. 3. The master presents the subaddress (I2C register within SN65DSI83-Q1 device) to be written, consisting of one byte of data, MSB-first. 4. The SN65DSI83-Q1 device acknowledges the subaddress cycle. 5. The master presents the first byte of data to be written to the I2C register. 6. The SN65DSI83-Q1 device acknowledges the byte transfer. 7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the SN65DSI83-Q1 device. 8. The master terminates the write operation by generating a stop condition (P). The following procedure is followed to read the SN65DSI83-Q1 I2C registers: 1. The master initiates a read operation by generating a start condition (S), followed by the SN65DSI83-Q1 device 7-bit address and a one-value W/R bit to indicate a read cycle. 2. The SN65DSI83-Q1 device acknowledges the address cycle. 3. The SN65DSI83-Q1 device transmits the contents of the memory registers MSB-first starting at register 00h. If a write to the SN65DSI83-Q1 I2C register occurred prior to the read, then the SN65DSI83-Q1 device starts at the subaddress specified in the write. 4. The SN65DSI83-Q1 device waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I2C master acknowledges reception of each data byte transfer. 5. If an ACK is received, the SN65DSI83-Q1 device transmits the next byte of data. 6. The master terminates the read operation by generating a stop condition (P). The following procedure is followed for setting a starting subaddress for I2C reads: 1. The master initiates a write operation by generating a start condition (S), followed by the SN65DSI83-Q1 device 7-bit address and a zero-value W/R bit to indicate a write cycle. 2. The SN65DSI83-Q1 device acknowledges the address cycle. 3. The master presents the subaddress (I2C register within the SN65DSI83-Q1 device) to be written, consisting of one byte of data, MSB first. 4. The SN65DSI83-Q1 device acknowledges the subaddress cycle. 5. The master terminates the write operation by generating a stop condition (P). 22 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 SN65DSI83-Q1 www.ti.com SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 8.5 Register Maps 8.5.1 Control and Status Registers Overview Many of the SN65DSI83-Q1 functions are controlled by the Control and Status Registers (CSR). All CSR registers are accessible through the local I2C interface. See the following tables for the SN65DSI83-Q1 CSR descriptions. Reserved or undefined bit fields should not be modified. Otherwise, the device may operate incorrectly. 8.5.1.1 CSR Bit Field Definitions – ID Registers 8.5.1.1.1 Registers 0x00 – 0x08 Figure 18. Registers 0x00 – 0x08 7 6 5 4 3 2 1 0 Reserved R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4. Registers 0x00 – 0x08 Field Descriptions Bit Field Type 7-0 Reserved R Reset Description Reserved Addresses 0x08 - 0x00 = {0x01, 0x20, 0x20, 0x20, 0x44, 0x53, 0x49, 0x38, 0x35} 8.5.1.2 CSR Bit Field Definitions – Reset and Clock Registers 8.5.1.2.1 Register 0x09 Figure 19. Register 0x09 7 6 5 4 Reserved R 3 2 1 0 SOFT_RESET W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 5. Register 0x09 Field Descriptions Bit Field Type 7-1 Reserved R SOFT_RESET W 0 Reset Description Reserved 0 This bit automatically clears when set to ‘1’ and returns zeros when read. This bit must be set after the CSR’s are updated. This bit must also be set after making any changes to the DIS clock rate or after changing between DSI burst and non-burst modes. 0 – No action (default) 1 – Reset device to default condition excluding the CSR bits. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 23 SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 www.ti.com 8.5.1.2.2 Register 0x0A Figure 20. Register 0x0A 7 PLL_EN_STAT R 6 5 Reserved R 4 3 2 LVDS_CLK_RANGE R/W 1 0 HS_CLK_SRC R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6. Register 0x0A Field Descriptions Bit Field Type Reset Description PLL_EN_STAT R 0 0 – PLL not enabled (default) 1 – PLL enabled Note: After PLL_EN_STAT = 1, wait at least 3ms for PLL to lock. 6-4 Reserved R 3-1 LVDS_CLK_RANGE R/W 101 This field selects the frequency range of the LVDS output clock. 000 – 25 MHz ≤ LVDS_CLK < 37.5 MHz 001 – 37.5 MHz ≤ LVDS_CLK < 62.5 MHz 010 – 62.5 MHz ≤ LVDS_CLK < 87.5 MHz 011 – 87.5 MHz ≤ LVDS_CLK < 112.5 MHz 100 – 112.5 MHz ≤ LVDS_CLK < 137.5 MHz 101 – 137.5 MHz ≤ LVDS_CLK ≤ 154 MHz (default) 110 – Reserved 111 – Reserved HS_CLK_SRC R/W 0 0 – LVDS pixel clock derived from input REFCLK (default) 1 – LVDS pixel clock derived from MIPI D-PHY channel A HS continuous clock 7 0 8.5.1.2.3 Register 0x0B Figure 21. Register 0x0B 7 6 5 DSI_CLK_DIVIDER R/W 4 3 2 Reserved R 1 0 REFCLK_MULTIPLIER R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7. Register 0x0B Field Descriptions Bit Field Type Reset Description 7-3 DSI_CLK_DIVIDER R/W 00000 When CSR 0x0A.0 = ‘1’, this field controls the divider used to generate the LVDS output clock from the MIPI D-PHY Channel A HS continuous clock. When CSR 0x0A.0 = ‘0’, this field must be programmed to 00000. 00000 – LVDS clock = source clock (default) 00001 – Divide by 2 00010 – Divide by 3 00011 – Divide by 4 • • • 10111 – Divide by 24 11000 – Divide by 25 11001 through 11111 – Reserved Reserved R REFCLK_MULTIPLIER R/W 00 When CSR 0x0A.0 = ‘0’, this field controls the multiplier used to generate the LVDS output clock from the input REFCLK. When CSR 0x0A.0 = ‘1’, this field must be programmed to 00. 00 – LVDS clock = source clock (default) 01 – Multiply by 2 10 – Multiply by 3 11 – Multiply by 4 2 1-0 24 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 SN65DSI83-Q1 www.ti.com SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 8.5.1.2.4 Register 0x0D Figure 22. Register 0x0D 7 6 5 4 Reserved R 3 2 1 0 PLL_EN R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8. Register 0x0D Field Descriptions Bit Field Type 7-1 Reserved R 0 PLL_EN R/W Reset Description Reserved 0 When this bit is set, the PLL is enabled with the settings programmed into CSR 0x0A and CSR 0x0B. The PLL should be disabled before changing any of the settings in CSR 0x0A and CSR 0x0B. The input clock source must be active and stable before the PLL is enabled. 0 – PLL disabled (default) 1 – PLL enabled 8.5.1.3 CSR Bit Field Definitions – DSI Registers 8.5.1.3.1 Register 0x10 Figure 23. Register 0x10 7 6 Reserved 5 4 3 CHA_DSI_LANES R 2 R/W 1 Reserved 0 SOT_ERR_TO L_DIS R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 9. Register 0x10 Field Descriptions Bit Field Type 7-5 Reserved R 4-3 CHA_DSI_LANES R/W 2-1 Reserved R SOT_ERR_TOL_DIS R/W 0 Reset Description Reserved 11 This field controls the number of lanes that are enabled for DSI Channel A. 00 – Four lanes are enabled 01 – Three lanes are enabled 10 – Two lanes are enabled 11 – One lane is enabled (default) Note: Unused DSI input pins on the SN65DSI83-Q1 should be left unconnected. Reserved 0 0 – Single bit errors are tolerated for the start of transaction SoT leader sequence (default) 1 – No SoT bit errors are tolerated Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 25 SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 www.ti.com 8.5.1.3.2 Register 0x11 Figure 24. Register 0x11 7 6 CHA_DSI_DATA_EQ R/W 5 4 3 2 CHA_DSI_CLK_EQ R/W Reserved R 1 0 Reserved R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 10. Register 0x11 Field Descriptions Bit Field Type Reset Description 7-6 CHA_DSI_DATA_EQ R/W 00 This field controls the equalization for the DSI Channel A Data Lanes 00 – No equalization (default) 01 – 1 dB equalization 10 – Reserved 11 – 2 dB equalization 5-4 Reserved R 3-2 CHA_DSI_CLK_EQ R/W 1-0 Reserved R Reserved 00 This field controls the equalization for the DSI Channel A Clock 00 – No equalization (default) 01 – 1 dB equalization 10 – Reserved 11 – 2 dB equalization Reserved 8.5.1.3.3 Register 0x12 Figure 25. Register 0x12 7 6 5 4 3 CHA_DSI_CLK_RANGE R/W 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 11. Register 0x12 Field Descriptions 26 Bit Field Type Reset Description 7-0 CHA_DSI_CLK_RANGE R/W 0 This field specifies the DSI Clock frequency range in 5 MHz increments for the DSI Channel A Clock 0x00 through 0x07 – Reserved 0x08 – 40 ≤ frequency < 45 MHz 0x09 – 45 ≤ frequency < 50 MHz ... 0x63 – 495 ≤ frequency < 500 MHz 0x64 – 500 MHz 0x65 through 0xFF – Reserved Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 SN65DSI83-Q1 www.ti.com SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 8.5.1.4 CSR Bit Field Definitions – LVDS Registers 8.5.1.4.1 Register 0x18 Figure 26. Register 0x18 7 DE_NEG_POL ARITY R/W 6 HS_NEG_POL ARITY R/W 5 VS_NEG_POL ARITY R/W 4 Reserved R 3 CHA_24BPP_ MODE R/W 2 Reserved R 1 CHA_24BPP_F ORMAT1 R/W 0 Reserved R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 12. Register 0x18 Field Descriptions Bit Field Type Reset Description 7 DE_NEG_POLARITY R/W 0 0 – DE is positive polarity driven ‘1’ during active pixel transmission on LVDS (default) 1 – DE is negative polarity driven ‘0’ during active pixel transmission on LVDS 6 HS_NEG_POLARITY R/W 1 0 – HS is positive polarity driven ‘1’ during corresponding sync conditions 1 – HS is negative polarity driven ‘0’ during corresponding sync (default) 5 VS_NEG_POLARITY R/W 1 0 – VS is positive polarity driven ‘1’ during corresponding sync conditions 1 – VS is negative polarity driven ‘0’ during corresponding sync (default) 4 Reserved R 3 CHA_24BPP_MODE R/W 2 Reserved R 1 CHA_24BPP_FORMAT1 R/W 0 Reserved R Reserved. Do not write to this filed. Must remain at default. 0 0 – Force 18bpp; LVDS channel A lane 4 (A_Y3P/N) is disabled (default) 1 – Force 24bpp; LVDS channel A lane 4 (B_Y3P/N) is enabled Reserved. Do not write to this filed. Must remain at default. 0 This field selects the 24bpp data format 0 – LVDS channel A lane A_Y3P/N transmits the 2 most significant bits (MSB) per color; Format 2 (default) 1 – LVDS channel B lane A_Y3P/N transmits the 2 least significant bits (LSB) per color; Format 1 Note1: This field must be ‘0’ when 18bpp data is received from DSI. Note2: If this field is set to ‘1’ and CHA_24BPP_MODE is ‘0’, the SN65DSI83-Q1 will convert 24bpp data to 18bpp data for transmission to an 18bpp panel. In this configuration, the SN65DSI83-Q1 will not transmit the 2 LSB per color on LVDS channel A, because LVDS channel A lane A_Y3P/N is disabled. Reserved. Do not write to this filed. Must remain at default. 8.5.1.4.2 Register 0x19 Figure 27. Register 0x19 7 Reserved R 6 CHA_LVDS_V OCM R/W 5 Reserved 4 3 2 CHA_LVDS_VOD_SWING R R/W 1 0 Reserved R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 27 SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 www.ti.com Table 13. Register 0x19 Field Descriptions Bit Field Type 7 Reserved R 6 CHA_LVDS_VOCM R/W 5-4 Reserved R 3-2 CHA_LVDS_VOD_SWING R/W 1-0 Reserved R Reset Description Reserved. Do not write to this filed. Must remain at default. 0 This field controls the common mode output voltage for LVDS Channel A 0 – 1.2V (default) 1 – 0.9V (CSR 0x1B.5:4 CHA_LVDS_CM_ADJUST must be set to ‘01b’) Reserved. Do not write to this filed. Must remain at default. 01 This field controls the differential output voltage for LVDS Channel A. See the Electrical Characteristics table for |VOD| for each setting: 00, 01 (default), 10, 11. Reserved. Do not write to this filed. Must remain at default. 8.5.1.4.3 Register 0x1A Figure 28. Register 0x1A 7 6 Reserved R 5 CHA_REVERS E_LVDS R/W 4 3 Reserved 2 R 1 CHA_LVDS_TE RM R/W 0 Reserved R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 14. Register 0x1A Field Descriptions Bit Field Type 7-6 Reserved R CHA_REVERSE_LVDS R/W 5 Reset Description Reserved. Do not write to this filed. Must remain at default. 0 This bit controls the order of the LVDS pins for Channel A. 0 – Normal LVDS Channel A pin order. LVDS Channel A pin order is the same as listed in the Terminal Assignments Section. (default) 1 – Reversed LVDS Channel A pin order. LVDS Channel A pin order is remapped as follows: • • • • • • • • • • 4-2 28 Reserved R 1 CHA_LVDS_TERM R/W 0 Reserved R A_Y0P → A_Y3P A_Y0N → A_Y3N A_Y1P → A_CLKP A_Y1N → A_CLKN A_Y2P → A_Y2P A_Y2N → A_Y2N A_CLKP → A_Y1P A_CLKN → A_Y1N A_Y3P → A_Y0P A_Y3N → A_Y0N Reserved. Do not write to this filed. Must remain at default. 1 This bit controls the near end differential termination for LVDS Channel A. This bit also affects the output voltage for LVDS Channel A. 0 – 100Ω differential termination 1 – 200Ω differential termination (default) Reserved. Do not write to this filed. Must remain at default. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 SN65DSI83-Q1 www.ti.com SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 8.5.1.4.4 Register 0x1B Figure 29. Register 0x1B 7 6 Reserved R 5 4 CHA_LVDS_CM_ADJUST R/W 3 2 1 0 Reserved R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 15. Register 0x1B Field Descriptions Bit Field Type 7-6 Reserved R 5-4 CHA_LVDS_CM_ADJUST R/W 3-0 Reserved R Reset Description Reserved 00 This field can be used to adjust the common mode output voltage for LVDS Channel A. 00 – No change to common mode voltage (default) 01 – Adjust common mode voltage down 3% 10 – Adjust common mode voltage up 3% 11 – Adjust common mode voltage up 6% Reserved Note for all video registers: 1. TEST PATTERN GENERATION PURPOSE ONLY registers are for test pattern generation use only. Others are for normal operation unless the test pattern generation feature is enabled. 8.5.1.5 CSR Bit Field Definitions – Video Registers 8.5.1.5.1 Register 0x20 Figure 30. Register 0x20 7 6 5 4 3 CHA_ACTIVE_LINE_LENGTH_LOW R/W 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 16. Register 0x20 Field Descriptions Bit Field Type Reset Description 7-0 CHA_ACTIVE_LINE_LENGTH_LO W R/W 0 This field controls the length in pixels of the active horizontal line line that are received on DSI Channel A and output to LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). The value in this field is the lower 8 bits of the 12-bit value for the horizontal line length. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 29 SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 www.ti.com 8.5.1.5.2 Register 0x21 Figure 31. Register 0x21 7 6 5 4 3 Reserved R 2 1 CHA_ACTIVE_LINE_LENGTH_HIGH R/W 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 17. Register 0x21 Field Descriptions Bit Field Type 7-4 Reserved R 3-0 CHA_ACTIVE_LINE_LENGTH_HIG H R/W Reset Description Reserved 0 This field controls the length in pixels of the active horizontal line that are received on DSI Channel A and output to LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). The value in this field is the upper 4 bits of the 12-bit value for the horizontal line length. 8.5.1.5.3 Register 0x24 Figure 32. Register 0x24 7 6 5 4 3 CHA_VERTICAL_DISPLAY_SIZE_LOW R/W 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18. Register 0x24 Field Descriptions Bit Field 7-0 CHA_VERTICAL_DISPLAY_SIZE_L R/W OW Type Reset Description 0 TEST PATTERN GENERATION PURPOSE ONLY. This field controls the vertical display size in lines for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0. The value in this field is the lower 8 bits of the 12-bit value for the vertical display size. 8.5.1.5.4 Register 0x25 Figure 33. Register 0x25 7 6 5 4 3 Reserved R 2 1 CHA_VERTICAL_DISPLAY_SIZE_HIGH R/W 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 19. Register 0x25 Field Descriptions Bit Field Type 7-4 Reserved R 3-0 CHA_VERTICAL_DISPLAY_SIZE_ HIGH R/W Reset Description Reserved 0 TEST PATTERN GENERATION PURPOSE ONLY. This field controls the vertical display size in lines for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). The value in this field is the upper 4 bits of the 12-bit value for the vertical display size 8.5.1.5.5 Register 0x28 30 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 SN65DSI83-Q1 www.ti.com SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 Figure 34. Register 0x28 7 6 5 4 3 CHA_SYNC_DELAY_LOW R/W 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 20. Register 0x28 Field Descriptions Bit Field Type Reset Description 7-0 CHA_SYNC_DELAY_LOW R/W 0 This field controls the delay in pixel clocks from when an HSync or VSync is received on the DSI to when it is transmitted on the LVDS interface for Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). The delay specified by this field is in addition to the pipeline and synchronization delays in the SN65DSI83-Q1. The additional delay is approximately 10 pixel clocks. The Sync delay must be programmed to at least 32 pixel clocks to ensure proper operation. The value in this field is the lower 8 bits of the 12-bit value for the Sync delay. 8.5.1.5.6 Register 0x29 Figure 35. Register 0x29 7 6 5 4 3 Reserved R 2 1 CHA_SYNC_DELAY_HIGH R/W 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 21. Register 0x29 Field Descriptions Bit Field Type 7-4 Reserved R 3-0 CHA_SYNC_DELAY_HIGH R/W Reset Description Reserved 0 This field controls the delay in pixel clocks from when an HSync or VSync is received on the DSI to when it is transmitted on the LVDS interface for Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). The delay specified by this field is in addition to the pipeline and synchronization delays in the SN65DSI83-Q1. The additional delay is approximately 10 pixel clocks. The Sync delay must be programmed to at least 32 pixel clocks to ensure proper operation. The value in this field is the upper 4 bits of the 12-bit value for the Sync delay. 8.5.1.5.7 Register 0x2C Figure 36. Register 0x2C 7 6 5 4 3 CHA_HSYNC_PULSE_WIDTH_LOW R/W 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 22. Register 0x2C Field Descriptions Bit Field Type Reset Description 7-0 CHA_HSYNC_PULSE_WIDTH_LO W R/W 0 This field controls the width in pixel clocks of the HSync Pulse Width for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). The value in this field is the lower 8 bits of the 10-bit value for the HSync Pulse Width. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 31 SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 www.ti.com 8.5.1.5.8 Register 0x2D Figure 37. Register 0x2D 7 6 5 4 3 2 Reserved R 1 0 CHA_HSYNC_PULSE_WIDTH_ HIGH R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 23. Register 0x2D Field Descriptions Bit Field Type 7-2 Reserved R 1-0 CHA_HSYNC_PULSE_WIDTH_HIG R/W H Reset Description Reserved 0 This field controls the width in pixel clocks of the HSync Pulse Width for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). The value in this field is the upper 2 bits of the 10-bit value for the HSync Pulse Width. 8.5.1.5.9 Register 0x30 Figure 38. Register 0x30 7 6 5 4 3 CHA_VSYNC_PULSE_WIDTH_LOW R/W 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 24. Register 0x30 Field Descriptions Bit Field Type Reset Description 7-0 CHA_VSYNC_PULSE_WIDTH_LO W R/W 0 This field controls the length in lines of the VSync Pulse Width for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). The value in this field is the lower 8 bits of the 10-bit value for the VSync Pulse Width. 8.5.1.5.10 Register 0x31 Figure 39. Register 0x31 7 6 5 4 3 2 Reserved R 1 0 CHA_VSYNC_PULSE_WIDTH_ HIGH R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 25. Register 0x31 Field Descriptions Bit Field Type 7-2 Reserved R 1-0 CHA_VSYNC_PULSE_WIDTH_HIG R/W H Reset Description Reserved 0 This field controls the length in lines of the VSync Pulse Width for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). The value in this field is the upper 2 bits of the 10-bit value for the VSync Pulse Width. 8.5.1.5.11 Register 0x34 32 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 SN65DSI83-Q1 www.ti.com SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 Figure 40. Register 0x34 7 6 5 4 3 CHA_HORIZONTAL_BACK_PORCH R/W 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 26. Register 0x34 Field Descriptions Bit Field Type Reset Description 7-0 CHA_HORIZONTAL_BACK_PORC H R/W 0 This field controls the time in pixel clocks between the end of the HSync Pulse and the start of the active video data for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). 8.5.1.5.12 Register 0x36 Figure 41. Register 0x36 7 6 5 4 3 CHA_VERTICAL_BACK_PORCH R/W 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 27. Register 0x36 Field Descriptions Bit Field Type Reset Description 7-0 CHA_VERTICAL_BACK_PORCH R/W 0 TEST PATTERN GENERATION PURPOSE ONLY. This field controls the number of lines between the end of the VSync Pulse and the start of the active video data for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). 8.5.1.5.13 Register 0x38 Figure 42. Register 0x38 7 6 5 4 3 CHA_HORIZONTAL_FRONT_PORCH R/W 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 28. Register 0x38 Field Descriptions Bit Field Type Reset Description 7-0 CHA_HORIZONTAL_FRONT_POR CH R/W 0 TEST PATTERN GENERATION PURPOSE ONLY. This field controls the time in pixel clocks between the end of the active video data and the start of the HSync Pulse for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 33 SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 www.ti.com 8.5.1.5.14 Register 0x3A Figure 43. Register 0x3A 7 6 5 4 3 CHA_VERTICAL_FRONT_PORCH R/W 2 1 0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 29. Register 0x3A Field Descriptions Bit Field Type Reset Description 7-0 CHA_VERTICAL_FRONT_PORCH R/W 0 TEST PATTERN GENERATION PURPOSE ONLY. This field controls the number of lines between the end of the active video data and the start of the VSync Pulse for LVDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). 8.5.1.5.15 Register 0x3C Figure 44. Register 0x3C 7 6 Reserved 5 4 CHA_TEST_PA TTERN R/W R 3 2 1 0 Reserved R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 30. Register 0x3C Field Descriptions Bit Field Type 7-5 Reserved R CHA_TEST_PATTERN R/W Reserved R 4 3-0 Reset Description Reserved 0 TEST PATTERN GENERATION PURPOSE ONLY. When this bit is set, the SN65DSI83-Q1 will generate a video test pattern based on the values programmed into the Video Registers for LDS Channel A in single LVDS Channel mode(CSR 0x18.4=1), Channel A and B in dual LVDS Channel mode(CSR 0x18.4=0). Reserved 8.5.1.6 CSR Bit Field Definitions – IRQ Registers 8.5.1.6.1 Register 0xE0 Figure 45. Register 0xE0 7 6 5 4 Reserved R 3 2 1 0 IRQ_EN R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 31. Register 0xE0 Field Descriptions 34 Bit Field Type 7-1 Reserved R 0 IRQ_EN R/W Reset Description Reserved 0 When enabled by this field, the IRQ output is driven high to communicate IRQ events. 0 – IRQ output is high-impedance (default) 1 – IRQ output is driven high when a bit is set in registers 0xE5 that also has the corresponding IRQ_EN bit set to enable the interrupt condition Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 SN65DSI83-Q1 www.ti.com SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 8.5.1.6.2 Register 0xE1 Figure 46. Register 0xE1 7 CHA_SYNCH_ ERR_EN R/W 6 CHA_CRC_ER R_EN R/W 5 CHA_UNC_EC C_ERR_EN R/W 4 3 2 CHA_COR_EC CHA_LLP_ERR CHA_SOT_BIT C_ERR_EN _EN _ERR_EN R/W R/W R/W 1 Reserved R 0 PLL_UNLOCK_ EN R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 32. Register 0xE1 Field Descriptions Bit Field Type Reset Description 7 CHA_SYNCH_ERR_EN R/W 0 0 – CHA_SYNCH_ERR is masked 1 – CHA_SYNCH_ERR is enabled to generate IRQ events 6 CHA_CRC_ERR_EN R/W 0 0 – CHA_CRC_ERR is masked 1 – CHA_CRC_ERR is enabled to generate IRQ events 5 CHA_UNC_ECC_ERR_EN R/W 0 0 – CHA_UNC_ECC_ERR is masked 1 – CHA_UNC_ECC_ERR is enabled to generate IRQ events 4 CHA_COR_ECC_ERR_EN R/W 0 0 – CHA_COR_ECC_ERR is masked 1 – CHA_COR_ECC_ERR is enabled to generate IRQ events 3 CHA_LLP_ERR_EN R/W 0 0 – CHA_LLP_ERR is masked 1 – CHA_ LLP_ERR is enabled to generate IRQ events 2 CHA_SOT_BIT_ERR_EN R/W 0 0 – CHA_SOT_BIT_ERR is masked 1 – CHA_SOT_BIT_ERR is enabled to generate IRQ events 1 Reserved R 0 PLL_UNLOCK_EN R/W Reserved 0 0 – PLL_UNLOCK is masked 1 – PLL_UNLOCK is enabled to generate IRQ events Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 35 SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 www.ti.com 8.5.1.6.3 Register 0xE5 Figure 47. Register 0xE5 7 CHA_SYNCH_ ERR R/W 6 CHA_CRC_ER R R/W 5 CHA_UNC_EC C_ERR R/W 4 3 2 CHA_COR_EC CHA_LLP_ERR CHA_SOT_BIT C_ERR _ERR R/W R/W R/W 1 Reserved 0 PLL_UNLOCK R R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 33. Register 0xE5 Field Descriptions Bit 36 Field Type Reset Description 7 CHA_SYNCH_ERR R/W 0 When the DSI channel A packet processor detects an HS or VS synchronization error, that is, an unexpected sync packet; this bit is set; this bit is cleared by writing a ‘1’ value. 6 CHA_CRC_ERR R/W 0 When the DSI channel A packet processor detects a data stream CRC error, this bit is set; this bit is cleared by writing a ‘1’ value. 5 CHA_UNC_ECC_ERR R/W 0 When the DSI channel A packet processor detects an uncorrectable ECC error, this bit is set; this bit is cleared by writing a ‘1’ value. 4 CHA_COR_ECC_ERR R/W 0 When the DSI channel A packet processor detects a correctable ECC error, this bit is set; this bit is cleared by writing a ‘1’ value. 3 CHA_LLP_ERR R/W 0 When the DSI channel A packet processor detects a low level protocol error, this bit is set; this bit is cleared by writing a ‘1’ value. Low level protocol errors include SoT and EoT sync errors, Escape Mode entry command errors, LP transmission sync errors, and false control errors. Lane merge errors are reported by this status condition. 2 CHA_SOT_BIT_ERR R/W 0 When the DSI channel A packet processor detects an SoT leader sequence bit error, this bit is set; this bit is cleared by writing a ‘1’ value. 1 Reserved R 0 PLL_UNLOCK R/W Reserved 1 This bit is set whenever the PLL Lock status transitions from LOCK to UNLOCK. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 SN65DSI83-Q1 www.ti.com SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The SN65DSI83-Q1 device is primarily targeted for portable applications such as tablets and smart phones that utilize the MIPI DSI video format. The SN65DSI83-Q1 device can be used between a GPU with DSI output and a video panel with LVDS inputs. 9.1.1 Video STOP and Restart Sequence When the system requires to stop outputting video to the display, TI recommends to use the following sequence for the SN65DSI83-Q1 device: 1. Clear the PLL_EN bit to 0 (CSR 0×0D.0). 2. Stop video streaming on DSI inputs. 3. Drive all DSI data lanes to LP11, but keep the DSI CLK lanes in HS. When the system is ready to restart the video streaming. 1. Start video streaming on DSI inputs. 2. Set the PLL_EN bit to 1 (CSR 0×0D.0). 3. Wait for minimum of 3 ms. 4. Set the SOFT_RESET bit (0×09.0). 9.1.2 Reverse LVDS Pin Order Option For ease of PCB routing, the SN65DSI83-Q1 device supports reversing the pin order via configuration register programming. The order of the LVDS pin for LVDS channel A can be reversed by setting the address 0×1A bit 5 CHA_REVERSE_LVDS. See the corresponding register bit definition for details. 9.1.3 IRQ Usage The SN65DSI83-Q1 device provides an IRQ pin that can be used to indicate when certain errors occur on DSI. The IRQ output is enabled through the IRQ_EN bit (CSR 0×E0.0). The IRQ pin is asserted when an error occurs on DSI, the corresponding error enable bit is set, and the IRQ_EN bit is set. An error is cleared by writing a 1 to the corresponding error status bit. NOTE If the SOFT_RESET bit is set while the DSI video stream is active, some of the error status bits may be set. NOTE If the DSI video stream is stopped, some of the error status bits may be set. These error status bits must be cleared before restarting the video stream. NOTE If the DSI video stream starts before the device is configured, some of the error status bits may be set. TI recommends to start streaming after the device is correctly configured as recommended in the initialization sequence in the Initialization Sequence section. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 37 SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 www.ti.com 9.2 Typical Application Figure 48 shows a typical application using the SN65DSI83-Q1 device for a single channel DSI receiver to interface a single-channel DSI application processor to an LVDS single-link 18 bit-per-pixel panel supporting 1280 × 800 WXGA resolutions at 60 frames per second. SN65DSI83-Q1 A_Y0N DA1P DA1N DA2P DA2N DA3P DA3N 100Ω A_Y1N A_Y1P 100Ω To column driver A_Y2N A_Y2P 100Ω To row driver A_CLKN A_CLKP 100Ω 18bpp TCON DA0P DA0N Application Processor A_Y0P A_Y3N A_Y3P DACP DACN SCL SDA IRQ EN ADDR REFCLK GND 1.8V VCC C1 Copyright © 2016, Texas Instruments Incorporated Figure 48. Typical WXGA 18-bpp Panel Application 9.2.1 Design Requirements Table 34 shows the SN65DSI83-Q1 desgin parameters. Table 34. Design Parameters DESIGN PARAMETERS EXAMPLE VALUE VCC 1.8 V (±5%) Clock source (REFCLK or DSIA_CLK) DSIA_CLK REFCKL frequency N/A DSIA clock frequency 500 MHz PANEL INFORMATION Pixel clock (MHz) 38 83 MHz Horizontal active (pixels) 1280 Horizontal blanking (pixels) 384 Vertical active (lines) 800 Vertical blanking (lines) 30 Horizontal sync offset (pixels) 64 Horizontal sync pulse width (pixels) 128 Vertical sync offset (lines) 3 Vertical sync pulse width (lines) 7 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 SN65DSI83-Q1 www.ti.com SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 Table 34. Design Parameters (continued) DESIGN PARAMETERS EXAMPLE VALUE PANEL INFORMATION (continued) Horizontal sync pulse polarity Negative Vertical sync pulse polarity Negative Color bit depth (6 bpc or 8 bpc) 6-bit Number of LVDS lanes 1 × [3 Data Lanes + 1 Clock Lane] DSI INFORMATION Number of DSI lanes 1 × [4 Data Lanes + 1 Clock Lane] DSI clock frequency(MHz) 500 MHz Dual DSI configuration(odd/even or left/right) N/A 9.2.2 Detailed Design Procedure The video resolution parameters required by the panel need to be programmed into the SN65DSI83-Q1 device. For this example, the parameters programmed are the following: Horizontal Active = 1280 or 0×500 CHA_ACTIVE_LINE_LENGTH_LOW = 0×00 CHA_ACTIVE_LINE_LENGTH_HIGH = 0×05 Vertical Active = 800 or 0×320 CHA_VERTICAL_DISPLAY_SIZE_LOW = 0×20 CHA_VERTICAL_DISPLAY_SIZE_HIGH = 0×03 Horizontal Pulse Width = 128 or 0×80 CHA_HSYNC_PULSE_WIDTH_LOW = 0×80 CHA_HSYNC_PULSE_WIDTH_HIGH = 0×00 Vertical Pulse Width = 7 CHA_VSYNC_PULSE_WIDTH_LOW = 0×07 CHA_VSYNC_PULSE_WIDTH_HIGH = 0×00 Horizontal Backporch = HorizontalBlanking – (HorizontalSyncOffset + HorizontalSyncPulseWidth) Horizontal Backporch = 384 – (64 + 128) Horizontal Backporch = 192 or 0×C0 CHA_HORIZONTAL_BACK_PORCH = 0×C0 Vertical Backporch = VerticalBlanking – (VerticalSyncOffset +VerticalSyncPulseWidth) Vertical Backporch = 30 – (3 + 7) Vertical Backporch = 20 or 0×14 CHA_VERTICAL_BACK_PORCH = 0×14 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 39 SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 www.ti.com Horizontal Frontporch = HorizontalSyncOffset Horizontal Frontporch = 64 or 0×40 CHA_HORIZONTAL_FRONT_PORCH = 0×40 Vertical Frontporch = VerticalSyncOffset Vertical Frontporch = 3 CHA_VERTICAL_FRONT_PORCH = 0×03 The pattern generation feature can be enabled by setting the CHA_TEST_PATTERN bit at address 0×3C and configuring the TEST PATTERN GENERATION PURPOSE ONLY register as shown in Table 30. LVDS clock is derived from the DSI channel A clock. When the MIPI D-PHY channel A HS clock is used as the LVDS clock source, it is divided by the factor in DSI_CLK_DIVIDER (CSR 0×0B.7:3) to generate the LVDS output clock. Additionally, LVDS_CLK_RANGE (CSR 0×0A.3:1) and CH_DSI_CLK_RANGE(CSR 0×12) must be set to the frequency range of the LVDS output clock and DSI Channel A input clock respectively for the internal PLL to operate correctly. After these settings are programmed, PLL_EN (CSR 0×0D.0) must be set to enable the internal PLL. LVDS_CLK_RANGE = 2 – 62.5 MHz ≤ LVDS_CLK < 87.5 MHz HS_CLK_SRC = 1 – LVDS pixel clock derived from MIPI D-PHY channel A DSI_CLK_DIVIDER = 00101 – Divide by 6 CHA_DSI_LANES = 00 – Four lanes are enabled CHA_DSI_CLK_RANGE = 0×64 – 500 MHz 40 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 SN65DSI83-Q1 www.ti.com SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 9.2.2.1 Example Script This example configures the SN65DSI83-Q1 device for the following configuration: =====SOFTRESET======= 09 01 ======PLL_EN(bit 0) - Enable LAST after addr 0A and 0B configured====== 0D 00 ======HS_CLK_SRC bit0=== ======LVDS_CLK_Range bit 3:1====== 0A 05 ======DSI_CLK_DIVIDER bit7:3===== ======RefCLK multiplier(bit1:0)====== ======00 - LVDSclk=source clk, 01 - x2, 10 -x3, 11 - x4====== 0B 28 ======DSI Ch Confg Left_Right Pixels(bit7 - 0 for A ODD, B EVEN, 1 for the other config)====== ======DSI Ch Mode(bit6:5) 00 - Dual, 01 - single, 10 - two single ======= ======SOT_ERR_TOL_DIS(bit0)======= 10 26 ====500M==== 12 64 ======bit7: DE_Pol, bit6:HS_Pol, bit5:VS_Pol, bit4: LVDS Link Cfg, bit3:CHA 24bpp, bit2: CHB 24bpp, bit1: CHA 24bpp fmt1, bit0: CHB 24bpp fmt1====== 18 72 19 00 ======CHA_LINE_LENGTH_LOW======== 20 00 ======CHA_LINE_LENGTH_HIGH======== 21 05 ======CHA_VERTICAL_DISPLAY_SIZE_LOW======== 24 00 ======CHA_VERTICAL_DISPLAY_SIZE_HIGH======== 25 04 ======CHA_SYNC_DELAY_LOW======== 28 20 ======CHA_SYNC_DELAY_HIGH======== 29 01 ======CHA_HSYNC_PULSE_WIDTH_LOW======== 2C 80 ======CHA_HSYNC_PULSE_WIDTH_HIGH======== 2D 00 ======CHA_VSYNC_PULSE_WIDTH_LOW======== 30 07 ======CHA_VSYNC_PULSE_WIDTH_HIGH======== 31 00 ======CHA_HOR_BACK_PORCH======== 34 C0 ======CHA_VER_BACK_PORCH======== 36 00 ======CHA_HOR_FRONT_PORCH======== Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 41 SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 www.ti.com 38 00 ======CHA_VER_FRONT_PORCH======== 3A 00 ======CHA/CHB TEST PATTERN(bit4 CHA, bit0 CHB)======== 3C 00 ======PLL_EN(bit 0) - Enable LAST after addr 0A and 0B configured====== 0D 01 ======Read====== 00 ======Read====== 00 9.2.3 Application Curve 120 ICC (mA) 115 110 105 100 95 1.6 1.65 1.7 1.75 1.8 1.85 VCC (V) 1.9 1.95 2 D001 B. SN65DSI83-Q1: SINGLE Channel DSI to SINGLE Channel DSI, 1280 × 800 a. number of LVDS lanes = 3 data lanes + 1 CLK lane b. number of DSI lanes = 4 data lanes + 1 CLK lane c. LVDS CLK OUT = 83 M d. DSI CLK = 500 M e. RGB666, LVDS 18 bpp Figure 49. Power Consumption 42 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 SN65DSI83-Q1 www.ti.com SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 10 Power Supply Recommendations 10.1 VCC Power Supply Each VCC power supply pin must have a 100-nF capacitor to ground connected as close as possible to the SN65DSI83-Q1 device. It is recommended to have one bulk capacitor (1 µF to 10 µF) on it. It is also recommended to have the pins connected to a solid power plane. 10.2 VCORE Power Supply This pin must have a 100-nF capacitor to ground connected as close as possible to the SN65DSI83-Q1 device. It is recommended to have one bulk capacitor (1 µF to 10 µF) on it. It is also recommended to have the pins connected to a solid power plane. 11 Layout 11.1 Layout Guidelines 11.1.1 Package Specific For the PAP package, to minimize the power supply noise floor, provide good decoupling near the SN65DSI83Q1 device power pins. The use of four ceramic capacitors (2 × 0.1 μF and 2 × 0.01 μF) provides good performance. At the least, TI recommends to install one 0.1-μF and one 0.01-μF capacitor near the SN65DSI83Q1 device. To avoid large current loops and trace inductance, the trace length between decoupling capacitor and device power inputs pins must be minimized. Placing the capacitor underneath the SN65DSI83-Q1 device on the bottom of the PCB is often a good choice. 11.1.2 Differential Pairs • Differential pairs must be routed with controlled 100-Ω differential impedance (± 20%) or 50-Ω single-ended impedance (±15%). • Keep away from other high speed signals • Keep lengths to within 5 mils of each other. • Length matching must be near the location of mismatch. • Each pair must be separated at least by 3 times the signal trace width. • The use of bends in differential traces must be kept to a minimum. When bends are used, the number of left and right bends must be as equal as possible and the angle of the bend must be ≥ 135 degrees. This arrangement minimizes any length mismatch caused by the bends and therefore minimizes the impact that bends have on EMI. • Route all differential pairs on the same of layer. • The number of vias must be kept to a minimum. It is recommended to keep the via count to 2 or less. • Keep traces on layers adjacent to ground plane. • Do NOT route differential pairs over any plane split. • Adding Test points cause impedance discontinuity and therefore negatively impacts signal performance. If test points are used, they must be placed in series and symmetrically. They must not be placed in a manner that causes a stub on the differential pair. 11.1.3 Ground TI recommends that only one board ground plane be used in the design. This provides the best image plane for signal traces running above the plane. The thermal pad of the SN65DSI83-Q1 must be connected to this plane with vias. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 43 SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 www.ti.com IRQ VCC 1.8V A_Y3N A_Y3P A_CLKN A_CLKP VCC 1.8V A_Y2P A_Y2N VCC 1.8V A_Y1N A_Y1P A_Y0N VCC 1.8V NC pin must not be connected to any signal, power or ground A_Y0P 11.2 Layout Example Place Vcc decoupling caps as close to Vcc as possible VCC 1.8V VCC 1.8V 1uF DA3N DA3P GND DA2N DA2P VCC 1.8V GND DACN GND DACP GND VCC 1.8V DA1N DA1P DA0N DA0P VCC 1.8V VCC 1.8V VCC 1.8V 4.7NŸ 10NŸ GND 1 4.7NŸ VCC 1.8V 4.7NŸ VCC 1.8V SCL EN Differential pairs must be routed with controlled 100- differential impedance VCC 1.8V VCC 1.8V SDA Copyright © 2016, Texas Instruments Incorporated Figure 50. SN65DSI83-Q1 Layout Example 44 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 SN65DSI83-Q1 www.ti.com SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • SN65DSI8x Video Configuration Guide and Configuration Tool Software Users Manual • SN65DSI83, SN65DSI84, and SN65DSI85 Hardware Implementation Guide 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Community Resource The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks PowerPAD, E2E are trademarks of Texas Instruments. MIPI is a registered trademark of Arasan Chip Systems, Inc. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 45 SN65DSI83-Q1 SLLSEW7A – DECEMBER 2016 – REVISED JUNE 2018 www.ti.com 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 46 Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Product Folder Links: SN65DSI83-Q1 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN65DSI83TPAPRQ1 ACTIVE HTQFP PAP 64 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 DSI83TQ1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of