SN65LBC175AMDREP

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents SN65LBC175A-EP SLLSEU5 – DECEMBER 2016 SN65LBC175A-EP Quadruple RS-485 Differential Line Receiver 1 Features 3 Description • The SN65LBC175A-EP is a quadruple differential line receiver with 3-state outputs, designed for TIA/EIA485 (RS-485), TIA/EIA-422 (RS-422), and ISO 8482 (Euro RS-485) applications. 1 • • • • • • • Designed for TIA/EIA-485, TIA/EIA-422 and ISO 8482 Applications Signaling Rates (1) Exceeding 50 Mbps Fail-Safe in Bus Short-Circuit, Open-Circuit, and Idle-Bus Conditions ESD Protection on Bus Inputs Exceeds 6 kV Common-Mode Bus Input Range –7 V to 12 V Propagation Delay Times < 18 ns Low Standby Power Consumption < 32 µA Pin-Compatible Upgrade for MC3486, DS96F175, LTC489, and SN75175 2 Applications • Supports Defense, Aerospace, and Medical Applications – Controlled Baseline – One Assembly and Test Site – One Fabrication Site – Extended Product Life Cycle – Extended Product-Change Notification – Product Traceability This device is optimized for balanced multipoint bus communication at data rates up to and exceeding 50 million bits per second. The transmission media may be twisted-pair cables, printed-circuit board traces, or backplanes. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The receiver operates over a wide range of positive and negative common-mode input voltages, and features ESD protection to 6 kV, making it suitable for high-speed multipoint data transmission applications in harsh environments. These devices are designed using LinBiCMOS®, facilitating low power consumption and robustness. Two EN inputs provide pair-wise enable control, or these can be tied together externally to enable all four drivers with the same signal. . Device Information(1) PART NUMBER SN65LBC175A-EP (1) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). PACKAGE SOIC (16) BODY SIZE (NOM) 9.90 mm × 3.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram 1,2EN 1A 1Y 1B 2A 2B 2Y 3,4EN 3A 3Y 3B 4A 4Y 4B Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN65LBC175A-EP SLLSEU5 – DECEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 4 5 5 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. 8.3 Feature Description................................................. 10 8.4 Device Functional Modes........................................ 10 9 Application and Implementation ........................ 12 9.1 Application Information............................................ 12 9.2 Typical Application .................................................. 12 10 Power Supply Recommendations ..................... 14 11 Layout................................................................... 14 11.1 Layout Guidelines ................................................. 14 11.2 Layout Example .................................................... 14 12 Device and Documentation Support ................. 15 12.1 12.2 12.3 12.4 12.5 Parameter Measurement Information .................. 8 Detailed Description ............................................ 10 Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 15 15 15 15 15 13 Mechanical, Packaging, and Orderable Information ........................................................... 16 8.1 Overview ................................................................. 10 8.2 Functional Block Diagram ....................................... 10 4 Revision History 2 DATE REVISION NOTES December 2016 * Initial release. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: SN65LBC175A-EP SN65LBC175A-EP www.ti.com SLLSEU5 – DECEMBER 2016 5 Pin Configuration and Functions D Package 16-Pin SOIC Top View 1B 1 16 VCC 1A 2 15 4B 1Y 3 14 4A 1,2EN 4 13 4Y 2Y 5 12 3,4EN 2A 6 11 3Y 2B 7 10 3A GND 8 9 3B Not to scale Pin Functions PIN NAME NO. 1A 2 1B 1Y I/O DESCRIPTION I RS-485 differential input (noninverting). 1 I RS-485 differential input (inverting). 3 O Logic level output. 2A 6 I RS-485 differential input (noninverting). 2B 7 I RS-485 differential input (inverting). 2Y 5 O Logic level output. 3A 10 I RS-485 differential input (noninverting). 3B 9 I RS-485 differential input (inverting). 3Y 11 O Logic level output. 4A 14 I RS-485 differential input (noninverting). 4B 15 I RS-485 differential input (inverting). 4Y 13 O Logic level output. 1,2EN 4 I Active-low and active-high select. 3,4EN 12 I Active-low and active-high select. GND 8 — Ground. VCC 16 — Power supply. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: SN65LBC175A-EP 3 SN65LBC175A-EP SLLSEU5 – DECEMBER 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply voltage, VCC (2) –0.3 6 V Voltage at any bus input (steady state), A and B –10 15 V Voltage at any bus (transient pulse through 100 Ω, see Figure 10) –30 30 V Input voltage at 1,2EN and 3,4EN, VI –0.5 VCC + 0.5 V Receiver output current, IO –10 10 mA Storage temperature, Tstg –65 150 °C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to GND and are steady-state (unless otherwise specified). 6.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) (1) (2) A and B to GND ±6000 All pins ±5000 All pins ±2000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions VCC Supply voltage Voltage at any bus terminal VIH High-level input voltage VIL Low-level input voltage A, B EN Output current TJ Y Junction temperature MIN NOM MAX UNIT 4.75 5 5.25 V –7 12 V 2 VCC V 0 0.8 –8 8 mA V –55 125 °C 6.4 Thermal Information SN65LBC175A-EP THERMAL METRIC (1) D (SOIC) UNITS 16 PINS θJA Junction-to-ambient thermal resistance 78 °C/W θJCtop Junction-to-case (top) thermal resistance 39.5 °C/W θJB Junction-to-board thermal resistance 35.4 °C/W ψJT Junction-to-top characterization parameter 8.5 °C/W ψJB Junction-to-board characterization parameter 35.1 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: SN65LBC175A-EP SN65LBC175A-EP www.ti.com SLLSEU5 – DECEMBER 2016 6.5 Electrical Characteristics over recommended operating conditions PARAMETER TEST CONDITIONS VIT+ Positive-going differential input voltage threshold VIT- Negative-going differential input voltage threshold –7 V ≤ VCM ≤ 12 V (VCM = (VA + VB) / 2) MIN TYP (1) MAX UNIT –80 –10 mV –200 –120 mV –40 mV –1.5 –0.8 V 2.7 4.8 V VHYS Hysteresis voltage (VIT+ – VIT–) VIK Input clamp voltage II = –18 mA VOH High-level output voltage VID = 200 mV, IOH = –8 mA VOL Low-level output voltage VID = –200 mV, IOL = 8 mA IOZ High-impedance-state output current VO = 0 V to VCC II Line input current IIH High-level input current IIL Low-level input current RI Input resistance ICC Supply current (1) See Figure 6 0.2 0.4 V 1 µA –1 Other input at 0 V, VCC = 0 V or 5 V VI = 12 V 0.9 VI = –7 V –0.7 110 Enable inputs A, B inputs VID = 5 V 1,2EN, 3,4EN at 0 V No load 1,2EN, 3,4EN at VCC mA µA –100 µA 12 kΩ 11 32 µA 16 mA All typical values are at VCC = 5 V and 25°C. 6.6 Switching Characteristics Over recommended operating conditions PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tr Output rise time 2 7 ns tf Output fall time 2 7 ns tPLH Propagation delay time, low-to-high level output 8 12 18 ns tPHL Propagation delay time, high-to-low level output 8 12 18 ns tPZH Propagation delay time, high-impedance to high-level output 27 39 ns tPHZ Propagation delay time, high-level-output to high-impedance tPZL Propagation delay time, high-impedance to low-level output tPLZ Propagation delay time, low-level-output to high-impedance tsk(p) Pulse skew (|tPLH – tPHL|) Output skew tsk(pp) Part-to-part skew (2) (2) See Figure 8 See Figure 9 (1) tsk(o) (1) VID = –3 V to 3 V, See Figure 7 7 24 ns 29 39 ns 12 18 ns 0.2 2 ns 3 ns 3 ns Output skew (tsk(o)) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together. Part-to-part skew (tsk(pp)) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test circuits. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: SN65LBC175A-EP 5 SN65LBC175A-EP SLLSEU5 – DECEMBER 2016 www.ti.com 100 Life (yr) 10 1 0.1 85 105 125 Operating Junction Temperature (qC) 145 165 D001 (1) See data sheet for absolute maximum and minimum recommended operating conditions. (2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life). (3) Enhanced plastic product disclaimer applies. Figure 1. SN65LBC175A-EP Wirebond Life Derating Chart 6 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: SN65LBC175A-EP SN65LBC175A-EP www.ti.com SLLSEU5 – DECEMBER 2016 6.7 Typical Characteristics 6 800 600 5 400 VO − Output Voltage − V Bus Input Current −µ A VCC = 0 V VCC = 5 V 200 0 −200 VIC = −7 V VIC = 0 V VIC = 12 V 4 VIC = −7 V VIC = 0 V VIC = 12 V 3 2 1 −400 −600 −10 −5 0 5 10 0 −150 15 −100 Bus Input Voltage − V VCC = 5 V 14 50 13.5 Propagation Delay Time (ns) I CC − Supply Current − mA 60 40 VCC = 5.25 V, CL = 15 pF VCC = 5 V, CL = 15 pF VCC = 4.75 V, CL = 15 pF 20 0 50 TA = 25°C Figure 3. Output Voltage vs Differential Input Voltage Figure 2. Bus Input Current vs Bus Input Voltage 30 −50 Differential Input Voltage − mV 13 12.5 12 11.5 TPHL TPLH 10 VCC = 5 V, No Load 11 -55 -35 -15 5 25 45 65 85 Operating Junction Temperature (qC) 105 0 1 125 D005 10 100 Signaling Rate (All Four Channels) − Mbps Figure 4. Supply Current vs Signaling Rate (All Four Channels) Figure 5. Propagation Delay Time vs Free-Air Temperature Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: SN65LBC175A-EP 7 SN65LBC175A-EP SLLSEU5 – DECEMBER 2016 www.ti.com 7 Parameter Measurement Information VA IO VID VB VO Figure 6. Voltage and Current Definitions Generator Input B A 50 Ω 3V 1.5 V 1.5 V Y Input A B 0V tPLH Generator CL = 15 pF (Includes Probe and Jig Capacitance) 50 Ω Output Y tPHL 90% 10% 1.5 V tr VOH 90% 10% VOL tf Generators: PRR = 1 MHz, 50% Duty Cycle, tr