SN65LBC176AMDREP

         


SGLS151C − DECEMBER 2002 − REVISED JULY 2004 D Controlled Baseline D D D D D D D D D D D D D D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −40°C to 125°C and −55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree† High-Speed Low-Power LinBiCMOS Circuitry Designed for Signaling Rates‡ Up to 30 Mbps Bus-Pin ESD Protection Exceeds 12-kV HBM Compatible With ANSI Standard TIA/EIA-485-A and ISO 8482:1987(E) Low Skew Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments Low Disabled Supply Current Requirements . . . 700 µA Maximum Common-Mode Voltage Range of −7 V to 12 V Thermal-Shutdown Protection Driver Positive and Negative Current Limiting Open-Circuit Fail-Safe Receiver Design Receiver Input Sensitivity . . . ± 200 mV Max Receiver Input Hysteresis . . . 50 mV Typ Glitch-Free Power-Up and Power-Down Protection † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. ‡ Signaling rate by TIA/EIA-485-A definition restrict transition times to 30% of the bit length, and much higher signaling rates may be achieved without this requirement as displayed in the TYPICAL CHARACTERISTICS of this device. D Package (TOP VIEW) R RE DE D 1 8 2 7 3 6 4 5 VCC B A GND logic diagram (positive logic) DE 3 4 D RE R 2 6 1 7 A Bus B Function Tables DRIVER INPUT D H L X Open ENABLE DE H H L H OUTPUTS A B H L L H Z Z H L RECEIVER DIFFERENTIAL INPUTS VA −VB VID ≥ 0.2 V −0.2 V < VID < 0.2 V VID ≤ − 0.2 V X Open H = high level, X = irrelevant, ENABLE RE L L L H L OUTPUT R H ? L Z H L = low level, ? = indeterminate, Z = high impedance (off) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinBiCMOS and LinASIC are trademarks of Texas Instruments. Copyright  2004, Texas Instruments Incorporated     !"#   $"%&! '#( '"! !  $#!! $# )# #  #* "# '' +,( '"! $!#- '#  #!#&, !&"'# #-  && $##( POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1          

SGLS151C − DECEMBER 2002 − REVISED JULY 2004 description/ordering information The SN65LBC176A-EP differential bus transceiver is a monolithic, integrated circuits designed for bidirectional data communication on multipoint bus-transmission lines. The SN65LBC176A-EP is designed for balanced transmission lines and is compatible with ANSI standard TIA/EIA-485-A and ISO 8482. The SN65LBC176A-EP offers improved switching performance over its predecessors without sacrificing significantly more power. The SN65LBC176A-EP combines a 3-state, differential line driver and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables, respectively, which can externally connect together to function as a direction control. The driver differential outputs and the receiver differential inputs connect internally to form a differential input/output (I/O) bus port that is designed to offer minimum loading to the bus whenever the driver is disabled or VCC = 0. This port features wide positive and negative common-mode voltage ranges, making the device suitable for party-line applications. Low device supply current can be achieved by disabling the driver and the receiver. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE† TA TOP-SIDE MARKING −40°C to 125°C SOIC − D Tape and Reel SN65LBC176AQDREP 176AEP −55°C to 125°C SOIC − D Tape and Reel SN65LBC176AMDREP 176MEP † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. schematics of inputs and outputs A Input VCC D, DE, and RE Inputs VCC 16 V 100 kΩ 100 kΩ 4 kΩ 18 kΩ 1 kΩ Input Input 16 V 8V 4 kΩ B Input R Output VCC VCC 16 V 40 Ω 4 kΩ Output 18 kΩ Input 100 kΩ 8V 2 POST OFFICE BOX 655303 16 V • DALLAS, TEXAS 75265 4 kΩ          

SGLS151C − DECEMBER 2002 − REVISED JULY 2004 absolute maximum ratings† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V Voltage range at any bus terminal (A or B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10 V to 15 V Input voltage, VI (D, DE, R, or RE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.5 V Electrostatic discharge: Bus terminals and GND, Class 3, A: (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . 12 kV Bus terminals and GND, Class 3, B: (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . 400 V All terminals, Class 3, A: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 kV All terminals, Class 3, B: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 V Continuous total power dissipation (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Storage temperature range, Tstg (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltage, are with respect to network ground terminal. 2. The maximum operating junction temperature is internally limited. Use the dissipation rating table to operate below this temperature. 3. Tested in accordance with MIL−STD−883C, Method 3015.7 4. Long-term, high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR‡ ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING D 725 mW 5.8 mW/°C 464 mW 377 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when the board is mounted and with no air flow. 145 mW OPERATING LIFE DERATING TABLE − SN65LBC176AMDREP 1/tf vs 1/TJ in °K 0.0001 140°C (29.1k Hrs, 3.3 Yrs) 1/tf in Hours 135°C (51.0k Hrs, 5.8 Yrs) 130°C (90.1k Hrs, 10.3 Yrs) 0.00001 125°C (161.8 kHrs, 18.5 Yrs) R = 0.9881 0.000001 1/TJ in °K NOTES: A. See the data sheet for absolute maximum and maximum recommended operating conditions. B. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life). C. Attached enhanced plastic product disclaimer applies. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3          

SGLS151C − DECEMBER 2002 − REVISED JULY 2004 recommended operating conditions Supply voltage, VCC MIN NOM MAX UNIT 4.75 5 5.25 V 12 Voltage at any bus terminal (separately or common mode), VI or VIC High-level input voltage, VIH (output recessive) D, DE, and RE 2 Low-level input voltage, VIL (output dominant) D, DE, and RE 0 −12§ Differential input voltage, VID (see Note 5) Driver High-level output current, IOH V −7 Receiver V 12 V mA −8 60 Receiver Operating free-air temperature, TA V −60 Driver Low-level output current, IOL VCC 0.8 8 SN65LBC176AQ-EP −40 125 SN65LBC176AM-EP −55 125 mA °C § The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet. NOTE 5: Differential input /output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B. driver electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VIK | VOD | Input clamp voltage Differential output voltage TEST CONDITIONS II = − 18 mA IO = 0 RL = 54 Ω, See Figure 1 Vtest = − 7 V to 12 V, See Figure 2 MIN TYP† −1.5 −0.8 1.5 4 6 0.9 1.5 6 0.9 1.5 6 MAX UNIT V V ∆| VOD | Change in magnitude of differential output voltage See Figure 1 and Figure 2 VOC(SS) Steady-state common-mode output voltage See Figure 1 1.8 ∆ VOC(SS) Change in steady-state common-mode output voltage† See Figure 1 −0.2 IOZ High-impedance output current See receiver input currents IIH High-level enable input current VI = 2 V −100 µA IIL Low-level enable input current VI = 0.8 V −100 µA IOS Short-circuit output current −7 V ≤ VO ≤ 12 V ICC Supply current VI = 0 or VCC, No load 2.4 0.2 V 3 V 0.2 V ±70 250 Receiver disabled and driver enabled 5 9 Receiver disabled and driver disabled 0.4 0.7 Receiver enabled and driver enabled 8.5 15 −250 † All typical values are at VCC = 5 V, TA = 25°C. 4 −0.2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 mA mA          

SGLS151C − DECEMBER 2002 − REVISED JULY 2004 driver switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX Propagation delay time, low-to-high level output tsk(p) tr Pulse skew ( | tPLH − tPHL | ) tf tPZH Differential output signal fall time Propagation delay time, high-impedance to high-level output RL = 110 Ω, See Figure 4 22 ns tPZL tPHZ Propagation delay time, high-impedance to low-level output RL = 110 Ω, See Figure 5 25 ns Propagation delay time, high-level to high-impedance output RL = 110 Ω, See Figure 4 22 ns RL = 110 Ω, See Figure 5 22 ns Propagation delay time, high-to-low level output RL = 54 Ω, Ω CL = 50 pF, See Figure 3 Differential output signal rise time 2 12 2 12 1.2 11 UNIT tPLH tPHL 2 1.2 tPLZ Propagation delay time, low-level to high-impedance output † All typical values are at VCC = 5 V, TA = 25°C. ns 11 receiver electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VIT + Positive-going input threshold voltage VIT − Negative-going input threshold voltage Vhys VIK Hysteresis voltage (VIT + − VIT −) VOH VOL High-level output voltage IOZ High-impedance-state output current II IIH IIL ICC Enable-input clamp voltage Low-level output voltage Bus input current High-level enable-input current Low-level enable-input current Supply current TEST CONDITIONS MIN TYP† IO = −8 mA MAX 0.2 −0.2 IO = 8 mA VID = 200 mV, VO = 0 to VCC IOH = − 8 mA, IOL = 8 mA, See Figure 6 −0.8 4 4.9 0.1 −10 VIH = 12 V, VIH = 12 V, VCC = 5 V VCC = 0 VIH = − 7 V, VIH = − 7 V, VCC = 5 V VCC = 0 Other input at 0 V VIH = 2 V VIL = 0.8 V VI = 0 or VCC, No load −1.5 See Figure 6 V V 50 II = − 18 mA VID = 200 mV, UNIT mV V V 0.8 V 10 µA 0.4 1 0.5 1 −0.8 −0.4 −0.8 −0.3 mA µA −100 µA −100 Receiver enabled and driver disabled 4 7 Receiver disabled and driver disabled 0.4 0.7 Receiver enabled and driver enabled 8.5 15 mA † All typical values are at VCC = 5 V, TA = 25°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5          

SGLS151C − DECEMBER 2002 − REVISED JULY 2004 receiver switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER tPLH tPHL Propagation delay time, output↑ tsk(p) tr Pulse skew ( | tPHL − tPLH | ) Rise time, output tf Fall time, output tPZH tPZL MIN TYP† MAX UNIT 7 30 ns 7 30 ns 6 ns 5 ns 5 ns Output enable time to high level 50 ns Output enable time to low level 50 ns 60 ns 40 ns Propagation delay time, output↓ tPHZ Output disable time from high level tPLZ Output disable time from low level † All typical values are at VCC = 5 V, TA = 25°C. 6 TEST CONDITIONS VID = − 1.5 V to 1.5 V, See Figure 7 See Figure 7 CL = 10 pF, See Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265          

SGLS151C − DECEMBER 2002 − REVISED JULY 2004 PARAMETER MEASUREMENT INFORMATION Vtest R1 375 Ω Y 27 Ω VOD 0 or 3 V D RL = 60 Ω 0 V or 3 V VOD 27 Ω VOC Z Figure 1. Driver VOD and VOC R2 375 Ω −7 V < Vtest < 12 V Vtest Figure 2. Driver VOD3 3V Input Generator (see Note A) 50 Ω RL = 54 Ω 1.5 V CL = 50 pF (see Note B) 1.5 V 0V tPLH VO Output tPHL 90% 50% ≈ 1.5 V 10% ≈ − 1.5 V tf VOLTAGE WAVEFORMS tr TEST CIRCUIT NOTES: D. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. E. CL includes probe and jig capacitance. Figure 3. Driver Test Circuit and Voltage Waveforms Output 3V S1 Input 1.5 V 1.5 V 3V Generator (see Note A) 50 Ω CL = 50 pF (see Note B) tPZH RL = 110 Ω 0V 0.5 V VOH Output TEST CIRCUIT 2.3 V tPHZ Voff ≈ 0 V VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 4. Driver Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7          

SGLS151C − DECEMBER 2002 − REVISED JULY 2004 PARAMETER MEASUREMENT INFORMATION 5V S1 0V Generator (see Note A) 3V Input RL = 110 Ω 1.5 V 1.5 V 0V tPZL Output tPLZ CL = 50 pF (see Note B) 50 Ω 5V 0.5 V 2.3 V Output VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 5. Driver Test Circuit and Voltage Waveforms IO VID VO Figure 6. Receiver VOH and VOL 3V Input Generator (see Note A) 1.5 V 1.5 V Output 50 Ω 1.5 V CL = 10 pF (see Note B) 0V Output 0V tPHL tPLH 1.3 V 10% 1.3 V tR TEST CIRCUIT VOH 90% VOL tF VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 7. Receiver Test Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265          

SGLS151C − DECEMBER 2002 − REVISED JULY 2004 PARAMETER MEASUREMENT INFORMATION S1 1.5 V 2 kΩ −1.5 V S2 5V CL = 10 pF (see Note B) Generator (see Note A) 5 kΩ 50 Ω S3 TEST CIRCUIT Input 1.5 V 3V S1 to 1.5 V S2 Open S3 Closed 0V Input 1.5 V tPZH 3V S1 to −1.5 V S2 Closed S3 Open 0V tPZL VOH ≈ 4.5 V 1.5 V Output Output 1.5 V 0V VOL 1.5 V Input 3V S1 to 1.5 V S2 Closed S3 Closed 0V Input tPHZ 3V S1 to −1.5 V S2 Closed S3 Closed 0V 1.5 V tPLZ ≈ 1.3 V VOH Output 0.5 V Output 0.5 V ≈ 1.3 V VOL VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 8. Receiver Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9          

SGLS151C − DECEMBER 2002 − REVISED JULY 2004 TYPICAL CHARACTERISTICS Receiver Output Driver Input 120 Ω 120 Ω Driver Input Receiver Output Figure 9. Typical Waveform of Non-Return-To-Zero (NRZ), Pseudorandom Binary Sequence (PRBS) Data at 100 Mbps Through 15m, of CAT 5 Unshielded Twisted Pair (UTP) Cable TIA/EIA-485-A defines a maximum signaling rate as that in which the transition time of the voltage transition of a logic-state change remains less than or equal to 30% of the bit length. Transition times of greater length perform quite well, even though they do not meet the standard by definition. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265          

SGLS151C − DECEMBER 2002 − REVISED JULY 2004 TYPICAL CHARACTERISTICS AVERAGE SUPPLY CURRENT vs FREQUENCY LOGIC INPUT CURRENT vs INPUT VOLTAGE 40 −30 Driver −25 30 I I − Input Current − µ A I CC − Average Supply Current − mA 35 25 20 15 10 −20 −15 −10 Receiver −5 5 0 0.05 0.5 1 2 5 10 20 0 30 0 1 f − Frequency − MHz Figure 10 5 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 800 2.00 600 1.75 VOL − Low-Level Output voltage − V I I − Input Current − µ A 4 3 Figure 11 INPUT CURRENT vs INPUT VOLTAGE 400 200 0 −200 Bus Input Current −400 −600 −8 2 VI − Input Voltage − V 1.50 VCC = 5 1.25 1.00 0.75 0.50 0.25 0.00 −6 −4 −2 0 2 4 6 8 10 12 VI − Input Voltage − V 0 10 20 30 40 50 60 70 80 IOL − Low-Level Output Current − mA Figure 12 Figure 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11          

SGLS151C − DECEMBER 2002 − REVISED JULY 2004 TYPICAL CHARACTERISTICS DRIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs AVERAGE CASE TEMPERATURE 5 VOD − Average Differential Output Voltage − V 2 VOH − High-Level Output Voltage − V 4.5 4 VCC = 5.25 V 3.5 3 2.5 VCC = 5 V 2 VCC = 4.75 V 1.5 1 0.5 0 1.5 1 0.5 0 0 −10 −20 −30 −40 −50 −60 −70 −80 −40 Figure 14 13.8 7.4 13.7 7.2 13.6 7 Propagation Delay Time − ns TPHL Receiver (ns) 70 85 DRIVER PROPAGATION DELAY TIME vs CASE TEMPERATURE 13.5 13.4 13.3 13.2 13.1 13 6.8 6.6 6.4 6.2 6 5.8 0 70 25 80 5.6 −40 0 25 Figure 16 Figure 17 POST OFFICE BOX 655303 70 Case Temperature − ° C Case Temperature −° C 12 25 Figure 15 RECEIVER PROPAGATION TIME vs CASE TEMPERATURE 12.9 −40 0 Average Case Temperature − °C I OH − High-Level Output Current − (mA) • DALLAS, TEXAS 75265 85          

SGLS151C − DECEMBER 2002 − REVISED JULY 2004 TYPICAL CHARACTERISTICS DRIVER OUTPUT CURRENT vs SUPPLY VOLTAGE 90 I O − Output Current − mA 65 40 15 IOH −10 −35 −60 −85 −110 −135 IOL −160 −185 −210 0 3 5 4 VCC − Supply Voltage − V 6 Figure 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN65LBC176AMDREP ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 176MEP SN65LBC176AQDREP ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 176AEP V62/03671-01XE ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 176AEP V62/03671-02XE ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 176MEP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of