SN74ACT373MDWREP

     
    
 
SCAS726 − OCTOBER 2003 D Controlled Baseline D D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† 4.5-V to 5.5-V VCC Operation D Inputs Accept Voltages to 5.5 V D Max tpd of 10 ns at 5 V D Inputs Are TTL-Voltage Compatible DW PACKAGE (TOP VIEW) OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE description/ordering information This 8-bit latch features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches are D-type transparent latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines in bus-organized systems without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING −55°C to 125°C SOIC − DW Tape and reel SN74ACT373MDWREP SACT373MEP ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated     !   "#$ %!& %   "! "! '! !  !( ! %% )*& % "!+ %!  !!$* $%! !+  $$ "!!& POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
     
    
 
SCAS726 − OCTOBER 2003 FUNCTION TABLE (each latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic diagram (positive logic) OE LE 1 11 C1 1D 3 2 1Q 1D To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W Storage temperature range, Tstg (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. Long-term high−temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
     
    
 
SCAS726 − OCTOBER 2003 recommended operating conditions (see Note 4) MIN MAX 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 IOL ∆t/∆v High-level input voltage 2 UNIT V V 0.8 V VCC VCC V High-level output current −24 mA Low-level output current 24 mA 8 ns/V Input transition rise or fall rate V TA Operating free-air temperature −55 125 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS A IOH = −50 µA VOH IOH = −24 mA IOL = 50 µA A VOL IOL = 24 mA IOZ II VO = VCC or GND VI = VCC or GND ICC VI = VCC or GND, One input at 3.4 V, Other inputs at GND or VCC ∆ICC† IO = 0 TA = 25°C TYP MAX VCC MIN MIN 4.5 V 4.4 4.49 4.4 5.5 V 5.4 5.49 5.4 4.5 V 3.86 3.7 5.5 V 4.86 4.7 MAX UNIT V 4.5 V 0.1 5.5 V 0.1 0.1 4.5 V 0.36 0.44 5.5 V 0.36 0.44 5.5 V ±0.25 ±5 µA 5.5 V ±0.1 ±1 µA 5.5 V 4 80 µA 1.5 mA 5.5 V 0.1 0.6 Ci VI = VCC or GND 5V 4.5 † This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. V pF timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX MIN MAX UNIT tw tsu Pulse duration, LE high 7 8.5 ns Setup time, data before LE↓ 7 8.5 ns th Hold time, data after LE↓ 0 1 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
     
    
 
SCAS726 − OCTOBER 2003 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q tPHZ tPLZ OE Q MIN TA = 25°C TYP MAX MIN MAX 2.5 8.5 10 1.5 12.5 2 8 10 1.5 12.5 2.5 8.5 11 1.5 12.5 2 8 10 1.5 11.5 2 8 9.5 1.5 11.5 2 7.5 9 1.5 11 2.5 9 11 1.5 14 1.5 7.5 8.5 1.5 11 UNIT ns ns ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance CL = 50 pF, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz TYP 40 UNIT pF 
     
    
 
SCAS726 − OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test CL = 50 pF (see Note A) Open 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC Open 3V 1.5 V Timing Input LOAD CIRCUIT 0V th tsu 3V 1.5 V Data Input tw 0V 3V 1.5 V Input 1.5 V VOLTAGE WAVEFORMS 1.5 V 0V VOLTAGE WAVEFORMS Output Control (low-level enabling) 3V 1.5 V 1.5 V 0V tPZL 3V Input 1.5 V 1.5 V 0V tPLH Output tPHL 50% VCC VOH 50% VCC VOL Output Waveform 1 S1 at 2 × VCC (see Note B) tPLZ ≈VCC 50% VCC tPZH Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) SN74ACT373MDWREP ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 SACT373MEP V62/04619-01XE ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 SACT373MEP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of