SN74ACT74MDREP

  
               
 SCAS722 − OCTOBER 2003 D Controlled Baseline D D D D − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree† D D D D 4.5-V to 5.5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 10.5 ns at 5 V Inputs Are TTL-Voltage Compatible D PACKAGE (TOP VIEW) 1CLR 1D 1CLK 1PRE 1Q 1Q GND † Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q description/ordering information The SN74ACT74-EP is a dual positive-edge-triggered D-type flip-flop. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE‡ TA TOP-SIDE MARKING −55°C to 125°C SOIC − D Tape and reel SN74ACT74MDREP SACT74MEP ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each flip-flop) INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H§ H§ H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 § This configuration is nonstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated     !"#   $"%&! '#( '"! !  $#!! $# )# #  #* "# '' +,( '"! $!#- '#  #!#&, !&"'# #-  && $##( POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
  
               
 SCAS722 − OCTOBER 2003 logic diagram, each flip-flop (positive logic) PRE CLK C C C Q TG C C C C D TG TG TG C C C Q CLR absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W Storage temperature range, Tstg (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. Long-term high−temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
  
               
 SCAS722 − OCTOBER 2003 recommended operating conditions (see Note 4) MIN MAX 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 IOL ∆t/∆v High-level input voltage 2 UNIT V V 0.8 V VCC VCC V High-level output current −24 mA Low-level output current 24 mA 8 ns/V Input transition rise or fall rate V TA Operating free-air temperature −55 125 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −50 µA A VOH IOH = −24 mA IOL = 50 µA A VOL IOL = 24 mA II ICC VI = VCC or GND VI = VCC or GND, ∆ICC† Ci One input at 3.4 V, IO = 0 Other inputs at GND or VCC TA = 25°C TYP MAX MIN VCC MIN 4.5 V 4.4 4.49 4.4 5.5 V 5.4 5.49 5.4 4.5 V 3.86 3.7 5.5 V 4.86 4.7 MAX V 4.5 V 0.001 0.1 0.1 5.5 V 0.001 0.1 0.1 4.5 V 0.36 0.5 5.5 V 0.36 0.5 5.5 V ±0.1 ±1 5.5 V 5.5 V UNIT 2 0.6 V µA 40 µA 1.6 mA VI = VCC or GND 5V 3 † This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. pF timing characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX fclock Clock frequency tw Pulse duration tsu Setup time, data before CLK↑ th Hold time, data after CLK↑ MIN 145 POST OFFICE BOX 655303 PRE or CLR low 5 7 CLK 5 7 Data 3 4 PRE or CLR inactive 0 0.5 1 1 • DALLAS, TEXAS 75265 MAX UNIT 85 MHz ns ns ns 3 
  
               
 SCAS722 − OCTOBER 2003 switching characteristics over recommended operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH FROM (INPUT) TO (OUTPUT) PRE or CLR Q or Q CLK Q or Q tPHL MIN TA = 25°C TYP MAX MIN MAX 145 210 1 5.5 9.5 85 1 11.5 1 6 10 1 12.5 1 7.5 11 1 14 1 6 10 1 12 UNIT MHz ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 4 TEST CONDITIONS Power dissipation capacitance CL = 50 pF, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz TYP 45 UNIT pF 
  
               
 SCAS722 − OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC 500 Ω From Output Under Test CL = 50 pF (see Note A) S1 Open 500 Ω TEST S1 tPLH/tPHL Open tw LOAD CIRCUIT 3V 3V Input 1.5 V 0V VOLTAGE WAVEFORMS tPHL tPLH VOH 50% VCC VOL 50% VCC 3V Timing Input tPLH tPHL Out-of-Phase Output 1.5 V 1.5 V 0V In-Phase Output 1.5 V Input VOH 50% VCC VOL 50% VCC 1.5 V th tsu 0V 3V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) SN74ACT74MDREP ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 SACT74MEP V62/04725-01XE ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 SACT74MEP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of