SN74ALVCH16500DL

www.ti.com SN74ALVCH16500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES023I – JULY 1995 – REVISED OCTOBER 2004 FEATURES • • • • • • • Member of the Texas Instruments Widebus™ Family EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process UBT™ (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-UP Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages DESCRIPTION This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the high-to-low transition of CLKAB. Output-enable OEAB is active high. When OEAB is high, the B-port outputs are active. When OEAB is low, the B-port outputs are in the high-impedance state. DGG OR DL PACKAGE (TOP VIEW) OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 GND CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA GND xxxxxx Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active high, and OEBA is active low). To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pullup resistor, and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16500 is characterized for operation from -40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, EPIC, UBT are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1995–2004, Texas Instruments Incorporated SN74ALVCH16500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES023I – JULY 1995 – REVISED OCTOBER 2004 FUNCTION TABLE (1) INPUTS (1) (2) (3) OEAB LEAB CLKAB A OUTPUT B L X X X Z H H X L L H H X H H H L ↓ L L H L ↓ H H H L H X B0 (2) H L L X B0 (3) A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low Output level before the indicated steady-state input conditions were established LOGIC SYMBOL(1) OEAB CLKAB LEAB 1 55 2 27 OEBA CLKBA LEBA A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 (1) 2 30 28 3 EN1 2C3 C3 G2 EN4 5C6 C6 G5 3D 1 1 4 1 6D 54 5 52 6 51 8 49 9 48 10 47 12 45 13 44 14 43 15 42 16 41 17 40 19 38 20 37 21 36 23 34 24 33 26 31 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 This symbol is in accordance with ANSI/EEEE Std 91-1984 and IEC Publication 617-12. SN74ALVCH16500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES023I – JULY 1995 – REVISED OCTOBER 2004 LOGIC DIAGRAM (POSITIVE LOGIC) 1 OEAB 55 CLKAB 2 LEAB 28 LEBA 30 CLKBA 27 OEBA 3 A1 1D C1 CLK 54 B1 1D C1 CLK To 17 Other Channels 3 SN74ALVCH16500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES023I – JULY 1995 – REVISED OCTOBER 2004 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage range MIN MAX -0.5 4.6 Except I/O ports (2) -0.5 4.6 I/O ports (2) (3) -0.5 VCC + 0.5 -0.5 VCC + 0.5 UNIT V VI Input voltage range VO Output voltage range (2) (3) IIK Input clamp current VI < 0 -50 mA IOK Output clamp current VO < 0 -50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through each VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) DGG package 64 DL package 56 -65 150 V V °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. This value is limited to 4.6 V maximum. The package thermal impedance is calculated in accordance with JESD 51. RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage VIH High-level input voltage VCC = 1.65 V to 1.95 V MIN MAX 1.65 3.6 Low-level input voltage VI Input voltage VO Output voltage IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature (1) 4 V 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 V 0.35 × VCC VCC = 1.65 V to 1.95 V VIL UNIT VCC = 2.3 V to 2.7 V 0.7 VCC = 2.7 V to 3.6 V 0.8 V 0 VCC V 0 VCC V VCC = 1.65 V -4 VCC = 2.3 V -12 VCC = 2.7 V -12 VCC = 3 V -24 VCC = 1.65 V 4 VCC = 2.3 V 12 VCC = 2.7 V 12 VCC = 3 V 24 -40 mA mA 10 ns/V 85 °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. SN74ALVCH16500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES023I – JULY 1995 – REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = -100 µA 1.65 V to 3.6 V IOH = -6 mA 2.3 V 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = -24 mA 3V 2 IOL = 100 µA V 1.65 V to 3.6 V 0.2 1.65 V 0.45 IOL = 6 mA 2.3 V 0.4 2.3 V 0.7 IOL = 24 mA 2.7 V 0.4 3V 0.55 ±5 VI = VCC or GND 3.6 V VI = 0.58 V 1.65 V 25 VI = 1.07 V 1.65 V -25 VI = 0.7 V 2.3 V 45 VI = 1.7 V 2.3 V -45 VI = 0.8 V 3V 75 3V -75 VI = 2 V VI = 0 to 3.6 V (2) IOZ (3) VO = VCC or GND ICC VI = VCC or GND, IO = 0 ∆ICC One input at VCC - 0.6 V, Other inputs at VCC or GND UNIT 1.2 IOL = 4 mA IOL = 12 mA II(hold) MAX VCC - 0.2 1.65 V IOH = -12 mA II MIN TYP (1) IOH = -4 mA VOH VOL VCC V µA µA 3.6 V ±500 3.6 V ±10 µA 3.6 V 40 µA 3 V to 3.6 V 750 µA Ci Control inputs VI = VCC or GND 3.3 V 4 pF Cio A or B ports 3.3 V 8 pF (1) (2) (3) VO = VCC or GND All typical values are at VCC = 3.3 V, TA = 25°C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. For I/O ports, the parameter IOZ includes the input leakage current. 5 SN74ALVCH16500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES023I – JULY 1995 – REVISED OCTOBER 2004 TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3) VCC = 1.8 V MIN MAX fclock tw tsu Setup time (1) 150 150 150 3.3 3.3 3.3 CLK high or low (1) 3.3 3.3 3.3 Data before CLK↓ (1) 1.7 1.4 1.3 CLK high (1) 1.1 1 1 CLK low (1) 1.9 1.6 1.4 (1) 1.7 1.6 1.3 CLK high (1) 2 1.8 1.5 CLK low (1) 1.6 1.5 1.2 Data after LE↓ UNIT MIN MAX (1) Data before LE↓ Hold time MIN MAX LE high Data after CLK↓ th MIN MAX (1) Clock frequency Pulse duration VCC = 2.5 V VCC = 3.3 V VCC = 2.7 V ± 0.2 V ± 0.3 V MHz ns ns ns This information was not available at the time of publication. SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3) FROM (INPUT) PARAMETER TO (OUTPUT) VCC = 1.8 V MIN A or B B or A LEAB or LEBA CLKAB or CLKBA (1) TYP (1) fmax tpd VCC = 2.5 V ± 0.2 V A or B MIN MAX 150 VCC = 2.7 V MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 (1) 1 5.1 4.7 (1) 1 5.9 (1) 1 6.6 MHz 1 3.9 5.5 1 4.7 6.6 1.1 5.5 ns ten OEAB B (1) 1 5.7 5.4 1 4.6 ns tdis OEAB B (1) 1 6.1 5.7 1.5 5 ns 1 6.2 6.2 1 5.2 ns 1 5.4 4.6 1 4.3 ns ten OEBA A (1) tdis OEBA A (1) This information was not available at the time of publication. OPERATING CHARACTERISTICS TA = 25°C PARAMETER Cpd (1) 6 Power dissipation capacitance TEST CONDITIONS Outputs enabled Outputs disabled CL = 50 pF, f = 10 MHz This information was not available at the time of publication. VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP (1) 40 51 (1) 6 6 UNIT pF SN74ALVCH16500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES023I – JULY 1995 – REVISED OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 2 × VCC S1 1 kΩ From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 30 pF (see Note A) 1 kΩ S1 Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 7 SN74ALVCH16500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES023I – JULY 1995 – REVISED OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 30 pF (see Note A) 500 Ω S1 Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 8 SN74ALVCH16500 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS www.ti.com SCES023I – JULY 1995 – REVISED OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V Input 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V Output Control (low-level enabling) 1.5 V 0V tPZL 2.7 V Input 1.5 V 1.5 V 0V tPLH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ 3V 1.5 V VOL + 0.3 V VOL tPZH VOH Output Output Waveform 1 S1 at 6 V (see Note B) tPHL 1.5 V Output Waveform 2 S1 at GND (see Note B) tPHZ 1.5 V VOH − 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms 9 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) SN74ALVCH16500DLR ACTIVE SSOP DL 56 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ALVCH16500 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of