SN74GTLP817
GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER
SCES285E – OCTOBER 1999 – REVISED AUGUST 2001
D
D
D
D
D
D
D
D
D
D
D
D
DGV, DW, OR PW PACKAGE
(TOP VIEW)
OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
GTLP-to-LVTTL 1-to-6 Fanout Driver
LVTTL-to-GTLP 1-to-2 Fanout Driver
LVTTL Interfaces Are 5-V Tolerant
Medium-Drive GTLP Outputs (50 mA)
Reduced-Drive LVTTL Outputs
(–12 mA/12 mA)
Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
Ioff and Power-Up 3-State Support Hot
Insertion
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
AI
AO1
GNDT
AO2
VCC
AO3
GNDT
AO4
VCC
AO5
GNDT
AO6
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
GNDT
OEAB
BO1
GNDG
VREF
GNDG
ERC
BO2
GNDG
BI
OEBA
GNDT
description
The SN74GTLP817 is a medium-drive fanout driver that provides LVTTL-to-GTLP and GTLP-to-LVTTL
signal-level translation. The device provides a high-speed interface between cards operating at LVTTL logic
levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard
TTL or LVTTL) backplane operation is a direct result of GTLP reduced output swing ( VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4
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SN74GTLP817
GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER
SCES285E – OCTOBER 1999 – REVISED AUGUST 2001
recommended operating conditions (see Notes 4 through 7)
VCC
Supply voltage
VTT
Termination voltage
VREF
Reference voltage
VI
Input voltage
VIH
High-level input voltage
MIN
NOM
MAX
UNIT
3.15
3.3
3.45
V
GTL
1.14
1.2
1.26
GTLP
1.35
1.5
1.65
GTL
0.74
0.8
0.87
GTLP
0.87
1
1.1
VCC
VTT
5.5
V
VCC
5.5
V
BI
AI, OE
BI
ERC
AI, OE
VREF+0.05
VCC–0.6
Low-level input voltage
IIK
IOH
Input clamp current
GND
ERC
AI, OE
High-level output current
IOL
Low level output current
Low-level
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
TA
Power-up ramp rate
V
2
BI
VIL
V
VREF–0.05
0.6
V
0.8
–18
mA
AO port
–12
mA
AO port
12
BO port
50
Outputs enabled
10
–40
ns/V
µs/V
20
Operating free-air temperature
mA
85
°C
NOTES: 4. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5. Normal connection sequence is GND first and VCC = 3.3 V, I/O, control inputs, VTT, VREF (any order) last.
6. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
7. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT.
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5
SN74GTLP817
GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER
SCES285E – OCTOBER 1999 – REVISED AUGUST 2001
electrical characteristics over recommended operating free-air temperature range for GTLP
(unless otherwise noted)
PARAMETER
VIK
VOH
AO port
AO port
TEST CONDITIONS
II
BI, AI, OE, ERC
AO port
IOZH
BO port
AO port
IOZL
ICC
∆ICC‡
Ci
Co
BO port
AO or BO port
AI, OE
AI, OE, ERC
BI
AO port
BO port
TYP†
MAX
UNIT
–1.2
V
VCC = 3.15 V,
VCC = 3.15 V to 3.45 V,
II = –18 mA
IOH = –100 µA
VCC = 3.15 V
IOH = –100 µA
IOH = –6 mA
VCC = 3.15 V to 3.45 V,
IOH = –12 mA
IOL = 100 µA
0.2
VCC = 3.15 V
IOL = 100 µA
IOL = 6 mA
IOL = 12 mA
IOL = 100 µA
0.5
VOL
BO port
MIN
VCC = 3.15 V
VCC–0.2
VCC–0.2
V
2.4
2.2
0.2
0.4
IOL = 40 mA
IOL = 50 mA
VCC = 3.45 V
VCC = 3
3.45
45 V
VCC = 3
3.45
45 V
VCC = 3.45 V, IO = 0,
VI (AI or control input) = VCC or GND,
VI (BI input) = VTT or GND
V
0.2
0.5
0.55
VI = 0 or 5.5 V
±5
VO = VCC
10
VO = 1.5 V
5
VO = GND
–10
VO = 5.5 V
Outputs high
–5
Outputs low
10
Outputs disabled
10
µA
µA
µA
10
VCC = 3.45 V, One A-port or control input at VCC – 0.6 V,
Other A-port or control inputs at VCC or GND
1
VI = VCC or 0
VI = VTT or 0
VO = VCC or 0
VO = VTT or 0
4
4.4
3.5
3.9
4
4.5
5
5.4
mA
mA
pF
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the increase in supply current for each input that is at the specified LVTTL voltage level rather than VCC or GND.
hot-insertion specifications for A port over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Ioff
IOZPU
VCC = 0,
VCC = 0 to 1.5 V,
VI or VO = 0 to 5.5 V
VO = 0.5 V to 3 V,
10
µA
OE = 0
±30
µA
IOZPD
VCC = 1.5 V to 0,
VO = 0.5 V to 3 V,
OE = 0
±30
µA
hot-insertion specifications for B port over recommended operating free-air temperature range
PARAMETER
6
TEST CONDITIONS
Ioff
IOZPU
VCC = 0,
VCC = 0 to 1.5 V,
VI or VO = 0 to 1.5 V
VO = 0.5 V to 1.5 V,
IOZPD
VCC = 1.5 V to 0,
VO = 0.5 V to 1.5 V,
POST OFFICE BOX 655303
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MIN
MAX
UNIT
10
µA
OE = 0
±30
µA
OE = 0
±30
µA
SN74GTLP817
GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER
SCES285E – OCTOBER 1999 – REVISED AUGUST 2001
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE†
tPLH
tPHL
AI
BO
Slow
tPLH
tPHL
AI
BO
Fast
ten
tdis
OEAB
BO
Slow
ten
tdis
OEAB
BO
Fast
tr
Ri time,
Rise
ti
B outputs
t t (20% to
t 80%)
tf
F ll time,
Fall
ti
B outputs
t t (80% to
t 20%)
tPLH
tPHL
ten
tdis
MIN
TYP‡
3
6
1.8
4.7
2
5
1.5
4.2
3
6.1
2
4.7
2.1
6
1.5
4.7
Slow
2.5
Fast
1.4
Slow
1.7
Fast
1
BI
AO
–
OEBA
AO
–
MAX
UNIT
ns
ns
ns
ns
ns
ns
2.3
6
1.9
4.7
1.1
6.3
1.2
5
ns
ns
† Slow (ERC = VCC) and Fast (ERC = GND)
‡ All typical values are at VCC = 3.3 V, TA = 25°C.
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7
SN74GTLP817
GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER
SCES285E – OCTOBER 1999 – REVISED AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
1.5 V
6V
500 Ω
From Output
Under Test
S1
Open
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 50 pF
(see Note A)
500 Ω
25 Ω
S1
Open
6V
GND
From Output
Under Test
Test
Point
CL = 30 pF
(see Note A)
LOAD CIRCUIT FOR BO PORTS
LOAD CIRCUIT FOR AO PORTS
3V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
VOH
1V
Output
1V
3V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(AI to BO port)
1V
1V
0V
tPLH
1.5 V
1.5 V
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLZ
3V
1.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
tPHL
VOH
Output
1.5 V
tPZL
1.5 V
Input
Output
Control
1.5 V
VOL
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
VOH
VOH – 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(AO ports)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(BI to AO port)
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
8
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SN74GTLP817
GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER
SCES285E – OCTOBER 1999 – REVISED AUGUST 2001
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The preceding switching characteristics table shows the switching characteristics of the device into a lumped load
(Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation
is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a resistor inductance
capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC
circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC
load, to help the designer better understand the performance of the GTLP device in this typical backplane. See
www.ti.com/sc/gtlp for more information.
38 Ω
.25”
ZO = 70 Ω
2”
Conn.
1”
Conn.
2”
Conn.
1.5 V
19 Ω
Conn.
1”
1”
.25”
38 Ω
1.5 V
1.5 V
From Output
Under Test
1”
Rcvr
Rcvr
Rcvr
Slot 2
Slot 9
Slot 10
LL = 19 nH
Test
Point
CL = 9 pF
Drvr
Slot 1
Figure 2. Medium-Drive Test Backplane
Figure 3. Medium-Drive RLC Network
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE†
tPLH
tPHL
AI
BO
Slow
tPLH
tPHL
AI
BO
Fast
ten
tdis
OEAB
BO
Slow
ten
tdis
OEAB
BO
Fast
tr
Ri time,
Rise
ti
B outputs
t t (20% to
t 80%)
tf
F ll time,
Fall
ti
B outputs
t t (80% to
t 20%)
TYP‡
4.4
4.4
3.2
3.2
4
4.4
2.9
3.1
Slow
1.8
Fast
1
Slow
2
Fast
1.6
UNIT
ns
ns
ns
ns
ns
ns
† Slow (ERC = VCC) and Fast (ERC = GND)
‡ All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
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9
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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