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SN54HC132
SN74HC132
SCLS034G – DECEMBER 1982 – REVISED JUNE 2016
SNx4HC132 Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
The SNx4HC132 device functions as a NAND gate,
but because of the Schmitt action, it has different
input threshold levels for positive and negative going
signals. The SNx4HC132 devices perform the
Boolean
function
Y = A • B or Y = A + B in positive logic.
1
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive up to 10 LSTTL Loads
Low Power Consumption, 20-µA Maximum ICC
Typical tpd = 14 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Maximum
Operation from Very Slow Input Transitions
Temperature-Compensated Threshold Levels
High Noise Immunity
Same Pinouts as SN74HC00
2 Applications
•
•
•
•
Electronic Points-of-Sale
Telecom Infrastructure
Network Switches
Tests and Measurements
These circuits are temperature compensated and can
be triggered from the slowest of input ramps and still
give clean jitter-free output signals.
Device Information(1)
PACKAGE
(PINS)
PART NUMBER
BODY SIZE (NOM)
SN54HC132J
CDIP (14)
19.56 mm × 6.67 mm
SN74HC132D
SOIC (14)
4.90 mm × 3.91 mm
SN74HC132N
PDIP (14)
19.30 mm × 6.35 mm
SN54HC132FK
LCCC (20)
8.89 mm × 8.89 mm
SN54HC132W
CFP (14)
9.21 mm × 5.97 mm
SN74HC132PW
TSSOP (14)
5.00 mm × 4.40 mm
SN74HC132NS
SO (14)
10.30 mm × 5.30 mm
SN74HC132DB
SSOP (14)
6.20 mm × 5.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
A
Y
B
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54HC132
SN74HC132
SCLS034G – DECEMBER 1982 – REVISED JUNE 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
6
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information .................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 8
9
Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
9.2 Typical Application ................................................... 9
10 Power Supply Recommendations ..................... 10
11 Layout................................................................... 10
11.1 Layout Guidelines ................................................. 10
11.2 Layout Example .................................................... 10
12 Device and Documentation Support ................. 11
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
11
11
11
11
11
11
11
13 Mechanical, Packaging, and Orderable
Information ........................................................... 11
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (November 2004) to Revision G
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Removed Ordering Information table, see POA at the end of the data sheet........................................................................ 1
2
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Copyright © 1982–2016, Texas Instruments Incorporated
Product Folder Links: SN54HC132 SN74HC132
SN54HC132
SN74HC132
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SCLS034G – DECEMBER 1982 – REVISED JUNE 2016
5 Pin Configuration and Functions
D, DB, N, NS, J, W, or PW Package
14-Pin SOIC, SSOP, PDIP, SO, or TSSOP
Top View
1B
1A
NC
VCC
4B
3
2
1
20
19
FK Package
20-Pin LCCC
Top View
VCC
1B
2
13
4B
1Y
3
12
4A
2A
4
11
4Y
1Y
4
18
4A
2B
5
10
3B
NC
5
17
NC
2Y
6
9
3A
2A
6
16
4Y
GND
7
8
3Y
NC
7
15
NC
2B
8
14
3B
3A
3Y
9
2Y
GND
NC
Not to scale
13
14
12
1
10
11
1A
Not to scale
Pin Functions (1)
PIN
SOIC, SSOP,
PDIP, SO,
TSSOP
LCCC
1A
1
2
I
1A Input
1B
2
3
I
1B Input
1Y
3
4
O
1Y Output
2A
4
6
I
2A Input
2B
5
8
I
2B Input
2Y
6
9
O
2Y Output
3A
9
13
I
3A Input
3B
10
14
I
3B Input
3Y
8
12
O
3Y Output
4A
12
18
I
4A Input
4B
13
19
I
4B Input
4Y
11
16
O
4Y Output
GND
7
10
—
Ground Pin
NC
—
1, 5, 7, 11, 15,
17
—
No Connection
VCC
14
20
—
Power Pin
NAME
(1)
I/O
DESCRIPTION
NC – no connection
Copyright © 1982–2016, Texas Instruments Incorporated
Product Folder Links: SN54HC132 SN74HC132
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SN54HC132
SN74HC132
SCLS034G – DECEMBER 1982 – REVISED JUNE 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
(2)
MIN
MAX
UNIT
–0.5
7
V
IIK
Input clamp current
VI < 0 or VI > VCC
±20
mA
IOK
Output clamp current (2)
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
Continuous current through VCC or GND
±50
mA
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
See
(1)
MIN
NOM
MAX
VCC
Supply voltage
2
5
6
V
VI
Input voltage
0
VCC
V
VO
Output voltage
V
TA
(1)
Operating free-air temperature
0
VCC
SN54HC132
–55
125
SN74HC132
–40
85
UNIT
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs.
6.4 Thermal Information
SN74HC132
THERMAL METRIC
(1)
D
(SOIC)
DB
(SSOP)
N
(PDIP)
NS
(SO)
PW
(TSSOP)
UNIT
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance (2)
84.3
99.1
50.9
84.3
113.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
44.8
51.3
38.2
42.2
42.8
°C/W
RθJB
Junction-to-board thermal resistance
38.5
46.3
30.8
43.0
54.8
°C/W
ψJT
Junction-to-top characterization parameter
13.9
17.7
23.1
13.5
4.0
°C/W
ψJB
Junction-to-board characterization parameter
38.2
45.8
30.7
42.7
54.3
°C/W
(1)
(2)
4
For more information about traditional and new thermal metrics, see the application report, Semiconductor and IC Package Thermal
Metrics.
The package thermal impedance is calculated in accordance with JESD 51-7.
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SCLS034G – DECEMBER 1982 – REVISED JUNE 2016
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VT+
VT−
VT+ – VT−
IOH = –20 µA
VCC
VI = VIH or VIL
IOH = –4 mA
SN54HC132
TYP
2V
0.7
1.2
1.5
1.55
2.5
3.15
6V
2.1
3.3
4.2
2V
0.3
0.6
1
4.5 V
0.9
1.6
2.45
6V
1.2
2
3.2
2V
0.2
0.6
1.2
4.5 V
0.4
0.9
2.1
6V
0.5
1.3
2.5
2V
1.9
1.998
4.5 V
4.4
4.499
6V
5.9
5.999
3.98
4.3
4.5 V
3.7
SN74HC132
SN54HC132
5.48
6V
SN74HC132
IOL = 20 µA
VI = VIH or VIL
IOL = 4 mA
SN54HC132
0.002
0.1
4.5 V
0.001
0.1
6V
0.001
0.1
0.17
0.26
4.5 V
0.4
0.15
6V
SN54HC132,
SN74HC132
VI = VCC or 0, IO = 0
SN54HC132
±0.1
6V
±100
±1000
nA
2
6V
40
SN74HC132
Ci
0.26
0.4
TA = 25°C
ICC
V
0.33
TA = 25°C
VI = VCC or 0
V
0.33
SN74HC132
II
V
5.34
TA = 25°C
SN54HC132
V
5.2
SN74HC132
IOL = 5.2 mA
V
5.8
2V
TA = 25°C
VOL
UNIT
3.84
TA = 25°C
IOH = –5.2 mA
MAX
4.5 V
TA = 25°C
VOH
MIN
µA
20
2 V to 6 V
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3
10
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pF
5
SN54HC132
SN74HC132
SCLS034G – DECEMBER 1982 – REVISED JUNE 2016
www.ti.com
6.6 Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 3)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
VCC
TA
MIN
TYP
2V
SN54HC132
186
SN74HC132
156
TA = 25°C
60
TA = 25°C
tpd
A or B
Y
4.5 V
18
37
31
14
28
SN54HC132
95
TA = 25°C
4.5 V
8
15
SN54HC132
22
SN74HC132
19
TA = 25°C
6V
75
110
SN74HC132
Any
21
27
TA = 25°C
tt
ns
32
SN74HC132
2V
25
SN74HC132
SN54HC132
UNIT
120
SN54HC132
TA = 25°C
6V
MAX
6
ns
13
SN54HC132
19
SN74HC132
16
6.7 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per gate
TYP
No load
20
UNIT
pF
60
30
50
25
40
20
tt (ns)
tPD (ns)
6.8 Typical Characteristics
30
20
15
10
10
5
CL=50pF
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VCC (V)
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5.5
6.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VCC (V)
C002
Figure 1. Propagation Delay vs VCC
6
CL=50pF
0
5.5
6.0
C001
Figure 2. Transition Time vs VCC
Copyright © 1982–2016, Texas Instruments Incorporated
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SCLS034G – DECEMBER 1982 – REVISED JUNE 2016
7 Parameter Measurement Information
From Output
Under Test
Test
Point
Input
VCC
50%
50%
0V
CL = 50 pF
(see Note A)
tPLH
In-Phase
Output
LOAD CIRCUIT
tPHL
90%
50%
10%
90%
tr
Input
50%
10%
90%
tPHL
VCC
90%
50%
10% 0 V
tr
Out-of-Phase
Output
tPLH
90%
50%
10%
tf
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOH
50%
10%
VOL
tf
50%
10%
90%
tf
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time, with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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SN54HC132
SN74HC132
SCLS034G – DECEMBER 1982 – REVISED JUNE 2016
www.ti.com
8 Detailed Description
8.1 Overview
The SNx4HC132 is a quadruple 2-input positive-NAND gate with low drive that produces slow rise and fall times.
This reduces ringing on the output signal.
Each circuit functions as a NAND gate, but because of the Schmitt action, it has different input threshold levels
for positive- and negative-going signals.
These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give
clean, jitter-free output signals.
8.2 Functional Block Diagram
A
Y
B
Figure 4. Logic Diagram (Positive Logic)
8.3 Feature Description
The SNx4HC132 has a wide operating range of 2 V to 6 V. The SNx4HC132 also has a low power consumption
where the maximum ICC is 20 µA.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SNx4HC132.
Table 1. Function Table (Each Gate)
INPUTS
8
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A
B
OUTPUT
Y
H
H
L
L
X
H
X
L
H
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SCLS034G – DECEMBER 1982 – REVISED JUNE 2016
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74HC132 is a low-drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates minimize overshoot and undershoot on the
outputs. The inputs can accept voltages to VCC. The current consumption of the device is low with maximum
20-µA ICC.
9.2 Typical Application
3.3- or 5-V Accessory
5-V Regulated
0.1 µF
Figure 5. Typical Application Diagram
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads, so
consider routing and load conditions to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table.
– For specified high and low levels, see VIH and VIL in the Recommended Operating Conditions table.
2. Recommend Output Conditions:
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs must not be pulled above VCC.
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SN54HC132
SN74HC132
SCLS034G – DECEMBER 1982 – REVISED JUNE 2016
www.ti.com
Typical Application (continued)
9.2.3 Application Curve
AC132
HC132
AHC132
Figure 6. Switching Characteristics Comparison
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply-voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply,
0.1 µF is recommended. If there are multiple VCC pins then a 0.01 µF or a 0.022 µF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 µF and a
1 µF are commonly used in parallel. The bypass capacitor must be installed as close to the power pin as
possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs must not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins must not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they are tied to GND or
VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it disables the outputs section of the part when asserted.
This does not disable the input section of the I/Os so they also cannot float when disabled.
11.2 Layout Example
Vcc
Unused Input
Input
Output
Output
Unused Input
Input
Figure 7. Layout Diagram
10
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SCLS034G – DECEMBER 1982 – REVISED JUNE 2016
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
Implications of Slow or Floating CMOS Inputs (SCBA004)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54HC132
Click here
Click here
Click here
Click here
Click here
SN74HC132
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1982–2016, Texas Instruments Incorporated
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11
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-89845022A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
596289845022A
SNJ54HC
132FK
5962-8984502CA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8984502CA
SNJ54HC132J
5962-8984502DA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8984502DA
SNJ54HC132W
5962-8984502VCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8984502VC
A
SNV54HC132J
5962-8984502VDA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8984502VD
A
SNV54HC132W
SN54HC132J
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN54HC132J
SN74HC132D
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC132
SN74HC132DBR
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC132
SN74HC132DBRG4
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC132
SN74HC132DE4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC132
SN74HC132DR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC132
SN74HC132DRE4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC132
SN74HC132DRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC132
SN74HC132DT
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC132
SN74HC132DTE4
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC132
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Aug-2018
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74HC132N
ACTIVE
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC132N
SN74HC132NE4
ACTIVE
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC132N
SN74HC132NSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC132
SN74HC132NSRG4
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC132
SN74HC132PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC132
SN74HC132PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC132
SN74HC132PWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC132
SN74HC132PWT
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC132
SNJ54HC132FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
596289845022A
SNJ54HC
132FK
SNJ54HC132J
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8984502CA
SNJ54HC132J
SNJ54HC132W
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8984502DA
SNJ54HC132W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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