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SN54HC32, SN74HC32
SCLS200E – DECEMBER 1982 – REVISED JULY 2016
SNx4HC32 Quadruple 2-Input Positive-OR Gates
1 Features
3 Description
•
•
•
•
•
•
The SNx4HC32 devices contain four independent
2-input OR gates. They perform the boolean function
Y = A • B or Y = A + B in positive logic.
1
Wide Operating Voltage Range: 2 V to 6 V
Outputs Can Drive Up to 10 LSTTL Loads
Low Power Consumption ICC: 20 µA (Maximum)
Typical tpd: 8 ns
±4-mA Output Drive at 5 V
Low Input Current: 1 µA (Maximum)
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN54HC32J
CDIP (14)
19.94 mm × 7.62 mm
SN54HC32W
CFP (14)
9.21 mm × 7.11 mm
2 Applications
SN54HC32FK
LCCC (20)
8.89 mm × 8.89 mm
•
•
•
•
•
•
•
•
•
SN74HC32D
SOIC (14)
4.90 mm × 3.91 mm
SN74HC32DB
SSOP (14)
6.20 mm × 5.30 mm
SN74HC32N
PDIP (14)
19.30 mm × 6.35 mm
SN74HC32NS
SO (14)
10.30 mm × 5.30 mm
SN74HC32PW
TSSOP (14)
5.00 mm × 4.40 mm
Education
Toys
Musical Instruments
Medical Healthcare and Fitness
Grid Infrastructure
Electronic Point of Sale
Test and Measurement
Factory Automation and Control
Building Automation
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
A
B
Y
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54HC32, SN74HC32
SCLS200E – DECEMBER 1982 – REVISED JULY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
5
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings: SN74HC32 .........................................
Recommended Operating Conditions.......................
Thermal Information: SN54HC32..............................
Thermal Information: SN74HC32..............................
Electrical Characteristics..........................................
Switching Characteristics.........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8.1 Overview .................................................................. 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description .................................................. 9
8.4 Device Functional Modes ......................................... 9
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application .................................................. 10
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 12
12 Device and Documentation Support ................. 13
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13
13
13
13 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (August 2003) to Revision E
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Removed Ordering Information table ..................................................................................................................................... 1
•
Updated values in the Thermal Information tables to align with JEDEC standards............................................................... 5
2
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SCLS200E – DECEMBER 1982 – REVISED JULY 2016
5 Pin Configuration and Functions
D, DB, J, N, NS, PW, W Package
14-Pin SOIC, SSOP, CDIP, PDIP, SOP, TSSOP, CFP
Top View
1B
1A
NC
VCC
4B
3
2
1
20
19
FK Package
20-Pin LCCC
Top View
1B
2
13
4B
1Y
3
12
4A
2A
4
11
4Y
1Y
4
18
4A
2B
5
10
3B
NC
5
17
NC
2Y
6
9
3A
2A
6
16
4Y
GND
7
8
3Y
NC
7
15
NC
2B
8
14
3B
3A
3Y
NC
GND
2Y
9
Not to scale
13
VCC
12
14
11
1
10
1A
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
D, DB, J, N,
NS, PW, W
FK
1A
1
2
I
Gate 1 input A
1B
2
3
I
Gate 1 input B
1Y
3
4
O
Gate 1 output
2A
4
6
I
Gate 2 input A
2B
5
8
I
Gate 2 input B
2Y
6
9
O
Gate 2 output
3A
9
13
I
Gate 3 input A
3B
10
14
I
Gate 3 input B
3Y
8
12
O
Gate 3 output
4A
12
18
I
Gate 4 input A
4B
13
19
I
Gate 4 input B
4Y
11
16
O
Gate 4 output
GND
7
10
—
Ground
NC
—
1, 5, 7,
11, 15, 17
—
No internal connection
VCC
14
20
—
Power supply
NAME
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SCLS200E – DECEMBER 1982 – REVISED JULY 2016
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage range
(2)
MIN
MAX
UNIT
–0.5
7
V
IIK
Input clamp current
VI < 0 or VI > VCC
±20
mA
IOK
Output clamp current (2)
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
Continuous current through VCC or GND
±50
mA
TJ
Operating virtual junction temperature
150
°C
Tstg
Storage temperature range
150
°C
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings: SN74HC32
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±750
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
MIN
NOM
MAX
2
5
6
VCC = 4.5 V
3.15
0.5
VCC = 4.5 V
1.35
VCC = 6 V
VI
Input voltage
VO
Output voltage
TA
(1)
4
Input transition rise or fall time
Operating free-air temperature
V
1.8
0
0
VCC = 2 V
∆t/∆v
V
4.2
VCC = 2 V
Low-level input voltage
V
1.5
VCC = 6 V
VIL
UNIT
VCC
V
VCC
V
1000
VCC = 4.5 V
500
VCC = 6 V
400
SN54HC32
–55
125
SN74HC32
–40
85
ns
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to Implications of Slow or Floating
CMOS Inputs application report.
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SCLS200E – DECEMBER 1982 – REVISED JULY 2016
6.4 Thermal Information: SN54HC32
SN54HC32
THERMAL METRIC (1)
CDIP (J)
CFP (W)
LCCC (FK)
14 PINS
14 PINS
20 PINS
UNIT
—
—
—
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
54.9
88.3
61
°C/W
RθJB
Junction-to-board thermal resistance
80.1
156
59.6
°C/W
ψJT
Junction-to-top characterization parameter
—
—
—
°C/W
ψJB
Junction-to-board characterization parameter
—
—
—
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
25.1
15.2
11.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: SN74HC32
SN74HC32
THERMAL METRIC
(1)
SOIC (D)
SSOP (DB)
PDIP (N)
SOP (NS)
TSSOP (PW)
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient
thermal resistance
90.1
105.4
54.9
88.8
119.6
°C/W
RθJC(top)
Junction-to-case (top)
thermal resistance
50.3
57.3
42.5
46.5
48.4
°C/W
RθJB
Junction-to-board
thermal resistance
44.4
52.7
34.7
47.6
61.3
°C/W
ψJT
Junction-to-top
characterization parameter
17.9
22.6
27.9
16.8
5.6
°C/W
ψJB
Junction-to-board
characterization parameter
44.1
52.2
34.6
47.2
60.7
°C/W
RθJC(bot)
Junction-to-case (bottom)
thermal resistance
—
—
—
—
—
°C/W
(1)
6.6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –20 µA
VOH
VI = VIH or VIL
IOH = –4 mA, VCC = 4.5 V
IOH = –5.2 mA, VCC = 6 V
MIN
TYP
VCC = 2 V
1.9
1.998
VCC = 4.5 V
4.4
4.499
VCC = 6 V
5.9
5.999
TA = 25°C
3.98
4.3
SN54HC32
3.7
SN74HC32
3.84
TA = 25°C
5.48
SN54HC32
5.2
SN74HC32
5.34
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MAX
UNIT
V
5.8
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SCLS200E – DECEMBER 1982 – REVISED JULY 2016
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Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOL = 20 µA
VOL
VI = VIH or VIL
IOL = 4 mA, VCC = 4.5 V
MIN
TYP
MAX
VCC = 2 V
0.002
0.1
VCC = 4.5 V
0.001
0.1
VCC = 6 V
0.001
0.1
TA = 25°C
0.17
0.26
SN54HC32
0.4
SN74HC32
0.33
TA = 25°C
IOL = 5.2 mA, VCC = 6 V
II
VI = VCC or 0, VCC = 6 V
ICC
VI = VCC or 0, IO = 0, VCC = 6 V
Ci
VCC = 2 V to 6 V
0.15
0.4
SN74HC32
0.33
±0.1
SNx4HC32
Cpd
6.7
Power dissipation
capacitance
per gate
±100
±1000
TA = 25°C
2
SN54HC32
40
SN74HC32
V
0.26
SN54HC32
TA = 25°C
UNIT
nA
µA
20
3
TA = 25°C, no load
10
20
pF
pF
Switching Characteristics
over operating free-air temperature range (unless otherwise noted; see Figure 4)
PARAMETER
TEST CONDITIONS
MIN
TA = 25°C
VCC = 2 V
TYP
MAX
50
100
SN54HC32
150
SN74HC32
TA = 25°C
tpd
CL = 50 pF, from A or B (input)
to Y (output)
VCC = 4.5 V
VCC = 6 V
125
10
30
SN74HC32
25
8
SN54HC32
TA = 25°C
CL = 50 pF, to Y (output)
VCC = 4.5 V
95
8
SN54HC32
VCC = 6 V
6
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15
22
SN74HC32
TA = 25°C
75
110
SN74HC32
tt
17
21
38
SN54HC32
TA = 25°C
ns
25
SN74HC32
VCC = 2 V
20
SN54HC32
TA = 25°C
UNIT
ns
19
6
13
SN54HC32
19
SN74HC32
16
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SCLS200E – DECEMBER 1982 – REVISED JULY 2016
6.8 Typical Characteristics
TA = 25°C and CL = 50 pF
80
tt (max)(ns)
70
60
TA = 25oC
CL = 50 pF
40
20
10
2
0
4
5
6
Vcc
Figure 1. tt vs VCC
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7 Parameter Measurement Information
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
Figure 2. Load Current
Input
50%
10%
90%
VCC
50%
10% 0 V
90%
tr
tf
Figure 3. Input Rise and Fall Times
VCC
Input
50%
50%
0V
tPLH
In-Phase
Output
50%
10%
tPHL
90%
VOH
50%
10%
VOL
tf
90%
tr
tPHL
Out-of-Phase
Output
90%
tPLH
50%
10%
50%
10%
tf
NOTES:
90%
VOH
VOL
tr
A.
CL includes probe and test-fixture capacitance.
B.
Phase relationship between waveforms were chosen arbitrarily. All input pulses are supplied
by generators having the following characteristics:
PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C.
The outputs are measured one at a time with one input transition per measurements.
D.
tPLH and tPHL are the same as tpd.
Figure 4. Propagation Delay and Output Transition Times
8
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8 Detailed Description
8.1 Overview
The SNx4HC32 devices are quad 2-input OR gates. These devices are members of the High-Speed CMOS (HC)
logic family. The HC family of logic is optimized to operate with a 5-V supply, is low noise without characteristic
overshoot and undershoot, has low power consumption, small propagation delay, balanced propagation delay
and transition times, and operates over a wide temperature range.
8.2 Functional Block Diagram
A
Y
B
Copyright © 2016, Texas Instruments Incorporated
Figure 5. Logic Diagram (Positive Logic)
8.3 Feature Description
8.3.1 Operating Voltage Range
The SNx4HC series of devices offer a wide operating voltage range from 2 V to 6 V.
8.3.2 LSTTL Loads
The outputs of the SNx4HC series can drive up to 10 LSTTL loads.
8.3.3 Low Power Consumption
The SNx4HC32 offers low power consumption of 20 μA (maximum).
8.3.4 Output Drive Capability
At 5 V, the outputs have ±4 mA of output drive capability.
8.3.5 Low Input Current Leakage
Inputs have low input current leakage of 1 μA (maximum).
8.4 Device Functional Modes
Table 1 lists the functional modes of SNx4HC32.
Table 1. Function Table
(Each Gate)
INPUTS
OUTPUT
A
B
Y
H
X
H
X
H
H
L
L
L
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SNx4HC32 is an extremely versatile device with far more available applications than could be listed here.
The application chosen as an example is using all four OR gates in a single package to provide a four channel
output enable from a single active low enable signal (Enable). This circuit outputs a logic HIGH on all channels
when disabled (Enable is HIGH), and passes the input signals when enabled (Enable is LOW).
9.2 Typical Application
VCC
Enable
Input 1
Input 2
Input 3
Input 4
0.1 PF
Output 1
Output 2
Output 3
Output 4
Copyright © 2016, Texas Instruments Incorporated
Using a quad OR gate as a 4-channel active low enable with high output off state.
Figure 6. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads, so
routing and load conditions must be considered to prevent ringing.
The minimum output pulse time is approximately three times tpd from Switching Characteristics for the selected
VCC, device, and temperature range.
9.2.2 Detailed Design Procedure
Logic
•
•
•
All four input channels are to be enabled or disabled simultaneously
The enable signal is active low (LOW = enabled, HIGH = disabled)
All four outputs are to output logic HIGH while disabled
Inputs
•
10
Each input must follow requirements specified in Absolute Maximum Ratings:
– Avoid exceeding input voltages
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Typical Application (continued)
•
– If input voltages ratings must be exceeded, ensure that the maximum input current ratings are not
exceeded.
– Ensure that the input signals have edge rates that are equal to or faster than that listed in Recommended
Operating Conditions. Slower signals can cause incorrect behavior and possibly damage to the part.
Each output must also follow requirements in Absolute Maximum Ratings:
– Avoid bus contention by only connecting outputs together when inputs are tied together directly.
– Avoid forcing output voltages outside those specified in Absolute Maximum Ratings.
– If output voltage ratings must be exceeded, ensure that the maximum output current ratings are not
exceeded.
– Ensure that the total current output does not exceed the continuous current through VCC or GND listed in
Absolute Maximum Ratings.
9.2.3 Application Curves
Enable
Input x
Output x
Dotted lines indicate Enable signal changes
Figure 7. Application Timing Diagram
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating Conditions. Each VCC pin must have a good bypass capacitor to prevent power
disturbance. For devices with a single supply, TI recommends a 0.1-μF bypass capacitor. If there are multiple
VCC pins, TI recommends a 0.01-μF or 0.022-μF bypass capacitors for each power pin. It is acceptable to parallel
multiple bypass capacitors to reject different frequencies of noise. Two bypass capacitors of value 0.1-μF and 1μF are commonly used in parallel. For best results, install the bypass capacitor(s) as close to the power pin as
possible.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs must not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins must not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states. Specified in Absolute
Maximum Ratings are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally they are tied to GND or
VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it disables the outputs section of the part when asserted.
This does not disable the input section of the I/Os so they also cannot float when disabled.
11.2 Layout Example
Figure 8. Layout Recommendation
12
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Implications of Slow or Floating CMOS Inputs (SCBA004)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54HC32
Click here
Click here
Click here
Click here
Click here
SN74HC32
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-8404501VCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8404501VC
A
SNV54HC32J
5962-8404501VDA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8404501VD
A
SNV54HC32W
84045012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
84045012A
SNJ54HC
32FK
8404501CA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
8404501CA
SNJ54HC32J
8404501DA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
8404501DA
SNJ54HC32W
JM38510/65201B2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
JM38510/
65201B2A
JM38510/65201BCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65201BCA
JM38510/65201BDA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65201BDA
M38510/65201B2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
JM38510/
65201B2A
M38510/65201BCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65201BCA
M38510/65201BDA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
65201BDA
SN54HC32J
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN54HC32J
SN74HC32D
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC32
SN74HC32DBR
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC32
SN74HC32DE4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC32
SN74HC32DR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
HC32
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74HC32DRE4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC32
SN74HC32DRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC32
SN74HC32DT
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC32
SN74HC32N
ACTIVE
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC32N
SN74HC32NE4
ACTIVE
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74HC32N
SN74HC32NSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC32
SN74HC32PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC32
SN74HC32PWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC32
SN74HC32PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
HC32
SN74HC32PWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC32
SN74HC32PWT
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC32
SN74HC32PWTG4
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC32
SNJ54HC32FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
84045012A
SNJ54HC
32FK
SNJ54HC32J
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
8404501CA
SNJ54HC32J
SNJ54HC32W
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
8404501DA
SNJ54HC32W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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