SN74LVC138DBR

SN74LVC138 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS291B – MARCH 1993 – REVISED JULY 1995 D D D D D D D EPIC  (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C Inputs Accept Voltages to 5.5 V Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages D, DB, OR PW PACKAGE (TOP VIEW) A B C G2A G2B G1 Y7 GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 description This 3-line to 8-line decoder/demultiplexer is designed for 2.7-V to 3.6-V VCC operation. The SN74LVC138 is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder minimizes the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight input lines. Two active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. The SN74LVC138 is characterized for operation from – 40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright  1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74LVC138 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS291B – MARCH 1993 – REVISED JULY 1995 FUNCTION TABLE ENABLE INPUTS G1 G2A X X SELECT INPUTS G2B C B H X X X H X OUTPUTS A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X H H H H H H H H X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L logic symbols (alternatives)† A B C G1 1 2 3 6 4 G2A G2B 5 BIN/OCT 1 0 2 1 4 2 3 & 4 EN 5 6 7 15 14 13 12 11 10 9 7 Y0 A Y1 B Y2 C 1 G1 Y5 G2A Y6 G2B 3 6 4 5 Y7 POST OFFICE BOX 655303 G 2 0 7 1 2 & 3 4 5 6 7 † These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 0 2 Y3 Y4 DMUX 0 • DALLAS, TEXAS 75265 15 14 13 12 11 10 9 7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 SN74LVC138 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS291B – MARCH 1993 – REVISED JULY 1995 logic diagram (positive logic) 15 A 1 14 Select Inputs B C 13 3 12 10 Enable Inputs 6 9 4 7 G2A G2B Y1 2 11 G1 Y0 Y2 Y3 Data Outputs Y4 Y5 Y6 Y7 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74LVC138 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS291B – MARCH 1993 – REVISED JULY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA Maximum power dissipation at TA = 55°C (in still air): (see Note 3) D package . . . . . . . . . . . . . . . . . . . 1.3 W DB package . . . . . . . . . . . . . . . . 0.55 W PW package . . . . . . . . . . . . . . . . . 0.5 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions (see Note 4) VCC Supply voltage VIH VIL High-level input voltage VI VO Input voltage Operating Data retention only VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V Low-level input voltage Output voltage IOH High level output current High-level VCC = 2.7 V VCC = 3 V IOL Low level output current Low-level VCC = 2.7 V VCC = 3 V ∆t /∆v Input transition rise or fall rate TA Operating free-air temperature NOTE 4: Unused inputs must be held high or low to prevent them from floating. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN MAX 2 3.6 1.5 2 UNIT V V 0.8 V 0 5.5 V 0 VCC – 12 V – 24 12 24 mA mA 0 10 ns / V – 40 85 °C SN74LVC138 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS291B – MARCH 1993 – REVISED JULY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VCC† MIN to MAX TEST CONDITIONS IOH = – 100 µA VOH IOH = – 12 mA IOH = – 24 mA IOL = 100 µA MIN TYP‡ 2.7 V VCC – 0.2 2.2 3V 2.4 3V 2.2 MAX UNIT V MIN to MAX 0.2 VOL IOL = 12 mA IOL = 24 mA 2.7 V 0.4 3V 0.55 II ICC VI = 5.5 V or GND VI = VCC or GND, 3.6 V ±5 µA 3.6 V 10 µA 500 µA nICC IO = 0 Other inputs at VCC or GND One input at VCC – 0.6 V, 2.7 V to 3.6 V Co VO = VCC or GND 3.3 V † For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. ‡ All typical values are at VCC = 3.3 V, TA = 25°C. 5 V pF switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) VCC = 3.3 V ± 0.3 V TO (OUTPUT) MIN MAX 1 6.7 7.9 1 6.5 7.4 1 5.8 6.4 A or B or C tpd Y G2A or G2B VCC = 2.7 V G1 tsk(o)§ MIN UNIT MAX 1 ns ns § Skew between any two outputs of the same package switching in the same direction. This parameter is warranted but not production tested. operating characteristics, VCC = 3.3 V, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 10 MHz TYP UNIT 27 pF 5 SN74LVC138 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS291B – MARCH 1993 – REVISED JULY 1995 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 0V tPLH tPHL VOH 1.5 V 2.7 V Output Control (low-level enabling) 1.5 V 1.5 V VOL tPLZ 3V Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) 1.5 V 0V tPZL 2.7 V Output 1.5 V 1.5 V tsu Input Input 1.5 V VOL + 0.3 V VOL tPHZ tPZH 1.5 V VOH – 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. v Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 v v IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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