SN74LVC1G14-Q1
SCES865C – FEBRUARY 2015 – REVISED AUGUST 2021
SN74LVC1G14-Q1 Single Schmitt-Trigger Inverter
1 Features
3 Description
•
•
This single Schmitt-trigger inverter is designed for
1.65-V to 5.5-V VCC operation.
•
•
•
•
•
•
•
Qualified for automotive applications
AEC-Q100 qualified with the following results:
– Device temperature grade 1: –40°C to +125°C
ambient operating temperature range
– Device human-body model (HBM) ESD
classification level 2
– Device charged-device model (CDM) ESD
classification level C5
Supports 5 V VCC operation
Inputs accept voltages to 5.5 V
Maximum tpd of 4.6 ns at 3.3 V
Low power consumption, 10-µA maximum ICC
±24-mA output drive at 3.3 V
Ioff supports partial-power-down mode operation
Latch-up performance exceeds 100 mA per JESD
78, class II
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables
the outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
PACKAGE
SN74LVC1G14-Q1
2 Applications
•
•
•
•
The SN74LVC1G14-Q1 device contains one inverter
and performs the Boolean function Y = A. The device
functions as an independent inverter, but because of
Schmitt action, it may have different input threshold
levels for positive-going (VT+) and negative-going
(VT–) signals.
Body control modules
Engine control modules
Infotainment systems
Telematics
(1)
A
BODY SIZE (NOM)
SC70 (5)
2.10 mm × 2.00 mm
SON (6)
1.45 mm × 1.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
2
4
Y
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G14-Q1
www.ti.com
SCES865C – FEBRUARY 2015 – REVISED AUGUST 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics, CL = 15 pF........................ 6
6.7 Switching Characteristics, CL = 30 pF or 50 pF.......... 6
6.8 Operating Characteristics........................................... 6
6.9 Typical Characteristics................................................ 6
7 Parameter Measurement Information............................ 7
8 Detailed Description........................................................9
8.1 Overview..................................................................... 9
8.2 Functional Block Diagram........................................... 9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes............................................9
9 Application and Implementation.................................. 10
9.1 Application Information............................................. 10
9.2 Typical Application.................................................... 10
10 Power Supply Recommendations..............................11
11 Layout........................................................................... 11
11.1 Layout Guidelines....................................................11
11.2 Layout Example.......................................................11
12 Device and Documentation Support..........................12
12.1 Receiving Notification of Documentation Updates..12
12.2 Support Resources................................................. 12
12.3 Trademarks............................................................. 12
12.4 Electrostatic Discharge Caution..............................12
12.5 Glossary..................................................................12
13 Mechanical, Packaging, and Orderable
Information.................................................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (August 2019) to Revision C (August 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated the pin numbers for VCC and N.C. in the Pin Functions table for the DRY package to match the pin
configuration....................................................................................................................................................... 3
• Updated the TPD Across Temperature at 3.3 V VCC image in the Typical Characteristics ................................6
Changes from Revision A (March 2017) to Revision B (August 2019)
Page
• Added SON (6) DRY package to Device Information table................................................................................ 1
• Added DRY package pinout to Pin Configurations and Functions section ........................................................ 3
Changes from Revision * (February 2015) to Revision A (March 2017)
Page
• Changed package type to DCK (SC70) and corrected Body Size in Device Information table.......................... 1
• Deleted θJA from Absolute Maximum Ratings table........................................................................................... 4
2
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74LVC1G14-Q1
SN74LVC1G14-Q1
www.ti.com
SCES865C – FEBRUARY 2015 – REVISED AUGUST 2021
5 Pin Configuration and Functions
N.C.
A
GND
5
1
2
3
4
1
6
VCC
A
2
5
N.C.
GND
3
4
Y
N.C.
VCC
Y
Figure 5-1. DCK Package 5-Pin SC70 (Top View)
N.C. – No internal connection
See mechanical drawings for dimensions.
Figure 5-2. DRY Package 6-Pin SON Transparent
Top View
Pin Functions
PIN
DCK (SC70)
DRY (SON)
NO.
NO.
A
2
2
I
GND
3
3
—
Ground
N.C.
1
1, 5
—
No internal connection.
VCC
5
6
—
Supply or power pin
Y
4
4
O
Output
NAME
I/O
DESCRIPTION
Input
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74LVC1G14-Q1
3
SN74LVC1G14-Q1
www.ti.com
SCES865C – FEBRUARY 2015 – REVISED AUGUST 2021
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
MIN
MAX
Supply voltage
–0.5
6.5
V
voltage(2)
–0.53
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
VI
Input
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
state(2) (3)
UNIT
VO
Voltage range applied to any output in the high or low
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
150
°C
Continuous current through VCC or GND
Tstg
(1)
(2)
(3)
Storage temperature
–65
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC
Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
UNIT
±2000
V
±750
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
See(1)
VCC
Supply voltage
VI
Input voltage
VO
Output voltage
Operating
Data retention only
MIN
MAX
1.65
5.5
1.5
5.5
V
0
VCC
V
–4
VCC = 2.3 V
High-level output current
–8
–16
VCC = 3 V
–32
VCC = 1.65 V
4
VCC = 2.3 V
Low-level output current
8
16
VCC = 3 V
(1)
4
Operating free-air temperature
mA
24
VCC = 4.5 V
TA
mA
–24
VCC = 4.5 V
IOL
V
0
VCC = 1.65 V
IOH
UNIT
32
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74LVC1G14-Q1
SN74LVC1G14-Q1
www.ti.com
SCES865C – FEBRUARY 2015 – REVISED AUGUST 2021
6.4 Thermal Information
SN74LVC1G14-Q1
THERMAL
METRIC(1)
DCK (SC70)
DRY (SON)
5 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
280
264
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
66
167
°C/W
RθJB
Junction-to-board thermal resistance
67
142
°C/W
ψJT
Junction-to-top characterization parameter
2
26
°C/W
ψJB
Junction-to-board characterization parameter
66
142
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VT+
Positive-going
input threshold
voltage
VT–
Negative-going
input threshold
voltage
ΔVT
Hysteresis
(VT+ – VT–)
MIN TYP(1)
MAX
1.65 V
0.79
1.16
2.3 V
1.11
1.56
VCC
3V
1.5
1.87
4.5 V
2.16
2.74
5.5 V
2.61
3.33
1.65 V
0.39
0.64
2.3 V
0.58
0.89
3V
0.84
1.16
4.5 V
1.41
1.79
5.5 V
1.87
2.29
1.65 V
0.37
0.62
2.3 V
0.48
0.77
3V
0.56
0.87
4.5 V
0.71
1.04
0.71
1.11
5.5 V
IOL = –100 µA
VOH
1.65 V to 4.5 V
1.65 V
1.2
IOL = –8 mA
2.3 V
1.9
3V
IOL = –24 mA
VOL
4.5 V
1.65 V to 4.5 V
0.1
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.3
IOL = 24 mA
IOL = 32 mA
II
A input
4.5 V
VI = 5.5 V or GND
Ioff
VI or VO = 5.5 V
ICC
VI = 5.5 V or GND,
IO = 0
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
V
2.3
IOL = 100 µA
3V
V
V
2.4
IOL = –32 mA
IOL = 16 mA
V
VCC – 0.1
IOL = –4 mA
IOL = –16 mA
UNIT
3.8
0.4
V
0.55
0.70
0 to 5.5 V
±5
µA
0
±10
µA
1.65 V to 5.5 V
10
µA
3 V to 5.5 V
500
µA
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74LVC1G14-Q1
5
SN74LVC1G14-Q1
www.ti.com
SCES865C – FEBRUARY 2015 – REVISED AUGUST 2021
6.5 Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC
MIN TYP(1)
3.3 V
4.5
TEST CONDITIONS
Ci
VI = VCC or GND
(1)
All typical values are at VCC = 3.3 V, TA = 25°C.
MAX
UNIT
pF
6.6 Switching Characteristics, CL = 15 pF
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A
Y
tpd
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.8
9.9
1.6
5.5
1.5
4.6
0.9
4.4
ns
6.7 Switching Characteristics, CL = 30 pF or 50 pF
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A
Y
tpd
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.8
13
2
8
1.8
6.5
1.2
6
ns
6.8 Operating Characteristics
TA = 25°C
Cpd
PARAMETER
TEST CONDITIONS
Power dissipation capacitance
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
20
21
22
25
UNIT
pF
6.9 Typical Characteristics
3.8
8
3.7
7
TPD
6
TPD (ns)
TPD (ns)
3.6
3.5
3.4
3.3
5
4
3
2
3.2
1
TPD
3.1
-100
0
-50
0
50
100
Temperature (°C)
0
1
D001
Figure 6-1. TPD Across Temperature at 3.3 V VCC
6
150
2
3
VCC (V)
4
5
6
D002
Figure 6-2. TPD Across VCC at 25°C
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74LVC1G14-Q1
SN74LVC1G14-Q1
www.ti.com
SCES865C – FEBRUARY 2015 – REVISED AUGUST 2021
7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MW
1 MW
1 MW
1 MW
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH − VD
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 7-1. Load Circuit and Voltage Waveforms
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74LVC1G14-Q1
7
SN74LVC1G14-Q1
www.ti.com
SCES865C – FEBRUARY 2015 – REVISED AUGUST 2021
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
0V
VLOAD/2
VM
tPZH
VOH
Output
VM
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + VD
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VM
VOH − VD
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 7-2. Load Circuit and Voltage Waveforms
8
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74LVC1G14-Q1
SN74LVC1G14-Q1
www.ti.com
SCES865C – FEBRUARY 2015 – REVISED AUGUST 2021
8 Detailed Description
8.1 Overview
The SN74LVC1G14-Q1 device contains one Schmitt Trigger Inverter and performs the Boolean function Y = A.
The device functions as an independent inverter, but because of Schmitt Trigger action, it will have different input
threshold levels for a positive-going (Vt+) and negative-going (Vt-) signals.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuit disables the output,
preventing damaging current back-flow through the device when it is powered down.
8.2 Functional Block Diagram
A
2
4
Y
8.3 Feature Description
•
•
•
•
•
•
Wide operating voltage range
Operates from 1.65 V to 5 V VCC and Input Operation
Inputs Accept Voltages to 5.5 V
Allows down voltage translation
±24-mA Output Drive at 3.3 V
Ioff Supports Partial-Power-Down Mode Operation which allows voltages on the inputs and outputs, when VCC
is 0 V
8.4 Device Functional Modes
Table 8-1 shows the functional modes of the SN74LVC1G14-Q1 device.
Table 8-1. Function Table
INPUT
A
OUTPUT
Y
H
L
L
H
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74LVC1G14-Q1
9
SN74LVC1G14-Q1
www.ti.com
SCES865C – FEBRUARY 2015 – REVISED AUGUST 2021
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1G14-Q1 is a high drive CMOS device that can be used for a multitude of buffer type functions
where the input is slow or noisy. It can produce 24 mA of drive current at 3.3 V making it ideal for driving multiple
outputs and good for high speed applications up to 100 MHz. The inputs are 5.5-V tolerant allowing it to translate
down to VCC.
9.2 Typical Application
RF
~2.2 MΩ
SN74LVC1G14-Q1
RS
C
50 pF
~1 kΩ
C1
~32 pF
CL
16 pF
C2
~32 pF
Copyright © 2017, Texas Instruments Incorporated
Figure 9-1. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because
it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads
so routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
• Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.
• Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
• Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC .
2. Recommended Output Conditions
• Load currents should not exceed (IO max) per output and should not exceed (continuous current through
VCC or GND) total current for the part. These limits are located in the Absolute Maximum Ratings table.
• Outputs should not be pulled above VCC.
10
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74LVC1G14-Q1
SN74LVC1G14-Q1
www.ti.com
SCES865C – FEBRUARY 2015 – REVISED AUGUST 2021
9.2.3 Application Curve
10
Icc
Icc
Icc
Icc
9
8
1.8V
2.5V
3.3V
5V
Icc - mA
7
6
5
4
3
2
1
0
0
20
40
Frequency - MHz
60
80
D003
Figure 9-2. ICC vs Frequency
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply a 0.1-µF capacitor is recommended and if there are multiple VCC pins then a 0.01-µF or 0.022-µF
capacitor is recommended for each power pin. It is ok to parallel multiple bypass capacitors to reject different
frequencies of noise. 0.1-µF and 1-µF capacitors are commonly used in parallel. The bypass capacitor should be
installed as close to the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only
3 of the 4 buffer gates are used. Such input terminals should not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. Specified below are the rules that
must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high
or low bias to prevent them from floating. The logic level that should be applied to any particular unused input
depends on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or
is more convenient.
11.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
Figure 11-1. Layout Schematic
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74LVC1G14-Q1
11
SN74LVC1G14-Q1
www.ti.com
SCES865C – FEBRUARY 2015 – REVISED AUGUST 2021
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74LVC1G14-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jul-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LVC1G14QDCKRQ1
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
SJM
SN74LVC1G14QDRYRQ1
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
FE
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
