Order
Now
Product
Folder
Technical
Documents
Support &
Community
Tools &
Software
SN74LVC1G32-Q1
SCES648A – FEBRUARY 2006 – REVISED AUGUST 2019
SN74LVC1G32-Q1 Single 2-input positive-OR gate
1 Features
•
1
•
•
•
•
•
•
•
•
•
3 Description
2
Available in the small 1.45 mm
Package (DRY) with 0.5-mm Pitch
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5-V
Supports Down Translation to VCC
Max tpd of 3.6 ns at 3.3-V
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3-V
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
This single 2-input positive-OR gate is designed for
1.65-V to 5.5-V VCC operation.
The SN74LVC1G32-Q1 device performs the Boolean
function Y = A + B or Y = A • B in positive logic.
The CMOS device has high output drive while
maintaining low static power dissipation over a broad
VCC operating range.
The SN74LVC1G32-Q1 device is available in a
variety of packages, including the small DRY package
with a body size of 1.45 × 1.00 mm.
Device Information
DEVICE NAME
PACKAGE (PINS)
BODY SIZE
SN74LVC1G32QDBV
SOT-23 (5)
2.90mm × 2.80mm
SN74LVC1G32QDCK
SC70 (5)
2.00mm × 1.25mm
SN74LVC1G32QDRY
SON (6)
1.45mm × 1.00mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
AV Receiver
Blu-ray Player and Home Theater
Digital Picture Frame (DPF)
Embedded PC
IP Phone: Wireless
High-Speed Data Acquisition and Generation
Motor Control: High-Voltage
Optical Networking: Video Over Fiber and EPON
Personal Navigation Device (GPS)
Portable Media Player
Private Branch Exchange (PBX)
Server PSU
SSD: Internal and External
TV: LCD/Digital and High-Definition (HDTV)
Telecom Shelter: Power Distribution Unit (PDU),
Power Monitoring Unit (PMU), Wireless Battery
Monitoring, Remote Electrical Tilt Unit (RET),
Remote Radio Unit (RRU), Tower Mounted
Amplifier (TMA)
Video Conferencing: IP-Based HD
Vector Signal Analyzer and Generator
WiMAX and Wireless Infrastructure Equipment
Wireless Headset, Keyboard, Mouse, and
Repeater
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G32-Q1
SCES648A – FEBRUARY 2006 – REVISED AUGUST 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
4
4
5
5
6
6
6
7
7
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, CL = 15 pF ......................
Switching Characteristics, 1.8 V and 2.5V................
Switching Characteristics, 3.3 V and 5 V..................
Operating Characteristics..........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 8
Detailed Description ............................................ 10
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
10
Application and Implementation ........................ 11
9.1 Application Information............................................ 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 12
12 Device and Documentation Support ................. 13
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13
13 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (February 2006) to Revision A
Page
•
Changed data sheet format to new TI standard .................................................................................................................... 1
•
Added SON (6) DRY package to Device Information table ................................................................................................... 1
•
Added DRY Package to Pin Configuration and Functions section. ....................................................................................... 3
2
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G32-Q1
SN74LVC1G32-Q1
www.ti.com
SCES648A – FEBRUARY 2006 – REVISED AUGUST 2019
5 Pin Configuration and Functions
DBV package
5-Pin SOT-23
(Top View)
1
A
B
DCK package
5-Pin SC-70
(Top View)
VCC
5
A
1
B
2
GND
3
5
VCC
4
Y
2
GND
3
Y
4
DRY package
6-Pin SON
(Transparent Top View)
A
1
6
VCC
B
2
5
NC
GND
3
4
Y
NC = No Connect
See Mechanical drawings at the end of the data sheet for dimensions
Pin Functions
PIN
DESCRIPTION
NAME
DBV, DCK
DRY
A
1
1
Input
B
2
2
Input
GND
3
3
Ground
Y
4
4
Output
VCC
5
6
Power pin
NC
–
5
Not connected
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G32-Q1
3
SN74LVC1G32-Q1
SCES648A – FEBRUARY 2006 – REVISED AUGUST 2019
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
(2)
VI
Input voltage range
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
150
°C
150
°C
Continuous current through VCC or GND
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
6.2 ESD Ratings
PARAMETER
V(ESD)
(1)
(2)
4
Electrostatic
discharge
DEFINITION
VAUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
(1)
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
UNIT
±2000
±1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G32-Q1
SN74LVC1G32-Q1
www.ti.com
SCES648A – FEBRUARY 2006 – REVISED AUGUST 2019
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Operating
Supply voltage
Data retention only
1.65
5.5
VCC = 3 V to 3.6 V
V
2
0.7 × VCC
VCC = 1.65 V to 1.95 V
Low-level input voltage
V
1.7
VCC = 4.5 V to 5.5 V
VIL
UNIT
0.65 × VCC
VCC = 2.3 V to 2.7 V
High-level input voltage
MAX
1.5
VCC = 1.65 V to 1.95 V
VIH
MIN
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
V
0.3 × VCC
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
VCC = 1.65 V
–4
VCC = 2.3 V
–8
–16
VCC = 3 V
VCC = 4.5 V
–32
VCC = 1.65 V
4
VCC = 2.3 V
IOL
Low-level output current
Δt/Δv
8
16
VCC = 3 V
Input transition rise or fall rate
(1)
Operating free-air temperature
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
TA
mA
–24
ns/V
5
DSBGA package
–40
85
°C
All other packages
-40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6.4 Thermal Information
SN74LVC1G32-Q1
THERMAL METRIC
(1)
DBV
DCK
DRY
5 PINS
5 PINS
6 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
229
278
439
°C/W
RθJCtop
Junction-to-case (top) thermal resistance
164
93
277
°C/W
RθJB
Junction-to-board thermal resistance
62
65
271
°C/W
ψJT
Junction-to-top characterization parameter
44
2
84
°C/W
ψJB
Junction-to-board characterization parameter
62
64
271
°C/W
RθJCbot
Junction-to-case (bottom) thermal resistance
–
–
–
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G32-Q1
5
SN74LVC1G32-Q1
SCES648A – FEBRUARY 2006 – REVISED AUGUST 2019
www.ti.com
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP (1)
MIN
IOH = –100 µA
VOH
1.65 V to 5.5 V
VCC – 0.1
VCC – 0.1
1.2
1.2
IOH = –8 mA
2.3 V
1.9
1.9
2.4
2.4
2.3
2.3
3V
3.8
TYP
UNIT
MAX
V
IOH = –32 mA
4.5 V
IOL = 100 µA
1.65 V to 5.5 V
0.1
0.1
IOL = 4 mA
1.65 V
0.45
0.45
IOL = 8 mA
2.3 V
0.3
0.4
0.4
0.5
0.55
0.65
0.55
0.65
IOL = 16 mA
3.8
3V
IOL = 24 mA
IOL = 32 mA
A or B inputs
MIN
1.65 V
IOH = –24 mA
II
MAX
IOH = –4 mA
IOH = –16 mA
VOL
–40°C to 125°C
RECOMMENDED
–40°C to 85°C
VCC
4.5 V
VI = 5.5 V or GND
Ioff
VI or VO = 5.5 V
ICC
VI = 5.5 V or GND,
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
(1)
All typical values are at VCC = 3.3 V, TA = 25°C.
IO = 0
V
0 to 5.5 V
±5
±5
µA
0
±10
±25
µA
1.65 V to 5.5 V
10
10
µA
3 V to 5.5 V
500
500
µA
3.3 V
4
4
pF
6.6 Switching Characteristics, CL = 15 pF
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3)
–40°C to 85°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1.9
7.2
0.8
4.4
0.9
3.6
0.8
3.4
ns
6.7 Switching Characteristics, 1.8 V and 2.5V
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (1) (see Figure 4)
PARAMETER
tpd
(1)
6
FROM
(INPUT)
A or B
TO
(OUTPUT)
Y
–40°C to 85°C
–40°C to 125°C
RECOMMENDED
–40°C to 85°C
–40°C to 125°C
RECOMMENDED
VCC = 1.8 V
± 0.15 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 2.5 V
± 0.2 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.8
8
2.8
9
1.2
5.5
1.2
6
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G32-Q1
SN74LVC1G32-Q1
www.ti.com
SCES648A – FEBRUARY 2006 – REVISED AUGUST 2019
6.8 Switching Characteristics, 3.3 V and 5 V
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (1) (see Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A or B
Y
(1)
–40°C to 85°C
–40°C to 125°C
RECOMMENDED
–40°C to 85°C
–40°C to 125°C
RECOMMENDED
VCC = 3.3 V
± 0.3 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1.1
4.5
1
4
1
4
1
4.5
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested
6.9 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST
CONDITIONS
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
f = 10 MHz
20
20
21
22
Power dissipation capacitance
UNIT
pF
6.10 Typical Characteristics
8
6
TPD
7
5
6
TPD - ns
TPD - ns
4
3
5
4
3
2
2
1
1
TPD
0
-100
0
-50
0
50
Temperature - °C
100
150
0
1
2
D001
Figure 1. TPD Across Temperature
at 3.3 V VCC
3
Vcc - V
4
5
6
D002
Figure 2. TPD Across VCC at 25°C
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G32-Q1
7
SN74LVC1G32-Q1
SCES648A – FEBRUARY 2006 – REVISED AUGUST 2019
www.ti.com
7 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MW
1 MW
1 MW
1 MW
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
VM
VOL
tPHL
tPLZ
VLOAD/2
VM
tPZH
VM
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VOH
Output
VM
tPZL
tPHL
VM
Output
VI
Output
Control
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G32-Q1
SN74LVC1G32-Q1
www.ti.com
SCES648A – FEBRUARY 2006 – REVISED AUGUST 2019
Parameter Measurement Information (continued)
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
Output
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G32-Q1
9
SN74LVC1G32-Q1
SCES648A – FEBRUARY 2006 – REVISED AUGUST 2019
www.ti.com
8 Detailed Description
8.1 Overview
The SN74LVC1G32-Q1 device contains one 2-input positive OR gate device and performs the Boolean function
Y = A + B or Y = A • B This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down.
8.2 Functional Block Diagram
8.3 Feature Description
•
•
•
•
Wide operating voltage range.
– Operates from 1.65 V to 5.5 V.
Allows down voltage translation.
Inputs accept voltages to 5.5 V.
Ioff feature allows voltages on the inputs and outputs, when VCC is 0 V.
8.4 Device Functional Modes
Table 1. Function Table
INPUTS
B
OUTPUT
Y
H
X
H
X
H
H
L
L
L
A
10
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G32-Q1
SN74LVC1G32-Q1
www.ti.com
SCES648A – FEBRUARY 2006 – REVISED AUGUST 2019
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1G32-Q1 device is a high drive CMOS device that can be used for implementing OR logic with a
high output drive, such as an LED application. It can produce 24 mA of drive current at 3.3 V making it Ideal for
driving multiple outputs and good for high speed applications up to 100 MHz. The inputs are 5.5-V tolerant
allowing translation down to VCC.
9.2 Typical Application
Basic LED Driver
OR Logic Function
VCC
VCC
uC or Logic
uC or Logic
uC or Logic
LVC1G32
LVC1G32
uC or Logic
uC or Logic
Figure 5. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads, so routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommend Output Conditions:
– Load currents should not exceed (IO max) per output and should not exceed total current (continuous
current through VCC or GND) for the part. These limits are located in the Absolute Maximum Ratings
table.
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G32-Q1
11
SN74LVC1G32-Q1
SCES648A – FEBRUARY 2006 – REVISED AUGUST 2019
www.ti.com
Typical Application (continued)
– Outputs should not be pulled above VCC.
9.2.3 Application Curves
10
8
Icc
Icc
Icc
Icc
1.8V
2.5V
3.3V
5V
Icc - mA
6
4
2
0
-2
-20
0
20
40
Frequency - MHz
60
80
D003
Figure 6. ICC vs Frequency
10 Power Supply Recommendations
The power supply can be any voltage between the min and max supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF capacitor is recommended. If there are multiple VCC pins, then a 0.01-μF or 0.022-μF capacitor
is recommended for each power pin. It is ok to parallel multiple bypass capacitors to reject different frequencies
of noise. A 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed
as close to the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two
inputs of a triple-input AND gate are used, or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states.
Specified in Layout Example are the rules that must be observed under all circumstances. All unused inputs of
digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that
should be applied to any particular unused input depends on the function of the device. Generally they will be
tied to GND or VCC, whichever make more sense or is more convenient.
11.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
Figure 7. Layout Example
12
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G32-Q1
SN74LVC1G32-Q1
www.ti.com
SCES648A – FEBRUARY 2006 – REVISED AUGUST 2019
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2006–2019, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G32-Q1
13
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74LVC1G32QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
C32O
SN74LVC1G32QDCKRQ1
ACTIVE
SC70
DCK
5
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
CGO
SN74LVC1G32QDRYRQ1
ACTIVE
SON
DRY
6
5000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
FW
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
