SN74LVT16500DL

SN54LVT16500, SN74LVT16500 3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS146D – MAY 1992 – REVISED NOVEMBER 1996 D D D D D D D D D D D D D State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low-Static Power Dissipation Members of the Texas Instruments Widebus  Family Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Support Live Insertion Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings SN54LVT16500 . . . WD PACKAGE SN74LVT16500 . . . DGG OR DL PACKAGE (TOP VIEW) OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 GND CLKAB B1 GND B2 B3 VCC B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VCC B16 B17 GND B18 CLKBA GND description The ’LVT16500 are 18-bit universal bus transceivers designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/flip-flop on the high-to-low transition of CLKAB. Output-enable OEAB is active high. When OEAB is high, the B-port outputs are active. When OEAB is low, the B-port outputs are in the high-impedance state. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and UBT are trademarks of Texas Instruments Incorporated. Copyright  1996, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LVT16500, SN74LVT16500 3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS146D – MAY 1992 – REVISED NOVEMBER 1996 description (continued) Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active high and OEBA is active low). Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. The SN74LVT16500 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same printed circuit board area. The SN54LVT16500 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LVT16500 is characterized for operation from –40°C to 85°C. FUNCTION TABLE† INPUTS OEAB LEAB CLKAB A OUTPUT B Z L X X X H H X L L H H X H H H L ↓ L L H L ↓ H H L H X H B0‡ B0§ † A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. ‡ Output level before the indicated steady-state input conditions were established § Output level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low H 2 L L POST OFFICE BOX 655303 X • DALLAS, TEXAS 75265 SN54LVT16500, SN74LVT16500 3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS146D – MAY 1992 – REVISED NOVEMBER 1996 logic symbol† OEAB CLKAB LEAB 1 55 2 27 OEBA CLKBA LEBA A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 30 28 3 EN1 2C3 C3 G2 EN4 5C6 C6 G5 3D 1 1 4 1 6D 54 5 52 6 51 8 49 9 48 10 47 12 45 13 44 14 43 15 42 16 41 17 40 19 38 20 37 21 36 23 34 24 33 26 31 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LVT16500, SN74LVT16500 3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS146D – MAY 1992 – REVISED NOVEMBER 1996 logic diagram (positive logic) OEAB CLKAB LEAB LEBA CLKBA OEBA A1 1 55 2 28 30 27 3 1D C1 CLK 54 B1 1D C1 CLK To 17 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . . –0.5 V to 7 V Current into any output in the low state, IO: SN54LVT16500 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVT16500 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVT16500 . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74LVT16500 . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . 1 W DL package . . . . . . . . . . . . . . . . . . . 1.4 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVT16500, SN74LVT16500 3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS146D – MAY 1992 – REVISED NOVEMBER 1996 recommended operating conditions (see Note 4) SN54LVT16500 SN74LVT16500 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 0.8 Input voltage 5.5 5.5 V IOH IOL High-level output current –24 –32 mA 48 64 mA ∆t/∆v Input transition rise or fall rate 10 10 ns/V 85 °C High-level input voltage 2 Low-level output current Outputs enabled TA Operating free-air temperature NOTE 4: Unused control inputs must be held high or low to prevent them from floating. –55 2 125 –40 V V V PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LVT16500, SN74LVT16500 3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS146D – MAY 1992 – REVISED NOVEMBER 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH SN54LVT16500 TYP† MAX TEST CONDITIONS VCC = 2.7 V, VCC = 2.7 V to 3.6 V, II = –18 mA IOH = –100 µA VCC = 2.7 V, IOH = –8 mA IOH = –24 mA VCC = 3 V VCC = 2 2.7 7V VOL VCC = 3 V VCC = 3.6 V, VCC = 0 or 3.6 V, II VCC = 3.6 V Ioff VCC = 0, II(hold) I(h ld) VCC = 3 V IOZH IOZL VCC = 3.6 V, VCC = 3.6 V, MIN –1.2 VCC–0.2 2.4 VCC = 3.6 V, VI = VCC or GND –1.2 VCC–0.2 2.4 IOH = –32 mA IOL = 100 µA 0.2 IOL = 24 mA IOL = 16 mA 0.5 0.5 0.4 0.4 IOL = 32 mA IOL = 48 mA 0.5 0.5 VI = 5.5 V VI = 5.5 V VI = VCC VI = 0 V 0.55 0.55 Control inputs A or B ports‡ VI or VO = 0 to 4.5 V VI = 0.8 V A or B ports VI = 2 V VO = 3 V Ci VI = 3 V or 0 VO = 3 V or 0 20 20 5 5 –10 –10 ±100 ±100 75 –75 3.5 µA µA µA 1 Outputs low VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND ±1 10 75 Outputs disabled ∆ICC§ ±1 10 –75 VO = 0.5 V IO = 0, V 2 0.2 IOL = 64 mA VI = VCC or GND UNIT V 2 Outputs high ICC SN74LVT16500 TYP† MAX MIN 1 µA µA –1 –1 0.12 0.12 5 5 0.12 0.12 0.2 0.2 mA mA 3.5 pF Cio 12 12 † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ Unused pins at VCC or GND § This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVT16500, SN74LVT16500 3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS146D – MAY 1992 – REVISED NOVEMBER 1996 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVT16500 VCC = 3.3 V ± 0.3 V fclock tw tsu th Clock frequency Pulse duration Setup time Hold time MIN MAX 0 150 SN74LVT16500 VCC = 2.7 V MIN MAX 0 125 VCC = 3.3 V ± 0.3 V MIN MAX 0 150 VCC = 2.7 V MIN MAX 0 125 LE high 3.3 3.3 3.3 3.3 CLK high or low 3.3 3.3 3.3 3.3 A before CLKAB↓ 1.8 1.1 1.8 1.1 B before CLKBA↓ 1.9 1.2 1.9 1.2 A or B before LE↓ , CLK high 2.2 1.3 2.2 1.3 A or B before LE↓ , CLK low 2.7 1.9 2.7 1.9 A or B after CLK↓ 1.2 1.2 1.2 1.2 A or B after LE↓ 0.9 1.1 0.9 1.1 UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LVT16500 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ MAX 150 B or A A or B LEBA or LEAB A or B CLKBA or CLKAB A or B OEBA or OEAB A or B OEBA or A or B OEAB tPLZ † All typical values are at VCC = 3.3 V, TA = 25°C. SN74LVT16500 VCC = 2.7 V MIN MAX 125 VCC = 3.3 V ± 0.3 V MIN TYP† MAX 150 VCC = 2.7 V MIN UNIT MAX 125 MHz 1.7 5.8 7 1.7 3 5.4 6.8 1.6 6 7.8 1.6 3.2 5.9 7.7 2.3 7.3 8.9 2.3 4 7 8.5 2.7 8.2 9.8 2.7 4.3 7.9 9.7 2 7.4 8.8 2 4.1 7 8.3 2.4 8.1 10 2.4 4.4 7.9 9.9 1.2 5.2 6.1 1.2 3 5 5.9 1.5 5.9 7 1.5 3 5.8 6.9 2.7 7.7 8.6 2.7 4.6 7.4 8.3 2.8 7.3 7.7 2.8 4.7 6.7 7.2 ns ns ns ns ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54LVT16500, SN74LVT16500 3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS146D – MAY 1992 – REVISED NOVEMBER 1996 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 500 Ω 2.7 V LOAD CIRCUIT 1.5 V Timing Input 0V tw tsu 2.7 V Input 1.5 V 1.5 V th 2.7 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 1.5 V 0V VOH 1.5 V Output 1.5 V VOL tPLH tPHL VOH Output 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPHL tPLH 2.7 V Output Control tPLZ Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) 1.5 V tPZH 3V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 1-Aug-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp NRND TSSOP DGG 56 TBD Call TI Call TI 74LVT16500DGGRG4 NRND TSSOP DGG 56 TBD Call TI Call TI SN74LVT16500DGGR OBSOLETE TSSOP DGG 56 TBD Call TI Call TI SN74LVT16500DL OBSOLETE SSOP DL 56 TBD Call TI Call TI SN74LVT16500DLR NRND SSOP DL 56 SN74LVT16500DLRG4 OBSOLETE SSOP DL 56 Green (RoHS & no Sb/Br) TBD Samples (Requires Login) 74LVT16500DGGRE4 1000 (3) CU NIPDAU Level-1-260C-UNLIM Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LVT16500DLR Package Package Pins Type Drawing SSOP DL 56 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 32.4 Pack Materials-Page 1 11.35 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 18.67 3.1 16.0 32.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVT16500DLR SSOP DL 56 1000 346.0 346.0 49.0 Pack Materials-Page 2 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. 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