SN74AHC32, SN54AHC32
SCLS247K – OCTOBER 1995 – REVISED OCTOBER 2023
SNx4AHC32 Quadruple 2-Input Positive-OR Gates
1 Features
3 Description
•
•
•
•
The SNx4AHC32 devices are quadruple 2-input
positive-OR gates. These devices perform the
Boolean function Y = A × B or Y = A + B in positive
logic.
Operating range 2-V to 5.5-V VCC
Low power consumption, 10-µA maximum ICC
±8-mA output drive at 5 V
Latch-up performance exceeds 250 mA
per JESD 17
2 Applications
•
•
•
Device Information
PART NUMBER
Enable or disable a digital signal
Controlling an indicator LED
Translation between communication modules and
system controllers
RATING
PACKAGE(1)
FK (LCCC, 20)
SN54AHC32
Military
J (CDIP, 14)
W (CFP, 14)
DB (SSOP, 14)
DGV (TVSOP, 14)
D (SOIC, 14)
SN74AHC32
Commercial
N (PDIP, 14)
NS (SO, 14)
PW (TSSOP, 14)
RGY (VQFN, 14)
BQA (WQFN, 14)
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
A
Y
B
Logic Diagram (Positive Logic)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AHC32, SN54AHC32
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SCLS247K – OCTOBER 1995 – REVISED OCTOBER 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V...........6
6.7 Switching Characteristics, VCC = 5 V ± 0.5 V..............7
6.8 Noise Characteristics.................................................. 7
6.9 Operating Characteristics........................................... 7
7 Parameter Measurement Information............................ 8
8 Detailed Description........................................................9
8.1 Overview..................................................................... 9
8.2 Functional Block Diagram........................................... 9
8.3 Feature Description.....................................................9
8.3.1 Standard CMOS Inputs........................................ 9
8.3.2 Balanced CMOS Push-Pull Outputs.....................9
8.3.3 Clamp Diode Structure......................................... 9
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Application.................................................... 11
9.2.1 Design Requirements......................................... 11
9.2.2 Detailed Design Procedure................................ 12
9.2.3 Application Curves............................................. 13
9.3 Power Supply Recommendations.............................13
9.4 Layout....................................................................... 13
9.4.1 Layout Guidelines...............................................13
9.4.2 Layout Example..................................................14
10 Device and Documentation Support..........................14
10.1 Receiving Notification of Documentation Updates..14
10.2 Support Resources................................................. 14
10.3 Trademarks............................................................. 14
10.4 Electrostatic Discharge Caution..............................14
10.5 Glossary..................................................................14
11 Mechanical, Packaging, and Orderable
Information.................................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (May 2023) to Revision K (October 2023)
Page
• Updated RθJA values: PW = 113 to 147.7, all values in °C/W .......................................................................... 6
Changes from Revision I (June 2013) to Revision J (May 2023)
Page
• Added the BQA package information to the data sheet..................................................................................... 1
• Updated the Device Information table................................................................................................................ 1
• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
2
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5 Pin Configuration and Functions
1A
1
14
VCC
1B
2
13
4B
1Y
3
12
4A
2A
4
11
4Y
2B
5
10
3B
2Y
6
9
3A
GND
7
8
3Y
Figure 5-1. SN54AHC32 J or W
SN74AHC32 D, DB, DGV, N, NS or PW Package,
14-Pin (Top View)
1A
VCC
1
14
1B
2
13
4B
1Y
3
12
4A
2A
4
11
4Y
2B
5
10
3B
2Y
6
9
3A
PAD
7
8
GND
3Y
Figure 5-2. SN74AHC32 RGY or BQA Package, 14Pin (Top View)
1B 1A NC VCC 4B
1Y
4
3
2
1
20 19
18
4A
NC
5
17
NC
4Y
2A
6
16
NC
7
15
NC
2B
8
14
9 10 11 12 13
3B
2Y GND NC 3Y 3A
Figure 5-3. SN54AHC32 FK Package, 20-Pin (Top View)
Table 5-1. Pin Functions
PIN
SN74AHC32
NAME
SN54AHC32
TYPE(1)
DESCRIPTION
D, DB, DGV, N, NS,
PW, RGY, BQA
J, W
FK
1A
1
1
2
I
1A Input
1B
2
23
3
I
1B Input
1Y
3
3
4
O
1Y Output
2A
4
4
6
I
2A Input
2B
5
5
8
I
2B Input
2Y
6
6
9
O
2Y Output
3A
9
9
13
I
3A Input
3B
10
10
14
I
3B Input
3Y
8
8
12
O
3Y Output
4A
12
12
18
I
4A Input
4B
13
13
19
I
4B Input
4Y
11
11
16
O
4Y Output
GND
7
7
10
—
Ground Pin
NC
—
—
1, 5, 7,
11, 15, 17
—
No Connection
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Table 5-1. Pin Functions (continued)
PIN
SN74AHC32
NAME
TYPE(1)
DESCRIPTION
D, DB, DGV, N, NS,
PW, RGY, BQA
J, W
FK
VCC
14
14
20
—
Power Pin
Thermal
Pad(2)
–
–
–
–
Thermal Pad
(1)
(2)
4
SN54AHC32
Signal Types: I = Input, O = Output, I/O = Input or Output.
RGY and BQA Package Only
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
Supply voltage range, VCC
–0.5
7
UNIT
V
Input voltage range, VI (2)
–0.5
7
V
Output voltage range, VO (2)
–0.5
VCC + 0.5
V
Input clamp current, IIK (VI < 0)
-20
mA
Output clamp current, IOK (VO < 0 or VO > VCC)
±20
mA
Continuous output current, IO (VO = 0 to VCC)
±25
mA
Continuous current through VCC or GND
±50
mA
150
°C
Storage temperature range, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V (ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±2000
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002
(2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
SN54AHC32
VCC
Supply voltage
VCC= 2 V
VIH
High-level input voltage
VCC= 3V
VCC= 5.5 V
VIL
Low-level Input voltage
VI
Input voltage
VO
Output voltage
MAX
2
5.5
1.5
IOL
Low-level output current
Input Transition rise or fall rate
TA
Operating free-air temperature
2
5.5
UNIT
V
1.5
2.1
3.85
V
VCC= 2 V
0.5
0.5
VCC= 3 V
0.9
0.9
1.65
V
1.65
0
5.5
0
5.5
V
0
VCC
0
VCC
V
–50
–50
VCC= 3.3 V ± 0.3 V
–4
–4
VCC= 5 V ± 0.5 V
–8
–8
VCC= 2 V
50
50
4
4
VCC= 3.3 V ± 0.3 V
VCC= 5 V ± 0.5 V
Δt/Δv
MAX
2.1
VCC= 2 V
High-level output current
MIN
3.85
VCC= 5.5 V
IOH
SN74AHC32
MIN
VCC= 3.3 V ± 0.3 V
VCC= 5 V ± 0.5 V
–55
8
8
100
100
20
20
125
–40
125
mA
mA
ns/V
°C
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6.4 Thermal Information
SNx4AHC32
THERMAL METRIC(1)
R θJA
(1)
(2)
(3)
D(2)
DB(2)
DGV(2)
N(2)
NS(2)
PW(2)
RGY(3)
BQA
14
14
14
14
14
14
14
14
86
96
127
80
76
147.7
47
88.3
Junction-to-ambient
thermal resistance
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
The package thermal impedance is calculated in accordance with JESD 51-7.
The package thermal impedance is calculated in accordance with JESD 51-5
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –50 µA
SN54AHC32
SN74AHC32
MAX
MIN
MAX
MIN
TA = –40°C TO
125°C
Recommended
MIN
TYP
2V
1.9
2
1.9
1.9
1.9
MAX
MIN
2.9
2.9
3
2.9
2.9
4.4
4.5
4.4
4.4
4.4
IOH = –4 mA
3V
2.58
2.48
2.48
2.48
IOH = –8 mA
4.5 V
3.94
IOL = 50 µA
VI = 5.5 V or GND
ICC
VI = VCC or
GND,
Ci
VI = VCC or GND
IO = 0
3.8
MAX
V
3.8
2V
0.1
0.1
0.1
0.1
3V
0.1
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
0.1
3V
0.36
0.5
0.44
0.5
4.5 V
0.36
0.5
0.44
0.5
0 V to 5.5
V
±0.1
±1(1)
±1
±1
µA
2
20
20
20
µA
IOH = 4 mA
IOH = 8 mA
3.8
UNIT
SN74AHC32
3V
VOL
(1)
TA = –40°C TO
85°C
4.5 V
VOH
II
TA = 25°C
VCC
TA = –55°C TO
125°C
5.5 V
5V
2
10
10
V
pF
On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
6.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
(1)
6
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A or B
Y
CL = 15 pF
A or B
Y
CL = 50 pF
TA = 25°C
TA = –40°C TO
125°C
TA = –55°C TO
125°C
TA = –40°C TO
85°C
SN54AHC32
SN74AHC32
SN74AHC32
MIN
MIN
MIN
MAX
MAX
Recommended
TYP
MAX
5.5(1)
7.9(1)
1(1)
9.5(1)
1
9.5
1
9.5
5.5(1)
7.9(1)
1(1)
9.5(1)
1
9.5
1
9.5
8
11.4
1
13
1
13
1
13
8
11.4
1
13
1
13
1
13
UNIT
MAX
ns
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
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6.7 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range(unless otherwise noted) (see Figure 7-1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A or B
Y
CL = 15 pF
A or B
Y
CL = 50 pF
TA = 25°C
TA = –55°C TO
125°C
TA = –40°C TO
85°C
SN54AHC32
SN74AHC32
MIN
MIN
MAX
TA = –40°C TO
125°C
Recommended
UNIT
SN74AHC32
TYP
MAX
3.8(1)
5.5(1)
1(1)
6.5(1)
1
MAX
6.5
MIN
1
MAX
6.5
3.8(1)
5.5(1)
1(1)
6.5(1)
1
6.5
1
6.5
5.3
7.5
1
8.5
1
8.5
1
8.5
5.3
7.5
1
8.5
1
8.5
1
8.5
ns
ns
6.8 Noise Characteristics
VCC = 5 V, CL = 50 pF, TA = 25°C(1)
SN74AHC32
PARAMETER
TYP
MAX
VOL(P)
Quiet output, maximum dynamic VOL
0.3
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.3
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
4.7
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
MIN
UNIT
V
3.5
V
1.5
V
Characteristics are for surface-mount packages only.
6.9 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
No load,
f = 1 MHz
TYP
14
UNIT
pF
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7 Parameter Measurement Information
A.
B.
C.
D.
E.
CL includes probe and jig capacitance.
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
The outputs are measured one at a time with one input transition per measurement.
All parameters and waveforms are not applicable to all devices.
Figure 7-1. Load Circuit and Voltage Waveforms
8
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8 Detailed Description
8.1 Overview
The SNx4AHC32 contains four independent 2-input OR Gates. Each gate performs the Boolean function Y = A +
B in positive logic.
8.2 Functional Block Diagram
xA
xY
xB
8.3 Feature Description
8.3.1 Standard CMOS Inputs
This device includes standard CMOS inputs. Standard CMOS inputs are high impedance and are typically
modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst
case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the
maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I).
Standard CMOS inputs require that input signals transition between valid logic states quickly, as defined
by the input transition time or rate in the Recommended Operating Conditions table. Failing to meet this
specification will result in excessive power consumption and could cause oscillations. More details can be found
in Implications of Slow or Floating CMOS Inputs.
Do not leave standard CMOS inputs floating at any time during operation. Unused inputs must be terminated at
VCC or GND. If a system will not be actively driving an input at all times, then a pull-up or pull-down resistor can
be added to provide a valid input voltage during these times. The resistor value will depend on multiple factors; a
10-kΩ resistor, however, is recommended and will typically meet all requirements.
8.3.2 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads, so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
8.3.3 Clamp Diode Structure
The outputs to this device have both positive and negative clamping diodes, and the inputs to this device have
negative clamping diodes only as shown in Figure 8-1.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage
to the device. The input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed.
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VCC
Device
+IOK
Input
Output
Logic
-IIK
-IOK
GND
Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Table 8-1 lists the functional modes of the SNx4AHC32.
Table 8-1. Function Table
INPUTS(1)
(1)
10
A
B
OUTPUT
Y
H
H
H
L
H
H
H
L
H
L
L
L
H = high voltage level, L = low voltage level, X = do not care, Z = high impedance
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
In this application, three 2-input OR gates are combined to produce a 4-input OR gate function as shown in
Figure 9-1. The fourth gate can be used for another application in the system, or the inputs can be grounded and
the channel left unused.
The SNx4AHC32 is used to directly control the Enable pin of a fan driver. The fan driver requires only one input
signal to be HIGH before being enabled, and should be disabled in the event that all signals go LOW. The
4-input OR gate function combines the four individual overheat signals into a single active-high enable signal.
Temperature sensors can often be spread throughout a system rather than being in a centralized location. This
would mean longer length traces or wires to pass signals through leading to slower edge transitions. This makes
the SNx4AHC32 useful for combining the incoming signals.
9.2 Typical Application
Device 1
Overheat
Device 2
Overheat
Fan
Driver
EN
Device 3
Overheat
Device 4
Overheat
Figure 9-1. Typical Application Block Diagram
9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions.
The supply voltage sets the electrical characteristics of the device as described in the Electrical Characteristics
section.
The positive voltage supply must be capable of sourcing current equal to the maximum static supply current, ICC,
listed in the Electrical Characteristics, and any transient current required for switching.
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The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SNx4AHC32 plus the maximum supply current, ICC, listed in the Electrical Characteristics, and any transient
current required for switching. The logic device can only sink as much current that can be sunk into its ground
connection. Be sure to not exceed the maximum total current through GND listed in the Absolute Maximum
Ratings.
The SNx4AHC32 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all of
the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to exceed
50 pF.
The SNx4AHC32 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and
current defined in the Electrical Characteristics table with VOL. When outputting in the HIGH state, the output
voltage in the equation is defined as the difference between the measured output voltage and the supply voltage
at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation application note.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices application note.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.2.1.2 Input Considerations
Input signals must cross to be considered a logic LOW, and to be considered a logic HIGH. Do not exceed the
maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. The unused inputs can be directly terminated if the
input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The drive current of the controller, leakage current into the SNx4AHC32 (as specified
in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10-kΩ resistor
value is often used due to these factors.
Refer to the Feature Description section for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to the Feature Description section for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit; by design, however, it will
optimize performance. This can be accomplished by providing short, appropriately sized traces from the
SNx4AHC32 to one or more of the receiving devices.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. Doing this will prevent the maximum
output current from the Absolute Maximum Ratings from being violated. Most CMOS inputs have a resistive
load measured in MΩ; much larger than the minimum calculated previously.
12
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4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.2.3 Application Curves
Device 1
Device 2
Device 3
Device 4
EN
Figure 9-2. Application Timing Diagram
9.3 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent
power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple
bypass capacitors to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in
parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results, as
shown in the following layout example.
9.4 Layout
9.4.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices, inputs must never be left floating. In many cases,
functions or parts of functions of digital logic devices are unused (for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used). Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: SN74AHC32 SN54AHC32
13
SN74AHC32, SN54AHC32
www.ti.com
SCLS247K – OCTOBER 1995 – REVISED OCTOBER 2023
9.4.2 Layout Example
GND
VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
0.1 F
Avoid 90°
corners for
signal lines
Bypass capacitor
placed close to
the device
1A
1
14
VCC
1B
2
13
4B
1Y
3
12
4A
2A
4
11
4Y
2B
5
10
3B
2Y
6
9
3A
GND
7
8
3Y
Unused inputs
tied to VCC
Unused output
left floating
Figure 9-3. Example Layout for the SNx4AHC32
10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: SN74AHC32 SN54AHC32
PACKAGE OPTION ADDENDUM
www.ti.com
2-Dec-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9682501Q2A
ACTIVE
LCCC
FK
20
55
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629682501Q2A
SNJ54AHC
32FK
5962-9682501QCA
ACTIVE
CDIP
J
14
25
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9682501QC
A
SNJ54AHC32J
5962-9682501QDA
ACTIVE
CFP
W
14
25
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9682501QD
A
SNJ54AHC32W
SN74AHC32BQAR
ACTIVE
WQFN
BQA
14
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC32
Samples
SN74AHC32DBR
ACTIVE
SSOP
DB
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA32
Samples
SN74AHC32DGVR
ACTIVE
TVSOP
DGV
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA32
Samples
SN74AHC32DR
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC32
Samples
SN74AHC32N
ACTIVE
PDIP
N
14
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 125
SN74AHC32N
Samples
SN74AHC32NSR
ACTIVE
SO
NS
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC32
Samples
SN74AHC32PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA32
Samples
SN74AHC32RGYR
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HA32
Samples
SNJ54AHC32FK
ACTIVE
LCCC
FK
20
55
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629682501Q2A
SNJ54AHC
32FK
SNJ54AHC32J
ACTIVE
CDIP
J
14
25
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9682501QC
A
SNJ54AHC32J
SNJ54AHC32W
ACTIVE
CFP
W
14
25
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9682501QD
A
SNJ54AHC32W
Addendum-Page 1
Samples
Samples
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Dec-2023
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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