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TAS2552
SLAS898B – JANUARY 2014 – REVISED APRIL 2015
TAS2552 4.0-W Class-D Mono Audio Amplifier with Class-G Boost and Speaker Sense
1 Features
3 Description
•
The TAS2552 is a high efficiency Class-D audio
power amplifier with advanced battery current
management and an integrated Class-G boost
converter. The device constantly measures the
current and voltage across the load and provides a
digital stream of this information.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Analog or Digital Input Mono Boosted Class-D
Amplifier
4.0 W into 8 Ω Load from 4.2 V Supply (1%
THD+N)
Efficiency of 85% at Rated Power
I2S, Left-Justified, Right-Justified, DSP, PDM, and
TDM Input and Output Interface
Input Sample Rates from 8 kHz to 192 kHz
High Efficiency Class-G Boost Converter
– Automatically Adjusts Class-D Supply
Built-In Speaker Sense
– Measures Speaker Current and Voltage
– Measures VBAT and VBOOST Voltages
Built-In Automatic Gain Control (AGC)
– Limits Battery Current Consumption
Adjustable Class-D Switching Edge-Rate Control
Power Supplies
– Boost Input: 3.0 V to 5.5 V
– Analog: 1.65 V to 1.95 V
– Digital I/O: 1.5 V to 3.6 V
Thermal and Short-Circuit Protection
I2C Interface for Register Control
Stereo Configuration Using Two TAS2552s
– I2C Address Select Terminal (ADDR)
2.855 mm x 2.575 mm, 0.4 mm Pitch 30-Ball
WCSP
2 Applications
•
•
•
•
•
Mobile Phones
PND
Portable Audio Docks
Tablets
Gaming Devices
The Class-G boost converter generates the Class-D
amplifier supply rail. During low Class-D output
power, the boost improves efficiency by deactivating
and connecting VBAT directly to the Class-D amplifier
supply. When high power audio is required, the boost
quickly activates to provide significantly louder audio
than a stand-alone amplifier connected directly to the
battery.
The AGC automatically adjusts Class-D gain to
reduce battery current at end-of-charge voltages,
preventing output clipping, distortion and early system
shutdown. The fixed gain is adjustable via I2C. The
gain range is -7 dB to +24 dB in 1 dB steps.
In addition to a differential mono analog input, the
TAS2552 has built-in a 16-bit D/A converter used with
a digital input. Moving the D/A converter from the
digital host processor into the integrated amplifier
process provides better dynamic performance at
lower system cost. Additionally, since the PCB routing
is digital rather than analog, sensitivity to external
perturbations such as GSM frame-rate noise is
decreased at the system level.
Device Information
ORDER NUMBER
TAS2552YFF
PACKAGE
BODY SIZE
WCSP (30)
2.855 mm x 2.575 mm
2.2 uH
VBAT
2 SW
10 nF
VREG
+
Audio
Input
VBOOST
-
PVDD
22 uF
PDM CLK
MCLK
TAS2552
Ferrite bead
(opt.)
OUT+
I2S
4
I2C
3
Enable
OUTFerrite bead
(opt.)
+
To
- Speaker
VSENSE+
VSENSE-
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS2552
SLAS898B – JANUARY 2014 – REVISED APRIL 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
7.5 Register Map........................................................... 31
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
8
9
10 Layout................................................................... 51
Detailed Description ............................................ 13
11 Device and Documentation Support ................. 53
7.1
7.2
7.3
7.4
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements/Timing Diagrams....................
Typical Characteristics ..............................................
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
13
13
14
20
8
Applications and Implementation ...................... 42
8.1 Application Information............................................ 42
8.2 Typical Applications ................................................ 42
8.3 Initialization ............................................................. 48
9
Power Supply Recommendations...................... 49
9.1 Power Supplies ....................................................... 49
9.2 Power Supply Sequencing ...................................... 49
9.3 Boost Supply Details ............................................... 50
10.1 Layout Guidelines ................................................. 51
10.2 Layout Example .................................................... 51
10.3 Package Dimensions ............................................ 52
11.1 Trademarks ........................................................... 53
11.2 Electrostatic Discharge Caution ............................ 53
11.3 Glossary ................................................................ 53
12 Mechanical, Packaging, and Orderable
Information ........................................................... 54
4 Revision History
Changes from Revision A (February 2014) to Revision B
Page
•
Added clarification on EN Pin Function and Configuration..................................................................................................... 3
•
Changed VBAT MAX = 2.45 V. Added footnote to avoid VBAT reset. .................................................................................. 7
•
Added clarification on wait time regarding DEV_RESET Register....................................................................................... 32
•
Added clarification on VBAT reset range for normal operation mode. ................................................................................. 49
Changes from Original (January 2014) to Revision A
•
2
Page
Changed from Product Preview to Production Data .............................................................................................................. 1
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SLAS898B – JANUARY 2014 – REVISED APRIL 2015
5 Pin Configuration and Functions
30-Ball WCSP
YFF Package
(Top View)
F5
F4
F3
F2
F1
MCLK
BCLK
WCLK
EN
IOVDD
E5
E4
E3
E2
E1
SCL
IVCLKIN
DOUT
AIN+
AVDD
D5
D4
D3
D2
D1
SDA
ADDR
DIN
AIN-
VBAT
C5
C4
C3
C2
C1
PGND
PGND
VREG
AGND
AGND
B5
B4
B3
B2
B1
SW
SW
VSENSE+
VSENSE-
BIAS
A5
A4
A3
A2
A1
VBOOST
PVDD
OUT+
OUT-
PGND
Pin Functions
TERMINAL
INPUT/OUTPUT/
POWER
DESCRIPTION
NAME
BALL WCSP
PGND
A1
P
Power ground. Connect to high current ground plane.
OUT–
A2
O
Inverting Class D output.
OUT+
A3
O
Non-inverting Class D output.
PVDD
A4
P
Class-D power supply. Connected internally to VBOOST – do not drive this terminal
externally.
VBOOST
A5
P
8.5 V boost output. Connected internally to PVDD – do not drive this terminal
externally.
BIAS
B1
O
Mid-rail reference for Class D channel.
VSENSE–
B2
I
Inverting voltage sense input.
VSENSE+
B3
I
Non-inverting voltage sense input.
SW
B4,B5
I/O
AGND
C1,C2
P
Analog ground. Connect to low noise ground plane.
VREG
C3
O
High-side FET gate drive boost converter.
PGND
C4,C5
P
Power ground. Connect to high current ground plane.
VBAT
D1
P
Battery power supply. Connect to 3.0 V to 5.5 V battery supply.
AIN–
D2
I
Inverting analog input.
DIN
D3
I
Audio serial data input. Format is I2S, LJF, RJF, or TDM data.
ADDR
D4
I
I2C address select terminal. Set ADDR = GND for device 7-bit address 0x40; set
ADDR = IOVDD for 7-bit address 0x41.
SDA
D5
I/O
AVDD
E1
P
Analog low voltage supply terminal. Connect to 1.65 V to 1.95 V supply.
AIN+
E2
I
Non-inverting analog input.
DOUT
E3
O
Serial I/V digital output. Format is I2S, LJF, RJF, TDM, or undecimated PDM data.
IVCLKIN
E4
I
Serial clock input for undecimated PDM I/V data.
SCL
E5
I
I2C control bus clock.
F2
I
Device enable (HIGH = Normal Operation, LOW = Standby)
EN
(1)
(1)
Boost switch terminal.
I2C control bus data.
Wait a minimum of 1ms after EN is pulled high or DEV_RESET is issued before accessing the control interface. EN=low will erase the
TAS2552 device configuration. The TAS2552 device must be configured (see Initialization) after EN=high.
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Pin Functions (continued)
TERMINAL
NAME
BALL WCSP
INPUT/OUTPUT/
POWER
WCLK
F3
I
Audio serial word clock.
BCLK
F4
I
Audio serial bit clock.
MCLK
F5
I
External master clock.
IOVDD
F1
P
Supply for digital input and output levels. Voltage range is 1.5 V to 3.6 V.
DESCRIPTION
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range, TA = 25°C (unless otherwise noted)
MIN
MAX
UNIT
VBAT
Battery voltage
–0.3
6.0
V
AVDD
Analog supply voltage
–0.3
2.5
V
IOVDD
I/O Supply voltage
–0.3
3.9
V
AIN+, AIN–
Analog input voltage
–0.3
AVDD + 0.3
V
–0.3
IOVDD + 0.3
Digital input voltage
Output continuous total power dissipation
See Thermal Information
V
NA
6.2 Handling Ratings
PARAMETER
Tstg
DEFINITION
Storage temperature range
ESD
MIN
MAX
UNIT
–65
150
°C
HBM
3000
CDM
1500
V
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
5.5
V
1.65
1.8
1.95
V
1.8
3.6
V
3.0
UNIT
VBAT
Battery voltage
AVDD
Analog supply voltage
IOVDD
I/O supply voltage
1.5
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
150
°C
6.4 Thermal Information
THERMAL METRIC (1)
TAS2552
YFF (30 TERMINALS)
θJA
Junction-to-ambient thermal resistance
θJCtop
Junction-to-case (top) thermal resistance
0.2
θJB
Junction-to-board thermal resistance
44.0
ψJT
Junction-to-top characterization parameter
1.6
ψJB
Junction-to-board characterization parameter
43.4
(1)
4
UNIT
76.5
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SLAS898B – JANUARY 2014 – REVISED APRIL 2015
6.5 Electrical Characteristics
VBAT = 3.6 V, AVDD = IOVDD = 1.8 V, EN = IOVDD, SWS = 0, Gain = 15 dB, ERC = 14 ns, RL = 8 Ω + 33 µH, 48 kHz
sample rate for digital input, ILIM = 2.5 A (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BOOST CONVERTER
Boost Output Voltage
Average voltage (w/o including ripple).
Includes load regulation (0-0.6A) and line
regulation (VBAT = 3.0 – 4.8V).
Boost Converter Switching Frequency
8.5
V
1.8
MHz
CLASS-D CHANNEL
Max Analog Input
For THD+N < 1%
1
VRMS
Full-Scale DAC Output
All digital interface modes
1
VRMS
8
Ω
Load Resistance (Load Spec
Reisistance)
6
Class-D Frequency
758
kHz
Class-D + Boost Efficiency
VBAT = 5.5, Pout = 1 W (sinewave)
Class-D Output Current Limit (Short
Circuit Protection)
VBOOST = 8.5 V, OUT– shorted to VBAT
or VBOOST
Class-D Output Offset Voltage in
Analog Input Mode
VBAT = 3.6 V, AV = 15 dB, RL = 8 Ω,
input shorted to ground through single
capacitor
-7.4
4.6
mV
Class-D Output Offset Voltage in
Digital Input Mode
VBAT = 3.6 V, AV = 15 dB, RL =8 Ω, 0's
data
-9.8
5.6
mV
Programmable Channel Gain Range
(PGA + class-D), minimum
Typical value, analog and digital input
-7
dB
Programmable Channel Gain Range
(PGA + class-D), maximum
Typical value, analog and digital input
24
dB
Programmable Channel Gain Step
(PGA + class-D)
Typical value, analog and digital input
1
dB
Mute Attenuation
Device in shutdown, digital input only
110
dB
VBAT Power Supply Rejection Ratio
(PSRR)
AVDD Power Supply Rejection Ratio
(PSRR)
Common Mode Rejection Ratio
THD+N
75%
3.6
Ripple of 200mVpp @ 217 Hz, Gain = 15
dB, analog and digital input
73
Ripple of 200mVpp @ 1 kHz, Gain = 15
dB, analog and digital input
72
Ripple of 200mVpp @ 4 kHz, Gain = 15
dB, analog and digital input
72
Ripple of 200mVpp @ 217 Hz, Gain = 15
dB, analog and digital input
77
Ripple of 200mVpp @ 1 kHz, Gain = 15
dB, analog and digital input
78
Ripple of 200mVpp @ 4 kHz, Gain = 15
dB, analog and digital input
84
Ripple of 200mVpp @ 217 Hz, Gain = 15
dB, analog input
59
1 kHz, Po = 0.1W, VBAT = 3.6 V,
RL = 8 Ω
0.1%
1 kHz, Po = 0.5W, VBAT = 3.6 V,
RL = 8 Ω
0.1%
1 kHz, Po = 1 W, VBAT = 3.6 V, RL = 8 Ω
0.1%
1 kHz, Po = 2 W, VBAT = 3.6 V, RL = 8 Ω
0.1%
A-wt Filter, Gain = 15 dB, DAC modulator
Output Integrated Noise (20Hz-20kHz) switching
- 8Ω
A-wt Filter, Gain = 15 dB, Analog In,
Inputs shorted
A
Product Folder Links: TAS2552
dB
dB
114%
µV
114%
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5
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SLAS898B – JANUARY 2014 – REVISED APRIL 2015
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Electrical Characteristics (continued)
VBAT = 3.6 V, AVDD = IOVDD = 1.8 V, EN = IOVDD, SWS = 0, Gain = 15 dB, ERC = 14 ns, RL = 8 Ω + 33 µH, 48 kHz
sample rate for digital input, ILIM = 2.5 A (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
THD+N = 1%, VBAT = 3.0 V, ILIM = 2.5 A
2.8
THD+N = 1%, VBAT = 3.6 V, ILIM = 2.5 A
3.3
THD+N = 1%, VBAT = 4.2 V, GAIN = 16
dB, ILIM = 3.0 A
4.0
Output Impedance in Shutdown
EN = 0 V
10
kΩ
Startup Time
Analog/digital input measured from time
when device is taken out of software
shutdown
8
mS
Shutdown Time
Measured from time when device is
programmed in software shutdown mode
1
µS
Max Output Power, 8-Ω Load
W
INPUT SECTION
Full-scale DAC output
All digital interface modes
Maximum analog input voltage
RIN
1.0
VRMS
1.0
VRMS
EN = IOVDD, Amplifier active
10
EN = 0 V, In shutdown
19
Current Sense Full Scale
Peak current which will give full scale
digital output
1.4
Current Sense Accuracy
IOUT = 354 mARMS (1 W)
Current Sense Offset
Input referred
Input impedance (terminals AIN+,
AIN-)
kΩ
CURRENT SENSE
1%
Current Sense Gain Error
THD+N
Distortion + Noise
APEAK
Po = 1.0W (Load = 8Ω + 33 µH)
0.002
mA
-0.09
dB
0.17%
VOLTAGE SENSE
Voltage Sense Full Scale
Peak voltage which will give full scale
digital output
Voltage Sense Accuracy
VOUT = 2.83 Vrms (1W)
Voltage Sense Offset
Input referred
8.5
2.2%
Voltage Sense Gain Error
THD+N
Distortion + Noise
VPEAK
Po = 1.0 W (Load = 8Ω + 33μH)
1.45
mV
-0.20
dB
0.08%
INTERFACE
FMCLK
MCLK frequency
0.512
49.15
MHz
FPDM
PDM Clock (IVCLK) Frequency Range
1.636
3.25
MHz
PDMDC
PDM Clock (IVCLK) Duty Cycle
Range
40%
60%
6
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Electrical Characteristics (continued)
VBAT = 3.6 V, AVDD = IOVDD = 1.8 V, EN = IOVDD, SWS = 0, Gain = 15 dB, ERC = 14 ns, RL = 8 Ω + 33 µH, 48 kHz
sample rate for digital input, ILIM = 2.5 A (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER CONSUMPTION
From VBAT, PLL off, no signal
Power Consumption with Analog Input
From AVDD, PLL off, no signal
and IV Sense Disabled
From IOVDD, PLL off, no signal
Power Consumption with Digital Input
and IV Sense Disabled
6.54
mA
4.01
mA
0.04
mA
From VBAT, PLL off, no signal
6.82
mA
From AVDD, PLL off, no signal
4.16
mA
From IOVDD, PLL off, no signal
0.34
mA
From VBAT, PLL on, no signal
6.54
mA
7.26
mA
0.05
mA
From VBAT, PLL on, no signal
6.59
mA
From AVDD, PLL on, no signal
8.34
mA
From IOVDD, PLL on, no signal
0.34
mA
From VBAT, EN = 0
0.1
µA
From AVDD, EN = 0
0.2
µA
From IOVDD, EN = 0
0.0
µA
From VBAT
6.5
µA
From AVDD
8.6
µA
From IOVDD
126
µA
Power Consumption with Analog Input
From AVDD, PLL on, no signal
and IV Sense Enabled
From IOVDD, PLL on, no signal
Power Consumption with Digital Input
and IV Sense Enabled
Power Consumption in Hardware
Shutdown
Power Consumption in Software
Shutdown
DIGITAL INPUT / OUTPUT
VIH
High-level digital input voltage
VIL
Low-level digital input voltage
VOH
High-level digital output voltage
VOL
Low-level digital output voltage
0.7 x
IOVDD
V
0.3 x
IOVDD
0.9 x
IOVDD
V
V
0.1 x
IOVDD
V
MISCELLANEOUS
(1)
AVDD Supply Under-voltage
Threshold
Device is in reset state
VBAT Supply Under-voltage
Threshold
Device is in reset state
0.9
Device comes out of reset state
Device comes out of reset state
1.4
1.8
2.45 (1)
V
V
VBAT must be ≥ 2.45 V to guarantee that the device is not reset.
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6.6 Timing Requirements/Timing Diagrams
For I2C interface signals over recommended operating conditions (unless otherwise noted). Note: All timing specifications are
measured at characterization but not tested at final test.
PARAMETER
TEST CONDITIONS
MIN
No wait states
TYP
MAX
UNIT
400
kHz
fSCL
Frequency, SCL
tW(H)
Pulse duration, SCL high
0.6
µs
tW(L)
Pulse duration, SCL low
1.3
µs
tsu1
Setup time, SDA to SCL
100
ns
th1
Hold time, SCL to SDA
10
ns
t(buf)
Bus free time between stop and start
condition
1.3
µs
tsu2
Setup time, SCL to start condition
0.6
µs
th2
Hold time, start condition to SCL
0.6
µs
tsu3
Setup time, SCL to stop condition
0.6
µs
tw(L)
tw(H)
SCL
th1
t su1
SDA
Figure 1. SCL and SDA Timing
SCL
th2
t(buf)
tsu2
tsu3
Start Condition
Stop Condition
SDA
Figure 2. Start and Stop Conditions Timing
8
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6.7 Typical Characteristics
VBAT = 3.6 V, AVDD = IOVDD = 1.8 V, EN = IOVDD, SWS = 0, RL = 8 Ω + 33 µH (unless otherwise noted).
100
100
VBAT = 3.0 V
VBAT = 3.0 V
VBAT = 3.6 V
VBAT = 4.2 V
10
VBAT = 5.0 V
VBAT = 5.0 V
THD+N - %
THD+N - %
VBAT = 3.6 V
VBAT = 4.2 V
10
VBAT = 5.5 V
1
VBAT = 5.5 V
1
0.1
0.1
0.01
0.0001
0.001
0.01
0.1
PO - Output Power - W
0.01
0.001
1
0.01
AGC = OFF, Gain = 15 dB
0.1
1
PO - Output Power - W
C004
C024
AGC = OFF, Gain = 15 dB
Figure 3. THD+N vs Output Power (8Ω) for Digital Input
Figure 4. THD+N vs Output Power (6Ω) for Digital Input
1
100
VBAT = 5.5 V
VBAT = 5.0 V
0.1
VBAT = 5.5 V
0.01
VBAT = 4.2 V
VBAT = 3.6 V
THD + N - %
THD+N - %
10
VBAT = 3.0 V
1
VBAT = 5.0 V
0.1
VBAT = 4.2 V
VBAT = 3.6 V
VBAT = 3.0 V
0.001
20
200
2000
f - Frequency - Hz
20000
0.01
0.001
0.01
AGC = OFF, Gain = 15 dB, Pout = 1 W
0.1
1
PO - Output Power - W
C005
C006
AGC = OFF, Gain = 15 dB, f = 1 kHz
Figure 5. THD+N vs Frequency (8Ω) for Digital Input
Figure 6. THD+N vs Output Power (8Ω) for Analog Input
4.0
1
PO - Output Power - W
THD + N - %
3.5
0.1
VBAT = 5.5 V
VBAT = 5.0 V
0.01
VBAT = 4.2 V
VBAT = 3.6 V
20
200
2.5
2.0
1.5
1.0
THD + N = 1%
0.5
THD + N = 10%
VBAT = 3.0 V
0.001
3.0
0.0
2000
f - Frequency - Hz
20000
2.5
AGC = OFF, Gain = 15 dB
3
3.5
4
4.5
5
VBAT - Supply Voltage - V
C007
5.5
C008
AGC = OFF, Gain = 24 dB, f = 1 kHz
Figure 7. THD+N vs Frequency (8Ω) for Analog Input
Figure 8. Output Power for 1% and 10% THD+N vs Supply
Voltage (8Ω)
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Typical Characteristics (continued)
VBAT = 3.6 V, AVDD = IOVDD = 1.8 V, EN = IOVDD, SWS = 0, RL = 8 Ω + 33 µH (unless otherwise noted).
100
1.000
80
0.100
60
APT Transition
VBAT = 5.5 V
0.010
Efficiency
IDD - Supply Current - A
10.000
VBAT = 5.5 V
40
VBAT = 5.0 V
VBAT = 5.0 V
VBAT = 4.2 V
VBAT = 4.2 V
0.001
20
VBAT = 3.6 V
VBAT = 3.6 V
VBAT = 3.0 V
VBAT = 3.0 V
0.000
0.010
0.100
0
0.01
1.000
PO - Total Output Power - W
0.010
Common Mode Rejection Ratio - dB
0
0.008
Supply Current - A
C010
Figure 10. Total Efficiency vs Output Power (8Ω)
Figure 9. VBAT Average Supply Current vs Class-D Output
Power (8Ω)
0.006
0.004
0.002
0.000
VBAT = 5.5 V
VBAT = 5.0 V
±20
VBAT = 4.2 V
VBAT = 3.6 V
±40
VBAT = 3.0 V
±60
±80
±100
3.0
3.5
4.0
4.5
VBAT - Supply Voltage - V
5.0
20
5.5
20000
C012
Figure 12. Common Mode Rejection vs Frequency
0
VBAT = 5.5 V
VBAT = 5.0 V
VBAT = 4.2 V
VBAT = 3.6 V
VBAT = 3.0 V
AVDD = 1.8 V
-20
PSRR - dB
±20
2000
20 Hz to 20 kHz, Analog Input, Gain = 15 dB
Figure 11. VBAT Quiescent Supply Current vs Supply
Voltage
0
200
f - Frequency - Hz
C011
VBAT = 3.0, 3.6, 4.2, 5.0, 5.5 V
PSRR - dB
1
AGC = OFF, Gain = 15 dB, f = 1 kHz
AGC = OFF, Gain = 15 dB, f = 1 kHz
±40
±60
-40
-60
-80
-100
±80
20
200
2000
f - Frequency - Hz
20000
20
200
2000
f - Frequency - Hz
C013
20000
C014
20 Hz to 20 kHz, Digital Input, Gain = 15 dB
20 Hz to 20 kHz, Digital Input, Gain = 15 dB
Figure 13. VBAT Supply Ripple Rejection vs Frequency
10
0.1
PO - Total Output Power - W
C009
Figure 14. AVDD Supply Ripple Rejection vs Frequency
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Typical Characteristics (continued)
VBAT = 3.6 V, AVDD = IOVDD = 1.8 V, EN = IOVDD, SWS = 0, RL = 8 Ω + 33 µH (unless otherwise noted).
10
10
THD + N - %
100
THD + N - %
100
1
VBAT = 5.5 V
1
VBAT = 5.5 V
VBAT = 4.2 V
0.1
VBAT = 4.2 V
0.1
VBAT = 3.6 V
VBAT = 3.6 V
VBAT = 3.0 V
0.01
0.001
0.01
VBAT = 3.0 V
0.1
1
0.01
0.001
10
PO - Output Power - W
0.01
0.1
AGC = OFF, Gain = 15 dB
1
10
PO - Output Power - W
C015
C025
AGC = OFF, Gain = 15 dB
Figure 15. I-Sense THD+N vs Output Power (8Ω)
Figure 16. I-Sense THD+N vs Output Power (6Ω)
100.000
10
Po = 100 mW
Po = 500 mW
10.000
THD + N = %
THD + N - %
Po = 3 W
1
1.000
0.100
VBAT = 5.5 V
VBAT = 5.0 V
0.010
VBAT = 4.2 V
VBAT = 3.6 V
0
20
200
2000
20000
f - Frequency - Hz
0.001
0.001
VBAT = 3.0 V
0.010
0.100
1.000
10.000
PO - Output Power - W
C016
C017
AGC = OFF, Input Level = -20 dBFS, Gain = 15 dB
8 Ω Load, AGC = OFF, Gain = 15 dB
Figure 18. V-Sense THD+N vs. Output Power (8Ω)
Figure 17. I-Sense THD+N vs Frequency (8Ω)
10
8.0
Po = 100 mW
Po = 500 mW
Output Voltage - Vpeak
7.0
THD + N - %
Po = 3 W
1
0.1
AGC Inflection Point
6.0
5.0
4.0
3.0
Battery Tracking = OFF
Battery Tracking = ON
2.0
0.01
20
200
2000
20000
f - Frequency - Hz
3.0
8 Ω Load, AGC = OFF, Input Level = -20 dBFS, Gain = 15 dB
Figure 19. V-Sense THD+N vs Frequency (8Ω)
3.5
4.0
4.5
5.0
VBAT - Voltage - V
C018
5.5
C021
f = 1 kHz, 0 dBFS, Gain = 15 dB,
Inflection point = 3.6 V, Slope = 4.5 V/V, No Load
Figure 20. Maximum Peak Output Voltage vs. Supply
Voltage (8Ω)
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Typical Characteristics (continued)
VBAT = 3.6 V, AVDD = IOVDD = 1.8 V, EN = IOVDD, SWS = 0, RL = 8 Ω + 33 µH (unless otherwise noted).
16
14
Gain - dB
12
10
8
6
4
AGC = OFF
2
AGC = ON
0
3.0
3.5
4.0
4.5
5.0
VBAT - V
5.5
C023
AGC = ON, Gain = 15 dB, f = 1 kHz, Inflection point = 3.6 V, Limiter value = 7.87 V, Slope = 4.5 V
Figure 21. Gain vs Supply Voltage
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7 Detailed Description
7.1 Overview
The TAS2552 is a high efficiency Class-D audio power amplifier with advanced battery current management and
an integrated Class-G boost converter. The TAS2552 provides real-time output current and voltage information to
the host processor via the I2S, LJF, RJF, TDM, DSP, or PDM interface. This output current and voltage
information is useful for speaker protection and sound enhancement algorithms, allowing the host to track the
speaker impedance and to enable usage of lower-cost, wider tolerance speakers reliably pushed to their rated
output power and beyond.
When auto-passthrough mode is enabled, the Class-G boost converter generates the Class-D amplifier supply
rail. During low Class-D output power, the boost improves efficiency by deactivating and connecting VBAT
directly to the Class-D amplifier supply. When high power audio is required, the boost quickly activates to provide
significantly louder audio than a stand-alone amplifier connected directly to the battery.
The battery monitor and AGC work together in the Battery Tracking AGC to automatically adjust the Class-D gain
to reduce battery current at end-of-charge voltage levels, preventing output clipping, distortion and early system
shutdown. The fixed gain is adjustable via I2C. The gain range is -7 dB to +24 dB in 1 dB steps.
In addition to a differential mono analog input, the TAS2552 has built-in a 16-bit D/A converter used with a digital
input. The digital audio interface supports I2S, Left-Justified, Right-Justified, DSP, PDM and TDM modes. Moving
the D/A converter from the digital host processor into the integrated amplifier process provides better dynamic
performance at lower system cost. Additionally, since the PCB routing is digital rather than analog, sensitivity to
external perturbations such as GSM frame-rate noise is decreased at the system level.
Stereo configuration can be achieved with two TAS2552s by using the ADDR terminal to address each TAS2552
seperately. Set ADDR to ground to configure the device for I2C address 0x40 (7-bit). Set ADDR to IOVDD for I2C
address 0x41 (7-bit). Refer to the General I2C Operation section for more details.
7.2 Functional Block Diagram
2.2 PH
VBAT
2
SW
10 nF
VREG
1 PF
Audio
Input
+
Battery
Monitor
IN+
Boost
Converter
VBOOST
22 PF
1 PF
IN-
Oscillator
PVDD
Ferrite bead
(opt.)
AVDD
OUT+
MUX
AVDD
EN
AGC
DAC
+
¦
PWM
OUT-
IOVDD
+
HBridge
Ferrite bead
(opt.)
-
To
Speaker
AGND
IVCLKIN
SDA
SCL
Digital I/O
& Control
PLL
VBAT
ADC
MCLK
VBOOST
VSENSE+
BCLK
I/V
Sense
WCLK
DIN
VSENSE-
DOUT
Bias
Control
ADDR
2
BIAS
AGND
3
PGND
1 PF
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7.3 Feature Description
7.3.1 General I2C Operation
The TAS2552 operates as an I2C slave over the IOVDD voltage range. It is adjustable to one of two I2C
addresses. This allows two TAS2552 devices in a system to connect to the same I2C bus.
Set the ADDR terminal to ground to assign the device I2C address to 0x40 (7-bit). This is equivalent to 0x80 (8bit) for writing and 0x81 (8-bit) for reading.
Set ADDR to IOVDD for I2C address 0x41 (7-bit). This is equivalent to 0x82 (8-bit) for writing and 0x83 (8-bit) for
reading.
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. The bus transfers data serially, one bit at a time. The address and data 8-bit bytes are transferred mostsignificant bit (MSB) first. In addition, each byte transferred on the bus is acknowledged by the receiving device
with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the
bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data
terminal (SDA) while the clock is at logic high to indicate start and stop conditions. A high-to-low transition on
SDA indicates a start, and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within
the low time of the clock period. Figure 22 shows a typical sequence.
The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then waits for an acknowledge condition. The TAS2552 holds SDA low during the acknowledge clock
period to indicate acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each
device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same
signals via a bi-directional bus using a wired-AND connection.
Use external pull-up resistors for the SDA and SCL signals to set the logic-high level for the bus. Use pull-up
resistors between 660 Ω and 4.7 kΩ. Do not allow the SDA and SCL voltages to exceed the TAS2552 supply
voltage, IOVDD.
8- Bit Data for
Register (N)
8- Bit Data for
Register (N+1)
Figure 22. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. Figure 22 shows a generic data
transfer sequence.
7.3.2 Single-Byte and Multiple-Byte Transfers
The serial control interface supports both single-byte and multiple-byte read/write operations for all registers.
During multiple-byte read operations, the TAS2552 responds with data, a byte at a time, starting at the register
assigned, as long as the master device continues to respond with acknowledges.
The TAS2552 supports sequential I2C addressing. For write transactions, if a register is issued followed by data
for that register and all the remaining registers that follow, a sequential I2C write transaction has taken place. For
I2C sequential write transactions, the register issued then serves as the starting point, and the amount of data
subsequently transmitted, before a stop or start is transmitted, determines to how many registers are written.
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Feature Description (continued)
7.3.3 Single-Byte Write
As shown in Figure 23, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write-data transfer, the read/write bit must be set to 0. After receiving the correct I2C
device address and the read/write bit, the TAS2552 responds with an acknowledge bit. Next, the master
transmits the register byte corresponding to the TAS2552 internal memory address being accessed. After
receiving the register byte, the TAS2552 again responds with an acknowledge bit. Finally, the master device
transmits a stop condition to complete the single-byte data-write transfer.
Start
Condition
Acknowledge
A6
A5
A4
A3
A2
A1
A0
Acknowledge
R/W ACK A7
A6
A5
I2C Device Address and
Read/Write Bit
A4
A3
A2
A1
Acknowledge
A0 ACK D7
D6
D5
Register
D4
D3
D2
D1
D0 ACK
Stop
Condition
Data Byte
Figure 23. Single-Byte Write Transfer
7.3.4 Multiple-Byte Write and Incremental Multiple-Byte Write
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the TAS2552 as shown in Figure 24. After receiving each data byte, the
TAS2552 responds with an acknowledge bit.
Register
Figure 24. Multiple-Byte Write Transfer
7.3.5 Single-Byte Read
As shown in Figure 25, a single-byte data-read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory
address to be read. As a result, the read/write bit is set to a 0.
After receiving the TAS2552 address and the read/write bit, the TAS2552 responds with an acknowledge bit. The
master then sends the internal memory address byte, after which the TAS2552 issues an acknowledge bit. The
master device transmits another start condition followed by the TAS2552 address and the read/write bit again.
This time, the read/write bit is set to 1, indicating a read transfer. Next, the TAS2552 transmits the data byte from
the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge
followed by a stop condition to complete the single-byte data read transfer.
The device address is 0x40 (7-bit). This is equivalent to 0x81 (8-bit) for reading.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
I2C Device Address and
Read/Write Bit
Acknowledge
A6
A5
A4
Register
A0 ACK
Not
Acknowledge
Acknowledge
A6
A5
A1
A0 R/W ACK D7
I2C Device Address and
Read/Write Bit
D6
D1
Data Byte
D0 ACK
Stop
Condition
Figure 25. Single-Byte Read Transfer
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Feature Description (continued)
7.3.6 Multiple-Byte Read
A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes
are transmitted by the TAS2552 to the master device as shown in Figure 26. With the exception of the last data
byte, the master device responds with an acknowledge bit after receiving each data byte.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A0 R/W ACK A7
I2C Device Address and
Read/Write Bit
Acknowledge
A6
A5
Register
A0 ACK
Acknowledge
A6
A0 R/W ACK D7
I2C Device Address and
Read/Write Bit
Acknowledge
D0
ACK D7
First Data Byte
Acknowledge
Not
Acknowledge
D0 ACK D7
D0 ACK
Other Data Bytes
Last Data Byte
Stop
Condition
Figure 26. Multiple-Byte Read Transfer
7.3.7 PLL
The TAS2552 has an on-chip PLL to generate the clock frequency for the audio DAC and I-V sensing ADCs. The
programmability of the PLL allows operation from a wide variety of clocks that may be available in the system.
The PLL input supports clocks varying from 512 kHz to 24.576 MHz and is register programmable to enable
generation of required sampling rates with fine resolution. Set Register 0x02, D(3) = 1 to activate the PLL. When
the PLL is enabled, the PLL output clock PLL_CLK is:
0.5 ´ PLL _ CLKIN ´ J.D
PLL _ CLK =
2P
(1)
J = 4, 5, 6, … 96
D = 0, 1, 2, ... 9999
P = 0,1
Choose J, D, P such that PLL_CLK = 22.5792 MHz (44.1ksps sampling rate) or 24.5760 MHz (48ksps sampling
rate). Program variable J in Register 0x08, D(6:0). Program variable D in Register 0x09, D(5:0) and Register
0x0A, D(7:0). The default value for D is 0. Program variable P in Register 0x08, D(7). The default value for P is
0.
Register 0x01, D(5:4) sets the PLL_CLKIN input to MCLK, BCLK, or IVCLKIN. Set Register 0x01, D(5:4) = 00 to
use MCLK, 01 to use BCLK, and 10 to use IVCLKIN.
There is also an option to use a 1.8 MHz internal oscillator for PLL_CLKIN. This is useful for systems using the
analog inputs and the I-V sense data returning to a host processor via PDM mode interface. Set Register 0x01,
D(5:4) = 11 to use the 1.8 MHz internal oscillator.
To bypass the PLL, set Register 0x09, D(7) = 1. Deactivate the PLL by setting Register 0x02, D(3) = 0.
When the PLL is enabled, the following conditions must be satisfied:
• If D = 0, the PLL clock input (PLL_CLKIN) must satisfy:
PLL_CLKIN
512 kHz £
£ 12.288 MHz
2P
• If D ≠ 0, the PLL clock input (PLL_CLKIN) must satisfy:
PLL_CLKIN
1.1 MHz £
£ 9.2 MHz
2P
Figure 27 shows the clock distribution tree and the registers required to set the audio input DAC and the I-V
sense ADC.
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Feature Description (continued)
1.8 MHz
Internal
IVCLKIN
MCLK
BCLK
00
Register 0x01, D(5:4)
10
01
11
PLL_CLKIN
u
0.5 u J.D
2P
Registers 0x08 - 0x0A
PLL_CLK
1
Register 0x09, D(7)
0
PLL_BYPASS
24.5760 MHz (for 16-bit, FS = 48 kHz)
22.5792 MHz (for 16-bit, FS = 44.1 kHz)
÷8
IVCLKIN
MCLK
BCLK
To DAC clock input
00
01
10
11
Register 0x11, D(1:0)
PDM_CLK
0 = falling edge
1 = rising edge
Register 0x03, D(6)
0 = PDM
1 = I2S / LJF / RJF / DSP
1
0
Register 0x11, D(2)
I2S_OUT_SEL
I-V sense
ADC clock generation
Figure 27. Clock Distribution Tree
7.3.8 Gain Settings
The TAS2552 has one gain register for both analog input and digital input (DAC output) gain. A mux selects only
one of these inputs for the Class-D speaker amplifier. The analog and digital inputs cannot be mixed together.
The full-scale DAC output voltage is the same as the maximum analog input voltage (for less than 1% THD): 1
VRMS, or 1.4 VPEAK.
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Table 1. TAS2552 Gain Table
GAIN BYTE:
GAIN[4:0]
NOMINAL GAIN
GAIN BYTE:
GAIN[4:0]
00000
–7 dB
10000
9 dB
00001
–6 dB
10001
10 dB
00010
–5 dB
10010
11 dB
00011
–4 dB
10011
12 dB
00100
–3 dB
10100
13 dB
00101
–2 dB
10101
14 dB
00110
–1 dB
10110
15 dB
00111
0 dB
10111
16 dB
01000
1 dB
11000
17 dB
01001
2 dB
11001
18 dB
01010
3 dB
11010
19 dB
01011
4 dB
11011
20 dB
01100
5 dB
11100
21 dB
01101
6 dB
11101
22 dB
01110
7 dB
11110
23 dB
01111
8 dB
11111
24 dB
NOMINAL GAIN
7.3.9 Class-D Edge Rate Control
The edge rate of the Class-D output is controllable via an I2C register. This allows users the ability to adjust the
switching edge rate of the Class-D amplifier, trading off some efficiency for lower EMI. Table 2 lists the typical
edge rates.
Table 2. Class-D Edge Rate Control
18
ERC BYTE:
EDGE[2:0]
TR AND TF
(TYPICAL)
000
50 ns
001
40 ns
010
30 ns
011
25 ns
100
14 ns
101
13 ns
110
12 ns
111
11 ns
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7.3.10 Battery Tracking AGC
The TAS2552 monitors battery voltage and the audio signal to automatically decrease gain when the battery
voltage is low and audio output power is high. This finds the optimal gain to maximize loudness and minimize
battery current, providing louder audio and preventing early shutdown at end-of-charge battery voltage levels.
VLIM
This does not mean the battery tracking AGC automatically decreases amplifier gain when VBAT is below the
inflection point. Rather, gain is decreased only when the Class-D output voltage exceeds the limiter level.
VLIM |
'VLIM
InflPt VBAT
8V
'VBAT
VLIM | 8 V
InflPt
VBAT
Figure 28. VLIM versus Supply Voltage (VBAT)
When VBAT is greater than the inflection point, VLIM - the peak allowed output voltage - is set by the boost
voltage. The inflection point is set in Register 0x0B, Bits 7-0. The inflection point range is 3.0 V to 5.5 V,
adjustable in 17.33 mV steps.
When VBAT is less than the inflection point, the peak output voltage is controlled by the slope. Set the VLIM vs.
VBAT slope in Register 0x0C, Bits 7-0. This ΔVLIM / ΔVBAT range is 1.2 V/V to 10.75 V/V and is adjustable in
37.3 mV/V steps.
If the audio signal is higher than VLIM, then the gain decreases until the audio signal is just below VLIM. The
gain decrease rate (attack time) is set via the I2C interface. If the audio signal is below VLIM and the gain is
below the fixed gain, the gain will increase. The gain increase rate (release time) is set via the I2C interface. The
attack and release times are selected via I2C interface. Eight attack times are available in 350 µs / dB steps.
Sixteen release times are in 105 ms / dB steps. ATK_TIME[2:0] is Register 0x0E, Bits 0-2. REL_TIM[3:0] is
Register 0x0F, Bits 3-0.
Table 3. Attack Time Selection
ATTACK TIME REGISTER
BYTE: ATK_TIME[2:0]
ATTACK TIME
( µS / STEP)
000
20
001
370
010
720
011
1070
100
1420
101
1770
110
2120
111
2470
Table 4. Release Time Selection
RELEASE TIME REGISTER
BYTE: REL_TIME[3:0]
RELEASE TIME
( MS / STEP)
RELEASE TIME REGISTER
BYTE: REL_TIME[4:0]
RELEASE TIME
(MS / STEP)
0000
50
1000
890
0001
155
1001
995
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Table 4. Release Time Selection (continued)
RELEASE TIME REGISTER
BYTE: REL_TIME[3:0]
RELEASE TIME
( MS / STEP)
RELEASE TIME REGISTER
BYTE: REL_TIME[4:0]
RELEASE TIME
(MS / STEP)
0010
260
1010
1100
0011
365
1011
1205
0100
470
1100
1310
0101
575
1101
1415
0110
680
1110
1520
0111
785
1111
1625
7.3.11 Configurable Boost Current Limit (ILIM)
The TAS2552 has a configurable boost current limit (ILIM).
Table 5. Current Limit Settings
CURRENT LIMIT REGISTER
Bit [7:6]
BOOST CURRENT LIMIT (ILIM)
(A)
00
1.5
01
2.0
10
2.5 (default)
11
3.0
Because changes to the current limit may require changes to the passive components connected to the boost, a
special I2C sequence is required to change the current limit values. To program the current limit of the TAS2552,
follow this I2C write sequence.
1. w 80 21 02
2. w 80 21 01
3. w 80 21 04
4. w 80 21 07
5. r 80 32 01 and save the value of register 0x32
6. w 80 32 0bYYXXXXXX where YY are the two bits from Table 5. RETAIN the values in the other bits read in
the step above.
7. w 80 21 07
7.4 Device Functional Modes
7.4.1 Audio Digital I/O Interface
Audio data is transferred between the host processor and the TAS2552 via the digital audio data serial interface,
or audio bus. The audio bus on this device is very flexible, including left or right-justified data options, support for
I2S or PCM protocols, programmable data length options, a TDM mode for multichannel operation, very flexible
master/slave configurability for each bus clock line, and the ability to communicate with multiple devices within a
system directly.
The audio bus of the TAS2552 can be configured for left or right-justified, I2S, DSP, or TDM modes of operation,
where communication with standard telephony PCM interfaces is supported within the TDM mode. These modes
are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring Register 0x05, D(1:0). In
addition, the word clock and bit clock can be independently configured in either Master or Slave mode, for
flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame,
and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to
the maximum of the selected ADC and DAC sampling frequencies.
The bit clock is used to clock in and clock out the digital audio data across the serial bus. This signal can be
programmed to generate variable clock pulses by controlling the bit-clock multiply-divide factor in Registers 0x08
through 0x10. The number of bit-clock pulses in a frame may need adjustment to accommodate various wordlengths as well as to support the case when multiple TAS2552 devices may share the same audio bus.
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Device Functional Modes (continued)
The TAS2552 also includes a feature to offset the position of start of data transfer with respect to the word-clock.
This offset is in number of bit-clocks and is programmed in Register 0x06.
To place the DOUT line into a Hi-Z (3-state) condition during all bit clocks when valid data is not being sent, set
Register 0x04, D(2) = 1. By combining this capability with the ability to program what bit clock in a frame the
audio data begins, time-division multiplexing (TDM) can be accomplished. This enables the use of multiple
devices on a single audio serial data bus. When the audio serial data bus is powered down while configured in
master mode, the terminals associated with the interface are put into a Hi-Z output state.
7.4.1.1 Right-Justified Mode
Set Register 0x03, D(6) = 0 and Register 0x05, D(3:2) = 10 to place the TAS2552 audio interface into rightjustified mode. In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock
preceding the falling edge of the word clock. Similarly, the LSB of the right channel is valid on the rising edge of
the bit clock preceding the rising edge of the word clock.
1/fs
WCLK
BCLK
Left Channel
DIN/
DOUT
0
n-1 n-2 n-3
Right Channel
2
MSB
1
0
n-1 n-2 n-3
LSB
2
MSB
1
0
LSB
Figure 29. Timing Diagram for Right-Justified Mode
For right-justified mode, the number of bit-clocks per frame should be greater than twice the programmed wordlength of the data.
7.4.1.2 Left-Justified Mode
Set Register 0x03, D(7:6) = 01 and Register 0x05, D(3:2) = 11 to place the TAS2552 audio interface into leftjustified mode. In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock
following the falling edge of the word clock. Similarly the MSB of the left channel is valid on the rising edge of the
bit clock following the rising edge of the word clock.
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
DATA
N N N
- - 1 2 3
3
2
1
N N N
- - 1 2 3
0
LD(n)
3
2
1
N N N
- - 1 2 3
0
RD(n)
LD(n) = n'th sample of left channel data
LD(n+1)
RD(n) = n'th sample of right channel data
Figure 30. Timing Diagram for Left-Justified Mode
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Device Functional Modes (continued)
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
DATA
N N N
- - 1 2 3
3
2
1
N N N
- - 1 2 3
0
LD(n)
3
2
1
0
RD(n)
LD(n) = n'th sample of left channel data
N N N
- - 1 2 3
LD(n+1)
RD(n) = n'th sample of right channel data
Figure 31. Timing Diagram for Light-Left Mode with Offset=1
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
N N N
- - 1 2 3
DATA
3
2
1
N N N
- - 1 2 3
0
LD(n)
3
2
1
0
RD(n)
LD(n) = n'th sample of left channel data
N N N
- - 1 2 3
3
LD(n+1)
RD(n) = n'th sample of right channel data
Figure 32. Timing Diagram for Left-Justified Mode with Offset=0 and Inverted Bit Clock
For left-justified mode, the number of bit-clocks per frame should be greater than twice the programmed wordlength of the data. Also, the programmed offset value should be less than the number of bit-clocks per frame by
at least the programmed word-length of the data.
7.4.1.3 I2S Mode
Set Register 0x03, D(7:6) = 01 and Register 0x05, D(3:2) = 00 to place the TAS2552 audio interface into I2S
mode. In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling
edge of the word clock. Similarly the MSB of the right channel is valid on the second rising edge of the bit clock
after the rising edge of the word clock.
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
DATA
N N N
- - 1 2 3
3
2
1
N N N
- - 1 2 3
0
LD(n)
3
2
1
0
RD(n)
LD(n) = n'th sample of left channel data
N N N
- - 1 2 3
3
LD(n+1)
RD(n) = n'th sample of right channel data
Figure 33. Timing Diagram for I2S Mode
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Device Functional Modes (continued)
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
N
1
DATA
5
4
3
2
1
N
1
0
5
4
LD(n)
3
2
1
N
1
0
RD(n)
LD(n) = n'th sample of left channel data
5
LD (n+1)
RD(n) = n'th sample of right channel data
Figure 34. Timing Diagram for I2S Mode with Offset=2
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
N N N
- - 1 2 3
DATA
3
2
1
N N N
- - 1 2 3
0
LD(n)
3
2
1
N N N
- - 1 2 3
0
RD(n)
LD(n) = n'th sample of left channel data
3
LD(n+1)
RD(n) = n'th sample of right channel data
Figure 35. Timing Diagram for I2S Mode with Offset=0 and Inverted Bit Clock
For I2S mode, the number of bit-clocks per channel should be greater than or equal to the programmed wordlength of the data. Also the programmed offset value should be less than the number of bit-clocks per frame by
at least the programmed word-length of the data.
7.4.1.4 Audio Data Serial Interface Timing (I2S, Left-Justified, Right-Justified Modes)
All specifications at 25°C, IOVDD = 1.8 V
NOTE
All timing specifications are measured at characterization but not tested at final test.
WCLK
td(WS)
BCLK
td(DO-WS)
td(DO-BCLK)
DOUT
tS(DI)
th(DI)
DIN
Figure 36. I2S/LJF/RJF Timing in Master Mode
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Device Functional Modes (continued)
Table 6. I2S/LJF/RJF Timing in Master Mode (see Figure 36)
IOVDD=1.8V
PARAMETER
MIN
IOVDD=3.3V
MAX
MIN
MAX
UNIT
td(WS)
WCLK delay
30
20
ns
td(DO-WS)
WCLK to DOUT delay (For LJF Mode only)
50
25
ns
td(DO-BCLK)
BCLK to DOUT delay
50
25
ns
ts(DI)
DIN setup
8
8
ns
th(DI)
DIN hold
8
8
ns
tr
Rise time
24
12
ns
tf
Fall time
24
15
ns
WCLK
th(WS)
BCLK
tL(BCLK)
tH(BCLK)
ts(WS)
td(DO-WS)
td(DO-BCLK)
DOUT
th(DI)
ts(DI)
DIN
Figure 37. I2S/LJF/RJF Timing in Slave Mode
Table 7. I2S/LJF/RJF Timing in Slave Mode (see Figure 37)
IOVDD=1.8V
PARAMETER
MIN
IOVDD=3.3V
MAX
MIN
MAX
UNIT
tH(BCLK)
BCLK high period
35
35
ns
tL(BCLK)
BCLK low period
35
35
ns
ts(WS)
(WS)
8
8
ns
th(WS)
WCLK hold
8
td(DO-WS)
WCLK to DOUT delay (For LJF Mode only)
50
25
ns
td(DO-BCLK)
BCLK to DOUT delay
50
25
ns
ts(DI)
DIN setup
8
8
th(DI)
DIN hold
8
8
tr
Rise time
4
4
ns
tf
Fall time
4
4
ns
24
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8
ns
ns
ns
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7.4.1.5 DSP Mode
Set Register 0x03, D(7:6) = 01 and Register 0x05, D(3:2) = 01 to place the TAS2552 audio interface into DSP
mode. In DSP mode, the rising edge of the word clock starts the data transfer with the left channel data first and
immediately followed by the right channel data. Each data bit is valid on the falling edge of the bit clock.
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
DATA
N N N
- - 1 2 3
3
2
1
0
N N N
- - 1 2 3
LD(n)
3
2
1
N N N
- - 1 2 3
0
RD(n)
LD(n) = n'th sample of left channel data
3
LD (n+1)
RD(n) = n'th sample of right channel data
Figure 38. Timing Diagram for DSP Mode
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
DATA
N N N
- - 1 2 3
3
2 1 0
N N N
- - 1 2 3
LD(n)
3 2 1
N N N
- - 1 2 3
0
RD(n)
LD(n) = n'th sample of left channel data
LD(n+1)
RD(n) = n'th sample of right channel data
Figure 39. Timing Diagram for DSP Mode with Offset=1
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
DATA
N N N
- - 1 2 3
3
2
1
0
LD(n)
N N N
- - 1 2 3
3
2
1
0
N N N
- - 1 2 3
RD(n)
3
LD(n+1)
Figure 40. Timing Diagram for DSP Mode with Offset=0 and Inverted Bit Clock
For DSP mode, the number of bit-clocks per frame should be greater than twice the programmed word-length of
the data. Also the programmed offset value should be less than the number of bit-clocks per frame by at least
the programmed word-length of the data.
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7.4.1.6 DSP Timing
All specifications at 25°C, IOVDD = 1.8 V
NOTE
All timing specifications are measured at characterization but not tested at final test.
WCLK
td(WS)
td(WS)
BCLK
td(DO-BCLK)
DOUT
th(DI)
ts(DI)
DIN
Figure 41. DSP Timing in Master Mode
Table 8. DSP Timing in Master Mode (see Figure 41)
IOVDD=1.8V
PARAMETER
MIN
IOVDD=3.3V
MAX
MIN
MAX
UNIT
td(WS)
WCLK delay
30
20
ns
td(DO-BCLK)
BCLK to DOUT delay
40
20
ns
ts(DI)
DIN setup
8
8
th(DI)
DIN hold
8
8
tr
Rise time
4
4
ns
tf
Fall time
4
4
ns
ns
ns
WCLK
th(ws)
BCLK
tH(BCLK)
ts(ws)
th(ws)
th(ws)
tL(BCLK)
td(DO-BCLK)
DOUT
ts(DI)
th(DI)
DIN
Figure 42. DSP Timing in Slave Mode
26
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Table 9. DSP Timing in Slave Mode (see Figure 42)
IOVDD=1.8V
PARAMETER
MIN
IOVDD=3.3V
MAX
MIN
MAX
UNIT
tH(BCLK)
BCLK high period
35
35
ns
tL(BCLK)
BCLK low period
35
35
ns
ts(WS)
(WS)
8
8
ns
th(WS)
WCLK hold
8
8
ns
td(DO-WS)
WCLK to DOUT delay (For LJF Mode only)
ts(DI)
DIN setup
8
8
ns
th(DI)
DIN hold
8
8
ns
tr
Rise time
4
4
ns
tf
Fall time
4
4
ns
40
22
ns
7.4.2 TDM Mode
Time-division multiplexing (TDM) allows two or more devices to share a common DIN connection and a common
DOUT connection. Using TDM mode, all devices transmit their DOUT data in user-specified sub-frames within
one WCLK period. When one device transmits its DOUT information, the other devices place their DOUT
terminals in a high impedance tri-state mode.
TDM mode is useable with I2S, LJF, RJF, and DSP interface modes. Refer to the respective sections for a
description of how to set the TAS2552 into those modes. TDM cannot be used with PDM mode. This is because
the PDM requires a continuous stream of samples from one data source.
Use Register 0x06 to set the clock cycle offset from WCLK to the MSB. Each data bit is valid on the falling edge
of the bit clock. Set Register 0x04, D(2) = 1 to force DOUT into tri-state when it is not transmitting data. This
allows DOUT terminals from multiple TAS2552 devices to share a common wire to the host.
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
BIT
CLOCK
DATA
N
1
5
4
3
2
1
N
1
0
5
LD(n)
4
3
2
1
0
RD(n)
LD(n) = n'th sample of left channel data
N
1
5
LD (n+1)
RD(n) = n'th sample of right channel data
Figure 43. Timing Diagram for I2S in TDM Mode with Offset=2
For TDM mode, the number of bit-clocks per frame should be less than the programmed word-length of the data.
Also the programmed offset value should be less than the number of bit-clocks per frame by at least the
programmed word-length of the data.
Figure 44 shows how to configure the TAS2552 with the TI codec, AIC3254, with both devices sharing DIN and
DOUT
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Host (Baseband /
Apps Processor)
AIC3254
MCLK
MCLK
HPR
BCLK
BCLK
HPL
WCLK
WCLK
DOUT
DIN
Headphone
Output
LOL
SDA
SDA
SCL
SCL
LOR
Line
Output
DOUT
DIN
7-Bit I2C Address:
0x18
IOVDD
DOUT
ADDR
MCLK
OUT+
BCLK
OUT-
WCLK
VSENSE+
DIN
VSENSE-
Speaker
Output
SDA
SCL
7-Bit I2C Address:
0x40 or 0x41
TAS2552
Figure 44. Configuration with TAS2552 and AIC3254 Muxed in TDM Mode
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Host (Baseband /
Apps Processor)
TAS2552
MCLK
MCLK
OUT+
BCLK
BCLK
OUT-
WCLK
WCLK
VSENSE+
DOUT
DIN
VSENSE-
SDA
SDA
SCL
SCL
DOUT
Speaker
Output
ADDR
DIN
7-Bit I2C Address:
0x40
IOVDD
7-Bit I2C Address:
0x41
DOUT
ADDR
MCLK
OUT+
BCLK
OUT-
WCLK
VSENSE+
DIN
VSENSE-
Speaker
Output
SDA
SCL
TAS2552
Figure 45. Stereo Configuration with Two TAS2552 DOUT Muxed in TDM Mode
7.4.3 PDM Mode
Set Register 0x03, D(7:6) = 00 to place the TAS2552 audio interface into PDM mode. In PDM mode, the data
stream is a continuous stream of undecimated pulse-modulated data that is 64x the sample rate. Because it is a
continuous stream, frame synchronization is not required and WCLK is not used. Specifying clocks-per-frame is
not required for PDM mode. The PDM input bit clock is IVCLKIN as set in Register 0x11, D(1:0).
The TAS2552 can be configured for I2S input mode and PDM output mode. Figure 46 shows the timing diagram
for PDM input mode. Timing specifications are listed in Table 10 and Table 11.
The TAS2552 clocks PDM input data on either the rising edge or falling edge of IVCLKIN as set in Register
0x11, D(2). The device does not read concurrent data on both edges. Set the I2C register to read either rising
clock edge or falling clock edge data.
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tH
tS
tr
tf
IVCLKIN
DIN
DATA
DATA
Figure 46. DIN Timing Diagram in PDM Mode, Register 0x11, D(2) = 0
tH
tS
tr
tf
IVCLKIN
DIN
DATA
DATA
Figure 47. DIN Timing Diagram in PDM Mode, Register 0x11, D(2) = 1
Table 10. PDM Input Timing (1)
IOVDD=1.8V (2)
PARAMETER
MIN
IOVDD=3.3V
MAX
MIN
MAX
UNIT
ts
DIN setup
20
20
ns
th
DIN hold
3
3
ns
tr
Rise time
4
4
ns
tf
Fall time
4
4
ns
(1)
(2)
All timing specifications are measured at characterization but not tested at final test.
All specifications at 25°C, IOVDD = 1.8 V
7.4.3.1 DOUT Timing – PDM Output Mode
Set Register 0x03, D(6) = 0 to transmit PDM data on the DOUT terminal. Register 0x07, D(7:6) selects either I
Data, V Data, or both for PDM transmission. Register 0x07, D(5) selects whether the data transmits on either the
rising edge or the falling edge of IVCLKIN. The DOUT terminal becomes high-impedance on the opposing clock
cycle.
td(DATA)
td(HI-Z)
td(DATA)
IVCLKIN
DOUT
HI-Z
DATA
HI-Z
DATA
HI-Z
Figure 48. DOUT Timing in PDM Mode (Data on IVCLKIN High)
30
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td(DATA)
td(HI-Z)
IVCLKIN
DOUT
DATA
DATA
HI-Z
HI-Z
DATA
Figure 49. DOUT Timing in PDM Mode (Data on IVCLKIN Low)
Table 11. DOUT Timing in PDM Mode (1)
IOVDD=1.8V (2)
PARAMETER
MIN
td(DATA)
IVCLKIN to DOUT delay
td(HI-Z)
IVCLKIN to high impedance state delay
(1)
(2)
IOVDD=3.3V
MAX
MIN
MAX
UNIT
30
30
ns
6
6
ns
All timing specifications are measured at characterization but not tested at final test.
All specifications at 25°C, IOVDD = 1.8 V
7.5 Register Map
The TAS2552 I2C address is 0x40 (7-bit) when ADDR = 0 and 0x41 (7-bit) when ADDR = 1. See the General I2C
Operation section for more details.
7.5.1 Register Map Summary
REGISTER
READ/WRITE
DEFAULT
0x00
R/W
0x00
Device Status Register
0x01
R/W
0x22
Configuration Register 1
2
0x02
R/W
0xFF
Configuration Register 2
3
0x03
R/W
0x80
Configuration Register 3
4
0x04
R/W
0x00
DOUT Tristate Mode
5
0x05
R/W
0x00
Serial Interface Control Register 1
6
0x06
R/W
0x00
Serial Interface Control Register 2
7
0x07
R/W
0xC0
Output Data Register
8
0x08
R/W
0x10
PLL Control Register 1
DEC
HEX
0
1
FUNCTION
9
0x09
R/W
0x00
PLL Control Register 2
10
0x0A
R/W
0x00
PLL Control Register 3
11
0x0B
R/W
0x8F
Battery Tracking Inflection Point Register
12
0x0C
R/W
0x80
Battery Tracking Slope Control Register
13
0x0D
R/W
0xBE
Limiter Level Control Register
14
0x0E
R/W
0x08
Limiter Attack Rate and Hysteresis Time
15
0x0F
R/W
0x05
Limiter Release Rate
16
0x10
R/W
0x00
Limiter Integration Count Control
17
0x11
R/W
0x01
PDM Configuration Register
18
0x12
R/W
0x00
PGA Gain Register
19
0x13
R/W
0x40
Class-D Edge Rate Control Register
20
0x14
R/W
0x00
Boost Auto-Pass Through Control Register
21
0x15
R/W
0x00
Reserved
22
0x16
R
0x00
Version Number
23
0x17
R/W
0x00
Reserved
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Register Map (continued)
REGISTER
READ/WRITE
DEFAULT
0x18
R
0x00
Reserved
0x19
R
0x00
VBAT Data Register
DEC
HEX
24
25
FUNCTION
7.5.2 Register 0x00: Device Status Register
This register uses latched faults. The fault bits are clear on write. Read-only commands retain the latched value
of the fault bit.
BIT
NAME
7-6
5
PLL_OUT_OF_LOCK
4-2
READ/WRITE
DEFAULT DESCRIPTION
R/W
00
Reserved. Write only default values.
R/W
0
PLL lock
0 = PLL is locked
1 = PLL is not locked
R/W
0
Reserved. Write only default values.
1
CLASSD_ILIM
R/W
0
Class-D over-current
0 = Normal operation
1 = Class-D output current limit has been exceeded
0
THERMAL
R/W
0
Thermal limit
0 = Normal operation
1 = Limit exceeded
7.5.3 Register 0x01: Configuration Register 1
BIT
NAME
7-6
5-4
PLL_SRC
3
(1)
READ/WRITE
DEFAULT DESCRIPTION
R/W
00
Reserved. Write only default values.
R/W
10
PLL Input
00 = MCLK
01 = BCLK
10 = IVCLKIN
11 = 1.8 MHz fixed internal oscillator
R/W
0
Reserved. Write only default values.
2
MUTE
R/W
0
Triggers mute of Class-D channel controller.
0 = Not muted
1 = Muted
1
SWS
R/W
1
Software shutdown. When high shuts down all blocks and places part in low
power mode. THIS BIT MUST BE SET TO ZERO ONLY AFTER THE
DEVICE CONFIGURATION IS COMPLETE.
0
DEV_RESET (1)
R/W
0
Synchronous reset of all digital registers & control circuitry.
Wait a minimum of 1ms after EN is pulled high or DEV_RESET is issued before accessing the control interface.
7.5.4 Register 0x02: Configuration Register 2
BIT
32
READ/WRITE
DEFAULT
DESCRIPTION
7
NAME
CLASSD_EN
R/W
1
Class D Enable
6
BOOST_EN
R/W
1
Boost Enable
5
APT_EN
R/W
1
Auto Pass-Thru Enable
4
RESERVED
R/W
0
Reserved. Write only default values.
3
PLL_EN
R/W
1
PLL Enable
2
LIM_EN
R/W
1
Battery Tracking AGC Enable
1
IVSENSE_EN
R/W
1
I/V Sense Enable
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BIT
0
(1)
NAME
RESERVED
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READ/WRITE
DEFAULT
R/W
1 (1)
DESCRIPTION
Reserved. MUST BE WRITTEN TO ZERO DURING CONFIGURATION
SEQUENCE as shown in Initialization.
Register 0x02, Bit 0 defaults to 1, but must be written to 0 during initialization.
7.5.5 Register 0x03: Configuration Register 3
BIT
NAME
READ /
WRITE
DEFAULT
DESCRIPTION
7
ANALOG_IN_SEL
R/W
1
Selects analog in path for data to class-D. When set to zero (digital in), no
signal should be present on the analog terminals.
0 = Digital Audio Input
1 = Analog Audio Input
6
I2S_OUT_SEL
R/W
0
Selects between PDM and I2S for I/V Sense output data format.
0 = PDM
1 = I2S
5
PDM_IN_SEL
R/W
0
Selects PDM as input to modulator
0 = PDM is not selected
1 = PDM is selected only if Digital Audio Input is selected (Reg 0x03 D[7] =
0)
4-3
DIN_SOURCE_SEL
R/W
00
DIN Source Select
00 = Modulator input muted
01 = Use left stream for modulator
10 = Use right stream for modulator
11 = Use average of left and right streams for modulator
2-0
WCLK_FREQ
R/W
000
WCLK Frequency
000 = 8 kHz
001 = 11.025 kHz / 12 kHz
010 = 16 kHz
011 = 22.05 kHz / 24 kHz
100 = 32 kHz
101 = 44.1 kHz / 48 kHz
110 = 88.2 kHz / 96 kHz
111 = 176.4 kHz / 192 kHz
7.5.6 Register 0x04: DOUT Tristate Mode
For systems with multiple devices sharing a common DOUT line with a TDM interface mode, set Bit 2 to 1 to
ensure DOUT stays in high-impedance tri-state mode when it is not transmitting data.
BIT
NAME
7-3
2
1-0
SDOUT_TRISTATE
READ /
WRITE
DEFAULT
R/W
0000 0
R/W
0
DOUT Tri-state Mode (for I2S mode only, see Reg 0x03, bit 7)
0 = DOUT set to logic low when not transmitting data
1 = DOUT in tristate when not transmitting data
R/W
00
Reserved. Write only default values.
DESCRIPTION
Reserved. Write only default values.
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7.5.7 Register 0x05: Serial Interface Control Register 1
BIT
NAME
READ/WRITE
DEFAULT
DESCRIPTION
7
WCLKDIR
R/W
0
WCLK Direction
0 = WCLK is an input terminal
1 = WCLK is an output terminal
6
BCLKDIR
R/W
0
BCLK Direction
0 = BCLK is an input terminal
1 = BCLK is an output terminal
5-4
CLKSPERFRAME
R/W
00
Clocks per Frame
00 = 32 clocks
01 = 64 clocks
10 = 128 clocks
11 = 256 clocks
3-2
DATAFORMAT
R/W
00
Data Format
00 = I2S format
01 = DSP (PCM format)
10 = Right justified format (RJF)
11 = Left justified format (LJF)
1-0
WORDLENGTH
R/W
00
Word Length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = 32 bits
7.5.8 Register 0x06: Serial Interface Control Register 2
This register sets the clock cycle offset between the WCLK edge to the MSB of serial interface patterns. This is
useful for TDM mode where multiple devices share DIN or DOUT lines.
34
BIT
NAME
7-0
I2S_SHIFT_REG
READ /
WRITE
DEFAULT
DESCRIPTION
R/W
0000 0000
Offset from WCLK to MSB in serial interface patterns.
0000 0000 = 0 bit offset
0000 0001 = 1 bit offset
….
1111 1111 = 255 bit offset
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7.5.9 Register 0x07: Output Data Register
This register sets the output data for DOUT. Most systems will simply set L_DATA_OUT to transmit output
current data and R_DATA_OUT to transmit voltage data. Other data is available, like VBAT voltage, VBOOST
voltage, and PGA gain.
Bit 5 is a dual-purpose bit. If I2S_OUT_SEL = 0 (Register 0x03, Bit 6) and the PDM_DATA_SEL bits are set to
transmit only I-Data or V-Data, then Bit 5 dictates if that data is transmitted on the clock rising edge or falling
edge. This allows two TAS2552 devices in PDM mode to tie their DOUT lines together and connect to the host
digital mic input. In this configuration, each device broadcasts its output current or output voltage information –
one on the rising edge of the clock, the other on the falling edge. This is a simple interface technique that does
not require programming the host for TDM-interface mode.
BIT
READ / WRITE
DEFAULT
7-6
PDM_DATA_SEL
NAME
R/W
11
DESCRIPTION
PDM Data Select
These bits are operative only if I2S_OUT_SEL = 0 for PDM mode (see
Register 0x03, Bit 6).
00 - I Data Only - Select Ch1 or Ch2 with bit[5]
01 - V Data Only - Select Ch1 or Ch2 with bit[5]
10 - I/V Data (Ch1/2)
11 - V/I Data (Ch1/2)
5-3
R_DATA_OUT
R/W
000
Serial Interface Data, Right Channel
Bit 5 is a dual-purpose bit, depending on the state of I2S_OUT_SEL
(Register 0x03, Bit 6).
If I2S_OUT_SEL = 0 and PDM_DATA_SEL = 00 or 01 (for singlechannel PDM output mode), then Bit 5 will select whether data is
transmitted on the rising or falling edge of the clock.
0xx = Falling Edge (Ch 1)
1xx = Rising Edge (Ch 2)
If I2S_OUT_SEL = 1, then Bits 5-3 have the same function as
L_DATA_OUT. Read the description in L_DATA_OUT for requirements
on BCLK and WORD_LENGTH.
000 = I Data (16'b)
001 = V Data (16'b)
010 = VBAT Data (8'b)
011 = VBOOST Data (8'b)
100 = PGA Gain (5'b)
101 = I Data, V Data (32'b)
110 = VBAT, VBOOST, PGA Gain (21'b)
111 = Disabled (Hi-Z)
NOTE: For VBAT and VBOOST, the device must be in a mode that uses
this information, such as Battery Tracking AGC.
2-0
L_DATA_OUT
R/W
000
Serial Interface Data, Left Channel
Users must provide enough BCLK cycles per WCLK frame to shift all the
data out. If there are additional BCLK cycles per WCLK frame beyond
the WORD_LENGTH setting, the data line will be HI-Z if
SDOUT_TRISTATE (Register 0x04, Bit 3) is set to 1; otherwise the data
line will be held low for the extra BCLK cycles.
Users must also program a sufficient WORD_LENGTH setting. If
selected data contains fewer bits than WORD_LENGTH setting, the
extra bits will be 0's.
000 = I Data (16'b)
001 = V Data (16'b)
010 = VBAT Data (8'b)
011 = VBOOST Data (8'b)
100 = PGA Gain (5'b)
101 = I Data, V Data (32'b)
110 = VBAT, VBOOST, PGA Gain (21'b)
111 = Disabled (Hi-Z)
NOTE: For VBAT and VBOOST, the device must be in a mode that uses
this information, such as Battery Tracking AGC.
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7.5.10 Register 0x08: PLL Control Register 1
The equation for the PLL frequency is:
0.5 ´ PLL _ CLKIN ´ J.D
PLL _ CLK =
2P
(2)
J = 4, 5, 6, … 96
D = 0, 1, 2, ... 9999
P = 0,1
Registers 0x08 – 0x0A will only update when the PLL is disabled. To update the J, D, and P coefficients, set
PLL_EN = 0 (Register 0x02, Bit 3) to disable the PLL, update Registers 0x08 – 0x0A, then set PLL_EN = 1 to
activate the PLL.
BIT
7
6-0
NAME
READ / WRITE
DEFAULT
PLL_PRESCALE_SEL
R/W
0
PLL_J
R/W
001 0000
DESCRIPTION
PLL P Pre-Scale Select
1: P = 1
0: P = 0
PLL J Characteristic Multiplier Value
000 0000 … 000 0011: Do not use
000 0100: J=4
…
001 0000: J=16
…
101 1111: J=95
110 0000: J=96
110 0001 ... 111 1111: Do not use
7.5.11 Register 0x09: PLL Control Register 2
BIT
7
NAME
PLL_BYPASS
READ /
WRITE
DEFAULT
R/W
0
1: Bypasses PLL by setting PLL_CLK = PLL_CLKIN
0: Sets PLL_CLK according to Equation 2
0
Reserved
6
5-0
PLL_D[13:8]
R/W
00 0000
DESCRIPTION
PLL D Mantissa Multiplier Value (LSB)
The complete PLL D value comprises PLL_D[13:8] (MSB) concatenated
with PLLD[7:0] (LSB)
00 0000 0000 0000: D=0000
00 0000 0000 0001: D=0001
…
10 0111 0000 1110: D=9998
10 0111 0000 1111: D=9999
10 0111 0001 0000 ... 11 1111 1111 1111: Do not use
7.5.12 Register 0x0A: PLL Control Register 3
36
BIT
NAME
7-0
PLL_D[7:0]
READ /
WRITE
DEFAULT
DESCRIPTION
R/W
0000 0000
PLL D Mantissa Multiplier Value (LSB)
The complete PLL D value comprises PLL_D[13:8] (MSB) concatenated
with PLLD[7:0] (LSB)
00 0000 0000 0000: D=0000
00 0000 0000 0001: D=0001
…
10 0111 0000 1110: D=9998
10 0111 0000 1111: D=9999
10 0111 0001 0000 ... 11 1111 1111 1111: Do not use
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7.5.13 Register 0x0B: Battery Tracking Inflection Point Register
BIT
NAME
7-0
INFLECTION
READ /
WRITE
DEFAULT
DESCRIPTION
R/W
1000 1111
Battery Inflection Point Value
0.01733 V per step
0000 0000 = RESERVED
…
0110 1100 = RESERVED
0110 1101 = 3.00 V
…
1111 1101 = 5.49 V
1111 1110 = 5.50 V
1111 1111 = RESERVED
7.5.14 Register 0x0C: Battery Tracking Slope Control Register
BIT
NAME
READ /
WRITE
DEFAULT
DESCRIPTION
7-0
SLOPE
R/W
1000 0000
Battery Tracking Slope Value (ΔVLIM / ΔVBAT)
0.0373 V/V per step
0000 0000 = 1.2 V/V
0000 0001 = 1.237 V/V
…
1111 1101 = 10.675 V/V
1111 1110 = 10.713 V/V
1111 1111 = 10.75 V/V
7.5.15 Register 0x0D: Reserved Register
BIT
7-0
NAME
READ /
WRITE
DEFAULT
DESCRIPTION
R/W
1011 1110
Write to 0xC0 during initialization. See Initialization.
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7.5.16 Register 0x0E: Battery Tracking Limiter Attack Rate and Hysteresis Time
BIT
NAME
7-6
HYSTERESIS
READ / WRITE
DEFAULT
R/W
00
Hysteresis before re-arming release time
00 = No hysteresis
01 = 4.36 mV hysteresis
10 = 13.08 mV hysteresis
11 = 30.52 mV hysteresis
5
DESCRIPTION
R/W
0
Write to 1 during initialization. See Initialization.
4-3
APT_DIS_VOLTAGE
R/W
01
VBAT threshold below which Boost APT is disabled and the boost
remains active regardless of Class-D output voltage.
00 = 2.5 V
01 = 2.7 V
10 = 2.9 V
11 = 3.1 V
2-0
ATTACK_TIME
R/W
000
Attack Time
350 µs / dB per step
000 = 20 µs / dB
001 = 370 µs / dB
…
110 = 2120 µs / dB
111 = 2470 µs / dB
7.5.17 Register 0x0F: Battery Tracking Limiter Release Rate
BIT
NAME
7-4
3-0
REL_TIME
READ /
WRITE
DEFAULT
R/W
00
R/W
0100
DESCRIPTION
Reserved. Write only default values.
Release Time
105 ms / dB per step
0000 = 50 ms / dB
0001 = 155 ms / dB
…
1110 = 1520 ms / dB
1111 = 1625 ms / dB
7.5.18 Register 0x10: Battery Tracking Limiter Integration Count Control
Limiter integration affects how the AGC state machine interprets the AGC output voltage trigger threshold.
Increasing the integration count requires more AGC output peaks to exceed the limiter threshold before the
limiter changes its gain.
38
READ /
WRITE
DEFAULT
UP_DWN_RATIO
R/W
00
INT_CNT
R/W
00 0000
BIT
NAME
7-6
5-0
DESCRIPTION
Control Integration Count Up/Down Ratio
The UP_DWN_RATIO sets the ratio of the addition to and the subtraction
from the integration count, meaning that the input has to be below the limit
threshold for 4UP_DWN_RATIO counts before the integration count is reduced.
Integration Count Control Register
Larger values increase filtering before the attack and decay time are
triggered.
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7.5.19 Register 0x11: PDM Configuration Register
Sets the PDM clock source and whether channel 1 data is transmitted on the rising or falling edge of the clock.
Channel 2 transmits on the opposite edge.
BIT
NAME
7-3
READ /
WRITE
DEFAULT
DESCRIPTION
R/W
0 0000
2
PDM_DATA_ES
R/W
0
Reserved. Write only default values.
PDM Data Edge Select
0 = falling edge
1 = rising edge
1-0
PDM_CLK_SEL
R/W
01
PDM Clock Select
00 = PLL / 8
01 = IVCLKIN
10 = BCLK
11 = MCLK
7.5.20 Register 0x12: PGA Gain Register
BIT
NAME
7-5
4-0
PGA_GAIN
READ /
WRITE
DEFAULT
R/W
000
R/W
0 0000
DESCRIPTION
Reserved. Write only default values.
PGA Gain Value
00000 = -7 dB
00001 = -6 dB
…
11110 = +23 dB
11111 = +24 dB
7.5.21 Register 0x13: Class-D Edge Rate Control Register
BIT
7
6-4
3-0
READ /
WRITE
DEFAULT
GAINCOMP_EN
R/W
0
ERC_SEL
R/W
100
Class-D Output Edge Rate Control
000 = 50 ns
001 = 40 ns
010 = 29 ns
011 = 25 ns
100 = 14 ns (default)
101 = 13 ns
110 = 12 ns
111 = 11 ns
R/W
0000
Reserved. Write only default values.
NAME
DESCRIPTION
I-V Sense Gain Compensation Control
Enables AGC compensation for current sense feedback. AGC
compensation increases the gain of the current sense data by the same
gain the AGC instantaneously attenuates.
0 = No I-V sense gain compensation
1 = Gain compensation enabled
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7.5.22 Register 0x14: Boost Auto-Pass Through Control Register
Auto-Pass Through deactivates the boost converter when the battery voltage is sufficient for the required ClassD output voltage. This register sets the threshold for activating the boost converter and the delay time between
the Class-D output voltage dropping below the threshold before the boost converter deactivates.
BIT
NAME
7-4
READ /
WRITE
DEFAULT
DESCRIPTION
R/W
0000
3-2
APT_THRESHOLD
R/W
00
Reserved. Write only default values.
Analog Input – Auto-Pass Through Threshold
The boost converter activates when the Class-D output voltage exceeds
this threshold voltage.
00 = 0.5 V
01 = 1.0 V
10 = 1.4 V
11 = 2.0 V
Digital Input – Auto-Pass Through Threshold
The boost converter activates when the Class-D output voltage exceeds
this threshold voltage.
00 = 0.2 V
01 = 0.7 V
10 = 1.1 V
11 = 1.7 V
1-0
APT_DELAY_SEL
R/W
00
Auto-Pass Thru Delay
The delay between the Class-D output voltage dropping below the autopass thru threshold voltage and the boost converter deactivating.
00 = 50 ms
01 = 75 ms
10 = 125 ms
11 = 200 ms
7.5.23 Register 0x15: Reserved Register
BIT
NAME
7-0
READ /
WRITE
DEFAULT
DESCRIPTION
R
0000 0000
Reserved
7.5.24 Register 0x16: Version Number
BIT
NAME
7-4
3-0
SILICON_VER
READ /
WRITE
DEFAULT
R
0000
Reserved
R
1000
Silicon version identifier bits
DESCRIPTION
7.5.25 Register 0x17: Reserved Register
BIT
NAME
7-0
READ /
WRITE
DEFAULT
DESCRIPTION
R
0000 0000
Reserved
7.5.26 Register 0x18: Reserved Register
BIT
7-0
40
NAME
READ /
WRITE
DEFAULT
DESCRIPTION
R
0000 0000
Reserved
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7.5.27 Register 0x19: VBAT Data Register
BIT
NAME
READ /
WRITE
DEFAULT
DESCRIPTION
7-0
VBAT
R
0000 0000
Battery Voltage Data
VBAT data is only available when the device is in a mode that uses the
VBAT measurement, such as Battery Tracking AGC.
1 LSB ≈ 17.33 mV
0000 0000 = RESERVED
...
0100 1001 = RESERVED
0101 0000 = 2.5 V
…
1111 1111 = 5.55 V
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8 Applications and Implementation
8.1 Application Information
The TAS2552 is a digital or analog input high efficiency Class-D audio power amplifier with advanced battery
current management and an integrated Class-G boost converter. In auto passthrough mode, the Class-G boost
converter generates the Class-D amplifier supply rail. During low Class-D output power, the boost improves
efficiency by deactivating and connecting VBAT directly to the Class-D amplifier supply. When high power audio
is required, the boost quickly activates to provide louder audio than a stand-alone amplifier connected directly to
the battery. To enable load monitoring, the TAS2552 constantly measures the current and voltage across the
load and provides a digital stream of this information back to a processor.
8.2 Typical Applications
8.2.1 Typical Application - Digital Audio Input
1.65 V À 1.95 V
3.0 V À 5.5 V
L1
2.2 PH
C1
10 PF
0.1 PF
0.1 PF
2
AVDD
1.5 V À
3.6 V
VBAT
SW
VREG
IOVDD
10 nF
0.1 PF
VBOOST
C2
22 PF
EN
Enable
PVDD
L2 (opt.)
IN+
OUT+
+
OUT-
-
INPDM Clock
(opt.)
L3 (opt.)
IVCLKIN
2
I C Address Select
I2C Interface
ADDR
VSENSE+
I2C
VSENSE-
C3
1 nF
(opt.)
To
Speaker
C4
1 nF
(opt.)
2
2
I2S
I S Interface
5
AGND
BIAS
PGND
2
3
1 PF
Figure 50. Typical Application Schematic
Table 12. Recommended External Components
COMPONENT
L1
L2, L3
DESCRIPTION
Boost Converter Inductor
EMI Filter Inductors (optional)
SPECIFICATION
MIN
TYP
µH
Saturation Current
2.6
A
Impedance at 100MHz
120
DC Current
Size
42
Boost Converter Input Capacitor
UNIT
2.2
DC Resistance
C1
MAX
Inductance, 20% Tolerance
Capacitance, 20% Tolerance
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10
Ω
0.095
Ω
1.5
A
EIA
µF
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Typical Applications (continued)
Table 12. Recommended External Components (continued)
COMPONENT
C2
C3, C4
DESCRIPTION
SPECIFICATION
Boost Converter Output Capacitor
EMI Filter Capacitors (optional, must
use L2, L3 if C3, C4 used)
MIN
Type
TYP
MAX
UNIT
47
µF
X5R
Capacitance, 20% Tolerance
22
Rated Voltage
16
V
Capacitance at 8.5 V
derating
7
µF
Capacitance
1
nF
8.2.1.1 Design Requirements
Table 13. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Audio Input
Digital Audio, I2S
Current and Voltage Data Stream
Digital Audio, I2S
Mono or Stereo Configuration
Mono
Max Output Power at 1% THD+N
3.3
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Audio Input/Output
The choice of digital or analog audio input is driven by system specific considerations. However, since a digital
audio interface will typically be used to send current and voltage data from the TAS2552 to a system processor,
using a bidirectional I2S interface is likely to be the best choice.
If a digital audio input is used, the analog inputs, IN+ and IN-, should be shorted together, and not tied to ground.
8.2.1.2.2 Mono/Stereo Configuration
In this application, the device is assumed to be operating in mono mode. See General I2C Operation for
information on changing the I2C address of the TAS2552 to support stereo operation. Mono or stereo
configuration does not impact the device performance.
8.2.1.2.3 Boost Converter Passive Devices
The boost converter requires three passive devices that are labeled L1, C1 and C2 in Figure 50 and whose
specifications are provided in Table 12. These specifications are based on the design of TAS2552 and are
necessary to meet the performance targets of the device. In particular, L1 should not be allowed to enter in the
current saturation region.
Specifically, the product of L1 and C2 (derated value at 8.5 V) has to be greater than 10e-12 for boost stability
after accounting worst case variation of L1 and C2. To satisfy sufficient energy transfer, L1 needs to be > 2 µH at
the boost switching frequency (~1.75 MHz). Minimum C2 (derated value at 8.5 V) should be > 4 µF for Class-D
power delivery specification. The saturation current for L1 should be > ILIM to deliver Class-D peak power.
8.2.1.2.4 EMI Passive Devices
The TAS2552 supports edge-rate control to minimize EMI, but the system designer may want to include passive
devices on the Class-D output devices. These passive devices that are labeled L2, L3, C3 and C4 in Figure 50
and their recommended specifications are provided in Table 12. If C3 and C4 are used, they must be placed
after L2 and L3 respectively to maintain the stability of the output stage.
8.2.1.2.5 Miscellaneous Passive Devices
•
•
VREG Capacitor: Needs to be 10 nF to meet boost and class-D power delivery and efficiency specs.
BIAS Capacitor: Needs to be 1 µF to meet PSSR and noise performance.
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8.2.1.3 Application Performance Plots
100
1
VBAT = 3.0 V
VBAT = 3.6 V
10
VBAT = 4.2 V
0.1
THD+N - %
THD+N - %
VBAT = 5.0 V
VBAT = 5.5 V
1
VBAT = 5.5 V
0.01
VBAT = 5.0 V
0.1
VBAT = 4.2 V
VBAT = 3.6 V
0.01
0.0001
0.01
0.1
1
20
PO - Output Power - W
5.0
0.02
4.0
-0.04
1.0
-0.06
0.0
Time - s
Use start-up sequence in Initialization
0.04
0
2.0
-0.02
-0.04
1.0
-0.06
-0.1
0.007
0.06
0.02
3.0
0.0
-0.08
0.005
ENABLE
Class-D Output
Output Voltage - V
-0.02
2.0
Output Voltage - V
IOVDD - V
0.04
0
3.0
-1.0
-0.0015
0.009
-0.08
-0.0005
0.0005
Time - s
C019
-0.1
0.0015
C020
Class D output and EN pulled low
Figure 53. Startup Timing
44
C005
Figure 52. THD+N vs Frequency (8Ω) for Digital Input
IOVDD - V
4.0
0.003
20000
AGC=OFF, Gain = 15 dB, Pout = 1 W
I2C to Enable Class-D
Class-D Output
0.001
2000
f - Frequency - Hz
Figure 51. THD+N vs Output Power (8Ω) for Digital Input
-1.0
-0.001
200
C004
AGC=OFF, Gain = 15 dB
5.0
VBAT = 3.0 V
0.001
0.001
Figure 54. Shutdown Timing
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8.2.2 Typical Application - Analog Audio Input
Using the analog audio input is very similar to the digital audio input case in Typical Application - Digital Audio
Input, and this section will only discuss the differences from the digital input configuration.
1.65 V À 1.95 V
3.0 V À 5.5 V
L1
2.2 PH
C1
10 PF
0.1 PF
0.1 PF
2
AVDD
1.5 V À
3.6 V
VBAT
SW
VREG
IOVDD
10 nF
0.1 PF
VBOOST
C2
22 PF
EN
Enable
PVDD
1 PF
Audio
Input
+
L2 (opt.)
IN+
+
OUT+
IN-
-
OUT-
1 PF
PDM Clock
(opt.)
IVCLKIN
2
I C Address Select
I2C Interface
ADDR
VSENSE+
I2C
VSENSE-
-
L3 (opt.)
C3
1 nF
(opt.)
To
Speaker
C4
1 nF
(opt.)
2
I2S Interface
I2S
5
AGND
BIAS
2
PGND
3
1 PF
Figure 55. Typical Application Schematic
8.2.2.1 Design Requirements
Table 14. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Audio Input
Analog
Current and Voltage Data Stream
Digital Audio, I2S
Mono or Stereo Configuration
Mono
Max Output Power at 1% THD+N
3.3
8.2.2.2 Detailed Design Procedure
8.2.2.2.1 Audio Input/Output
In this application, system considerations require the use of an analog audio input. Note that a digital audio
interface, such as I2S, still needs to be connected to send current and voltage data from the TAS2552 to a
system processor.
The analog inputs to TAS2552 should be ac-coupled to the device terminals to allow decoupling of signal
source's common mode voltage with that of TAS2552's common mode voltage. The input coupling capacitor in
combination with the selected input impedance of TAS2552 forms a high-pass filter.
Fc = 1/(2*π*RinCc)
Cc = 1/(2*π*RinFc)
(3)
(4)
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Signal Connector
Device Analog Input
Cc
Rin
Figure 56. Analog Input Connection
For high fidelity audio playback, it is desirable to keep the cutoff frequency of the high pass filter below the
minimum reproducible frequency of the speaker. For example, a 1 µF capacitor connected to the differential
analog inputs with input resistance 10 kΩ results in a cutoff frequency of 16 Hz.
8.2.2.3 Application Performance Plots
100
1
VBAT = 5.5 V
VBAT = 5.0 V
VBAT = 4.2 V
VBAT = 3.6 V
1
THD + N - %
THD + N - %
10
VBAT = 3.0 V
0.1
VBAT = 5.5 V
VBAT = 5.0 V
0.01
0.1
VBAT = 4.2 V
VBAT = 3.6 V
0.01
0.001
0.1
PO - Output Power - W
1
20
200
2000
f - Frequency - Hz
C006
AGC=OFF, Gain = 15 dB, f = 1 kHz
20000
C007
AGC=OFF, Gain = 15 dB
Figure 57. THD+N vs Output Power (8Ω) for Analog Input
46
VBAT = 3.0 V
0.001
0.01
Figure 58. THD+N vs Frequency (8Ω) for Analog Input
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8.2.3 Typical Application - Maximum Output Power, Analog Audio Input
This application is the same as Typical Application - Analog Audio Input, except that in this case the boost
current limit is set to the maximum value of 3.1 A and the boost inductor needs to be chosen appropriately. See
Configurable Boost Current Limit (ILIM) for instructions on setting the boost current limit. The same boost current
limit and resulting capacitor change can be used for digital audio input as well.
For schematic, see Figure 55.
Table 15. Recommended External Components
COMPONENT
L1
L2, L3
DESCRIPTION
SPECIFICATION
Boost Converter Inductor
MIN
Inductance, 20% Tolerance
EMI Filter Inductors (optional)
TYP
µH
3.1
A
Impedance at 100MHz
120
Ω
0.095
DC Current
1.5
Size
0402
C1
Boost Converter Input Capacitor
Capacitance, 20% Tolerance
C2
Boost Converter Output Capacitor
Type
EMI Filter Capacitors (optional, must
use L2, L3 if C3, C4 used)
UNIT
Saturation Current
DC Resistance
C3, C4
MAX
2.2
Ω
A
EIA
10
µF
X5R
Capacitance, 20% Tolerance
22
Rated Voltage
16
V
Capacitance at 8.5 V
derating
7
µF
Capacitance
47
1
µF
nF
8.2.3.1 Design Requirements
Table 16. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Audio Input
Analog
Current and Voltage Data Stream
Digital Audio, I2S
Mono or Stereo Configuration
Mono
Max Output Power at 1% THD+N
4.0
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8.2.3.2 Detailed Design Procedure
The Design Procedure is the same as in Detailed Design Procedure.
8.2.3.3 Application Performance Plots
100
THD + N - %
10
1
0.1
0.01
0.001
0.01
0.1
1
PO - Output Power - W
C026
AGC=OFF, Gain = 15 dB, f = 1 kHz, VBAT = 4.2 V
Figure 59. THD+N vs Output Power (8Ω) for Analog Input
8.3 Initialization
To
1.
2.
3.
48
configure the TAS2552, follow these steps.
Bring-up the power supplies as in Power Supply Sequencing.
Set the EN terminal to HIGH.
Configure the registers in the sequence below. Do not set the bits in the final two steps to zero anytime
before the end of the sequence.
– Configure device register
– ...
– ...
– ...
– Configure device register
– Set Register 0x0D D[7:0] = 0xC0
– Set Register 0x0E D[5] = 1
– Set Register 0x02 D[0] = 0
– Set Register 0x01 D[1] = 0
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9 Power Supply Recommendations
9.1 Power Supplies
The TAS2552 requires three power supplies:
• Boost Input (terminal: VBAT)
– Voltage: 3.0 V to 5.5 V
– Max Current: 2.6 A for ILIM = 2.5 A (default), 3.1 A for ILIM = 3.0 A
• Analog Supply (terminal: AVDD)
– Voltage: 1.65 V to 1.95 V
– Max Current: 30 mA
• Digital I/O Supply (terminal: IOVDD)
– Voltage: 1.5 V to 3.6 V
– Max Current: 5 mA
The decoupling capacitors for the power supplies should be placed close to the device terminals. For VBAT,
IOVDD and AVDD, a small decoupling capacitor of 0.1 µF should be placed close to the device terminals. Refer
to Figure 55 for the schematic.
9.2 Power Supply Sequencing
The power supplies should be started in the following order:
1. VBAT,
2. IOVDD,
3. AVDD.
The TAS2552 device has integrated reset circuitry, which requires that VBAT is above 2.45 V for the device to
enter normal operation mode. Figure 60 shows the internal thresholds and reset states. Normal operation mode
is within the green area of Figure 60.
VBAT [V]
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