TAS5412-Q1
www.ti.com
SLOS685A – AUGUST 2013 – REVISED OCTOBER 2013
TWO-CHANNEL AUTOMOTIVE DIGITAL AMPLIFIER
Check for Samples: TAS5412-Q1
FEATURES
1
•
•
•
•
234
•
•
•
•
•
•
•
•
•
TAS5412-Q1 - Single-Ended Input
2-Channel Digital Power Amplifier
2 Analog Inputs, 2 BTL Power Outputs
Typical Output Power per Channel at 10%
– 28 Watts/Ch, Into 4 Ω at 14.4 VDC
– 46 Watts/Ch, Into 2 Ω at 14.4 VDC
– 79 Watts/Ch, Into 4 Ω at 24 VDC
– 150 Watts Into 2 Ω at 24 VDC PBTL
– 90 Watts Into 1 Ω at 14.4 VDC PBTL
THD+N < 0.02%, 1 kHz, 1 W Into 4 Ω
Patented Pop- and Click-Reduction
Technology
Patented AM Interference Avoidance
Patented Cycle-by-Cycle Current Limit
75-dB PSRR
Four-Address I2C Serial Interface for Device
Configuration and Control
Channel Gains: 12 dB, 20 dB, 26 dB, 32 dB
Load Diagnostic Functions:
– Output Open and Shorted Load
– Output-to-Power and -to-Ground Shorts
– Patented Tweeter Detection
Protection and Monitoring Functions:
– Short-Circuit Protection
– 50-V Load-Dump Protection
– Fortuitous Open-Ground and -Power
Tolerant
– Patented Output DC Level Detection While
Music Is Playing
– Overtemperature Protection
– Over- and Undervoltage Protection
– Clip Detection
•
•
•
•
•
•
TAS5412-Q1 - 64-Pin QFP (PHD) PowerPAD™
Surface-Mount Package
Pin Compatible With 4-Channel Devices
Designed for Automotive EMC Requirements
Will Be Qualified According to AEC-Q100
ISO9000:2002 TS16949 Certified
–40 to 105°C Ambient Temperature Range
APPLICATIONS
•
•
Radio Head Units
External Amplifiers
DESCRIPTION
The device is a two-channel digital audio amplifier
designed for use in automotive head units and
external amplifiers. It provides two channels at 28 W
into 4 Ω at 10% THD+N from 14.4 V or 46 W into 2 Ω
at 10% THD+N. The digital PWM topology provides
dramatic improvements in efficiency over traditional
linear amplifier solutions. This reduces the power
dissipated by the amplifier by a factor of ten under
typical music playback conditions. The device
incorporates a patented PWM design that provides
excellent power-supply rejection in the harsh
electrical environment common in automotive
applications. Applications attain high efficiency
without the need for complicated power supply
schemes. The design allows synchronization of
multiple devices.
The device incorporates all the functionality needed
to perform in the demanding OEM applications area,
including load diagnostic functions for detecting and
diagnosing misconnected outputs.
This text, unrelated to other data-sheet content, is
intended only for adjusting column lengths on the first
page.
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Ceramique is a trademark of Arctic Silver Inc.
Arctic Silver is a registered trademark of Arctic Silver Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TAS5412-Q1
SLOS685A – AUGUST 2013 – REVISED OCTOBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TAS5412-Q1 FUNCTIONAL BLOCK DIAGRAM
PIN ASSIGNMENTS AND FUNCTIONS
The pin assignments are as follows:
2
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
TAS5412-Q1
www.ti.com
SLOS685A – AUGUST 2013 – REVISED OCTOBER 2013
GND
GND
GND
PVDD
PVDD
PVDD
GND
GND
GND
GND
GND
GND
OSC_SYNC
SDA
I2C_ADDR
SCL
TAS5412-Q1
PHD Package
(Top View)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
FAULT
1
48
NU
MUTE
2
47
NU
GND
3
46
GND
STANDBY
4
45
OUT1_M
D_BYP
5
44
OUT1_P
CLIP_OTW
6
43
GND
GND
7
42
CPC_TOP
GND
8
41
CP
GND
9
40
CP_BOT
REXT
10
39
GND
A_BYP
11
38
GND
GND
12
37
OUT2_M
CM_CAP1
13
36
OUT2_P
GND
14
35
GND
IN1_P
15
34
NU
GND
16
33
NU
GND
GND
GND
PVDD
PVDD
PVDD
GND
GND
GND
GND
GND
GND
CM_CAP2
IN_M
IN2_P
GND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P0070-03
Table 1. TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
TYPE
DESCRIPTION
A_BYP
11
PBY
Bypass pin for the AVDD analog regulator
CLIP_OTW
6
DO
Reports clip detect, tweeter detection, and overtemperature warning with open-drain
output
CM_CAP1
13
AI
Common mode capacitor
CM_CAP2
20
AI
Common mode capacitor
CP
41
CP
Top of main storage capacitor for charge pump
CPC_BOT
40
CP
Bottom of flying capacitor for charge pump
CPC_TOP
42
CP
Top of flying capacitor for charge pump
D_BYP
5
PBY
Bypass pin for DVDD regulator output
FAULT
1
DO
Global fault output (open-drain): UV, OV, OTSD, OCSD, dc
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
3
TAS5412-Q1
SLOS685A – AUGUST 2013 – REVISED OCTOBER 2013
www.ti.com
Table 1. TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
TYPE
DESCRIPTION
3, 7-9, 12,14,
16, 17, 21–26,
30–32, 35, 38,
39, 43, 49–51,
55–60
GND
I2C_ADDR
62
AI
I2C address bit
IN1_P
15
AI
Non-inverting analog input for channel 1
IN2_P
19
AI
Non-inverting analog input for channel 2
IN_M
18
ARTN
MUTE
2
DI
Gain-ramp control
No connect, do not connect to ground
GND
NU
Ground
Signal return for both analog channel inputs
33, 34, 47, 48
NC
OSC_SYNC
61
DI, DO
OUT1_M
45
PO
– polarity output for bridge 1
OUT1_P
44
PO
+ polarity output for bridge 1
OUT2_M
37
PO
– polarity output for bridge 2
OUT2_P
36
PO
+ polarity output for bridge 2
PVDD
27–29, 52–54
PWR
REXT
10
AI
Precision resistor pin to set analog reference
SCL
64
DI
I2C clock input from system I2C master
SDA
63
DI, DO
STANDBY
4
DI
Oscillator input from master or output to slave amplifiers
PVDD supply
I2C data I/O for communication with system I2C master
Active-low STANDBY pin. Standby (low), power up (high)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
–0.3 to 30
V
PVDD
DC supply voltage range
Relative to GND
PVDD MAX
Pulsed supply-voltage range
t ≤ 400 ms exposure
–1 to 50
V
PVDD RAMP
Supply-voltage ramp rate
15
V/ms
IPVDD
Externally imposed dc supply current per PVDD or GND pin
±12
A
IPVDD_MAX
Pulsed supply current per PVDD pin (one shot)
IO
Maximum allowed dc current per output pin
IO_MAX
(1)
t < 100 ms
Pulsed output current per output pin (single pulse)
17
A
±13.5
A
±17
A
DC or pulsed
±1
mA
DC or pulsed
±20
mA
7
mA
–0.3 to 6
V
t < 100 ms
(2)
IIN_MAX
Maximum current, all digital and analog input pins
IMUTE_MAX
Maximum current on MUTE pin
IIN_ODMAX
Maximum sinking current for open-drain pins
VLOGIC
Input voltage range for logic pin relative to GND (SCL and
SDA pins)
VI2C_ADDR
Input voltage range for I2C_ADDR pin relative to GND
–0.3 to 6
V
VSTANDBY
Input voltage range for STANDBY pin
–0.3 to 5.5
V
VOSC_SYNC
Input voltage range for OSC_SYNC pin relative to GND
–0.3 to 3.6
V
VAIN_AC_MAX_5412
Maximum ac-coupled input voltage (2), analog input pins
1.9
Vrms
VGND
Maximum voltage between GND pins
±0.3
V
TJ
Maximum operating junction temperature range
–55 to 150
°C
Tstg
Storage temperature range
–55 to 150
°C
(1)
(2)
4
Pulsed-current ratings are maximum survivable currents externally applied to the TAS5412-Q1. Reverse-battery, fortuitous open-ground,
and fortuitous open-supply fault conditions may result in high currents.
See Application Information section for information on analog input voltage and ac coupling.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
TAS5412-Q1
www.ti.com
SLOS685A – AUGUST 2013 – REVISED OCTOBER 2013
THERMAL CHARACTERISTICS
PARAMETER
RθJC
VALUE (Typical)
UNIT
1.7
°C/W
8×8
mm
Junction-to-case (heat slug) thermal resistance
Exposed pad dimensions
ELECTROSTATIC DISCHARGE (ESD)
PARAMETER
Human-body model (HBM) AECQ100-002
Charged-device model (CDM)
AEC-Q100-011
Machine model (MM) AEC-Q100003
PINS
VALUE (Typical)
ALL
3000
Corner pins excluding SCL
750
All pins (including SCL) except CP and CP_TOP
600
CP and CP_TOP pins
400
All
100
UNIT
V
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
5
TAS5412-Q1
SLOS685A – AUGUST 2013 – REVISED OCTOBER 2013
www.ti.com
RECOMMENDED OPERATING CONDITIONS
PVDDOP
DC supply voltage range relative to GND
2
PVDDI2C
VAIN_5412
(1)
DC supply voltage range for I C reporting
(2)
TA
Analog audio input signal level
AC-coupled input voltage
Ambient temperature
An adequate heat sink is required
to keep TJ within specified range.
MIN
NOM
MAX
6
14.4
24
5
14.4
0
26.5
0.25–1
(3)
UNIT
V
V
Vrms
–40
105
°C
–40
115
°C
TJ
Junction temperature
RL
Nominal speaker load impedance
2
4
VPU
Pullup voltage supply (for open-drain logic outputs)
3
3.3 or 5
5.5
V
10
47
100
kΩ
1
4.7
10
kΩ
100
kΩ
20.2
kΩ
120
nF
680
nF
RPU_EXT
External pullup resistor on open-drain logic outputs
RPU_I2C
I2C pullup resistance on SDA and SCL pins
Resistor connected between opendrain logic output and VPU supply
Ω
2
RI2C_ADD
Total resistance of voltage divider for I C address
slave 1 or slave 2, connected between D_BYP and
GND pins
RREXT
External resistance on REXT pin
CD_BYP, C A_BYP
External capacitance on D_BYP and A_BYP pins
COUT
External capacitnace to GND on OUT_X pins
CIN
External capacitance to analog input pin in series
with input signal
CFLY
Flying capacitor on charge pump
CP
Charge-pump capacitor
CMUTE
Capacitance on MUTE pin
COSCSYNC_MAX
Allowed loading capacitance on OSC_SYNC pin
(1)
(2)
(3)
6
10
1% tolerance required
19.8
20
10
150
1
50 V needed for load dump
µF
0.47
1
1.5
µF
0.47
1
1.5
µF
100
330
nF
75
pF
The Recommended Operating Conditionstable specifies only that the device is functional in the given range. See the Electrical
Characteristicstable for specified performance limits.
Signal input for full unclipped output with gains of 32 dB, 26 dB, 20 dB, and 12 dB
Maximum recommended input voltage is determined by the gain setting.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
TAS5412-Q1
www.ti.com
SLOS685A – AUGUST 2013 – REVISED OCTOBER 2013
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise noted): TCase= 25°C, PVDD = 14.4 V, RL= 4 Ω, fS = 417 kHz, Pout= 1 W/ch, Rext = 20 kΩ,
AES17 filter, master-mode operation (see application diagram)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
125
175
UNIT
OPERATING CURRENT
IPVDD_IDLE
IPVDD_Hi-Z
IPVDD_STBY
Both channels in MUTE mode
PVDD idle current
PVDD standby current
Both channels in Hi-Z mode
60
STANDBY mode, T J = 85°C
2
12
mA
µA
OUTPUT POWER
4 Ω, PVDD = 14.4 V, THD+N = 1%, 1 kHz, T c= 75°C
4 Ω, PVDD = 14.4 V, THD+N = 10%, 1 kHz, T c= 75°C
23
25
4 Ω, PVDD = 24 V, THD+N = 1%, 1 kHz, T c= 75°C
4 Ω, PVDD = 24 V, THD+N = 10%, 1 kHz, T c= 75°C
POUT
62
63
2 Ω, PVDD = 14.4 V, THD+N = 1%, 1 kHz, T c= 75°C
Output power per channel
2 Ω, PVDD = 14.4 V, THD+N = 10%, 1 kHz, T c= 75°C
Power efficiency
79
38
40
PBTL 2-Ω operation, PVDD = 24 V, THD+N = 10%,
1 kHz, T c= 75°C
EFFP
28
W
50
150
PBTL 1-Ω operation, PVDD = 14.4 V, THD+N = 10%,
1 kHz, T c= 75°C
90
2 channels operating, 23-W output power per ch, L = 10
µH, T J = 85°C
90
%
AUDIO PERFORMANCE
VNOISE
Noise voltage at output
G = 26 dB, zero input, and A-weighting
Crosstalk
Channel crosstalk
1 W, G = 26 dB, 1 kHz
60
75
PSRR
Power-supply rejection ratio
G = 26 dB, PVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz
60
75
THD+N
Total harmonic distortion + noise
P = 1 W, G = 26 dB, f = 1 kHz, 0°C = T J = 75°C
fS
Switching frequency
Switching frequency selectable for AM interference
avoidance
RAIN
Analog input resistance
Internal shunt resistance on each input pin
VIN_CM
Common-mode input voltage
AC-coupled common-mode input voltage (zero
differential input)
VCM_INT
Internal common-mode input bias voltage
Internal bias applied to IN_M pin
60
100
dB
dB
0.02%
0.1%
336
357
378
392
417
442
470
500
530
63
82
106
1.3
Voltage gain (VO / VIN)
Source impedance = 0 Ω, gain measurement taken at 1
W of power per channel
GCH
Channel-to-channel variation
Any gain commanded
kHz
kΩ
Vrms
3.37
G
µV
V
11
12
13
19
20
21
25
26
27
31
32
33
–1
0
1
dB
75
95
mΩ
±10
±50
mV
24.6
26.4
28.2
V
5
5.3
5.6
V
6.2
6.6
7.2
V
dB
PWM OUTPUT STAGE
rDSon
VO_OFFSET
FET drain-to-source resistance
Not including bond-wire resistance, T J= 25°C
Output offset voltage
Zero input signal, dc offset reduction enabled, and
G = 26 dB
PVDD OVERVOLTAGE (OV) PROTECTION
VOV
PVDD overvoltage shutdown
PVDD UNDERVOLTAGE (UV) PROTECTION
VUV_SET
PVDD undervoltage shutdown
VUV_CLEAR
Recovery voltage for PVDD UV
AVDD
VA_BYP
A_BYP pin voltage
6.5
V
VA_BYP_UV_SET
A_BYP UV voltage
3.5
V
VA_BYP_UV_CLEAR
Recovery voltage A_BYP UV
4.3
V
D_BYP pin voltage
3.3
V
DVDD
VD_BYP
POWER-ON RESET (POR)
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
7
TAS5412-Q1
SLOS685A – AUGUST 2013 – REVISED OCTOBER 2013
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Test conditions (unless otherwise noted): TCase= 25°C, PVDD = 14.4 V, RL= 4 Ω, fS = 417 kHz, Pout= 1 W/ch, Rext = 20 kΩ,
AES17 filter, master-mode operation (see application diagram)
PARAMETER
TEST CONDITIONS
VPOR
Maximum PVDD voltage for POR; I2C active
above this voltage
VPOR_HY
PVDD recovery hysteresis voltage for POR
MIN
TYP
MAX
4
UNIT
V
0.1
V
1.27
V
REXT
VREXT
Rext pin voltage
CHARGE PUMP (CP)
VCPUV_SET
CP undervoltage
4.8
V
VCPUV_CLEAR
Recovery voltage for CP UV
4.9
V
OVERTEMPERATURE (OT) PROTECTION
TOTW1_CLEAR
T OTW1_SET/
TOTW2_CLEAR
TOTW2_SET/
TOTW3_CLEAR
Junction temperature for overtemperature
warning
TOTW3_SET/
TOTSD_CLEAR
TOTSD
Junction temperature for overtemperature
shutdown
TFB
Junction temperature for overtemperature
foldback
Per channel
96
112
128
106
122
138
116
132
148
126
142
158
136
152
168
130
150
170
°C
CURRENT LIMITING PROTECTION
ILIM
Level 1
Current limit (load current)
Level 2 (default)
5.5
7.3
9
10.6
12.7
15
A
OVERCURRENT (OC) SHUTDOWN PROTECTION
IMAX
Level 1, any short to supply, ground, or other channels
Maximum current (peak output current)
Level 2 (default)
7.8
9.8
12.2
11.9
14.8
17.7
330
445
560
A
TWEETER DETECT
ITH_TW
Load-current threshold for tweeter detect
ILIM_TW
Load-current limit for tweeter detect
2.1
mA
A
STANDBY MODE
V IH_STBY
STANDBY input voltage for logic-level high
VIL_STBY
STANDBY input voltage for logic-level low
ISTBY_PIN
STANDBY pin current
2
V
0.1
0.7
V
0.2
µA
MUTE MODE
GMUTE
MUTE pin ≤ 0.5 Vdc for 200 ms, or I2C mute enabled
Output attenuation
100
dB
DC DETECT
VTH_DC_TOL
DC-detect threshold tolerance
tDCD
DC-detect step-response time for two
channels
25%
5.3
s
CLIP REPORT
VOH_CLIP_OTW
CLIP_OTW pin output voltage for logic level
high (open-drain logic output)
VOL_CLIP_OTW
CLIP_OTW pin output voltage for logic-level
low (open-drain logic output)
TDELAY_CLIPDET
Signal delay when output clipping detected
2.4
v
External 47-kΩ pullup resistor to 3 V–5.5 V
0.5
V
20
µs
MODE PINS (DIAG, SOFT_MUTE, I2C MODE)
VOH
Mode pin output voltage for logic-level high
(open-drain logic output)
2
5.5
V
VOL
Mode pin output voltage for logic-level low
(open-drain logic output)
0
0.7
V
FAULT REPORT
8
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
TAS5412-Q1
www.ti.com
SLOS685A – AUGUST 2013 – REVISED OCTOBER 2013
ELECTRICAL CHARACTERISTICS (continued)
Test conditions (unless otherwise noted): TCase= 25°C, PVDD = 14.4 V, RL= 4 Ω, fS = 417 kHz, Pout= 1 W/ch, Rext = 20 kΩ,
AES17 filter, master-mode operation (see application diagram)
PARAMETER
V OH_FAULT
V OL_FAULT
TEST CONDITIONS
FAULT pin output voltage for logic-level high
(open-drain logic output)
FAULT pin output voltage for logic-level low
(open-drain logic output)
MIN
TYP
MAX
UNIT
2.4
External 47-kΩ pullup resistor to 3 V–5.5 V
V
0.5
OPEN/SHORT DIAGNOSTICS
RS2P, RS2G
Maximum resistance to detect a short from
OUT pins to PVDD or ground
ROPEN_LOAD
Minimum load resistance to detect open
circuit
Including speaker wires
300
RSHORTED_LOAD
Maximum load resistance to detect short
circuit
Including speaker wires
0.5
Voltage on CS pin for address 0
Connect to GND
0%
0%
15%
Voltage on CS pin for address 1
25%
35%
45%
Voltage on CS pin for address 2
External resistors in series between D_BYP and GND as
a voltage divider
55%
65%
75%
Voltage on CS pin for address 3
Connect to D_BYP
85%
100%
100%
tHOLD_I2C
Power-on hold time before I2C
communication
STANDBY high
fSCL
SCL clock frequency
VIH_SCL
SCL pin input voltage for logic-level high
VIL_SCL
SCL pin input voltage for logic-level low
200
Ω
800
1300
Ω
1.0
1.5
Ω
CHIP SELECT
tLATCH_CS
VCS
Time delay to latch I2C address after POR
300
µs
VD_BYP
I2C
1
R PU_I2C= 5-kΩ pullup, supply voltage = 3.3 V or 5 V
ms
400
kHz
2.1
5.5
V
–0.5
1.1
V
2
VOH_SDA
SDA pin output voltage for logic-level high
I C read, RI2C= 5-kΩ pullup,
supply voltage = 3.3 V or 5 V
VOL_SDA
SDA pin output voltage for logic-level low
I2C read, 3-mA sink current
VIH_SDA
SDA pin input voltage for logic-level high
I2C write, RI2C= 5-kΩ pullup,
supply voltage = 3.3 V or 5 V
VIL_SDA
SDA pin input voltage for logic-level low
I2C write, RI2C= 5-kΩ pullup,
supply voltage = 3.3 V or 5 V
Ci
Capacitance for SCL and SDA pins
2.4
V
0.4
V
2.1
5.5
V
–0.5
1.1
V
10
pF
3.6
V
0.5
V
3.6
V
0.8
V
OSCILLATOR
VOH_OSCSYNC
OSC_SYNC pin output voltage for logiclevel high
2.4
CS pin set to MASTER mode
VOL_OSCSYNC
OSC_SYNC pin output voltage for logiclevel low
VIH_OSCSYNC
OSC_SYNC pin input voltage for logic-level
high
VIL_OSCSYNC
OSC_SYNC pin input voltage for logic-level
low
fOSC_SYNC
OSC_SYNC pin clock frequency
2
CS pin set to SLAVE mode
CS pin set to MASTER mode, fS= 500 kHz
3.76
4
4.24
CS pin set to MASTER mode, fS= 417 kHz
3.13
3.33
3.63
CS pin set to MASTER mode, fS= 357 kHz
2.68
2.85
3
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
MHz
9
TAS5412-Q1
SLOS685A – AUGUST 2013 – REVISED OCTOBER 2013
www.ti.com
TIMING REQUIREMENTS FOR I2C INTERFACE SIGNALS
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
ns
tr
Rise time for both SDA and SCL signals
300
tf
Fall time for both SDA and SCL signals
300
tw(H)
SCL pulse duration, high
0.6
µs
tw(L)
SCL pulse duration, low
1.3
µs
tsu2
Setup time for START condition
0.6
µs
th2
START condition hold time after which first clock pulse is generated
0.6
µs
tsu1
Data setup time
100
ns
th1
Data hold time
tsu3
Setup time for STOP condition
CB
Load capacitance for each bus line
(1)
ns
(1)
ns
0.6
µs
0
400
pF
A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of
SCL.
tw(H)
tw(L)
tf
tr
SCL
tsu1
th1
SDA
T0027-01
Figure 1. SCL and SDA Timing
SCL
t(buf)
th2
tsu2
tsu3
SDA
Start
Condition
Stop
Condition
T0028-01
Figure 2. Timing for Start and Stop Conditions
10
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
TAS5412-Q1
www.ti.com
SLOS685A – AUGUST 2013 – REVISED OCTOBER 2013
TYPICAL CHARACTERISTICS
THD+N
versus
BTL OUTPUT POWER AT 1 kHz
THD+N
versus
PBTL OUTPUT POWER at 1 kHz
Figure 3.
Figure 4.
THD+N
versus
FREQUENCY AT 1 W
COMMON-MODE REJECTION RATIO
versus
FREQUENCY
Figure 5.
Figure 6.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
11
TAS5412-Q1
SLOS685A – AUGUST 2013 – REVISED OCTOBER 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
CROSSTALK
versus
FREQUENCY
NOISE FFT
Figure 7.
Figure 8.
EFFICIENCY,
TWO CHANNELS AT 4 Ω EACH
100
90
80
Efficiency − %
70
60
50
40
30
20
10
0
0
4
8
12
16
20
24
28
32
P − Power Per Channel − W
G007
Figure 9.
12
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
TAS5412-Q1
www.ti.com
SLOS685A – AUGUST 2013 – REVISED OCTOBER 2013
DESCRIPTION OF OPERATION
OVERVIEW
The device is a two-channel analog-input audio amplifier for use in the automotive environment. The design uses
an ultra-efficient class-D technology developed by Texas Instruments. This technology allows for reduced power
consumption, reduced heat, and reduced peak currents in the electrical system. The device realizes an audio
sound system design with smaller size and lower weight than traditional class-AB solutions.
The device has the following major blocks:
• Preamplifier
• PWM
• Gate drive
• Power FETs
• Diagnostics
• Protection
• Power supply
• I2C serial communication bus
Preamplifier
The preamplifier is a high-input-impedance, low-noise, low-offset-voltage input stage with adjustable gain. The
high input impedance allows the use of low-cost input capacitors while still achieving extended low-frequency
response. A dedicated, internally regulated supply powers the preamplifier, giving excellent noise immunity and
channel separation. Also included in the preamplifier are:
1. Mute Pop-and-Click Control—Application of a mute at the crest or trough of an audio input signal reshapes
and amplifies the signal as a step. Listeners perceive such a step as a loud click. The TAS5412-Q1 avoids
clicks by ramping the gain gradually on reception of a mute or play command. The start or stopping of
switching in a class-D amplifier can cause another form of click and pop. The TAS5412-Q1 incorporates a
patented method to reduce the pop energy during the switching start-up and shutdown sequences. Fault
conditions require rapid protection response by the TAS5412-Q1, which does not have time to ramp the gain
down in a pop-free manner. The device transitions into Hi-Z mode when an OV, UV, OC, OT, or dc fault is
encountered. Also, activation of the STANDBY pin may not be pop-free.
2. Gain Control—The four gain settings are set in the preamplifier via I2C control registers. Setting of the gain
outside of the global feedback resistors of the TAS5412-Q1 thus allows for stability in the system at all gain
settings with properly loaded conditions.
Pulse-Width Modulator (PWM)
The PWM converts the analog signal from the preamplifier into a switched signal of varying duty cycle. This is
the critical stage that defines the class-D architecture. In the TAS5412-Q1, the modulator is an advanced design
with high bandwidth, low noise, low distortion, excellent stability, and full 0–100% modulation capability. The
patented PWM uses clipping recovery circuitry to eliminate the deep saturation characteristic of PWMs when the
input signal exceeds the modulator waveform.
Gate Drive
The gate driver accepts the low-voltage PWM signal and level-shifts it to drive a high-current, full-bridge, power
FET stage.
Power FETs
The BTL output for each channel comprises four rugged N-channel FETs, each of which is low rDSon for high
efficiency and maximum power transfer to the load. These FETs handle large voltage transients during load
dump.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: TAS5412-Q1
13
TAS5412-Q1
SLOS685A – AUGUST 2013 – REVISED OCTOBER 2013
www.ti.com
Load Diagnostics
The device incorporates load-diagnostic circuitry designed to help pinpoint the nature of output misconnections
during installation. The diagnostics include functions for detecting and determining the status of output
connections. The following diagnostics are supported:
• Short to GND
• Short to PVDD
• Short across load
• Open load
• Tweeter detection
Reporting the presence of any of the short or open conditions to the system is via I2C register read. One can
read the tweeter detect status from the CLIP_OTW pin when properly configured.
1. Output Short and Open Diagnostics—The device contains circuitry designed to detect shorts and open
conditions on the outputs. One can only invoke the load diagnostic function when the output is in the Hi-Z
mode. There are four phases of test during load diagnostics and two levels of test. In the full level, all
channels must be in the Hi-Z state. The diagnostic tests all four phases on each channel, and both channels
at the same time. When fewer than two channels are in Hi-Z, the reduced level of test is the only available
option. In the reduced level, the only available tests are short to PVDD and short to GND. Load diagnostics
can occur at power up before the amplifier is moved out of Hi-Z mode. If the amplifier is already in play
mode, it must Mute and then Hi-Z to allow performing the load diagnostic. By performing the mute function,
the normal pop- and click-free transitions occur before the diagnostics begin. The device performs the
diagnostics as shown in Figure 10. Figure 11 shows the impedance ranges for the open-load and shortedload diagnostics. Reading of the diagnostic results is from the diagnostic register for each channel via I2C.
Hi-Z
Channel Synchronization
Playback
/
Mute
OUT1_M
Phase1
Phase2
Phase3
Phase4
S2G
S2P
OL
SL
OUT1_P
VSpeaker
(OUT1_P – OUT1_M)
20 ms
~50 ms
~50 ms
~50 ms
~50 ms
20 ms
150 ms
~50 ms
~50 ms
~50 ms
~50 ms
200 ms
工商网监
湘ICP备2023018690号
