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TAS5753MD
SLASEA5C – MARCH 2016 – REVISED MAY 2017
TAS5753MD 20-W I²S Input Class-D Amplifier With Digital Audio Processor and
DirectPath™ HP and Line Driver
1 Features
2 Applications
•
•
•
•
1
•
•
Audio Input/Output
– Supports BTL Configuration With 4-Ω Load
– One Stereo Serial Audio Input
– I2C Address Selection Pin
– Supports 44.1-kHz and 48-kHz Sample Rates
(LJ/RJ/I2S)
Headphone Amplifier and Line Driver
– Independent Channel Volume Controls With
Gain of 24 dB to Mute in 0.125-dB Steps
– Programmable Three-Band Automatic Gain
Limiting (AGL)
– 20 Programmable Biquads for Speaker EQ
and Other Audio-Processing Features
General Features
– I2C Serial Control Interface Operational
Without MCLK
– Automatic Rate Detection
– Thermal, Short-Circuit, and Undervoltage
Protection
– 105-dB SNR, A-Weighted, Referenced to Full
Scale (0 dB)
– Up to 90% Efficient
– AD, BD, and Ternary Modulation
– PWM Level Meter
– Operates from 4.5-V to 24-V PVDD
LCD TV, LED TV
Low-Cost Soundbar
General Low-Cost Audio Equipment
3 Description
The TAS5753MD device is an efficient, digital-input
audio amplifier for driving stereo speakers configured
as a bridge tied load (BTL). One serial data input
allows processing of up to two discrete audio
channels and seamless integration to most digital
audio processors and MPEG decoders. The device
accepts a wide range of input data and data rates. A
fully programmable data path routes these channels
to the internal speaker drivers.
The TAS5753MD device is a slave-only device
receiving all clocks from external sources. The
TAS5753MD device operates with a PWM carrier
between a 384-kHz switching rate and a 288-kHz
switching rate, depending on the input sample rate.
Oversampling combined with a fourth-order noise
shaper provides a flat noise floor and excellent
dynamic range from 20 Hz to 20 kHz. The device has
an integrated Directpath™ Headphone amplifier and
linedriver to increase the system-level integration and
reduce total solution costs.
Device Information(1)
PART NUMBER
TAS5753MD
PACKAGE
BODY SIZE (NOM)
HTSSOP (48)
12.50 mm × 6.10 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Output Power vs Supply Voltage
Functional Block Diagram
55
DVDD
Inst. Power, Rspk = 8 :
Cont. Power, Rspk = 8 :
Inst. Power, Rspk = 6 :
Cont. Power, Rspk = 6 :
Inst. Power, Rspk = 4 :
Cont. Power, Rspk = 4 :
50
40
35
ANA_REG1 ANA_REG2 DIG_REG DRVDD DR_CN DR_CP
Analog Supply
Regulators
PVDD
DRVSS
GVDD_REG
Gate Drive
Regulator
Charge Pump
Digital Supply Regulator
PWM Power Stage
Digital Audio Processor
MCLK
SCLK
LRCLK
SDIN
30
Digital Equalizer, Three-Band
AGL, Coarse/Fine Volume
Control, THD Manager, PWM
Level Meter
Serial
Audio
Port
Open Loop
Digital PWM
Modulator
25
Gate
Drives
Gate
Drives
Full Bridge
Power
Stage A
SPK_OUTA
OverCurrent
Protection
Full Bridge
Power
Stage B
SPK_OUTB
SPK_OUTC
SPK_OUTD
Clock
Monitoring
20
Stereo HP / Line Driver
15
DR_INA
DR_INB
10
DR_INx
Die Temp. Monitor
DRVDD
-
Output Power (W)
45
AVDD
DR_OUTA
DR_OUTB
DR_OUTx
DRVSS
+
Internal Control Registers and State Machines
5
ADR / SPK_FAULT
0
4
6
8
10
12
14
16
18
Supply Voltage (V)
20
22
DR_SDI
PDN
RST
SCL
SDA
24
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS5753MD
SLASEA5C – MARCH 2016 – REVISED MAY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5
5
5
6
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Characteristics ............................................
Electrical Characteristics...........................................
Speaker Amplifier Characteristics in All Modes ........
Speaker Amplifier Characteristics in Stereo Bridge
Tied Load (BTL) Mode ...............................................
6.8 Speaker Amplifier Characteristics in Stereo PostFilter Parallel Bridge Tied Load (Post-Filter PBTL)
Mode ..........................................................................
6.9 Headphone Amplifier and Line Driver
Characteristics ...........................................................
6.10 Protection Circuitry Characteristics.........................
6.11 I²C Interface Timing Requirements .........................
6.12 Serial Audio Port Timing Requirements..................
7
7
7
8
8
8
6.13 Typical Electrical Power Consumption.................. 10
6.14 Typical Characteristics .......................................... 11
7
Detailed Description ............................................ 20
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
Overview .................................................................
Functional Block Diagram .......................................
Audio Signal Processing Overview .........................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
20
20
21
22
25
26
37
Application and Implementation ........................ 55
8.1 Application Information............................................ 55
8.2 Typical Applications ............................................... 56
9 Power Supply Recommendations...................... 64
10 Layout................................................................... 65
10.1 Layout Guidelines ................................................. 65
10.2 Layout Examples................................................... 66
11 Device and Documentation Support ................. 69
11.1
11.2
11.3
11.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
69
69
69
69
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2017) to Revision C
•
Page
Changed the "Device ID register" DEFAULT VALUE From: 0x40 To: 0x41 in the Register Summary table ...................... 37
Changes from Revision A (November 2016) to Revision B
Page
•
Changed output power TYP from 'TBD' to '20.'...................................................................................................................... 7
•
Changed output power TYP from 'TBD' to '39.'...................................................................................................................... 7
Changes from Original (March 2016) to Revision A
•
2
Page
Changed Product Status to Production Data ......................................................................................................................... 1
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SLASEA5C – MARCH 2016 – REVISED MAY 2017
5 Pin Configuration and Functions
DCA Package
48-Pin HTSSOP With PowerPAD™
Top View
PGND
SPK_OUTA
BSTRPA
PVDD
TEST1
TEST2
DR_INA
DR_OUTA
DR_OUTB
DR_INB
DRVSS
DR_CN
DR_CP
DRVDD
PLL_GND
PLL_FLTM
PLL_FLTP
ANA_REG1
AVDD
ADR / SPK_FAULT
MCLK
OSC_RES
OSC_GND
DIG_REG
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Thermal Pad
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SPK_OUTB
BSTRPB
BSTRPC
SPK_OUTC
PGND
SPK_OUTD
BSTRPD
PVDD
GVDD_REG
DR_SDI
SSTIMER
ANA_REG2
AGND
DGND
DVDD
TEST3
RST
NC
SCL
SDA
SDIN
SCLK
LRCLK
PDN
Pin Functions
PIN
NAME
NUMBER
TYPE (1)
TERMINATION
DESCRIPTION
ADR/SPK_FAULT
20
DI/DO
—
Dual-function pin which sets the LSB of the 7-bit I2C address to 0 if
pulled to GND, 1 if pulled to DVDD. If configured to be a fault output via
the System Control Register 2 (0x05), the pin is pulled low when an
internal fault with the speaker amplifier occurs. A pullup or pulldown
resistor is required, as is shown in the .
AGND
36
P
—
Ground for analog circuitry (2)
AVDD
19
P
—
Power supply for internal analog circuitry
ANA_REG1
18
P
—
Linear voltage regulator output derived from AVDD supply which is
used for internal analog circuitry. Nominal 1.8-V output. (3)
ANA_REG2
37
P
—
Linear voltage regulator output derived from AVDD supply which is
used for internal analog circuitry. Nominal 3.3-V output. (3)
3, 42, 46,
47
P
—
Connection points for the bootstrap capacitors which are used to create
a power supply for the high-side gate drive of the device.
DGND
35
P
—
Ground for digital circuitry (2)
DIG_REG
24
P
—
Linear voltage regulator output derived from the DVDD supply which is
used for internal digital circuitry. (3)
DR_CN
12
P
—
Negative pin for capacitor connection used in headphone amplifier and
line driver charge pump
DR_CP
13
P
—
Positive pin for capacitor connection used in headphone amplifier and
line driver charge pump
DR_INx
7, 10
AI
—
Input for channel A or B of headphone amplifier or line driver
DR_OUTx
8, 9
AO
—
Output for channel A or B of headphone amplifier or line driver
DR_SDI
39
DI
—
Places the headphone amplifier/line driver in shutdown when pulled
low.
BSTRPx
(1)
(2)
(3)
TYPE: AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, P = Power, G = Ground (0 V)
This pin should be connected to the system ground.
This pin is provided as a connection point for filtering capacitors for the supply and must not be used to power any external circuitry.
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Pin Functions (continued)
PIN
TYPE (1)
TERMINATION
11
P
—
Negative supply generated by charge pump for ground centered
headphone and line driver output
DRVDD
14
P
—
Power supply for internal headphone and line driver circuitry
DVDD
34
P
—
Power supply for the internal digital circuitry
GVDD_REG
40
P
—
Voltage regulator derived from PVDD supply (3)
LRCLK
26
DI
Pulldown
Word select clock of the serial audio port.
MCLK
21
DI
Pulldown
Master clock used for internal clock tree and sub-circuit and state
machine clocking
NC
31
—
—
Not connected inside the device (all NC terminals should be connected
to ground for optimal thermal performance)
OSC_GND
23
P
—
Ground for oscillator circuitry (the terminal should be connected to the
system ground)
OSC_RES
22
AO
—
Connection point for oscillator trim resistor
NAME
NUMBER
DRVSS
PDN
DESCRIPTION
Quick powerdown of the device that is used upon an unexpected loss
of the PVDD or DVDD power supply to quickly transition the outputs of
the speaker amplifier to Hi-Z. The quick powerdown feature avoids the
audible anamolies that would occur as a result of loss of either of the
supplies.
25
DI
Pullup
1, 44
P
—
Ground for power device circuitry (2)
PLL_FLTM
16
AI/AO
—
Negative connection point for the PLL loop filter components
PLL_FLTP
17
AI/AO
—
Positive connection point for the PLL loop filter components
PLL_GND
15
P
—
Ground for PLL circuitry (this terminal should be connected to the
system ground)
PowerPAD™
—
P
—
Thermal and ground pad that provides both an electrical connection to
the ground plane and a thermal path to the PCB for heat dissipation.
The pad must be grounded to the system ground. (2)
Power supply for internal power circuitry
PGND
PVDD
4, 41
P
—
RST
32
DI
Pullup
SCL
30
DI
—
SCLK
27
DI
Pulldown
SDA
29
DI/DO
—
SDIN
Places the device in reset when pulled low
I2C serial control port clock
Bit clock of the serial audio port
I2C serial control port data
28
DI
Pulldown
2, 43, 45,
48
AO
—
Speaker amplifier outputs
SSTIMER
38
AI
—
Controls ramp time of SPK_OUTx to minimize pop. Leave the pin
floating for BD mode. Requires capacitor to GND in AD mode, as is
shown in . The capacitor determines the ramp time.
TEST1/TEST2
5/6
DO
—
Used for testing during device production (the terminal must be left
floating)
TEST3
33
DI
—
Used for testing during device production (the terminal must be
connected to GND)
SPK_OUTx
4
Data line to the serial data port
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6 Specifications
6.1 Absolute Maximum Ratings (1)
Over operating free-air temperature range (unless otherwise noted).
Temperature
MIN
MAX
UNIT
0
85
°C
DVDD, DRVDD, AVDD
–0.3
4.2
V
PVDD
–0.3
30
V
DVDD referenced digital inputs
–0.5
DVDD + 0.5
Ambient operating temperature, TA
Supply voltage
Input voltage
5-V tolerant digital inputs
(2)
DR_INx
–0.5
DVDD + 2.5
V
(3)
V
DRVSS – 0.3
DRVDD + 0.3
V
12.8
N/A
Ω
HP Load
RLOAD(HP)
Line Driver Load
RLOAD(LD)
600
N/A
Ω
Voltage at speaker output pins
SPK_OUTx
–0.03
32
V
Voltage at BSTRPx pins
BSTRPx
–0.03
39
V
–40
125
°C
Storage temperature, Tstg
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods can affect device reliability.
5-V tolerant inputs are PDN, RESET, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL.
Maximum pin voltage should not exceed 6 V.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
TA
Ambient operating temperature
VDD
DVDD, DRVDD, and AVDD supply
PVDD
PVDD supply
VIH
Input logic high
VIL
Input logic low
RHP
Minimum HP load
RLD
Minimum line driver load
RSPK(BTL)
Minimum speaker load in BTL mode
RSPK(PBTL)
Minimum speaker load in post-filter PBTL mode
LFILT
Minimum output inductance under short-circuit condition
(1)
MIN
MAX
0
85
UNIT
°C
2.97
3.63
V
4.5
26.4 (1)
V
2
V
0.8
V
16
Ω
600
Ω
4
Ω
2
Ω
10
µH
For operation at PVDD levels greater than 18 V, the modulation limit must be set to 93.8% via the control port register 0x10.
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6.4 Thermal Characteristics
DCA (48 Pins)
THERMAL METRIC (1)
Special Test
Case
JEDEC
Standard 2Layer PCB
JEDEC
Standard 4Layer PCB
UNIT
49.9
26.2
°C/W
Junction-to-ambient thermal resistance (1)
RθJA
RθJC(top) Junction-to-case (top) thermal resistance (2)
14.9
°C/W
6.9
°C/W
Junction-to-board thermal resistance (3)
RθJB
(4)
ψJT
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter (5)
RθJC(bott
Junction-to-case (bottom) thermal resistance
(6)
1.1
0.8
°C/W
10.8
0.8
°C/W
1.7
°C/W
om)
(1)
(2)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard
test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3)
(4)
(5)
(6)
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
IIL
Low-level input current
IIH
High-level input current
IDD
3.3-V supply current
TEST CONDITIONS
ADR/SPK_FAULT and
SDA
Digital Inputs
3.3-V supply voltage
(DVDD, AVDD)
IOH = –4 mA
DVDD = AVDD = 3 V
MIN
TYP
MAX
2.4
UNIT
V
IOL = 4 mA
DVDD = AVDD = 3 V
0.5
VI < VIL
DVDD = AVDD = 3.6 V
75
VI > VIH
DVDD = AVDD = 3.6 V
75
Normal mode
49
68
Reset (RST = low, PDN
= high)
23
38
V
μA
μA
mA
6.6 Speaker Amplifier Characteristics in All Modes
over operating free-air temperature range (unless otherwise noted)
PARAMETER
fSPK_AMP
6
Speaker amplifier switching
frequency
RDS(ON)
On resistance of output MOSFET
(both high-side and low-side)
RPD
Internal pulldown resistor at output
of each half-bridge making up the
full bridge outputs
TEST CONDITIONS
MIN
TYP
MAX
UNIT
11.025-kHz, 22.05-kHz, or 44.1-kHz
data rate ±2%
352.8
kHz
48-kHz, 24-kHz, 12-kHz, 8-kHz, 16kHz, or 32-kHz data rate ±2%
384
kHz
PVDD = 15 V, TA = 25°C, die only
120
mΩ
PVDD = 15 V, TA = 25°C,
includes: die, bond wires, leadframe
160
mΩ
3
kΩ
Connected when drivers are hi-Z to
provide bootstrap capacitor charge
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6.7 Speaker Amplifier Characteristics in Stereo Bridge Tied Load (BTL) Mode
TA = 25°C, PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, audio input signal = 1-kHz sine wave, BTL, AD mode, fS = 48
kHz, RSPK = 8 Ω, AES17 filter, fPWM = 384 kHz, external components per , and in accordance with recommended operating
conditions (unless otherwise specified).
PARAMETER
ICN(SPK)
TEST CONDITIONS
Idle channel noise
MIN
PVDD = 18 V, A-Weighted
Maximum continuous output
power per channel
Signal-to-noise ratio (referenced
to 0dBFS input signal)
SNR(SPK)
THD+N(SPK)
Total harmonic distortion and
noise
Crosstalk (worst case between Lto-R and R-to-L coupling)
X-Talk(SPK)
MAX
UNIT
56
µVrms
4
W
PVDD = 13 V, 10% THD, 1-kHz
input signal
10.5
W
PVDD = 18 V, 10% THD, 1-kHz
input signal
20
W
105
dB
PVDD = 8 V, 10% THD, 1-kHz input
signal
PO(SPK)
TYP
PVDD = 18 V, A-weighted, f = 1
kHz, maximum power at THD < 1%
PVDD = 18 V; PO = 1 W
0.15%
PVDD = 13 V; PO = 1 W
0.13%
PVDD = 8 V; PO = 1 W
0.2%
PO = 1 W, f = 1 kHz (BD mode)
–70
dB
PO = 1 W, f = 1 kHz (AD mode)
–48
dB
6.8 Speaker Amplifier Characteristics in Stereo Post-Filter Parallel Bridge Tied Load (PostFilter PBTL) Mode
TA = 25°C, PVDD = 18 V, AVDD = DRVDD = DVDD = 3.3 V, audio input signal = 1-kHz sine wave, BTL, AD mode, fS = 48
kHz, RSPK = 4 Ω, AES17 filter, fPWM = 384 kHz, external components per , and in accordance with recommended operating
conditions (unless otherwise specified).
PARAMETER
ICN(SPK)
TEST CONDITIONS
Idle channel noise
MIN
PVDD = 18 V, A-Weighted
Maximum continuous output
power per channel
Signal-to-noise ratio (referenced
to 0dBFS input signal)
SNR(SPK)
THD+N(SPK)
Total harmonic distortion and
noise
MAX
42
PVDD = 13 V, 10% THD, 1-kHz
input signal
PO(SPK)
TYP
UNIT
µVrms
18.9
W
PVDD = 8 V, 10% THD, 1-kHz input
signal
7.2
W
PVDD = 18 V, 10% THD, 1-kHz
input signal
39
W
105
dB
PVDD = 18 V, A-weighted, f = 1
kHz, maximum power at THD < 1%
PVDD = 18 V; PO = 1 W
0.06%
PVDD = 13 V; PO = 1 W
0.03%
PVDD = 8 V; PO = 1 W
0.15%
6.9 Headphone Amplifier and Line Driver Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
fCP
PO(HP)
TEST CONDITIONS
Charge pump switching
frequency
Headphone amplifier output
power
RLOAD(HP) = 32 Ω, THD+N = 1%, outputs
in phase
SNR(HP)
Signal-to-noise ratio
SNR(LD)
Signal-to-noise ratio
MIN
TYP
MAX
UNIT
200
300
400
kHz
55
mW
(Referenced to 55-mW output signal),
RLOAD(HP) = 32 Ω, A-Weighted
101
dB
(Referenced to 2-Vrms output signal),
RLOAD(LD) = 10 kΩ, A-Weighted
105
dB
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6.10 Protection Circuitry Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
OCETHRES
Overcurrent threshold for each BTL
output
PVDD = 15 V, TA = 25°C
UVETHRES(PVDD)
Undervoltage error (UVE) threshold
UVETHRES(AVDD)
Undervoltage error (UVE) threshold
UVEHYST(PVDD)
UVEHYST(AVDD)
MIN
TYP
MAX
UNIT
4.5
A
PVDD falling
4
V
AVDD falling
4.1
V
UVE recovery threshold
PVDD rising
4.5
V
UVE recovery threshold
AVDD rising
2.7
V
150
°C
30
°C
OTETHRES
Overtemperature error (OTE) threshold
OTEHYST
OTE recovery threshold
6.11 I²C Interface Timing Requirements
MIN
TYP
MAX
UNIT
tw(RST)
Pulse duration, RST active
td(I²C_ready)
Time to enable I²C after RST goes high
100
13.5
ms
fSCL
Frequency, SCL
400
kHz
tw(H)
Pulse duration, SCL high
0.6
tw(L)
Pulse duration, SCL low
1.3
tr
Rise time, SCL and SDA
tf
Fall time, SCL and SDA
tsu1
Setup time, SDA to SCL
th1
Hold time, SCL to SDA
t(buf)
μs
μs
μs
300
ns
300
ns
100
ns
0
ns
Bus free time between stop and start conditions
1.3
μs
tsu2
Setup time, SCL to start condition
0.6
μs
th2
Hold time, start condition to SCL
0.6
μs
tsu3
Setup time, SCL to stop condition
0.6
μs
CL
Load capacitance for each bus line
400
pF
6.12 Serial Audio Port Timing Requirements
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
CL ≤ 30 pF
MIN
TYP
1.024
MAX
UNIT
12.288
MHz
fSCLKIN
Frequency, SCLK 32 × fS, 48 × fS, 64 × fS
tsu1
Setup time, LRCK to SCLK rising edge
10
ns
th1
Hold time, LRCK from SCLK rising edge
10
ns
tsu2
Setup time, SDIN to SCLK rising edge
10
ns
th2
Hold time, SDIN from SCLK rising edge
10
ns
LRCK frequency
8
48
48
SCLK duty cycle
40%
50%
60%
LRCK duty cycle
40%
50%
60%
SCLK rising edges between LRCK rising edges
kHz
32
64
SCLK
edges
–1/4
1/4
SCLK
period
t(edge)
LRCK clock edge with respect to the falling edge of SCLK
tr/tf
Rise/fall time for SCLK/LRCK
8
ns
LRCK allowable drift before LRCK reset
4
MCLKs
8
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RST
tw(RST)
2
2
I C Active
I C Active
td(I2C_ready)
System Initialization.
2
Enable via I C.
T0421-01
NOTE: On power up, hold the TAS5753MD RST LOW for at least 100 μs after DVDD has reached 3 V.
NOTE: If RST is asserted LOW while PDN is LOW, then RST must continue to be held LOW for at least 100 μs after PDN is
deasserted (HIGH).
Figure 1. Reset Timing
tw(H)
tw(L)
tf
tr
SCL
tsu1
th1
SDA
T0027-01
Figure 2. SCL and SDA Timing
SCL
t(buf)
th2
tsu2
tsu3
SDA
Start
Condition
Stop
Condition
T0028-01
Figure 3. Start and Stop Conditions Timing
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tr
tf
SCLK
(Input)
t(edge)
th1
tsu1
LRCLK
(Input)
th2
tsu2
SDIN
T0026-04
Figure 4. Serial Audio Port Timing
6.13 Typical Electrical Power Consumption
over operating free-air temperature range (unless otherwise noted), with DVDD = 3.3 V and AVDD = PVDD, external
components as specified on the EVM.
SPEAKER AMPLIFIER STATE
fSPK_AMP
384kHz
10
OPERATIONAL
STATE
CONFIGURATION SETTINGS
Idle
RST pulled high, speaker amplifier
outputs at 50/50 mute
Reset
RST pulled low, PDN pulled high
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VPVDD
[V]
18
IPVDD
[mA]
IVDD
[mA]
PDISS
(From all
Supplies)
[W]
20
48
0.51
5
21
0.16
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6.14 Typical Characteristics
Table 1. Quick Reference Table
OUTPUT CONFIGURATION
PLOT TITLE
FIGURE NUMBER
Output Power vs Supply Voltage – BTL
Figure 5
THD+N vs Frequency – BTL
Figure 6
THD+N vs Frequency – BTL
Figure 7
THD+N vs Frequency – BTL
Figure 8
Bridge Tied Load (BTL)
Configuration Curves
Figure 9
THD+N vs Output Power – BTL
Figure 10
THD+N vs Output Power – BTL
Figure 11
THD+N vs Output Power – BTL
Figure 12
THD+N vs Output Power – BTL
Figure 13
Noise vs Supply Voltage – BTL
Figure 14
Efficiency vs Output Power – BTL
Figure 15
Idle Channel Current vs Supply Voltage – BTL
Figure 16
Powerdown Current vs Supply Voltage – BTL
Figure 17
Output Power vs Supply Voltage – PBTL
Figure 18
Output Power vs Frequency – PBTL
Figure 19
Output Power vs Frequency – PBTL
Figure 20
Output Power vs Frequency – PBTL
Figure 21
Output Power vs Frequency – PBTL
Figure 22
THD+N vs Output Power – PBTL
Figure 23
THD+N vs Output Power – PBTL
Figure 24
THD+N vs Output Power – PBTL
Figure 25
THD+N vs Output Power – PBTL
Figure 26
Noise vs Supply Voltage – PBTL
Figure 27
Parallel Bridge Tied Load
(PBTL) Configuration Curves
Headphone Amplifier
Configuration Curves
THD+N vs Frequency – BTL
Efficiency vs Output Power – PBTL
Figure 28
Idle Channel Draw vs Supply Voltage – PBTL
Figure 29
Power Down Current vs Supply Voltage – PBTL
Figure 30
Headphone Total Harmonic Distortion + Noise vs Frequency
Figure 31
Headphone Total Harmonic Distortion + Noise vs Output Power
Figure 32
Headphone Crosstalk vs Frequency
Figure 33
Headphone Crosstalk vs Frequency
Figure 34
Line Driver Total Harmonic Distortion + Noise vs Frequency
Figure 35
Line Driver THD+N vs Output Voltage
Figure 36
Line Driver Crosstalk vs Frequency
Figure 37
Line Driver Configuration
Curves
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6.14.1 Typical Characteristics – BTL Mode
55
10
Inst. Power, Rspk = 8 :
Cont. Power, Rspk = 8 :
Inst. Power, Rspk = 6 :
Cont. Power, Rspk = 6 :
Inst. Power, Rspk = 4 :
Cont. Power, Rspk = 4 :
Output Power (W)
45
40
35
Rspk = 8 :
Rspk = 6 :
Rspk = 4 :
1
THD+N (%)
50
30
25
20
15
0.1
0.01
10
5
0
4
6
8
10
12
14
16
18
Supply Voltage (V)
20
22
0.001
20
24
100
D001
THD+N = 10%
1k
Frequency (Hz)
10k
D002
PO = 1 W
Figure 5. Output Power vs Supply Voltage – BTL
VPVDD = 12 V
Figure 6. THD+N vs Frequency – BTL
10
10
Rspk = 8 :
Rspk = 6 :
Rspk = 4 :
Rspk = 8 :
Rspk = 6 :
Rspk = 4 :
1
1
THD+N (%)
THD+N (%)
20k
0.1
0.01
0.1
0.01
0.001
20
100
1k
Frequency (Hz)
PO = 1 W
10k
0.001
20
20k
100
D003
VPVDD = 15 V
1k
Frequency (Hz)
10k
D004
PO = 1 W
Figure 7. THD+N vs Frequency – BTL
20k
VPVDD = 18 V
Figure 8. THD+N vs Frequency – BTL
10
20
Rspk = 8 :
Rspk = 6 :
Rspk = 4 :
Rspk = 8 :
Rspk = 6 :
Rspk = 4 :
10
THD+N (%)
THD+N (%)
1
0.1
1
0.1
0.01
0.001
20
100
1k
Frequency (Hz)
PO = 1 W
10k
0.01
0.0007
0.01
D005
VPVDD = 24 V
Figure 9. THD+N vs Frequency – BTL
12
20k
f = 1 kHz
0.1
Output Power (W)
1
10 20
D006
VPVDD = 12 V
Figure 10. THD+N vs Output Power – BTL
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Typical Characteristics – BTL Mode (continued)
20
10
20
Rspk = 8 :
Rspk = 6 :
Rspk = 4 :
Rspk = 8 :
Rspk = 6 :
Rspk = 4 :
10
THD+N (%)
THD+N (%)
1
0.1
1
0.1
0.01
0.001
0.0005
0.01
0.1
1
Output Power (W)
Input Signal = 1
kHz
10
0.01
0.0007
50
VPVDD = 15 V
0.1
1
Output Power (W)
10
50
D008
Input Signal = 1
kHz
Figure 11. THD+N vs Output Power – BTL
VPVDD = 16 V
Figure 12. THD+N vs Output Power – BTL
20
60
Rspk = 8 :
Rspk = 6 :
Rspk = 4 :
55
50
Idle Channel noise (PV)
10
THD+N (%)
0.01
D007
1
0.1
45
40
35
30
25
20
15
10
5
0.01
0.0007
0.01
0.1
1
Output Power (W)
Input Signal = 1
kHz
10
4
100
6
8
10
D009
VPVDD = 24 V
12
14
16
PVDD (V)
18
20
22
24
D010
RL = 8 Ω
Figure 14. Idle Channel Noise vs Supply Voltage – BTL
Figure 13. THD+N vs Output Power – BTL
1
0.9
0.8
Idle Current (ma)
Efficiency (%)
0.7
0.6
0.5
0.4
0.3
PVDD = 12 V
PVDD = 15 V
PVDD = 19.6 V
PVDD = 24 V
0.2
0.1
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
Total Output Power (W)
D011
RL = 8 Ω
80
75
70
65
60
55
50
45
40
35
30
25
20
15
4
6
8
10
12
14 16 18
PVDD (V)
20
22
24
26
D013
RL = 8 Ω
Figure 15. Efficiency vs Output Power – BTL
Figure 16. Idle Channel Current vs Supply Voltage – BTL
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Typical Characteristics – BTL Mode (continued)
20
Powerdown Current (mA)
18
16
14
12
10
8
6
4
2
0
6
8
10
12
14
16
PVDD (V)
18
20
22
24
D019
LPVDD = 158 µA
PDN = 0
DVDD = 3.3 V
Figure 17. Powerdown Current vs Supply Voltage – BTL
14
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6.14.2 Typical Characteristics – PBTL Mode
160
10
Inst. Power, Rspk = 6 :
Cont. Power, Rspk = 6 :
Inst. Power, Rspk = 4 :
Cont. Power, Rspk = 4 :
Inst. Power, Rspk = 3 :
Cont. Power, Rspk = 3 :
Inst. Power, Rspk = 2 :
Cont. Power, Rspk = 2 :
Output Power (W)
120
100
80
Rspk = 8 :
Rspk = 6 :
Rspk = 4 :
1
THD+N (%)
140
60
0.1
40
0.01
20
0
4
6
8
10
12
14
16
18
Supply Voltage (V)
20
22
0.002
20
24
100
D001
THD+N = 10%
1k
Frequency (Hz)
PO = 1 W
Figure 18. Output Power vs Supply Voltage – PBTL
20k
D002
VPVDD = 12 V
Figure 19. THD+N vs Frequency – PBTL
10
10
Rspk = 8 :
Rspk = 6 :
Rspk = 4 :
Rspk = 8 :
Rspk = 6 :
Rspk = 4 :
1
THD+N (%)
1
THD+N (%)
10k
0.1
0.01
0.1
0.01
0.001
20
100
1k
Frequency (Hz)
PO = 1 W
10k
0.001
20
20k
100
D002
VPVDD = 15 V
1k
Frequency (Hz)
PO = 1 W
Figure 20. THD+N vs Frequency – PBTL
10k
20k
D004
VPVDD = 18 V
Figure 21. THD+N vs Frequency – PBTL
10
20
10
Rspk = 8 :
Rspk = 6 :
Rspk = 4 :
Rspk = 8 :
Rspk = 6 :
Rspk = 4 :
1
THD+N (%)
THD+N (%)
1
0.1
0.01
0.1
0.01
0.001
20
100
1k
Frequency (Hz)
PO = 1 W
10k
20k
0.001
0.0005
0.01
D005
VPVDD = 24 V
Figure 22. THD+N vs Frequency – PBTL
f = 1 kHz
0.1
1
Output Power (W)
10
50
D006
VPVDD = 12 V
Figure 23. THD+N vs Output Power – PBTL
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Typical Characteristics – PBTL Mode (continued)
20
10
20
10
Rspk = 8 :
Rspk = 6 :
Rspk = 4 :
1
THD+N (%)
THD+N (%)
1
Rspk = 8 :
Rspk = 6 :
Rspk = 4 :
0.1
0.01
0.1
0.01
0.001
0.0005
0.01
0.1
1
Output Power (W)
10
0.001
0.0005
50
0.01
D007
f = 1 kHz
VPVDD = 15 V
f = 1 kHz
0.1
1
Output Power (W)
10
100
D008
Input Signal = 1
kHz Sine
VPVDD = 18 V
Figure 24. THD+N vs Output Power – PBTL
Figure 25. THD+N vs Output Power – PBTL
55
20
10
Rspk = 8 :
Rspk = 6 :
Rspk = 4 :
Idle Channel Noise (PV)
50
THD+N (%)
1
0.1
0.01
45
40
35
30
25
20
15
10
5
0.001
0.0005
0.01
f = 1 kHz
0.1
1
Output Power (W)
10
4
100
6
8
10
D009
Input Signal = 1
kHz Sine
VPVDD = 24 V
12
14
16
PVDD (V)
18
20
22
24
D010
RL = 8 Ω
Figure 27. Idle Channel Noise vs Supply Voltage – PBTL
Figure 26. THD+N vs Output Power – PBTL
100
100
90
90
Idle Current Draw (mA)
80
Efficiency (%)
70
60
50
40
30
PVDD = 12 V
PVDD = 15 V
PVDD = 19.6 V
PVDD = 24 V
20
10
5
10
15
20
25
Output Power (W)
30
35
60
50
40
20
40
4
6
8
D001
10
12
14 16 18
PVDD (V)
20
22
24
26
D013
RL = 8 Ω
RL = 8 Ω
Figure 28. Efficiency vs Output Power – PBTL
16
70
30
0
0
80
Figure 29. Idle Channel Draw vs Supply Voltage – PBTL
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Typical Characteristics – PBTL Mode (continued)
20
18
Power Down Current (mA)
16
14
12
10
8
6
4
2
0
6
8
10
12
14
16
PVDD (V)
18
20
22
24
D016
IPVDD = 159 µA
PDN = 0
DVDD = 3.3 V
Figure 30. Power Down Current vs Supply Voltage – PBTL
6.14.3 Typical Characteristics – Headphone Amplifier
10
10
RL = 16Ÿ
DRVDD = 3.3V
PO = 10mW
TA = 25°C
DRVDD = 3.3V
f = 1kHz
TA = 25°C
RL = 32Ÿ
1
0.1
THD+N (%)
THD+N (%)
1
0.01
0.1
0.01
0.001
RL = 32Ÿ
RL = 16Ÿ
0.0001
20
200
2k
20k
0.001
0.001
Frequency (Hz)
0.01
C021
DRVDD = 3.3 V
PO = 10 mW
0.1
Output Power (W)
TA = 25 ºC
Figure 31. Headphone Total Harmonic Distortion + Noise
vs Frequency
C022
DRVDD = 3.3 V
f = 1 kHz
TA = 25 ºC
Figure 32. Headphone Total Harmonic Distortion + Noise
vs Output Power
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Typical Characteristics – Headphone Amplifier (continued)
0
0
Right to Left
VO = 1Vrms
DRVDD = 3.3V
RL = 16Ÿ
TA = 25ƒC
±10
±20
±20
Left to Right
±30
Crosstalk (dB)
Crosstalk (dB)
±30
Right to Left
Vo = 1Vrms
DRVDD = 3.3V
RL = 32Ÿ
TA = 25ƒC
±10
Left to Right
±40
±50
±60
±40
±50
±60
±70
±70
±80
±80
±90
±90
±100
±100
20
200
2k
20k
20
200
Frequency (Hz)
2k
20k
Frequency (Hz)
C023
DRVDD = 3.3 V
TA = 25 ºC
VO = 1 Vrms
C024
RL = 16 Ω
Figure 33. Headphone Crosstalk vs Frequency
DRVDD = 3.3 V
TA = 25 ºC
VO = 1 Vrms
RL = 32 Ω
Figure 34. Headphone Crosstalk vs Frequency
6.14.4 Typical Characteristics – Line Driver
10
10
DRVDD = 3.3V
PO = 10mW
TA = 25ƒC
DRVDD = 3.3V
f = 1kHz
TA = 25°C
1
0.1
THD+N (%)
THD+N (%)
1
0.01
0.1
0.01
0.001
RL = 5kŸ
RL = 10kŸ
RL = 10kŸ
RL = 5kŸ
0.0001
20
200
2k
20k
0.001
0.01
0.1
Frequency (Hz)
1
Output Voltage (V)
C025
DRVDD = 3.3 V
PO = 10 mW
TA = 25 ºC
Figure 35. Line Driver Total Harmonic Distortion + Noise
vs Frequency
18
C026
DRVDD = 3.3 V
f = 1 kHz
TA = 25 ºC
Figure 36. Line Driver THD+N vs Output Voltage
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Typical Characteristics – Line Driver (continued)
0
Right to Left
VO = 1Vrms
DRVDD = 3.3V
RL = 5kŸ
TA = 25ƒC
-10
-20
Left to Right
Crosstalk (dB)
-30
-40
-50
-60
-70
-80
-90
-100
20
200
2k
20k
Frequency (Hz)
C027
DRVDD = 3.3 V
TA = 25 ºC
VO = 1 Vrms
RL = 5 kΩ
Figure 37. Line Driver Crosstalk vs Frequency
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7 Detailed Description
7.1 Overview
The TAS5753MD device is an efficient, digital-input audio amplifier for driving stereo speakers configured as a
bridge tied load (BTL). In parallel bridge tied load (PBTL) in can produce higher power by driving the parallel
outputs into a single lower impedance load. One serial data input allows processing of up to two discrete audio
channels and seamless integration to most digital audio processors and MPEG decoders. The device accepts a
wide range of input data and data rates. A fully programmable data path routes these channels to the internal
speaker drivers.
The TAS5753MD device is a slave-only device receiving all clocks from external sources. The TAS5753MD
device operates with a PWM carrier between a 384-kHz switching rate and a 288-kHz switching rate, depending
on the input sample rate. Over-sampling combined with a fourth-order noise shaper provides a flat noise floor
and excellent dynamic range from 20 Hz to 20 kHz.
7.2 Functional Block Diagram
DVDD
AVDD
ANA_REG1 ANA_REG2 DIG_REG DRVDD DR_CN DR_CP
Analog Supply
Regulators
PVDD
DRVSS
GVDD_REG
Gate Drive
Regulator
Charge Pump
Digital Supply Regulator
PWM Power Stage
Digital Audio Processor
MCLK
SCLK
LRCLK
SDIN
Digital Equalizer, Three-Band
AGL, Coarse/Fine Volume
Control, THD Manager, PWM
Level Meter
Serial
Audio
Port
Open Loop
Digital PWM
Modulator
Gate
Drives
Gate
Drives
Full Bridge
Power
Stage A
SPK_OUTA
OverCurrent
Protection
Full Bridge
Power
Stage B
SPK_OUTB
SPK_OUTC
SPK_OUTD
Clock
Monitoring
Stereo HP / Line Driver
DR_INx
DRVDD
-
DR_INA
DR_INB
Die Temp. Monitor
DR_OUTA
DR_OUTB
DR_OUTx
DRVSS
+
Internal Control Registers and State Machines
ADR / SPK_FAULT
DR_SDI
PDN
RST
SCL
SDA
Figure 38. TAS5753MD Functional Block Diagram
20
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7.3 Audio Signal Processing Overview
DC Block and LR Mixer
Equalizer
Multi Band AGL
0x59
Full Band AGL
Master Volume
0x3B - 0x3C, 0x40
Biquad
0x5E
0x72, 0x73
0x26
L
Biquad
0x27 - 0x2F, 0x58
Input
Mixer L
AGL 1
Low Band
0x8
0x51
Biquad
0x44 - 0x45, 0x48
10 Biquads
0x5A
0x3E - 0x3F, 0x43
0x07 - 0x57, 0x56
Mixer L
L
Vol 1
Biquad
0x5F
0x76, 0x77
AGL 2
High Band
0x9
0x42 - 0x41, 0x47
Vol 2
0x52
Biquad
Biquad
Master Volume,
Pre Scale,
Post Scale
0x31 - 0x39, 0x5D
0x30
R
AGL 4
Full Band
Input
Mixer R
10 Biquads
R
0x5B, 0x5C
Mixer R
2 Biquads
0x60, 0x61
AGL 3
Mid Band
2 Biquads
Figure 39. TAS5753MD Audio Process Flow
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7.4 Feature Description
7.4.1 Clock, Autodetection, and PLL
The TAS5753MD device is an I²S slave device. The TAS5753MD device accepts MCLK, SCLK, and LRCK. The
digital audio processor (DAP) supports all the sample rates and MCLK rates that are defined in the Clock Control
Register.
The TAS5753MD device checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only
supports a 1 × fS LRCK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The
clock section uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to
produce the internal clock (DCLK) running at 512 times the PWM switching frequency.
The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock
rates as defined in the Clock Control Register.
The TAS5753MD device has robust clock error handling that uses the built-in trimmed oscillator clock to quickly
detect changes/errors. Once the system detects a clock change/error, the system mutes the audio (through a
single-step mute) and then forces PLL to limp using the internal oscillator as a reference clock. Once the clocks
are stable, the system autodetects the new rate and reverts to normal operation. During this process, the default
volume is restored in a single step (also called hard unmute). The ramp process can be programmed to ramp
back slowly (also called soft unmute) as defined in the Volume Configuration Register.
7.4.2 PWM Section
The TAS5753MD DAP device uses noise-shaping and customized nonlinear correction algorithms to achieve
high power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise
shaper to increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from
the DAP and outputs two BTL PWM audio output channels.
The PWM section has individual-channel dc-blocking filters that can be enabled and disabled. The filter cutoff
frequency is less than 1 Hz.
The PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%. For PVDD > 18 V the
modulation index must be limited to 96.1% for safe and reliable operation.
7.4.3 PWM Level Meter
The structure in Figure 40 shows the PWM level meter that can be used to study the power profile.
Post-DAP Processing
1–a
–1
Z
Ch1
ABS
a
rms
32-Bit Level
ADDR = 0x6B
2
I C Registers
(PWM Level Meter)
1–a
–1
Z
Ch2
ABS
a
rms
32-Bit Level
ADDR = 0x6C
B0396-01
Figure 40. PWM Level Meter Structure
7.4.4 Automatic Gain Limiter (AGL)
The AGL scheme has three AGL blocks. One ganged AGL exists for the high-band left/right channels, the midband left/right channels, and the low-band left/right channels.
The AGL input/output diagram is shown in Figure 41.
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Output Level (dB)
Feature Description (continued)
1:1 Transfer Function
Implemented Transfer Function
T
Input Level (dB)
M0091-04
Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
• Each AGL has adjustable threshold levels.
• Programmable attack and decay time constants
• Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,
and decay times can be set slow enough to avoid pumping.
Figure 41. Automatic Gain Limiter
Alpha Filter Structure
S
a
–1
w
Z
T = 9.23 format, all other AGL coefficients are 3.23 format
Figure 42. AGL Structure
Table 2. AGL Structure
α, ω
T
αa, ωa / αd, ωd
AGL 1
0x3B
0x40
0x3C
AGL 2
0x3E
0x43
0x3F
AGL 3
0x47
0x41
0x42
AGL 4
0x48
0x44
0x45
7.4.5 Headphone/Line Amplifier
An integrated ground centered DirectPath combination headphone amplifier and line driver is integrated in the
TAS5729MD. This headphone/line amplifier can be used independently from the device speaker amplifier
modes, with analog single-ended inputs DR_INA and DR_INB, linked to the respective analog outputs
DR_OUTA, and DR_OUTB. A basic diagram of the headphone/line amplifier is shown in Figure 43.
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Figure 43. Headphone/Line Amplifier
The DR_SDI pin can be used to turn on or off the headphone amplifier and line driver. The DirectPath amplifier
makes use of the provided positive and negative supply rails generated by the IC. The output voltages are
centered at zero volts with the capability to swing to the positive rail or negative rail; combining this capability
with the built-in click and pop reduction circuit, the DirectPath amplifier requires no output dc blocking capacitors.
7.4.6 Fault Indication
ADR/FAULT is an input pin during power up. This pin can be programmed after RST to be an output by writing 1
to bit 0 of I²C register 0x05. In that mode, the ADR/FAULT pin has the definition shown in Table 3.
Any fault resulting in device shutdown is signaled by the ADR/FAULT pin going low (see Table 3). A latched
version of this pin is available on D1 of register 0x02. This bit can be reset only by an I²C write.
Table 3. ADR/FAULT Output States
ADR/FAULT
DESCRIPTION
0
Overcurrent (OC) or undervoltage (UVP) error or overtemperature error (OTE) or overvoltage
error
1
No faults (normal operation)
7.4.7 SSTIMER Pin Functionality
The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when
exiting all-channel shutdown. The capacitor on the SSTIMER pin is slowly charged through an internal current
source, and the charge time determines the rate at which the output transitions from a near-zero duty cycle to the
desired duty cycle. This allows for a smooth transition that minimizes audible pops and clicks. When the part is
shut down, the drivers are placed in the high-impedance state and transition slowly down through an internal 3kΩ resistor, similarly minimizing pops and clicks. The shutdown transition time is independent of the SSTIMER
pin capacitance. Larger capacitors increase the start-up time, while smaller capacitors decrease the start-up
time. The SSTIMER pin can be left floating for BD modulation.
7.4.8 Device Protection System
7.4.8.1 Overcurrent (OC) Protection With Current Limiting
The TAS5753MD device has independent, fast-reacting current detectors on all high-side and low-side powerstage FETs. The detector outputs are closely monitored to prevent the output current from increasing beyond the
overcurrent threshold defined in the Protection Circuitry Characteristics table.
If the output current increases beyond the overcurrent threshold, the device shuts down and the outputs
transition to the off or high impedance (Hi-Z) state. The device returns to normal operation once the fault
condition (i.e., a short circuit on the output) is removed. Current-limiting and overcurrent protection are not
independent for half-bridges. That is, if the bridge-tied load between half-bridges A and B causes an overcurrent
fault, half-bridges A, B, C, and D shut down.
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7.4.8.2 Overtemperature Protection
The TAS5753MD device has an overtemperature-protection system. If the device junction temperature exceeds
150°C (nominal), the device enters thermal shutdown, where all half-bridge outputs enter the high-impedance
(Hi-Z) state, and ADR/FAULT asserts low if the device is configured to function as a fault output. The
TAS5753MD device recovers automatically once the junction temperature of the device drops approximately
30°C.
7.4.8.3 Undervoltage Protection (UVP) and Power-On Reset (POR)
The UVP and POR circuits of the TAS5753MD device fully protect the device in any power-up/down and
brownout situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all
circuits are fully operational when the PVDD and AVDD supply voltages reach and 2.7 V, respectively. Although
PVDD and AVDD are independently monitored. For PVDD, if the supply voltage drops below the UVP threshold,
the protection feature immediately sets all half-bridge outputs to the high-impedance (Hi-Z) state and asserts
ADR/FAULT low.
7.5 Device Functional Modes
The TAS5753MD device is a digital input class-d amplifier with audio processing capabilities. The TAS5753MD
device has numerous modes to configure and control the device.
7.5.1 Serial Audio Port Operating Modes
The serial audio port in the TAS5753MD device supports industry-standard audio data formats, including I²S,
Left-justified(LJ) and Right-justified(RJ) formats. To select the data format that will be used with the device can
controlled by using the serial data interface registers 0x04. The default is 24bit, I²S mode. The timing diagrams
for the various serial audio port are shown in the Serial Interface Control and Timing section
7.5.2 Communication Port Operating Modes
The TAS5753MD device is configured via an I²C communication port. The I²C communication protocol is detailed
in the 7.7 I²C Serial Control Port Requirements and Specifications section.
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Device Functional Modes (continued)
7.5.3 Speaker Amplifier Modes
The TAS5753MD device can be configured as:
• Stereo Mode
• Mono Mode
7.5.3.1 Stereo Mode
Stereo mode is the most common option for the TAS5753MD. TAS5753MD can be connected in 2.0 mode to
drive stereo channels. Detailed application section regarding the stereo mode is discussed in the Stereo Bridge
Tied Load Application section.
7.5.3.2 Mono Mode
Mono mode is described as the operation where the two BTL outputs of amplifier are placed in parallel with one
another to provide increase in the output power capability. This mode is typically used to drive subwoofers, which
require more power to drive larger loudspeakers with high-amplitude, low-frequency energy. Detailed application
section regarding the mono mode is discussed in the Mono Parallel Bridge Tied Load Application section.
7.6 Programming
7.6.1 I²C Serial Control Interface
The TAS5753MD device has a bidirectional I²C interface that is compatible with the Inter IC (I²C) bus protocol
and supports both 100-kHz and 400-kHz data transfer rates for single- and multiple-byte write and read
operations. This is a slave-only device that does not support a multimaster bus environment or wait-state
insertion. The control interface is used to program the registers of the device and to read device status.
The DAP supports the standard-mode I²C bus operation (100 kHz maximum) and the fast I²C bus operation
(400 kHz maximum). The DAP performs all I²C operations without I²C wait cycles.
7.6.1.1 General I²C Operation
The I²C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte
(8-bit) format, with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A
high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit
transitions must occur within the low time of the clock period. These conditions are shown in Figure 44. The
master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then waits for an acknowledge condition. The TAS5753MD device holds SDA low during the
acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte
of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible
devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor
must be used for the SDA and SCL signals to set the high level for the bus.
SDA
R/
A
W
7-Bit Slave Address
7
6
5
4
3
2
1
0
8-Bit Register Address (N)
7
6
5
4
3
2
1
0
8-Bit Register Data For
Address (N)
A
7
6
5
4
3
2
1
8-Bit Register Data For
Address (N)
A
0
7
6
5
4
3
2
1
A
0
SCL
Start
Stop
T0035-01
Figure 44. Typical I²C Sequence
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Programming (continued)
No limit exists for the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 44.
The 7-bit address for the TAS5753MD device is 0101 010 (0x54) or 0101 011 (0x56) as defined by ADR/FAULT
(external pulldown for 0x54 and pullup for 0x56).
7.6.1.2 I²C Slave Address
The ADR/FAULT is an input pin during power-up and after each toggle of RST, which is used to set the I²C subaddress of the device. The ADR/FAULT can also operate as a fault output after power-up is complete and the
address has been latched in.
At power-up, and after each toggle of RST, the pin is read to determine its voltage level. If the pin is left floating,
an internal pull-up will set the I²C sub-address to 0x56. This will also be the case if an external resistor is used to
pull the pin up to AVDD. To set the sub-address to 0x54, an external resistor (specified in Typical Applications )
must be connected to the system ground.
As mentioned, the pin can also be reconfigured as an output driver via I²C for fault monitoring. Use System
Control Register 2 (0x05) to set ADR/FAULT pin to be used as a fault output during fault conditions.
7.6.1.2.1 I²C Device Address Change Procedure
1. Write to device address change enable register, 0xF8 with a value of 0xF9A5 A5A5.
2. Write to device register 0xF9 with a value of 0x0000 00XX, where XX is the new address.
3. Any writes after that should use the new device address XX.
7.6.1.3 Single- and Multiple-Byte Transfers
The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses
0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only multiplebyte read/write operations (in multiples of 4 bytes).
During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress
assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does
not contain 32 bits, the unused bits are read as logic 0.
During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes
that are required for each specific subaddress. For example, if a write command is received for a biquad
subaddress, the DAP must receive five 32-bit words. If fewer than five 32-bit data words have been received
when a stop command (or another start command) is received, the received data is discarded.
Supplying a subaddress for each subaddress transaction is referred to as random I²C addressing. The
TAS5753MD device also supports sequential I²C addressing. For write transactions, if a subaddress is issued
followed by data for that subaddress and the 15 subaddresses that follow, a sequential I²C write transaction has
taken place, and the data for all 16 subaddresses is successfully received by the TAS5753MD device. For I²C
sequential-write transactions, the subaddress then serves as the start address, and the amount of data
subsequently transmitted before a stop or start is transmitted determines how many subaddresses are written.
As was true for random addressing, sequential addressing requires that a complete set of data be transmitted. If
only a partial set of data is written to the last subaddress, the data for the last subaddress is discarded. However,
all other data written is accepted; only the incomplete data is discarded.
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Programming (continued)
7.6.1.4 Single-Byte Write
As shown in Figure 45, a single-byte data-write transfer begins with the master device transmitting a start
condition followed by the I²C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a data-write transfer, the read/write bit is a 0. After receiving the correct I²C device address
and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or
bytes corresponding to the internal memory address being accessed. After receiving the address byte, the
TAS5753MD device again responds with an acknowledge bit. Next, the master device transmits the data byte to
be written to the memory address being accessed. After receiving the data byte, the TAS5753MD device again
responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the singlebyte data-write transfer.
Start
Condition
Acknowledge
A6
A5
A4
A3
A2
A1
A0
Acknowledge
R/W ACK A7
A6
A5
2
A4
A3
A2
A1
Acknowledge
A0 ACK D7
D6
Subaddress
I C Device Address and
Read/Write Bit
D5
D4
D3
D2
D1
D0 ACK
Stop
Condition
Data Byte
T0036-01
Figure 45. Single-Byte Write Transfer
7.6.1.5 Multiple-Byte Write
A multiple-byte data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes
are transmitted by the master device to the DAP as shown in Figure 46. After receiving each data byte, the
TAS5753MD device responds with an acknowledge bit.
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
2
I C Device Address and
Read/Write Bit
A6
A5
A4
A3
Subaddress
A1
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A0 ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-02
Figure 46. Multiple-Byte Write Transfer
7.6.1.6 Single-Byte Read
As shown in Figure 47, a single-byte data-read transfer begins with the master device transmitting a start
condition, followed by the I²C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5753MD address
and the read/write bit, TAS5753MD device responds with an acknowledge bit. In addition, after sending the
internal memory address byte or bytes, the master device transmits another start condition followed by the
TAS5753MD address and the read/write bit again. This time, the read/write bit becomes a 1, indicating a read
transfer. After receiving the address and the read/write bit, the TAS5753MD device again responds with an
acknowledge bit. Next, the TAS5753MD device transmits the data byte from the memory address being read.
After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to
complete the single-byte data-read transfer.
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Programming (continued)
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
Acknowledge
A6
2
A5
A4
A0 ACK
A6
A5
A1
A0 R/W ACK D7
D6
2
I C Device Address and
Read/Write Bit
Subaddress
I C Device Address and
Read/Write Bit
Not
Acknowledge
Acknowledge
D1
D0 ACK
Stop
Condition
Data Byte
T0036-03
Figure 47. Single-Byte Read Transfer
7.6.1.7 Multiple-Byte Read
A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes
are transmitted by the TAS5753MD device to the master device as shown in Figure 48. Except for the last data
byte, the master device responds with an acknowledge bit after receiving each data byte.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A0 R/W ACK A7
2
I C Device Address and
Read/Write Bit
Acknowledge
A6
A6
A0 ACK
A5
2
Acknowledge
Acknowledge
Acknowledge
Not
Acknowledge
A0 R/W ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
I C Device Address and
Read/Write Bit
Subaddress
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-04
Figure 48. Multiple-Byte Read Transfer
7.6.2 Serial Interface Control and Timing
7.6.2.1 Serial Data Interface
Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5753MD DAP accepts serial
data in 16-bit, 20-bit, or 24-bit left-justified, right-justified, and I²S serial data formats.
7.6.2.2 I²S Timing
I²S timing uses LRCK to define when the data being transmitted is for the left channel and when the data is for
the right channel. LRCK is low for the left channel and high for the right channel. A bit clock running at 32 × fS,
48 × fS, or 64 × fS is used to clock in the data. A delay of one bit clock exists from the time the LRCK signal
changes state to the first bit of data on the data lines. The data is written MSB-first and is valid on the rising edge
of bit clock. The DAP masks unused trailing data bit positions.
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Programming (continued)
2
2-Channel I S (Philips Format) Stereo Input
32 Clks
LRCLK (Note Reversed Phase)
32 Clks
Right Channel
Left Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-01
NOTE: All data presented in two's-complement form with MSB first.
Figure 49. I²S 64-fS Format
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Programming (continued)
2
2-Channel I S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size)
LRCLK
24 Clks
24 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
MSB
LSB
17 16
9
8
5
4
13 12
5
4
1
0
9
1
0
3
2
1
0
LSB
23 22
17 16
9
8
5
4
19 18
13 12
5
4
1
0
15 14
9
1
0
3
2
1
20-Bit Mode
19 18
16-Bit Mode
15 14
8
8
T0092-01
NOTE: All data presented in two's-complement form with MSB first.
Figure 50. I²S 48-fS Format
2
2-Channel I S (Philips Format) Stereo Input
LRCLK
16 Clks
16 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
16-Bit Mode
15 14 13 12
MSB
LSB
11 10
9
8
5
4
3
2
1
0
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
T0266-01
NOTE: All data presented in two's-complement form with MSB first.
Figure 51. I²S 32-fS Format
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Programming (continued)
7.6.2.3 Left-Justified
Left-justified (LJ) timing uses LRCK to define when the data being transmitted is for the left channel and when
the data is for the right channel. LRCK is high for the left channel and low for the right channel. A bit clock
running at 32 × fS, 48 × fS, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at
the same time LRCK toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The
DAP masks unused trailing data bit positions.
2-Channel Left-Justified Stereo Input
32 Clks
32 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-02
NOTE: All data presented in two's-complement form with MSB first.
Figure 52. Left-Justified 64-fS Format
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Programming (continued)
2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks
24 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
21
LSB
17 16
9
8
5
4
13 12
5
4
1
0
9
1
0
1
0
MSB
LSB
21
17 16
9
8
5
4
19 18 17
13 12
5
4
1
0
15 14 13
9
1
0
23 22
1
0
20-Bit Mode
19 18 17
16-Bit Mode
15 14 13
8
8
T0092-02
NOTE: All data presented in two's-complement form with MSB first.
Figure 53. Left-Justified 48-fS Format
2-Channel Left-Justified Stereo Input
16 Clks
16 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
16-Bit Mode
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
0
MSB
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
0
T0266-02
NOTE: All data presented in two's-complement form with MSB first.
Figure 54. Left-Justified 32-fS Format
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Programming (continued)
7.6.2.4 Right-Justified
Right-justified (RJ) timing uses LRCK to define when the data being transmitted is for the left channel and when
the data is for the right channel. LRCK is high for the left channel and low for the right channel. A bit clock
running at 32 × fS, 48 × fS, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bitclock periods (for 24-bit data) after LRCK toggles. In RJ mode, the LSB of data is always clocked by the last bit
clock before LRCK transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP
masks unused leading data bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
32 Clks
32 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
MSB
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
20-Bit Mode
16-Bit Mode
T0034-03
All data presented in two's-complement form with MSB first.
Figure 55. Right-Justified 64-fS Format
34
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Programming (continued)
2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks
24 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
19 18
15 14
6
5
2
1
0
19 18
15 14
6
5
2
1
0
15 14
6
5
2
1
0
LSB
MSB
23 22
19 18
15 14
6
5
2
1
0
19 18
15 14
6
5
2
1
0
15 14
6
5
2
1
0
20-Bit Mode
16-Bit Mode
T0092-03
All data presented in two's-complement form with MSB first.
Figure 56. Right-Justified 48-fS Format
All data presented in two's-complement form with MSB first.
Figure 57. Right-Justified 32-fS Format
7.6.3 26-Bit 3.23 Number Format
All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23
numbers mean that the binary point has 3 bits to the left and 23 bits to the right. This is shown in Figure 58.
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Programming (continued)
2
–23
2
2
Bit
–5
Bit
–1
Bit
0
2 Bit
1
2 Bit
Sign Bit
S_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx
M0125-01
Figure 58. 3.23 Format
The decimal value of a 3.23 format number can be found by following the weighting shown in . If the most
significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct number. If
the most significant bit is a logic 1, then the number is a negative number. In the case every bit must be inverted,
a 1 added to the result, and then the weighting shown in Figure 59 applies to obtain the magnitude of the
negative number.
1
0
2 Bit
2 Bit
1
2
–1
Bit
0
(1 or 0) ´ 2 + (1 or 0) ´ 2 + (1 or 0) ´ 2
2
–1
–4
Bit
+ ....... (1 or 0) ´ 2
2
–4
–23
Bit
+ ....... (1 or 0) ´ 2
–23
M0126-01
Figure 59. Conversion Weighting Factors—3.23 Format to Floating Point
Gain coefficients, entered via the I²C bus, must be entered as 32-bit binary numbers. The format of the 32-bit
number (4-byte or 8-digit hexadecimal number) is shown in Figure 60.
Fraction
Digit 6
Sign
Bit
Fraction
Digit 1
Integer
Digit 1
Fraction
Digit 2
Fraction
Digit 3
Fraction
Digit 4
Fraction
Digit 5
u u u u
u u S x
x. x x x
x x x x
x x x x
x x x x
x x x x
x x x x 0
Coefficient
Digit 8
Coefficient
Digit 7
Coefficient
Digit 6
Coefficient
Digit 5
Coefficient
Digit 4
Coefficient
Digit 3
Coefficient
Digit 2
Coefficient
Digit 1
u = unused or don’t care bits
Digit = hexadecimal digit
M0127-01
Figure 60. Alignment of 3.23 Coefficient in 32-Bit I²C Word
36
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Table 4. Sample Calculation for 3.23 Format
db
Linear
Decimal
Hex (3.23 Format)
0
1
8,388,608
80 0000
5
1.77
14,917,288
00E3 9EA8
–5
0.56
4,717,260
0047 FACC
X
L = 10(X / 20)
D = 8,388,608 × L
H = dec2hex (D, 8)
Table 5. Sample Calculation for 9.17 Format
db
Linear
Decimal
0
1
131,072
2 0000
5
1.77
231,997
3 8A3D
–5
0.56
73,400
1 1EB8
D = 131,072 × L
H = dec2hex (D, 8)
X
(X / 20)
L = 10
Hex (9.17 Format)
7.7 Register Maps
7.7.1 Register Summary
SUBADDRESS
REGISTER NAME
NO. OF
BYTES
DEFAULT
VALUE
CONTENTS
A u indicates unused bits.
0x00
Clock control register
1
Description shown in subsequent section
0x6C
0x01
Device ID register
1
Description shown in subsequent section
0x41
0x02
Error status register
1
Description shown in subsequent section
0x00
0x03
System control register 1
1
Description shown in subsequent section
0xA0
0x04
Serial data interface register
1
Description shown in subsequent section
0x05
0x05
System control register 2
1
Description shown in subsequent section
0x40
0x06
Soft mute register
1
Description shown in subsequent section
0x00
0x07
Master volume
2
Description shown in subsequent section
0x03FF (mute)
0x08
Channel 1 vol
2
Description shown in subsequent section
0x00C0 (0 dB)
0x09
Channel 2 vol
2
Description shown in subsequent section
0x00C0 (0 dB)
0x0A
Channel 3 vol
2
Description shown in subsequent section
0x00C0 (0 dB)
0x0B
Reserved
2
Reserved (1)
0x03FF
0x0C
2
Reserved
(1)
0x00C0
0x0D
1
Reserved (1)
0xC0
0x0E
Volume configuration register
1
Description shown in subsequent section
0xF0
0x0F
Reserved
1
Reserved (1)
0x97
0x10
Modulation limit register
1
Description shown in subsequent section
0x01
0x11
IC delay channel 1
1
Description shown in subsequent section
0xAC
0x12
IC delay channel 2
1
Description shown in subsequent section
0x54
0x13
IC delay channel 3
1
Description shown in subsequent section
0xAC
0x14
IC delay channel 4
1
Description shown in subsequent section
0x54
0x15
Reserved
1
Reserved (1)
0xAC
0x16
0x54
0x17
(1)
0x00
0x18
PWM Start
0x0F
0x19
PWM Shutdown Group Register
1
Description shown in subsequent section
0x30
0x1A
Start/stop period register
1
Description shown in subsequent section
0x68
0x1B
Oscillator trim register
1
Description shown in subsequent section
0x82
Do not access reserved registers.
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Register Maps (continued)
SUBADDRESS
0x1C
REGISTER NAME
BKND_ERR register
0x1D–0x1F
1
CONTENTS
Description shown in subsequent section
(1)
DEFAULT
VALUE
0x57
1
Reserved
0x20
Input MUX register
4
Description shown in subsequent section
0x0001 7772
0x21
Reserved
4
Reserved (1)
0x00
0x0000 4303
0x22
4
0x0000 0000
0x23
4
0x0000 0000
0x24
4
0x0000 0000
0x25
PWM MUX register
4
Description shown in subsequent section
0x0102 1345
0x26
ch1_bq[0]
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
0x27
0x28
0x29
0x2A
0x2B
0x2C
38
NO. OF
BYTES
ch1_bq[1]
ch1_bq[2]
ch1_bq[3]
ch1_bq[4]
ch1_bq[5]
ch1_bq[6]
20
20
20
20
20
20
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Register Maps (continued)
SUBADDRESS
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
REGISTER NAME
ch1_bq[7]
ch1_bq[8]
ch1_bq[9]
ch2_bq[0]
ch2_bq[1]
ch2_bq[2]
ch2_bq[3]
ch2_bq[4]
ch2_bq[5]
NO. OF
BYTES
20
20
20
20
20
20
20
20
20
CONTENTS
DEFAULT
VALUE
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
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Register Maps (continued)
SUBADDRESS
0x36
0x37
0x38
0x39
REGISTER NAME
ch2_bq[6]
ch2_bq[7]
ch2_bq[8]
ch2_bq[9]
NO. OF
BYTES
20
20
20
20
CONTENTS
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
0x3A
Reserved
4
Reserved (1)
0x3B
AGL1 softening filter alpha
8
u[31:26], ae[25:0]
0x0008 0000
u[31:26], oe[25:0]
0x0078 0000
Description shown in subsequent section
0x0000 0100
Description shown in subsequent section
0xFFFF FF00
AGL1 softening filter omega
0x3C
AGL1 attack rate
AGL1 release rate
40
DEFAULT
VALUE
8
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0x0080 0000 0000
0000
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Register Maps (continued)
SUBADDRESS
REGISTER NAME
0x3D
0x3E
AGL2 softening filter alpha
NO. OF
BYTES
8
Reserved (1)
8
u[31:26], ae[25:0]
0x0008 0000
u[31:26], oe[25:0]
0x0078 0000
AGL2 softening filter omega
0x3F
AGL2 attack rate
DEFAULT
VALUE
CONTENTS
8
AGL2 release rate
u[31:26], at[25:0]
0x0008 0000
u[31:26], rt[25:0]
0xFFF8 0000
0x40
AGL1 attack threshold
4
T1[31:0] (9.23 format)
0x0800 0000
0x41
AGL3 attack threshold
4
T1[31:0] (9.23 format)
0x0074 0000
0x42
AGL3 attack rate
8
Description shown in subsequent section
0x0008 0000
Description shown in subsequent section
0xFFF8 0000
0x43
AGL3 release rate
AGL2 attack threshold
4
T2[31:0] (9.23 format)
0x0074 0000
0x44
AGL4 attack threshold
4
T1[31:0] (9.23 format)
0x0074 0000
0x45
AGL4 attack rate
8
0x0008 0000
AGL4 release rate
0xFFF8 0000
0x46
AGL control
4
Description shown in subsequent section
0x0002 0000
0x47
AGL3 softening filter alpha
8
u[31:26], ae[25:0]
0x0008 0000
u[31:26], oe[25:0]
0x0078 0000
u[31:26], ae[25:0]
0x0008 0000
u[31:26], oe[25:0]
0x0078 0000
AGL3 softening filter omega
0x48
AGL4 softening filter alpha
8
AGL4 softening filter omega
0x49
Reserved
4
Reserved
(1)
0x4A
4
0x1212 1010 E1FF
FFFF F95E 1212
0x4B
4
0x0000 296E
0x4C
4
0x0000 5395
0x4D
4
0x0000 0000
0x4E
4
0x0000 0000
0x4F
PWM switching rate control
4
u[31:4], src[3:0]
0x0000 0008
0x50
Bank switch control
4
Description shown in subsequent section
0x0F70 8000
0x51
Ch 1 output mixer
12
Ch 1 output mix1[2]
0x0080 0000
Ch 1 output mix1[1]
0x0000 0000
Ch 1 output mix1[0]
0x0000 0000
0x52
Ch 2 output mixer
12
Ch 2 output mix2[2]
0x0080 0000
Ch 2 output mix2[1]
0x0000 0000
Ch 2 output mix2[0]
0x0000 0000
0x53
16
Reserved (1)
0x0080 0000 0000
0000 0000 0000
0x54
16
Reserved (1)
0x0080 0000 0000
0000 0000 0000
0x56
Output post-scale
4
u[31:26], post[25:0]
0x0080 0000
0x57
Output pre-scale
4
u[31:26], pre[25:0] (9.17 format)
0x0002 0000
0x58
ch1_bq[10]
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
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Register Maps (continued)
SUBADDRESS
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
42
REGISTER NAME
ch1_cross_bq[0]
ch1_cross_bq[1]
ch1_cross_bq[2]
ch1_cross_bq[3]
ch2_bq[10]
ch2_cross_bq[0]
ch2_cross_bq[1]
ch2_cross_bq[2]
ch2_cross_bq[3]
IDF post scale
NO. OF
BYTES
20
20
20
20
20
20
20
20
20
4
CONTENTS
DEFAULT
VALUE
u[31:26], b0[25:0]
0x0080 0000
ch1_cross_bq[1]
0x0000 0000
ch1_cross_bq[2]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
Description shown in subsequent section
0x0000 0080
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Register Maps (continued)
SUBADDRESS
NO. OF
BYTES
REGISTER NAME
0x63–0x69
Reserved
4
0x6A
DEFAULT
VALUE
CONTENTS
Reserved (1)
0x0000 0000
0x007F 7CED
4
0x0000 8312
0x6B
Left channel PWM level meter
4
Data[31:0]
0x6C
Right channel PWM level meter
4
Data[31:0]
0x6D
Reserved
8
Reserved (1)
0x6E–0x6F
0x0000 0000
0x0000 0000 0000
0000
4
0x0000 0000
0x70
ch1 inline mixer
4
u[31:26], in_mix1[25:0]
0x0080 0000
0x71
inline_AGL_en_mixer_ch1
4
u[31:26], in_mixagl_1[25:0]
0x0000 0000
0x72
ch1 right_channel mixer
4
u[31:26], right_mix1[25:0]
0x0000 0000
0x73
ch1 left_channel_mixer
4
u[31:26], left_mix_1[25:0]
0x0080 0000
0x74
ch2 inline mixer
4
u[31:26], in_mix2[25:0]
0x0080 0000
0x75
inline_AGL_en_mixer_ch2
4
u[31:26], in_mixagl_2[25:0]
0x0000 0000
0x76
ch2 left_chanel mixer
4
u[31:26], left_mix1[25:0]
0x0000 0000
0x77
ch2 right_channel_mixer
4
u[31:26], right_mix_1[25:0]
0x0080 0000
0x78–0xF7
Reserved
(1)
0x0000 0000
0xF8
Update device address key
4
Dev Id Update Key[31:0] (Key =
0xF9A5A5A5)
0x0000 0054
0xF9
Update device address
4
u[31:8],New Dev Id[7:0] (New Dev Id = 0x54
for TAS5753MD)
0x0000 0054
4
Reserved (1)
0x0000 0000
0xFA–0xFF
All DAP coefficients are 3.23 format unless specified otherwise.
Registers 0x3B through 0x46 should be altered only during the initialization phase.
7.7.2 Detailed Register Descriptions
7.7.2.1 Clock Control Register (0x00)
The clocks and data rates are automatically determined by the TAS5753MD. The clock control register contains
the autodetected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency.
Table 6. Clock Control Register (0x00)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
–
–
–
–
–
fS = 32-kHz sample rate
0
0
1
–
–
–
–
–
Reserved
0
1
0
–
–
–
–
–
Reserved
0
1
1
–
–
–
–
–
fS = 44.1/48-kHz sample rate (1)
1
0
0
–
–
–
–
–
fS = 16-kHz sample rate
1
0
1
–
–
–
–
–
fS = 22.05/24-kHz sample rate
1
1
0
–
–
–
–
–
fS = 8-kHz sample rate
1
1
1
–
–
–
–
–
fS = 11.025/12-kHz sample rate
–
–
–
0
0
0
–
–
MCLK frequency = 64 × fS (2)
–
–
–
0
0
1
1
–
MCLK frequency = 128 × fS (2)
0
0
0
0
1
0
0
0
MCLK frequency = 192 × fS (3)
–
–
–
0
1
1
–
–
MCLK frequency = 256 × fS (1) (4)
(1)
(2)
(3)
(4)
FUNCTION
Default values are in bold.
Only available for 44.1-kHz and 48-kHz rates
Rate only available for 32/44.1/48-KHz sample rates
Not available at 8 kHz
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Product Folder Links: TAS5753MD
43
TAS5753MD
SLASEA5C – MARCH 2016 – REVISED MAY 2017
www.ti.com
Table 6. Clock Control Register (0x00) (continued)
D7
D6
D5
D4
D3
D2
D1
D0
–
–
–
1
0
0
–
–
MCLK frequency = 384 × fS
FUNCTION
–
–
–
1
0
1
–
–
MCLK frequency = 512 × fS
–
–
–
1
1
0
–
–
Reserved
–
–
–
1
1
1
–
–
Reserved
–
–
–
–
–
–
0
–
Reserved
–
–
–
–
–
–
–
0
Reserved
7.7.2.2 Device ID Register (0x01)
The device ID register contains the ID code for the firmware revision.
Table 7. General Status Register (0x01)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
(1)
FUNCTION
Identification code
(1)
Default values are in bold.
7.7.2.3 Error Status Register (0x02)
The error bits are sticky and are not cleared by the hardware. This means that the software must clear the
register (write zeroes) and then read them to determine if they are persistent errors.
Error definitions:
• MCLK error: MCLK frequency is changing. The number of MCLKs per LRCLK is changing.
• SCLK error: The number of SCLKs per LRCLK is changing.
• LRCLK error: LRCLK frequency is changing.
• Frame slip: LRCLK phase is drifting with respect to internal frame sync.
Table 8. Error Status Register (0x02)
D7
D6
D5
D4
D3
D2
D1
D0
1
-
–
–
–
–
–
–
MCLK error
–
1
–
–
–
–
–
–
PLL autolock error
–
–
1
–
–
–
–
–
SCLK error
–
–
–
1
–
–
–
–
LRCLK error
–
–
–
–
1
–
–
–
Frame slip
–
–
–
–
–
1
–
–
Clip indicator
–
–
–
–
–
–
1
–
Overcurrent, overtemperature, overvoltage, or undervoltage error
0
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
No errors
(1)
FUNCTION
(1)
Default values are in bold.
7.7.2.4 System Control Register 1 (0x03)
System control register 1 has several functions:
Bit D7:
If 0, the dc-blocking filter for each channel is disabled.
If 1, the dc-blocking filter (–3 dB cutoff
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