TB5R3LDR

TB5R3 www.ti.com SLLS643A – SEPTEMBER 2005 – REVISED OCTOBER 2007 QUAD DIFFERENTIAL PECL RECEIVERS FEATURES 1 • • • • • • • • • • Functional Replacement for the Agere BRF1A Pin Equivalent to General Trade 26LS32 High Input Impedance Approximately 8 kΩ 3 kV and CDM > 2 kV Operating Temperature Range: -40°C to 85°C Available in Gull-Wing SOIC (JEDEC MS-013, DW) and SOIC (D) Package APPLICATIONS • Digital Data or Clock Transmission Over Balanced Lines DESCRIPTION These quad differential receivers accept digital data over balanced transmission lines. They translate differential input logic levels to TTL output logic levels. The TB5R3 is a pin- and function-compatible replacement for the Agere systems BRF1A; it includes 3-kV HBM and 2-kV CDM ESD protection. The power-down loading characteristics of the receiver input circuit are approximately 8 kΩ relative to the power supplies; hence they do not load the transmission line when the circuit is powered down. The packaging for this differential line receiver is a 16-pin gull wing SOIC (DW) or a 16 pin SOIC (D). The enable inputs of this device include internal pull-up resistors of approximately 40 kΩ that are connected to VCC to ensure a logical high level input if the inputs are open circuited. FUNCTIONAL BLOCK DIAGRAM PIN ASSIGNMENTS AI SOIC PACKAGE (TOP VIEW) AO AI BI AI AI AO E1 BO BI BI GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC DI DI DO E2 CO CI CI BO BI C1 CO C1 D1 DO D1 E1 E2 Enable Truth Table E1 E2 OUTPUT CONDITION 0 0 Active 1 0 Active 0 1 Disabled 1 1 Active 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2007, Texas Instruments Incorporated TB5R3 www.ti.com SLLS643A – SEPTEMBER 2005 – REVISED OCTOBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PART MARKING PACKAGE (2) LEAD FINISH STATUS TB5R3DW TB5R3 Gull-Wing SOIC NiPdAu Production TB5R3D TB5R3 SOIC NiPdAu Production PART NUMBER (1) (2) (1) Add the R suffix for tape and reel carrier (i.e., TB5R3DR) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. POWER DISSIPATION RATINGS PACKAGE DW D (1) (2) (3) POWER RATING TA ≤ 25°C THERMAL RESISTANCE, JUNCTION-TO-AMBIENT WITH NO AIR FLOW Low-K (2) 831 mW High-K (3) 1240 mW Low-K (2) CIRCUIT BOARD MODEL High-K (3) DERATING FACTOR (1) TA ≥ 25°C POWER RATING TA = 85°C 120.3°C/W 8.3 mW/°C 332 mW 80.8°C/W 12.4 mW/°C 494 mW 763 mW 131.1°C/W 7.6 mW/°C 305 mW 1190 mW 84.1°C/W 11.9 mW/°C 475 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted with no air flow. In accordance with the low-K thermal metric definitions of EIA/JESD51-3. In accordance with the high-K thermal metric definitions of EIA/JESD51-7. THERMAL CHARACTERISTICS PARAMETER θJB Junction-to-Board Thermal Resistance θJC Junction-to-Case Thermal Resistance PACKAGE VALUE DW 53.7 D 47.5 DW 47.1 D 44.2 UNIT °C/W °C/W ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UNIT Supply voltage, VCC 0 V to 6 V Magnitude of differential bus (input) voltage, |VAI - VAI|, |VBI - VBI|, |VCI - VCI|, |VDI - VDI| ESD Human Body Model (2) Charged-Device Model (3) All pins ±3.5 kV All pins ±2 kV Continuous power dissipation See Dissipation Rating Table Storage temperature, Tstg (1) (2) (3) 2 8.4 V -65°C to 150°C Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. Submit Documentation Feedback Copyright © 2005–2007, Texas Instruments Incorporated Product Folder Link(s): TB5R3 TB5R3 www.ti.com SLLS643A – SEPTEMBER 2005 – REVISED OCTOBER 2007 RECOMMENDED OPERATING CONDITIONS Supply voltage, VCC Bus pin input voltage, VAI, VAI, VBIVBI, VCI , or VCI, VDI, VDI Magnitude of differential input voltage, |VAI - VAI|, |VBI - VBI|, |VCI - VCI|, |VDI - VDI| Low-level enable input voltage MIN NOM 4.5 5 5.5 V -1.2 (1) 7.2 V 0.1 6 V 0.8 V 85 °C (2) , VIL (VCC = 5.5 V) High-level enable input voltage (2), VIH (VCC = 5.5 V) 2 Operating free-air temperature, TA (1) (2) MAX UNIT V -40 The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet, unless otherwise noted. The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment. DEVICE ELECTRICAL CHARACTERISTICS over operating free-air temperature range unless otherwise noted PARAMETER Supply current (1) ICC (1) TEST CONDITIONS MIN TYP MAX UNIT Outputs disabled 50 mA Outputs enabled 48 mA Current is dc power draw as measured through GND pin and does not include power delivered to load. RECEIVER ELECTRICAL CHARACTERISTICS over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS VOL Output low voltage VCC = 4.5 V, IOL = 8 mA VOH Output high voltage VCC = 4.5 V, IOH = -400 µA MIN TYP MAX 0.4 2.4 UNIT V V VIK Enable input clamp voltage VCC = 4.5 V, VTH+ Positive-going differential input threshold voltage (2), (Vxl - VxI) x = A, B, C, or D 100 mV VTH- Negative-going differential input threshold voltage (2), (Vxl - VxI) x = A, B, C, or D 100 (1) mV VHYST Differential input threshold voltage hysteresis, (VTH+ - VTH–) IOZL VCC = 5.5 V IOS Output short circuit current VCC = 5.5 V IIL Enable input low current VCC = 5.5 V, IIH Enable input high current Enable input reverse current VCC = 5.5 V µA VO = 2.4 V 20 µA 400 (1) mA 400 (1) µA VIN = 2.7 V 20 µA VIN = 5.5 V 100 µA -2 (1) mA 1 mA VIN = 0.4 V VCC = 5.5V, VIN = -1.2 V IIH Differential input high current VCC= 5.5V, VIN = 7.2 V (1) (2) mV -20 (1) Differential input low current Small-signal output resistance V VO = 0.4 V IIL RO -1 50 Output off-state current, (High-Z) IOZH II = -5 mA (1) Output High 50 Output Low 25 Ω This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original Agere data sheet. The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment. Submit Documentation Feedback Copyright © 2005–2007, Texas Instruments Incorporated Product Folder Link(s): TB5R3 3 TB5R3 www.ti.com SLLS643A – SEPTEMBER 2005 – REVISED OCTOBER 2007 SWITCHING CHARACTERISTICS over operating free-air temperature range unless otherwise noted PARAMETER TEST CONDITIONS tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tPHZ Output disable time, high-level-to-high-impedance output (3) tskew1 Pulse-width distortion, |tPHL - tPLH| 1.57