TCA9511ADGKR

TCA9511A TCA9511A SCPS272C – OCTOBER 2019 – REVISED JANUARY 2021 SCPS272C – OCTOBER 2019 – REVISED JANUARY 2021 www.ti.com TCA9511A Hot Swappable I2C Bus and SMBus Buffer 1 Features • • • • • • • Supports bidirectional data transfer of bus signals Operating power-supply voltage range of 2.3 V to 5.5 V TA ambient air temperature range of -40 °C to 125 °C 1-V Precharge on all SDA and SCL lines prevents corruption during live insertion Accommodates standard mode and fast mode I2C devices Supports clock stretching, arbitration and synchronization Powered-off high-impedance I2C pins 2 Applications • • • • • 3 Description I2C Servers Enterprise Switching Telecom switching equipment Base stations Industrial automation equipment The TCA9511A is a hot-swappable I2C bus buffer that supports I/O card insertion into a live backplane without corruption of the data and clock lines. Control circuitry prevents the backplane-side I2C lines (in) from being connected to the card-side I2C lines (out) until a stop command or bus idle condition occurs on the backplane without bus contention on the card. When the connection is made, this device provides bidirectional buffering, keeping the backplane and card capacitances isolated. During insertion, the SDA and SCL lines are pre-charged to 1 V to minimize the current required to charge the parasitic capacitance of the device. When the I2C bus is idle, the TCA9511A can be put into shutdown mode by setting the EN pin low, reducing power consumption. When EN is pulled high, the TCA9511A resumes normal operation. It also includes an open drain READY output pin, which indicates that the backplane and card sides are connected together. When READY is high, the SDAIN and SCLIN are connected to SDAOUT and SCLOUT. When the two sides are disconnected, READY is low. Device Information PART NUMBER TCA9511A (1) PACKAGE(1) VSSOP (8) BODY SIZE (NOM) 3.00 mm × 3.00 mm For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic An©IMPORTANT NOTICEIncorporated at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyright 2021 Texas Instruments Submit Document Feedback intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: TCA9511A 1 TCA9511A www.ti.com SCPS272C – OCTOBER 2019 – REVISED JANUARY 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings ....................................... 4 6.2 ESD Ratings .............................................................. 4 6.3 Recommended Operating Conditions ........................4 6.4 Thermal Information ...................................................4 6.5 Electrical Characteristics ............................................5 6.6 Timing Requirements ................................................. 5 6.7 Switching Characteristics ...........................................6 6.8 Typical Characteristics................................................ 7 7 Parameter Measurement Information............................ 8 8 Detailed Description........................................................9 8.1 Overview..................................................................... 9 8.2 Functional Block Diagram........................................... 9 8.3 Feature Description...................................................10 8.4 Device Functional Modes..........................................10 9 Application Information Disclaimer............................. 12 9.1 Application Information............................................. 12 9.2 Typical Application.................................................... 12 9.3 Typical Application on a Backplane.......................... 15 10 Power Supply Recommendations..............................16 10.1 Power Supply Best Practices..................................16 10.2 Power-on Reset Requirements...............................16 11 Layout........................................................................... 17 11.1 Layout Guidelines................................................... 17 11.2 Layout Example...................................................... 18 12 Device and Documentation Support..........................19 12.1 Receiving Notification of Documentation Updates..19 12.2 Support Resources................................................. 19 12.3 Trademarks............................................................. 19 12.4 Electrostatic Discharge Caution..............................19 12.5 Glossary..................................................................19 13 Mechanical, Packaging, and Orderable Information.................................................................... 19 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (March 2020) to Revision C (January 2021) Page • Deleted the Device Comparision Table ..............................................................................................................3 • Changed the VCC pin recommended capacitance From: 0.01 μF To: 0.1 μF to match typical application section................................................................................................................................................................ 3 • Changed HBM ESD from 1500 V to 3500 V.......................................................................................................4 • Changed ICC values from 6 mA max to 4.5 mA, and typical improved to 2.5 mA............................................ 5 • Changed VOS typical from 50 mV to 60 mV.......................................................................................................5 Changes from Revision A (December 2019) to Revision B (March 2020) Page • Changed pin 7 From: SDAOUTL To: SDAOUT.................................................................................................. 3 • Changed text From: "pulled to roughly 160 mV." To: "pulled to roughly 150 mV" in the Bus active section..... 11 • Changed the device number of Figure 11-1 to TCA9511A .............................................................................. 18 Changes from Revision * (October 2019) to Revision A (December 2019) Page • Changed the device status From: Advanced Information To: Production data ..................................................1 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TCA9511A TCA9511A www.ti.com SCPS272C – OCTOBER 2019 – REVISED JANUARY 2021 5 Pin Configuration and Functions EN 1 8 VCC SCLOUT 2 7 SDAOUT SCLIN 3 6 SDAIN GND 4 5 RE ADY No t to scale Figure 5-1. 8-Pin VSSOP, DGK Package (Top View) Table 5-1. Pin Functions PIN NAME NO. I/O DESCRIPTION Active-high chip enable pin. If EN is low, the TCA9511A is in a low current mode. It also disables the rise-time accelerators, disables the bus pre-charge circuitry, drives READY low, isolates SDAIN from SDAOUT and isolates SCLIN from SCLOUT. EN should be high (at VCC) for normal operation. Connect EN to VCC if this feature is not being used. EN 1 I SCLOUT 2 I/O Serial clock output. Connect this pin to the SCL bus on the card. SCLIN 3 I/O Serial clock input. Connect this pin to the SCL bus on the backplane. GND 4 - Supply ground READY 5 O Connection flag/rise-time accelerator control. Ready is low when either EN is low or the start-up sequence has not been completed. READY goes high when EN is high and start-up is complete. Connect a 10-kΩ resistor from this pin to VCC to provide the pull-up current. SDAIN 6 I/O Serial data input. Connect this pin to the SDA bus on the backplane. SDAOUT 7 I/O Serial data output. Connect this pin to the SDA bus on the card. VCC 8 - Supply Power. Main input power supply from backplane. This is the supply voltage for the devices on the backplane I2C buses. Connect pull-up resistors from SDAIN and SCLIN (and also from SDAOUT and SCLOUT) to this supply. It is recommended to place a bypass capacitor of 0.1 μF close to this pin for best results. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TCA9511A 3 TCA9511A www.ti.com SCPS272C – OCTOBER 2019 – REVISED JANUARY 2021 6 Specifications 6.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC –0.5 7 V Input Voltage SDAIN, SCLIN, SDAOUT, SCLOUT –0.5 7 V IIK Input clamp current IOK EN, READY –0.5 7 V VI < 0 –50 mA Output clamp current VO < 0 –50 mA IO Continuous output current SDAIN, SDAOUT, SCLIN, SCLOUT, EN, READY ±50 mA ICC Continuous current through VCC or GND ±100 mA TJ Maximum junction temperature 130 °C Tstg Storage temperature 150 °C (1) –65 Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/ JEDEC JS-001, all pins(1) ±3500 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process 6.3 Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted) MIN MAX 2.3 5.5 EN input 0 5.5 SDAIN, SCLIN, SDAOUT, SCLOUT 0 5.5 VCC Supply voltage VI Input voltage range VIO Input/output voltage range VO Output voltage range READY TA Ambient temperature 0 5.5 –40 125 UNIT V °C 6.4 Thermal Information TCA9511 THERMAL METRIC(1) DGK UNIT 8 Pin RθJA Junction-to-ambient thermal resistance 177.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 64.5 °C/W RθJB Junction-to-board thermal resistance 99.6 °C/W ΨJT Junction-to-top characterization parameter 9.5 °C/W ΨJB Junction-to-board characterization parameter 97.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TCA9511A TCA9511A www.ti.com SCPS272C – OCTOBER 2019 – REVISED JANUARY 2021 6.5 Electrical Characteristics Over operating free-air temperature range (unless otherwise noted). Typical specifications are at TA = 25 °C, VCC = 3.3 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.5 4.5 mA 5 30 µA POWER SUPPLY VCC = 5.5V SDAIN, SCLIN = 0V SDAOUT, SCLOUT = 10k RPU ICC Supply current ISD EN = 0 V SDAIN, SCLIN, SDAOUT, SCLOUT = 0V Supply current in shutdown mode through or VCC the VCC pin(1) READY pin = Hi-Z EN pulled low after bus connection event (disable precharge) UVLO Under voltage lockout (rising) Under voltage lockout (falling) EN = VCC READY = 10 kΩ to VCC 2.1 V 2 V START-UP CIRCUITRY VPRE Pre-charge voltage SDA, SCL = Hi-Z 0.8 1 2 5 1.2 V RISE-TIME ACCELERATORS RTA pull-up current(2) IPU Position transition on SDA, SCL VSDA/SCL = 0.6 V, Slew rate = 1.25 V/µs. VCC = 3.3 V mA INPUT-OUTPUT CONNECTION ILI Input pin leakage SDA/SCL pins = 90% VCC, EN = VCC, GND SDA/SCL pins = 10% VCC, EN = GND VOS Input-output offset voltage (SCLIN to SCLOUT, SCLOUT to SCLIN and SDAIN to SDAOUT, SDAOUT to SDAIN RPU for SDA/SCL = 10 kΩ II_RDY Ready pin leakage EN = VCC, READY = VCC, Bus connected -1 1 µA 100 mV -1 1 µA 60 DIGITAL IO THRESHOLD VIH High-level input voltage EN 0.7 × VCC VCC VIL Low-level input voltage EN 0 0.3 × VCC Low-level output voltage SDAIN, SCLIN, SDAOUT, SCLOUT IOL = 4 mA VIN = 0.1 V VOL READY IOL = 3 mA V 0.15 0 0.4 0.4 DYNAMIC CHARACTERISTICS CIN (EN) EN input capacitance VEN = 0 V or VCC f = 400 kHz CIO READY output capacitance SDA/SCL pin capacitance (READY) CIO (SDA/ SCL) (1) (2) 1.6 4 VREADY = 0 V or VCC f = 400 kHz 7 10 VPIN = 0 V or VCC f = 400 kHz 5 10 pF In shutdown mode there will also be current flowing from VCC through the ready pin as this pin is pulled down to indicate the bus is disconnected. Determined by design, not tested in production. 6.6 Timing Requirements MIN fSCL_MAX Maximum SCL clock frequency 400 NOM MAX UNIT kHz Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TCA9511A 5 TCA9511A www.ti.com SCPS272C – OCTOBER 2019 – REVISED JANUARY 2021 6.6 Timing Requirements (continued) MIN tBUF (1) MAX UNIT 1.3 µs tHD;STA (1) Hold time for a repeated START condition 0.6 µs tSU;STA (1) Set-up time for a repeated START condition 0.6 µs tSU;STO (1) Set-up time for a STOP condition 0.6 µs tHD;DAT Bus free time between a STOP and START condition NOM (1) Data hold time tSU;DAT (1) Data set-up time 0 ns 100 ns (1) LOW period of the SCL clock 1.3 µs tHIGH (1) HIGH period of the SCL clock 0.6 µs tf (1) Fall time of both SDA and SCL signals 20 × (VCC/5.5 V) 300 ns tr (1) Rise time of both SDA and SCL signals 20 × (VCC/5.5 V) 300 ns tLOW (1) These are system-level timing specs and are dependent upon bus capacitance and pull up resistor value. It is up to the system designer to ensure they are met 6.7 Switching Characteristics Over operating free-air temperature range (unless otherwise noted). Typical specifications are at TA = 25 °C, VCC = 3.3 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT START-UP CIRCUITRY tPRECHAR Time from VCC to precharge enabled SDA,SCL = Hi-Z EN = VCC, GND 15 60 µs tEN Time from VPOR to digital being ready VCC transition from 0V to VCC Time from VPORR to earliest stop bit recongized 35 95 µs tIDLE Bus idle time to READY active SDA,SCL = 10 kΩ to VCC EN = VCC Measured at 0.5 × VCC 95 150 µs tDISABLE Time from EN high to low to READY low SDA,SCL = 10 kΩ to VCC READY = 10 kΩ to VCC Measured at 0.5 × VCC 30 200 ns tSTOP SDAIN to READY delay after stop condition SDA,SCL = 10 kΩ to VCC READY = 10 kΩ to VCC Measured at 0.5 × VCC 1.2 2 µs tREADY SCLOUT/SDAOUT to READY SDA,SCL = 10 kΩ to VCC READY = 10 kΩ to VCC Measured at 0.5 × VCC 0.8 1.5 µs GE INPUT-OUTPUT CONNECTION 6 tPLZ Low to high propagation delay RPU for SDA/SCL = 10 kΩ CL = 100 pF per pin Measured at 0.5 × VCC 0 10 ns tPZL High to low propagation delay RPU for SDA/SCL = 10 kΩ CL = 100 pF per pin Measured at 0.5 × VCC 70 150 ns Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TCA9511A TCA9511A www.ti.com SCPS272C – OCTOBER 2019 – REVISED JANUARY 2021 6.8 Typical Characteristics 4 4 2.3 V 2.5 V 3.3 V 5V 5.5 V 3.5 3.5 3 ICC (mA) ICC (mA) 3 2.5 2.5 2 2 1.5 1.5 1 -40 -40 °C 25 °C 85 °C 125 °C 1 -15 10 35 60 Temperature (°C) 85 110 130 2 2.5 Figure 6-1. ICC vs Temperature 5 5.5 150 125 125 100 100 75 75 50 50 25 25 1 -40 C 25 C 85 C 105 C 125 C 175 VO - VI (mV) VO-VI (mV) 4.5 200 -40 C 25 C 85 C 105 C 125 C 150 0 0.5 3.5 4 VCC (V) Figure 6-2. ICC vs VCC 200 175 3 1.5 2 2.5 IOL (mA) 3 3.5 0 0.5 4 Figure 6-3. VOS vs IOL (VCC = 2.3 V, VI = 0 V) 1 1.5 2 2.5 IOL (mA) 3 3.5 4 Figure 6-4. VOS vs IOL (VCC = 3.3 V, VI = 0 V) 200 175 -40 C 25 C 85 C 105 C 125 C 150 VO - VI (mV) 125 100 75 50 25 0 0.5 1 1.5 2 2.5 IOL (mA) 3 3.5 4 Figure 6-5. VOS vs IOL (VCC = 5.5 V, VI = 0 V) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TCA9511A 7 TCA9511A www.ti.com SCPS272C – OCTOBER 2019 – REVISED JANUARY 2021 7 Parameter Measurement Information SDAn/SCLn tEN ENABLE tIDLE(READY) tDIS READY Figure 7-1. Timing for tEN, tIDLE(READY), and tDIS SDAIN SCLIN SCLOUT SDAOUT tEN ENABLE tSTOP READY Figure 7-2. Timing for tSTOP 8 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TCA9511A TCA9511A www.ti.com SCPS272C – OCTOBER 2019 – REVISED JANUARY 2021 8 Detailed Description 8.1 Overview The TCA9511A is a hot-swappable I2C bus buffer that supports I/O card insertion into a live backplane without corruption of the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle condition occurs on the backplane without bus contention on the card. When the connection is made, this device provides bidirectional buffering, keeping the backplane and card capacitances isolated. During insertion, the SDA and SCL lines are pre-charged to 1 V to minimize the current required to charge the parasitic capacitance of the device. When the I2C bus is idle, the TCA9511A is put into shutdown mode by setting the EN pin low. When EN is high, the TCA9511A resumes normal operation. It also includes an open drain READY output pin, which indicates that the backplane and card sides are connected together. When READY is high, the SDAIN and SCLIN are connected to SDAOUT and SCLOUT. When the two sides are disconnected, READY is low. 8.2 Functional Block Diagram Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TCA9511A 9 TCA9511A www.ti.com SCPS272C – OCTOBER 2019 – REVISED JANUARY 2021 8.3 Feature Description 8.3.1 Hot bus insertion During a hot bus insertion event, the TCA9511A keeps the buses disconnected to ensure that no data corruption occurs on either bus. Once the buses are idle or a stop bit on the IN side is detected, the TCA9511A connects the buses and READY goes high. 8.3.2 Pre-charge voltage Both the SDA and SCL pins feature a 1-V pre-charge circuit through an internal 100 kΩ resistor prior to the pins being connected to an I2C bus. This feature helps minimize disruptions as a result of a hot bus insertion event. 8.3.3 Rise time accelerators The TCA9511A features a rise time accelerator (RTA) on all I2C pins that during a positive bus transition, switches on a current source to quickly slew the bus pins high. This allows the use of weaker pull-up resistors, which can lower VOLs and lower power system level power consumption. 8.3.4 Bus ready output indicator The READY pin is an open drain output that provides an indicator to whether the buses are connected and ready for traffic. This pin is pulled low when the connection between IN/OUT is high impedance. Once the bus is idle or a stop condition on the IN side is detected, and the connection between IN/OUT is made, the READY pin is released and pulled high by an external pull-up resistor, signaling that it is ready for traffic. 8.3.5 Powered-off high impedance for I2C and I/O pins When the supply voltage is below the UVLO threshold, the I2C and digital I/O pins are a high impedance state to prevent leakage currents from flowing through the device. When the EN pin is taken low, the device enters an isolation state, presenting a high impedance on all bus pins and pulling the READY pin low. 8.3.6 Supports clock stretching and arbitration The TCA9511A supports full clock stretching, and arbitration without lock up. 8.4 Device Functional Modes 8.4.1 Start-up and precharge When the TCA9511A first receives power on the VCC pin, either during power-up or during live insertion, it starts in an under voltage lockout (UVLO) state, ignoring any activity on the SDA and SCL pins until VCC rises above UVLO. Once the ENABLE pin goes high, the ‘Stop Bit and Bus Idle’ detect circuit is enabled and the device enters the bus idle state. When VCC rises above UVLO, the precharge circuitry will activate, which biases the bus pins on both sides to about 1 V through an internal 100 kΩ resistor. 8.4.2 Bus idle After the Stop Bit and Bus Idle detect circuits are enabled the device enters the bus idle state. The pre-charge circuitry becomes active and forces 1 V through 100 kΩ nominal resistors to the SCL and SDA pins. The precharge circuitry minimizes the voltage differential seen by the SCL/SDA pins during a hot insertion event. This minimizes the amount of disturbance seen by the I/O card. The device waits for the SDAIN and SCLIN pins to be high for the bus idle time or a STOP condition to be observed on the IN pins. The SDAOUT and SCLOUT pins must be high and the SDAIN and SCLIN pins must meet 1 of the 2 qualifiers (idle timer or a STOP condition) before connecting SDAIN to SDAOUT and SCLIN to SCLOUT. Once the bus connections have been made, the pre-charge circuitry is disabled and the device enters the bus active state. 10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TCA9511A TCA9511A www.ti.com SCPS272C – OCTOBER 2019 – REVISED JANUARY 2021 8.4.3 Bus active In the bus active mode, the I2C IN and OUT pins are connected, and the input is passed bi-directionally from IN/OUT side of the bus to the OUT/IN side respectively. The buses remain connected until the EN pin is taken low. When the bus is connected, the driven-low side of the device is reflected on the opposite side, but with a small offset voltage. For example, if the input is pulled low to 100 mV, the output side will be pulled to roughly 150 mV. This offset allows the device to determine which side is currently being driven and avoid getting stuck low. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TCA9511A 11 TCA9511A www.ti.com SCPS272C – OCTOBER 2019 – REVISED JANUARY 2021 9 Application Information Disclaimer Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The typical application is to place the TCA9511A on the card that is being inserted or connected to a live bus, rather than being placed on the live bus. The reason for this is to provide maximum benefit by ensuring that the bus stays disconnected until an idle condition or stop condition is seen. 9.2 Typical Application VCC 3.3 V C1 0.1 µF R1 10 k R2 10 k R3 10 k R4 10 k 8 VCC R5 10 k R6 10 k SCLIN 3 2 SCLOUT SDAIN 6 7 SDAOUT 1 5 ENABLE READY GND C2 0.1 µF 4 Figure 9-1. General Application Schematic 9.2.1 Design Requirements 9.2.1.1 Series connections It is possible to have multiple buffers in series, but care must be taken when designing a system. 2-wire system 1 2-wire system 2 VCC = 5 V VCC R4 10 k R4 10 k C1 0.01 µF SDA1 SCL1 To other system 1 devices C1 0.1 µF R4 10 k EN VCC R4 10 k R4 R4 5.1 k 5.1 k C1 0.1 µF R4 10 k VCC R4 10 k SDAOUT SDAOUT SDAIN SCLOUT SCLOUT SDAIN SCLIN READY READY SCLIN GND GND Long distance bus EN R4 10 k R4 10 k C1 0.01 µF SDA1 SCL1 To other system 2 devices Figure 9-2. Series Buffer Connections 12 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TCA9511A TCA9511A www.ti.com SCPS272C – OCTOBER 2019 – REVISED JANUARY 2021 Each buffer adds approximately 60 mV of offset. Maximum offset (VOFFSET) should be considered. The low level at the signal origination end is dependent upon bus load. The I2C-bus specification requires that a 3 mA current produces no larger than a 0.4 V VOL. As an example, if the VOL at the master is 0.1 V, and there are 4 buffers in series (each adding about 60 mV), then the VOL at the farthest buffer is approximately 0.34 V. This device has a rise time accelerator (RTA) that activates at 0.6 V. With great care, a system with 4 buffers may work, but as the VOL moves up, it may be possible to trigger the RTA, creating a false edge on the clock. It is recommended to limit the number of buffers in series to two, and to keep the load light to minimize the offset. Another special consideration of series connections is the effect on round-trip-delay. This is the sum of propagation delays through the buffers and any effects on rise time. It is possible that fast mode speeds (400 kHz) are not possible due to delays and bus loading. 9.2.1.2 Multiple connections to a common node It is possible to have multiple buffers in connect to a common node, but care must be taken when designing a system. Buffer A Buffer B Master Slave B Common node Buffer C Slave C Figure 9-3. Connections to Common Node It is important to try and avoid common node architectures. The multiple nodes sharing a common node can create glitches if the output voltage from a master slave device plus the offset voltage of the buffer are high enough to trip the RTA. Also keep in mind that the VOS must be crossed in order for a device to begin to regulate the other side. Consider a system with three buffers connected to a common node and communication between the Master and Slave B that are connected at either end of buffer A and buffer B in series as shown in Figure 9-3. Consider if the VOL at the input of buffer A is 0.3 V and the VOL of Slave B (when acknowledging) is 0.36 V with the direction changing from Master to Slave B and then from Slave B to Master. Before the direction change the user should observe VIL at the input of buffer A of 0.3 V and its output, the common node, is ~0.36 V. The output of buffer B and buffer C would be ~0.42 V, but Slave B is driving 0.4 V, so the voltage at Slave B is 0.4 V. The output of buffer C is ~0.52 V. When the Master pull-down turns off, the input of buffer A rises and so does its output, the common node, because it is the only part driving the node. The common node rises to ~0.5 V before the buffer B output turns on, if the pull-up is strong the node may bounce. If the bounce goes above the threshold for the rising edge accelerator ~0.6 V, the accelerators on both buffer A and buffer C will fire, contending with the output of buffer B. The node on the input of buffer A goes high as will the input node of buffer C. After the common node voltage is stable for a while, the rising edge accelerators turn off, and the common node returns to ~0.5 V because the buffer B is still on. The voltage at both the Master and Slave C nodes then fall to ~0.6 V until Slave B turned off. This does not cause a failure on the data line as long as the return to 0.5 V on the common node (~0.56 V at the Master and Slave C) occurred before the data setup time. If this were the SCL line, the parts on buffer A and buffer C would see a false clock rather than a stretched clock, which causes a system error. 9.2.1.3 Propagation delays The delay for a rising edge is determined by the combined pull-up current from the bus resistors and the rise time accelerator current source and the effective capacitance on the lines. If the pull-up currents are the same, Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TCA9511A 13 TCA9511A www.ti.com SCPS272C – OCTOBER 2019 – REVISED JANUARY 2021 any difference in rise time is directly proportional to the difference in capacitance between the two sides. The tPLH may be negative if the output capacitance is less than the input capacitance and would be positive if the output capacitance is larger than the input capacitance, when the currents are the same. The tPHL can never be negative because the output does not start to fall until the input is below 0.7 × VCC, the output turn on has a non-zero delay, and the output has a limited maximum slew rate. Even if the input slew rate is slow enough that the output catches up, it would still lag the falling voltage of the input by the offset voltage. The maximum tPHL occurs when the input is driven low with a very fast slew rate and the output is still limited by its turn-on delay and the falling edge slew rate. 9.2.2 Detailed Design Procedure The system pull-up resistors must be strong enough to provide a positive slew rate of 1.25 V/µs on the SDA and SCL pins, in order to activate the boost pull-up currents during rising edges. Choose maximum resistor value using the formula given in Equation 1. VCC (MIN ) F 0.6 R Q 800 × 103 l p C (1) where R is the pull-up resistor value in Ω, VCC(MIN) is the minimum VCC voltage in volts, and C is the equivalent bus capacitance in picofarads (pF). In addition, regardless of the bus capacitance, always choose RPU ≤ 65.7 kΩ for VCC = 5.5 V, RPU ≤ 45 kΩ for VCC = 3.3 V, and RPU ≤ 33 kΩ for VCC = 2.5 V. The start-up circuitry requires logic HIGH voltages on SDAOUT and SCLOUT to connect the backplane to the card, and these pull-up values are needed to overcome the precharge voltage. 9.2.3 Application Curves 70 50 RPU (k ) RPU (k ) RMAX = 45 k RMAX = 65.7 k 60 40 50 30 Rise time = 300 ns(2) 40 20 Rise time = 20 ns Rise time = 300 ns(2) 30 10 RMIN = 1 k 20 0 0 100 200 300 400 Cb (pF) Rise time = 20 ns 10 Test RMIN = 1.7 k Test 0 Test 0 100 200 300 400 Cb (pF) Figure 9-4. Example Bus Requirements for 3.3 V Systems 14 Figure 9-5. Example Bus Requirements for 5 V Systems Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TCA9511A TCA9511A www.ti.com SCPS272C – OCTOBER 2019 – REVISED JANUARY 2021 9.3 Typical Application on a Backplane As shown in Figure 9-6, the TCA9511A is used in a backplane connection. The TCA9511A is placed on the I/O peripheral card and connects the I2C devices on the card to the backplane safely upon a hot insertion event. Note that if the I/O cards were plugged directly into the backplane, all of the backplane and card capacitances would add directly together, making rise time and fall time requirements difficult to meet. Placing a bus buffer on the edge of each card; however, isolates the card capacitance from the backplane. For a given I/O card, the TCA9511A drives the capacitance of everything on the card and the backplane must drive only the capacitance of the bus buffer, which is less than 10 pF, the connector, trace, and all additional cards on the backplane. Backplane Backplane Connector Power Supply Hot Swap R1 10 k R2 10 k BD_SEL SDA SCL Staggered Connector VCC I/O Peripheral Card 1 Staggered Connector Staggered Connector R5 10 k R6 10 k SDAOUT CARD1_SDA SDAIN TCA9511 SCLOUT CARD1_SCL SCLIN GND READY I/O Peripheral Card 2 C3 0.1 µF R7 10 k R8 10 k R9 10 k R10 10 k VCC SDAOUT CARD2_SDA SDAIN TCA9511 SCLOUT CARD2_SCL SCLIN GND READY EN Power Supply Hot Swap R4 10 k VCC EN Power Supply Hot Swap C1 0.1 µF R3 10 k I/O Peripheral Card N C5 0.1 µF R11 10 k R12 10 k R13 10 k R14 10 k VCC SDAOUT CARDN_SDA SDAIN TCA9511 SCLOUT CARDN_SCL SCLIN GND READY EN Figure 9-6. Backplane Application Schematic 9.3.1 Design Requirements There are a few considerations when using these hot swap buffers. It is NOT recommended to place the TCA9511A on the backplane connector as it cannot isolate the cards from one another which will possibly result in disturbing on-going I2C transactions. Instead, place the TCA9511A on the I/O peripheral card to maximize benefit. 9.3.2 Detailed Design Procedure The design procedure is the same as outlined in Section 9.2.2. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TCA9511A 15 TCA9511A www.ti.com SCPS272C – OCTOBER 2019 – REVISED JANUARY 2021 10 Power Supply Recommendations 10.1 Power Supply Best Practices In order for the pre-charge circuitry to dampen the effect of hot-swap insertion of the TCA9511A into an active I2C bus, VCC must be applied before the SCL and SDA pins make contact to the main I2C bus. This is essential when the TCA9511A is placed on the add-on card circuit board, as in Section 9.3. Although the pre-charge circuitry exists on both the -IN and -OUT side, the example in Section 9.3 shows SCLIN and SDAIN connecting to the main bus. The supply voltage to VCC can be applied early by ensuring that the VCC and GND pin contacts are physically longer than the contacts for the SCLIN and SDAIN pins. If a voltage supervisor will also be used to control the voltage supply on the add-on card, additional delay will exist before the 1 V pre-charge voltage is present on the SCL and SDA pins. 10.2 Power-on Reset Requirements In order to ensure that the part starts up in the correct state, it is recommended that the power supply ramp rates meet the below requirements. Table 10-1. Recommended supply ramp rates 16 Parameter MIN MAX UNIT tRT Rise rate 0.1 1000 ms tFT Fall rate 0.1 1000 ms Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TCA9511A TCA9511A www.ti.com SCPS272C – OCTOBER 2019 – REVISED JANUARY 2021 11 Layout 11.1 Layout Guidelines For printed circuit board (PCB) layout of the TCA9511A, common PCB layout practices should be followed but additional concerns related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C signal speeds. In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller capacitor to filter out high frequency ripple. These capacitors should be placed as close to the TCA9511A as possible. These best practices are shown in Section 11.2. The layout example provided in Section 11.2 shows a 4 layer board, which is preferable for boards with higher density signal routing. On a 4 layer PCB, it is common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other internal layer to a power plane. In a board layout using planes or split planes for power and ground, vias are placed directly next to the surface mount component pad which needs to attach to VCC or GND and the via is connected electrically to the internal layer or the other side of the board. Vias are also used when a signal trace needs to be routed to the opposite side of the board, shown in the Section 11.2 for the VCC side of the resistor connected to the EN pin; however, this routing and via is not necessary if VCC and GND are both full planes as opposed to the partial planes depicted. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TCA9511A 17 TCA9511A www.ti.com SCPS272C – OCTOBER 2019 – REVISED JANUARY 2021 11.2 Layout Example D By-pass/De-coupling capacitors 1 EN 2 SCLOUT 3 SCLIN 4 GND TCA9511A VIA to Power Plane VIA to GND Plane VIA to opposite layer G N Power or GND Plane V LEGEND CC To add-on card VCC 8 SDAOUT 7 SDAIN 6 READY 5 To backplane (main I2C bus) Figure 11-1. Layout example for TCA9511A 18 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TCA9511A TCA9511A www.ti.com SCPS272C – OCTOBER 2019 – REVISED JANUARY 2021 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TCA9511A 19 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TCA9511ADGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 9511A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of