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THS4531
SLOS358C – SEPTEMBER 2011 – REVISED APRIL 2020
Ultra Low Power, Rail-to-Rail Output, Fully-Differential Amplifier
1 Features
3 Description
•
The THS4531 is a low-power, fully-differential op amp
with input common-mode range below the negative
rail and rail-to-rail output. The device is designed for
low-power data acquisition systems and high density
applications where power consumption and
dissipation is critical.
1
•
•
•
•
•
•
•
•
•
Ultra Low Power:
– Voltage: 2.5 V to 5.5 V
– Current: 250 µA
– Power-Down Mode: 0.5 µA (typical)
Fully-Differential Architecture
Bandwidth: 36 MHz
Slew Rate: 200 V/µs
THD: –120 dBc at 1 kHz (1 VRMS, RL= 2 kΩ)
Input Voltage Noise: 10 nV/√Hz (f = 1 kHz)
High DC Accuracy:
– VOS Drift: ±4 µV/˚C (–40°C to +125°C)
– AOL: 114 dB
Rail-to-Rail Output (RRO)
Negative Rail Input (NRI)
Output Common-Mode Control
The device features accurate output common-mode
control that allows for dc coupling when driving
analog-to-digital converters (ADCs). This control,
coupled with the input common-mode range below
the negative rail and rail-to-rail output, allows for easy
interface from single-ended ground-referenced signal
sources to successive-approximation registers
(SARs), and delta-sigma (ΔΣ) ADCs using only
single-supply 2.5 V to 5 V power. The THS4531 is
also a valuable tool for general-purpose, low-power
differential signal conditioning applications.
The THS4531 is characterized for operation over the
extended industrial temperature range from –40°C to
+125°C. The following package options are available:
2 Applications
•
•
•
•
•
Low-Power SAR, ΔΣ ADC Driver
Low Power, High Performance:
– Differential to Differential Amplifier
– Single-Ended to Differential Amplifier
Low-Power, Wide-Bandwidth Differential Driver
Low-Power, Wide-Bandwidth Differential Signal
Conditioning
High Channel Count and Power Dense Systems
Magnitude (dBV)
Figure 1. 1 kHz FFT Plot on Audio Analyzer
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
VS = 5 V
G = 1 V/V
VOUT = 1 VRMS
RF = 2 kΩ
RL = 600 Ω
0
5k
10k
15k
Frequency (Hz)
20k
Device Information(1)
DEVICE NUMBER
THS4531
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
WQFN (10)
2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Table 1. Device Comparison
DEVICE
BW
(MHz)
IQ (mA)
THS4521
145
1.14
THS4121
100
THS4131
150
THS4561
THD
VN
(dBc) at
(nV/√Hz)
100 kHz
RAIL-TORAIL
–120
4.6
–In/Out
16
–79
5.4
In/Out
16
–107
1.3
No
60
0.78
-116
4
–In/Out
THS4551
150
1.37
-128
3.3
–In/Out
THS4541
850
10.1
-137
2.2
–In/Out
24k
G071
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
THS4531
SLOS358C – SEPTEMBER 2011 – REVISED APRIL 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Electrical Specifications........................................
1
1
1
2
4
5.1 Absolute Maximum Ratings ......................................
5.2 Thermal Information ..................................................
5.3 Electrical Characteristics: VS = 2.7 V.......................
5.4 Electrical Characteristics: VS = 5 V..........................
4
4
5
8
Device Information............................................... 11
6.1 PIN Configurations .................................................. 11
6.2 Table of Graphs ..................................................... 12
7
8
9
Typical Characteristics: VS = 2.7 V.................... 13
Typical Characteristics: VS = 5 V....................... 19
Application Information....................................... 25
9.1 Typical Characteristics Test Circuits.......................
9.2 Application Circuits..................................................
9.3 Audio ADC Driver Performance: THS4531 AND
PCM4204 Combined Performance .........................
9.4 SAR ADC Performance ..........................................
9.5 EVM and Layout Recommendations .....................
25
30
36
38
41
10 Device and Documentation Support ................. 42
10.1
10.2
10.3
10.4
10.5
10.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
42
42
42
42
42
42
11 Mechanical, Packaging, and Orderable
Information ........................................................... 42
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2012) to Revision C
•
Page
Changed the continuous input current , Ii value in the Absolute Maximum Ratings section From: 7.5-mA To: 10-mA......... 4
Changes from Revision A (January 2012) to Revision B
Page
•
Deleted DC Performance, Input-referred offset voltage parameter typical specifications for TA = 0°C to +70°C,
–40°C to +85°C, and –40°C to +125°C in 2.7 V Electrical Characteristics table ................................................................... 6
•
Changed DC Performance, Input-referred offset voltage parameter maximum specifications for TA = 0°C to +70°C,
–40°C to +85°C, and –40°C to +125°C in 2.7 V Electrical Characteristics table ................................................................... 6
•
Changed DC Performance, Input offset voltage drift parameter typical and maximum specifications in 2.7 V
Electrical Characteristics table ............................................................................................................................................... 6
•
Deleted DC Performance, Input bias current parameter typical specifications for TA = 0°C to +70°C, –40°C to
+85°C, and –40°C to +125°C in 2.7 V Electrical Characteristics table .................................................................................. 6
•
Deleted DC Performance, Input bias current drift parameter typical specifications in 2.7 V Electrical Characteristics table 6
•
Deleted DC Performance, Input offset current parameter typical specifications for TA = 0°C to +70°C, –40°C to
+85°C, and –40°C to +125°C in 2.7 V Electrical Characteristics table .................................................................................. 6
•
Deleted DC Performance, Input-referred offset voltage parameter typical specifications for TA = 0°C to +70°C,
–40°C to +85°C, and –40°C to +125°C in 5 V Electrical Characteristics table ...................................................................... 9
•
Changed DC Performance, Input-referred offset voltage parameter maximum specifications for TA = 0°C to +70°C,
–40°C to +85°C, and –40°C to +125°C in 5 V Electrical Characteristics table ...................................................................... 9
•
Changed DC Performance, Input offset voltage drift parameter typical specifications in 5 V Electrical Characteristics
table ........................................................................................................................................................................................ 9
•
Deleted DC Performance, Input bias current parameter typical specifications for TA = 0°C to +70°C,–40°C to +85°C,
and –40°C to +125°C in 5 V Electrical Characteristics table.................................................................................................. 9
•
Deleted DC Performance, Input offset current parameter typical specifications for TA = 0°C to +70°C, –40°C to
+85°C, and –40°C to +125°C in 5 V Electrical Characteristics table ..................................................................................... 9
2
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THS4531
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SLOS358C – SEPTEMBER 2011 – REVISED APRIL 2020
Changes from Original (September 2011) to Revision A
•
Page
Changed status from product preview to production data...................................................................................................... 1
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3
THS4531
SLOS358C – SEPTEMBER 2011 – REVISED APRIL 2020
www.ti.com
Table 2. Packaging and Ordering Information (1)
PRODUCT
CHANNEL
COUNT
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
SOIC-8
D
–40°C to +125°C
VSSOP-8
DGK
–40°C to +125°C
WQFN-10
RUN
–40°C to +125°C
1
1
THS4531
1
1
1
1
(1)
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
T4531
THS4531ID
Rails, 75
T4531
THS4531IDR
Tape and reel, 2500
4531
THS4531IDGK
Rails, 80
4531
THS4531IDGKR
Tape and reel, 2500
4531
THS4531IRUNT
Tape and reel, 250
4531
THS4531IRUNR
Tape and reel, 3000
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
5 Electrical Specifications
5.1 Absolute Maximum Ratings
VALUE
Supply voltage, VS– to VS+
UNITS
5.5
Input/output voltage, VIN±, VOUT±, and VOCM pins
(VS–) – 0.7 to (VS+) + 0.7
V
Differential input voltage, VID
1
V
Continuous output current, IO
50
mA
10
mA
Continuous input current, Ii
Continuous power dissipation
See Thermal Information
Maximum junction temperature, TJ
150
°C
Operating free-air temperature range, TA
–40 to +125
°C
Storage temperature range, Tstg
–65 to +150
°C
Human body model (HBM)
3000
V
Charge device model (CDM)
500
V
Machine model (MM)
200
V
Electrostatic
discharge (ESD)
ratings:
5.2 Thermal Information
THERMAL METRIC (1)
THS4531
THS4531
THS4531
SOIC
(P)
VSSOP
(MSOP)
(DGK)
WQFN
(RUN)
8 PINS
8 PINS
10 PINS
163
θJA
Junction-to-ambient thermal resistance
133
198
θJCtop
Junction-to-case (top) thermal resistance
78
84
66
θJB
Junction-to-board thermal resistance
73
120
113
ψJT
Junction-to-top characterization parameter
26
19
17
ψJB
Junction-to-board characterization parameter
73
118
113
θJCbot
Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
(1)
4
UNITS
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
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5.3
SLOS358C – SEPTEMBER 2011 – REVISED APRIL 2020
Electrical Characteristics: VS = 2.7 V
Test conditions at TA = 25°C, VS+ = 2.7 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP, RF = 2 kΩ, RL = 2 kΩ differential, G = 1 V/V,
single-ended input, differential output, and input and output referenced to mid-supply, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TEST
LEVEL (1)
AC PERFORMANCE
Small-signal bandwidth
VOUT = 100 mVPP, G = 1
34
VOUT = 100 mVPP, G = 2
16
VOUT = 100 mVPP, G = 5
6
MHz
VOUT = 100 mVPP, G = 10
2.7
Gain-bandwidth product
VOUT = 100 mVPP, G = 10
27
MHz
Large-signal bandwidth
VOUT = 2 VPP, G = 1
34
MHz
Bandwidth for 0.1-dB flatness
VOUT = 2 VPP, G = 1
12
MHz
190/320
V/µs
5.2/6.1
ns
Slew rate, rise/fall, 25% to 75%
Rise/fall time, 10% to 90%
Settling time to 1%, rise and fall
Settling time to 0.1%, rise and fall
25/20
VOUT = 2 V step
60/60
Settling time to 0.01%, rise and fall
Overshoot/undershoot, rise and fall
2nd-order harmonic distortion
3rd-order harmonic distortion
2nd-order intermodulation
distortion
3rd-order intermodulation distortion
Input voltage noise
1/1
%
f = 10 kHz
–127
dBc
C
–59
f = 1 kHz, VOUT = 1 VRMS
–130
f = 10 kHz
–135
f = 1 MHz
–70
f = 1 MHz, 200 Hz tone spacing,
VOUT envelope = 1 VPP
–83
f = 1 kHz
45
f = 100 kHz
Overdrive recovery time
Overdrive = 0.5 V
Output balance error
Closed-loop output impedance
dBc
dBc
–81
10
Current noise 1/f corner frequency
(1)
ns
–122
Voltage noise 1/f corner frequency
Input current noise
150/110
f = 1 kHz, VOUT = 1 VRMS
f = 1 MHz
ns
nV/√Hz
Hz
0.25
pA/√Hz
6.5
kHz
65
ns
VOUT = 100 mV, f = 1 MHz
–65
dB
f = 1 MHz (differential)
2.5
Ω
Test levels (all values set by characterization and simulation): (A) 100% tested at +25°C; over temperature limits by characterization and
simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
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THS4531
SLOS358C – SEPTEMBER 2011 – REVISED APRIL 2020
www.ti.com
Electrical Characteristics: VS = 2.7 V (continued)
Test conditions at TA = 25°C, VS+ = 2.7 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP, RF = 2 kΩ, RL = 2 kΩ differential, G = 1 V/V,
single-ended input, differential output, and input and output referenced to mid-supply, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TEST
LEVEL (1)
dB
A
DC PERFORMANCE
Open-loop voltage gain (AOL)
100
TA = +25°C
Input-referred offset voltage
Input offset voltage drift (2)
±1405
TA = –40°C to +85°C
±1585
TA = –40°C to +125°C
±2000
TA = 0°C to +70°C
±1.7
TA = –40°C to +85°C
±1.8
±9
±2
±10
160
210
TA = +25°C
Input bias current drift (2)
221
TA = –40°C to +85°C
222
TA = –40°C to +125°C
233
TA = 0°C to +70°C
0.25
TA = –40°C to +85°C
0.25
TA = –40°C to +125°C
0.25
±5
Input offset current drift (2)
µV
µV/°C
B
±59
TA = –40°C to +85°C
±60
B
A
nA
nA/°C
±50
TA = 0°C to +70°C
TA = –40°C to +125°C
A
±9
TA = 0°C to +70°C
TA = +25°C
Input offset current
±1000
TA = 0°C to +70°C
TA = –40°C to +125°C
Input bias current
113
±200
B
B
A
nA
B
±75
TA = 0°C to +70°C
±0.05
±0.2
TA = –40°C to +85°C
±0.05
±0.2
TA = –40°C to +125°C
±0.05
±0.2
TA = +25°C, CMRR > 87 dB
VS– – 0.2
VS–
TA = –40°C to +125°C, CMRR > 87 dB
VS– – 0.2
VS–
nA/°C
B
INPUT
Common-mode input low
Common-mode input high
TA = +25°C, CMRR > 87 dB
VS+ – 1.2
VS+ – 1.1
TA = –40°C to +125°C, CMRR > 87 dB
VS+ – 1.2
VS+ – 1.1
90
116
Common-mode rejection ratio
Input impedance common-mode
V
dB
200 || 1.2
Input impedance differential mode
V
kΩ || pF
200 || 1
A
B
A
B
A
C
C
OUTPUT
Single-ended output voltage: low
Single-ended output voltage: high
TA = +25°C
VS– + 0.06
VS– +
0.2
TA = –40°C to +125°C
VS– + 0.06
VS– +
0.2
TA = +25°C
VS+ – 0.2
VS+ – 0.11
TA = –40°C to +125°C
VS+ – 0.2
VS+ – 0.11
Output saturation voltage: high
and low
Linear output current drive
(2)
6
110/60
TA = +25°C
±15
TA = –40°C to +125°C
±15
±22
A
V
V
mV
mA
B
A
B
C
A
B
Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end
points, computing the difference, and dividing by the temperature range.
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SLOS358C – SEPTEMBER 2011 – REVISED APRIL 2020
Electrical Characteristics: VS = 2.7 V (continued)
Test conditions at TA = 25°C, VS+ = 2.7 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP, RF = 2 kΩ, RL = 2 kΩ differential, G = 1 V/V,
single-ended input, differential output, and input and output referenced to mid-supply, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
230
330
270
370
UNITS
TEST
LEVEL (1)
V
B
POWER SUPPLY
Specified operating voltage
Quiescent operating current/ch
2.5
TA = +25°C, PD = VS+
TA = –40°C to +125°C, PD = VS+
Power-supply rejection (±PSRR)
87
5.5
108
µA
A
B
dB
A
2.1
V
A
50
500
nA
A
2
µA
A
ns
C
MHz
C
POWER DOWN
Enable voltage threshold
Specified on above 2.1 V
Disable voltage threshold
Specified off below 0.7 V
Disable pin bias current
PD = VS– + 0.5 V
Power-down quiescent current
PD = VS– + 0.5 V
0.5
Turn-on time delay
Time from PD = high to VOUT = 90% of final
value, RL= 200 Ω
650
Turn-off time delay
0.7
Time from PD = low to VOUT = 10% of original
value, RL= 200 Ω
A
20
OUTPUT COMMON-MODE VOLTAGE CONTROL (VOCM)
Small-signal bandwidth
VOCM input = 100 mVPP
Slew rate
VOCM input = 1 VSTEP
Gain
14
0.99
Common-mode offset voltage
Offset = output common-mode voltage – VOCM
input voltage
VOCM input bias current
VOCM = (VS+ – VS–)/2
VOCM input voltage range
0.8
VOCM input impedance
Default voltage offset from
(VS+ – VS–)/2
23
V/µs
C
0.996
1.01
V/V
A
±1
±5
mV
A
±20
±100
nA
A
0.75 to 1.9
1.75
V
A
kΩ || pF
C
mV
A
100 || 1.6
Offset = output common-mode voltage –
(VS+ – VS–)/2
±3
±10
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THS4531
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5.4
www.ti.com
Electrical Characteristics: VS = 5 V
Test conditions at TA = +25°C, VS+ = 5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP, RF = 2 kΩ, RL = 2 kΩ differential, G = 1 V/V,
single-ended input, differential output, and input and output referenced to mid-supply, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TEST
LEVEL (1)
AC PERFORMANCE
Small-signal bandwidth
VOUT = 100 mVPP, G = 1
36
VOUT = 100 mVPP, G = 2
17
VOUT = 100 mVPP, G = 5
6
MHz
VOUT = 100 mVPP, G = 10
2.7
Gain-bandwidth product
VOUT = 100 mVPP, G = 10
27
MHz
Large-signal bandwidth
VOUT = 2 VPP, G = 1
36
MHz
Bandwidth for 0.1 dB flatness
VOUT = 2 VPP, G = 1
15
MHz
220/390
V/µs
4.6/5.6
ns
25/20
ns
60/60
ns
150/110
ns
1/1
%
Slew rate, rise/fall, 25% to 75%
Rise/fall time, 10% to 90%
Settling time to 1%, rise and fall
Settling time to 0.1%, rise and fall
VOUT = 2-VStep
Settling time to 0.01%, rise and fall
Overshoot and undershoot, rise and
fall
2nd-order harmonic distortion
f = 1 kHz, VOUT = 1 VRMS
–122
f = 10 kHz
–128
f = 1 MHz
–60
f = 1 kHz, VOUT = 1 VRMS
–130
f = 10 kHz
–137
f = 1 MHz
–71
–85
3rd-order intermodulation distortion
f = 1 MHz, 200 kHz tone spacing,
VOUT envelope = 2 VPP
Input voltage noise
f = 1 kHz
3rd-order harmonic distortion
2nd-order intermodulation distortion
45
f = 100 kHz
Current noise 1/f corner frequency
Overdrive recovery time
Overdrive = 0.5 V
Output balance error
Closed-loop output impedance
(1)
8
–83
10
Voltage noise 1/f corner frequency
Input current noise
C
dBc
dBc
dBc
nV/√Hz
Hz
0.25
pA/√Hz
6.5
kHz
65
ns
VOUT = 100 mV, f = 1 MHz
–67
dB
f = 1 MHz (differential)
2.5
Ω
Test levels (all values set by characterization and simulation): (A) 100% tested at +25°C; over temperature limits by characterization and
simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
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SLOS358C – SEPTEMBER 2011 – REVISED APRIL 2020
Electrical Characteristics: VS = 5 V (continued)
Test conditions at TA = +25°C, VS+ = 5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP, RF = 2 kΩ, RL = 2 kΩ differential, G = 1 V/V,
single-ended input, differential output, and input and output referenced to mid-supply, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TEST
LEVEL (1)
dB
A
DC PERFORMANCE
Open-loop voltage gain (AOL)
100
TA = +25°C
Input-referred offset voltage
±1405
TA = –40°C to +85°C
±1650
TA = –40°C to +125°C
±2000
±1.7
±9
TA = –40°C to +85°C
±2
±10
TA = –40°C to +125°C
±2
±10
160
210
TA = +25°C
Input bias current
Input bias current drift (2)
TA = 0°C to +70°C
222
TA = –40°C to +85°C
223
TA = –40°C to +125°C
235
TA = 0°C to +70°C
0.04
0.25
TA = –40°C to +85°C
0.04
0.25
TA = –40°C to +125°C
0.04
0.25
±5
±50
TA = +25°C
Input offset current
TA = 0°C to +70°C
±59
TA = –40°C to +85°C
±60
TA = –40°C to +125°C
Input offset current drift (2)
±1000
TA = 0°C to +70°C
TA = 0°C to +70°C
Input offset voltage drift (2)
114
±200
A
µV
µV/°C
B
B
A
nA
nA/°C
B
B
A
nA
B
±75
TA = 0°C to +70°C
±0.05
±0.2
TA = –40°C to +85°C
±0.05
±0.2
TA = –40°C to +125°C
±0.05
±0.2
TA = +25°C, CMRR > 87 dB
VS– – 0.2
VS–
TA = –40°C to +125°C, CMRR > 87 dB
VS– – 0.2
VS–
nA/°C
B
INPUT
Common-mode input: low
Common-mode input: high
TA = +25°C, CMRR > 87 dB
VS+ – 1.2
VS+ –1.1
TA = –40°C to +125°C, CMRR > 87 dB
VS+ – 1.2
VS+ –1.1
90
116
Common-mode rejection ratio
Input impedance common-mode
200 || 1.2
Input impedance differential mode
200 || 1
V
V
dB
kΩ || pF
A
B
A
B
A
C
C
OUTPUT
Linear output voltage: low
Linear output voltage: high
TA = +25°C
TA = –40°C to +125°C
(2)
A
VS– + 0.1 VS– + 0.2
B
TA = +25°C
VS+ – 0.25
VS+ –
0.12
TA = –40°C to +125°C
VS+ – 0.25
VS+ –
0.12
Output saturation voltage: high/low
Linear output current drive
VS– + 0.1 VS– + 0.2
120/100
TA = +25°C
±15
TA = –40°C to +125°C
±15
±25
V
A
B
mV
mA
C
A
B
Input offset voltage drift, input bias current drift, and input offset current drift are average values calculated by taking data at the end
points, computing the difference, and dividing by the temperature range.
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Electrical Characteristics: VS = 5 V (continued)
Test conditions at TA = +25°C, VS+ = 5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP, RF = 2 kΩ, RL = 2 kΩ differential, G = 1 V/V,
single-ended input, differential output, and input and output referenced to mid-supply, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
250
350
290
390
UNITS
TEST
LEVEL (1)
V
B
POWER SUPPLY
Specified operating voltage
Quiescent operating current/ch
2.5
TA = 25°C, PD = VS+
TA = –40°C to 125°C, PD = VS+
Power-supply rejection (±PSRR)
87
5.5
108
µA
dB
A
B
A
POWER DOWN
Enable voltage threshold
Specified on above 2.1 V
Disable voltage threshold
Specified off below 0.7 V
Disable pin bias current
PD = VS– + 0.5 V
Power-down quiescent current
Turn-on time delay
Turn-off time delay
2.1
0.7
V
A
A
50
500
nA
A
PD = VS– + 0.5 V
0.5
2
µA
A
Time from PD = high to VOUT = 90% of final
value, RL= 200 Ω
600
ns
C
MHz
C
Time from PD = low to VOUT = 10% of
original value, RL= 200 Ω
15
OUTPUT COMMON-MODE VOLTAGE CONTROL (VOCM)
Small-signal bandwidth
VOCM input = 100 mVPP
Slew rate
VOCM input = 1 VSTEP
Gain
15
0.99
Common-mode offset voltage
Offset = output common-mode voltage –
VOCM input voltage
VOCM input bias current
VOCM = (VS+ – VS–)/2
VOCM input voltage range
0.95
VOCM input impedance
Default voltage offset from
(VS+ – VS–)/2
10
24
V/µs
C
0.996
1.01
V/V
A
±1
±5
mV
A
±20
±120
nA
A
0.75 to
4.15
4.0
V
A
kΩ || pF
C
mV
A
65 || 0.86
Offset = output common-mode voltage –
(VS+ – VS–)/2
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±10
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6 Device Information
6.1 PIN Configurations
THS4531
THS4531
SOIC-8 (D), VSSOP-8 (DGK) PACKAGE (TOP VIEW)
WQFN-10 (RUN) PACKAGE (TOP VIEW)
VS+
VIN-
1
8
VIN+
VOCM
2
7
PD
VOUT-
1
9
VOUT+
VS+
3
6
VS-
NC
2
8
NC
VOUT+
4
5
VOUT-
PD
3
7
VOCM
VIN+
4
6
VIN-
10
5
VS-
Table 3. PIN Functions
NUMBER
NAME
DESCRIPTION
THS4531 D, DGK PACKAGE
1
VIN–
Inverted (negative) output feedback
2
VOCM
Common-mode voltage input
3
VS+
Amplifier positive power-supply input
4
VOUT+
Non-inverted amplifier output
5
VOUT–
Inverted amplifier output
6
VS–
Amplifier negative power-supply input. Note: VS– tied together on multichannel devices.
7
PD
Power-down, PD = logic low = low power mode, PD = logic high = normal operation (pin must be driven)
8
VIN+
Non-inverted amplifier input
THS4531 RUN PACKAGE
VOUT–
Inverted amplifier output
2, 8
1
NC
No internal connection
3
PD
Power-down, PD = logic low = low power mode, PD = logic high = normal operation (pin must be driven)
4
VIN+
Noninverted amplifier input
5
VS–
Amplifier negative power-supply input. Note: VS– tied together on multichannel devices.
6
VIN–
Inverting amplifier input
7
VOCM
Common-mode voltage input
9
VOUT+
Noninverted amplifier output
10
VS+
Amplifier positive power-supply input
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6.2 Table of Graphs
Description
VS = 2.7 V
VS = 5 V
Small-signal frequency response
Figure 2
Figure 35
Large-signal frequency response
Figure 3
Figure 36
Large- and small-signal pulse response
Figure 4
Figure 37
Single-ended slew rate versus VOUT step
Figure 5
Figure 38
Differential slew rate versus VOUT step
Figure 6
Figure 39
Overdrive recovery
Figure 7
Figure 40
10-kHz FFT on audio analyzer
Figure 8
Figure 41
Harmonic distortion versus frequency
Figure 9
Figure 42
Harmonic distortion versus output voltage at 1 MHz
Figure 10
Figure 43
Harmonic distortion versus gain at 1 MHz
Figure 11
Figure 44
Harmonic distortion versus load at 1 MHz
Figure 12
Figure 45
Harmonic distortion versus VOCM at 1 MHz
Figure 13
Figure 46
Two-tone, 2nd and 3rd order intermodulation distortion versus frequency
Figure 14
Figure 47
Single-ended output voltage swing versus load resistance
Figure 15
Figure 48
Single-ended output saturation voltage versus load current
Figure 16
Figure 49
Main amplifier differential output impedance versus frequency
Figure 17
Figure 50
Frequency response versus CLOAD
Figure 18
Figure 51
RO versus CLOAD
Figure 19
Figure 52
Rejection ratio versus frequency
Figure 20
Figure 53
Turn-on time
Figure 21
Figure 54
Turn-off time
Figure 22
Figure 55
Input-referred voltage noise and current noise spectral density
Figure 23
Figure 56
Main amplifier differential open-loop gain and phase versus frequency
Figure 24
Figure 57
Output balance error versus frequency
Figure 25
Figure 58
VOCM small signal frequency response
Figure 26
Figure 59
VOCM large and small signal pulse response
Figure 27
Figure 60
VOCM input impedance versus frequency
Figure 28
Figure 61
Count versus input offset current
Figure 29
Figure 62
Count versus input offset current temperature drift
Figure 30
Figure 63
Input offset current versus temperature
Figure 31
Figure 64
Count versus input offset voltage
Figure 32
Figure 65
Count versus input offset voltage temperature drift
Figure 33
Figure 66
Input offset voltage versus temperature
Figure 34
Figure 67
12
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7 Typical Characteristics: VS = 2.7 V
21
18
15
12
9
6
3
0
−3
−6
VS = 2.7 V
−9
G = 1 V/V
−12
RF = 2 kΩ
−15
RL = 2 kΩ
VOUT = 100 mVpp
−18
−21
100k
1M
G = 1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
10M
Normalized Gain (dB)
100M
Frequency (Hz)
21
18
15
12
9
6
3
0
−3
−6
VS = 2.7 V
−9
G = 1 V/V
−12
RF = 2 kΩ
−15
RL = 2 kΩ
VOUT = 2 Vpp
−18
−21
100k
10M
100M
G002
Figure 3. Large-Signal Frequency Response
1.5
400
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
1
0.5-V Step
2-V Step
VS = 2.7 V
G = 2 V/V
RF = 2 kΩ
RL = 200 Ω
350
300
Slew Rate (V/µs)
Differential Output Voltage (V)
1M
Frequency (Hz)
G001
Figure 2. Small-Signal Frequency Response
0.5
0
−0.5
250
200
150
100
−1
−1.5
0
20
40
60
Time (ns)
80
0
100
0
G003
0.5
1
1.5
Differential VOUT (V)
2
G004
4
2
Differential Input Voltage (V)
VS = 2.7 V
G = 2 V/V
RF = 2 kΩ
RL = 200 Ω
200
150
100
50
1
2
3
4
Differential VOUT (V)
5
VIN
VOUT
1.5
1
2
1
0
0
−1
−0.5
VS = 2.7 V
G = 2 V/V
RF = 2 kΩ
RL = 2 kΩ
−1
−2
6
3
0.5
−1.5
Rising
Falling
0
2.5
Figure 5. Single-Snded Slew Rate vs VOUT Step
250
0
Rising
Falling
50
Figure 4. Large and Small-Signal Pulse Response
Slew Rate (V/µs)
G = 1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
0
−2
−3
−4
100 200 300 400 500 600 700 800 900 1000
Time (ns)
G053
Figure 6. Differential Slew Rate vs VOUT Step
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G005
Figure 7. Overdrive Recovery
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Differential Output Voltage (V)
Gain (dB)
Test conditions unless otherwise noted: VS+ = 2.7 V, VS– = 0 -, CM = open, VOUT = 2 Vpp, RF = 2 kΩ, RL = 2 kΩ differential, G
= 1 V/V, single-ended input, differential output, input and output referenced to mid-supply unless otherwise noted.
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Typical Characteristics: VS = 2.7 V (continued)
10
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 100 kΩ
VOUT = 4 Vpp
0
Harmonic Distortion (dBc)
Magnitude (dBV)
Test conditions unless otherwise noted: VS+ = 2.7 V, VS– = 0 -, CM = open, VOUT = 2 Vpp, RF = 2 kΩ, RL = 2 kΩ differential, G
= 1 V/V, single-ended input, differential output, input and output referenced to mid-supply unless otherwise noted.
5k
10k
15k
Frequency (Hz)
20k
24k
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
VOUT = 2 Vpp
Second Harmonic
Third Harmonic
1k
Figure 8. 10 kHz FFT On Audio Analyzer
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
f = 1 MHz
−30
−40
−50
−60
−50
−55
G007
−60
−65
−70
Second Harmonic
Third Harmonic
−75
1
2
3
−80
4
VOUT (Vpp)
0
2
4
6
8
10
Gain (V/V)
G008
Figure 10. Harmonic Distortion vs Output Voltage at 1 MHz
G009
Figure 11. Harmonic Distortion vs GAIN at 1 MHz
0
0
−20
−30
Second Harmonic
Third Harmonic
−10
Harmonic Distortion (dBc)
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
VOUT = 2 Vpp
f = 1 MHz
−10
Harmonic Distortion (dBc)
10M
VS = 2.7 V
RF = 2 kΩ
RL = 2 kΩ
VOUT = 2 Vpp
f = 1 MHz
−45
−70
−40
−50
−60
−70
−20
−30
−40
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
VOUT = 2 Vpp
f = 1 MHz
Second Harmonic
Third Harmonic
−50
−60
−70
−80
0
200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k
Load (Ω)
2k
Figure 12. Harmonic Distortion vs Load at 1 MHz
14
1M
−40
Second Harmonic
Third Harmonic
−20
−80
100k
Frequency (Hz)
Figure 9. Harmonic Distortion vs Frequency
−10
−80
10k
G006
−90
0.5
1
1.5
VOCM (V)
G010
2
G011
Figure 13. Harmonic Distortion vs VOCM at 1 MHz
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Typical Characteristics: VS = 2.7 V (continued)
Test conditions unless otherwise noted: VS+ = 2.7 V, VS– = 0 -, CM = open, VOUT = 2 Vpp, RF = 2 kΩ, RL = 2 kΩ differential, G
= 1 V/V, single-ended input, differential output, input and output referenced to mid-supply unless otherwise noted.
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
VOUT = 2 Vpp Envelope
−20
−30
−40
2.5
Single-Ended VOUT (V)
Intermodulation Distortion (dB)
−10
−50
−60
−70
−90
1
Differential Output Impedance (Ω)
Output Saturation Voltage (V)
0.8
0.6
VS = 2.7 V
G = 2 V/V
RF = 2 kΩ
0.2
0
0.1
1
10
Differential Load Current (mA)
1k
Load Resistance (Ω)
10k
G013
10
1
0.1
200
100
RO (Ω)
VS = 2.7 V, G = 1 V/V
RF = 2 kΩ, RL = 2 kΩ
VOUT = 100 mVpp
−9
−18
−21
100k
CL = 0 pF, RO = 0 Ω
CL = 15 pF, RO = 200 Ω
CL = 39 pF, RO = 100 Ω
CL = 120 pF, RO = 50 Ω
CL = 470 pF, RO = 20 Ω
CL = 1200 pF, RO = 12 Ω
1M
1M
Frequency (Hz)
10M
40M
G015
Figure 17. Main Amplifier Differential Output Impedance vs
Frequency
0
−15
100k
G014
3
−12
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
VOUT = 100 mVpp
0.01
10k
30
Figure 16. Single-Ended Output Saturation Voltage vs Load
Current
Gain (dB)
100
100
VSAT High
VSAT Low
−6
50
Figure 15. Single-Ended Output Voltage Swing vs Load
Resistance
1
−3
VS = 2.7 V
G = 2 V/V
RF = 2 kΩ
1
G012
Figure 14. Two-Tone, 2nd and 3rd Order Intermodulation
Distortion vs Frequency
0.4
1.5
0
10
Frequency (MHz)
2
0.5
Second Intermodulation
Third Intermodulation
−80
VOUT MAX
VOUT MIN
10
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
10M
100M
Frequency (Hz)
1
1
G016
Figure 18. Frequency Response vs CLOAD
10
100
CLOAD (pF)
1k
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G017
Figure 19. RO vs CLOAD
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Typical Characteristics: VS = 2.7 V (continued)
Test conditions unless otherwise noted: VS+ = 2.7 V, VS– = 0 -, CM = open, VOUT = 2 Vpp, RF = 2 kΩ, RL = 2 kΩ differential, G
= 1 V/V, single-ended input, differential output, input and output referenced to mid-supply unless otherwise noted.
−60
−70
1
2
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 200 Ω
0.5
1
−80
Power Down
VOUT
CMRR
PSRR
−90
−100
100k
1M
Frequency (Hz)
10M
0
30M
0
200
G018
1
0
0
10
20
30
Time (ns)
40
0.5
50
0
1
1
0
Magnitude
Phase
−45
−90
−135
100
1k
10k
100k
Frequency (Hz)
10
100
1M
1k
10k
Frequency (Hz)
0.1
1M
100k
G021
10M
−30
Open Loop Gain Phase (deg)
Open Loop Gain Magnitude (dB)
10
Figure 23. Input-referred Voltage Noise and Current Noise
Spectral Density
−180
100M
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
−40
−50
−60
−70
−80
100k
G022
Figure 24. Main Amplifier Differential Open-Loop Gain and
Phase vs Frequency
16
10
G020
120
110
100
90
80
70
60
50
10
100
Voltage Noise
Current Noise
0.1
Figure 22. Turn-Off Time
40
30
20
10
0
Input Referred Voltage Noise (nV/ Hz)
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 200 Ω
G019
100
Output Balance Error (dB)
Power Down (V)
1
2
Differential Output Voltage (V)
1.5
Power Down
VOUT
0
1000
800
Figure 21. Turn-On Time
Figure 20. Rejection Ratio vs Frequency
3
400
600
Time (ns)
Differential Output Voltage (V)
−50
Input Referred Current Noise (pA/ Hz)
−40
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
Power Down (V)
Rejection Ratio (dB)
−30
1.5
3
−20
1M
Frequency (Hz)
10M
30M
G023
Figure 25. Output Balance Error vs Frequency
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Typical Characteristics: VS = 2.7 V (continued)
Test conditions unless otherwise noted: VS+ = 2.7 V, VS– = 0 -, CM = open, VOUT = 2 Vpp, RF = 2 kΩ, RL = 2 kΩ differential, G
= 1 V/V, single-ended input, differential output, input and output referenced to mid-supply unless otherwise noted.
2
Output Common-Mode Voltage (V)
3
0
Gain (dB)
−3
−6
−9
−12
−15
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
VOUT = 100 mVpp
−18
100k
1M
Frequency (Hz)
10M
1.6
1.4
1.2
1
0.2-V Step
1-V Step
0.8
0.6
50M
0
G024
Figure 26. VOCM Small-Signal Frequency Response
100 200 300 400 500 600 700 800 900 1000
Time (ns)
G025
Figure 27. VOCM Large and Small-Signal Pulse Response
200k
600
VS = 2.7 V
100k
THS4531ID
VS = 2.7 V
TA = 25°C
500
400
10k
Count
300
200
1k
100
100
100k
1M
Frequency (Hz)
10M
0
50M
−50
−45
−40
−35
−30
−25
−20
−15
−10
−5
0
5
10
15
20
25
30
35
40
45
50
VOCM Input Impedance (Ω)
1.8
G026
Input Offset Current (nA)
Figure 28. VOCM Input Impedance vs Frequency
G055
Figure 29. Input Offset Current Histogram
50
14
THS4531ID
VS = 2.7 V
10
Count
THS4531ID
VS = 2.7 V
40
Input Offset Current (nA)
12
0°C to +70°C
−40°C to +85°C
−40°C to +125°C
8
6
4
2
30
20
10
0
−10
−20
−30
−40
−50
−50
−200
−180
−160
−140
−120
−100
−80
−60
−40
−20
0
20
40
60
80
100
120
140
160
180
200
0
Input Offset Current Temperature Drift (pA/°C)
G056
−25
0
25
50
Temperature (°C)
75
100
125
G057
Figure 31. Input Offset Current vs Temperature
Figure 30. Input Offset Current Temperature Drift Histogram
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Typical Characteristics: VS = 2.7 V (continued)
Test conditions unless otherwise noted: VS+ = 2.7 V, VS– = 0 -, CM = open, VOUT = 2 Vpp, RF = 2 kΩ, RL = 2 kΩ differential, G
= 1 V/V, single-ended input, differential output, input and output referenced to mid-supply unless otherwise noted.
10
200
THS4531ID
VS = 2.7 V
TA = 25°C
8
Count
150
Count
0°C to +70°C
−40°C to +85°C
−40°C to +125°C
100
THS4531ID
VS = 2.7 V
6
4
50
2
0
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
1
2
3
4
5
6
7
8
9
10
−1000
−900
−800
−700
−600
−500
−400
−300
−200
−100
0
100
200
300
400
500
600
700
800
900
1000
1100
0
Input Offset Voltage Temperature Drift (µV/°C)
Input Offset Voltage (µV)
G058
Figure 32. Input Offset Voltage Histogram
G059
Figure 33. Input Offset Voltage Temperature Drift Histogram
1000
THS4531ID
VS = 2.7 V
Input Offset Voltage (µV)
800
600
400
200
0
−200
−400
−600
−800
−1000
−50
−25
0
25
50
Temperature (°C)
75
100
125
G060
Figure 34. Input Offset Voltage vs Temperature
18
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8 Typical Characteristics: VS = 5 V
21
18
15
12
9
6
3
0
−3
−6
VS = 5 V
−9
G = 1 V/V
−12
RF = 2 kΩ
−15
RL = 2 kΩ
VOUT = 100 mVpp
−18
−21
100k
1M
G = 1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
Gain (dB)
10M
100M
Frequency (Hz)
21
18
15
12
9
6
3
0
−3
−6
VS = 5 V
−9
G = 1 V/V
−12
RF = 2 kΩ
−15
RL = 2 kΩ
VOUT = 2 Vpp
−18
−21
100k
1
0.5-V Step
2-V Step
G028
VS = 5 V
G = 2 V/V
RF = 2 kΩ
RL = 200 Ω
500
Slew Rate (V/µs)
Differential Output Voltage (V)
100M
600
VS = 5 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
0.5
0
−0.5
400
300
200
−1
100
0
20
40
60
Time (ns)
80
0
100
Rising
Falling
0
G029
Figure 37. Large and Small-Signal Pulse Response
1
2
3
Differential VOUT (V)
4
G030
6
3
200
Differential Input Voltage (V)
VS = 5 V
G = 2 V/V
RF = 2 kΩ
RL = 200 Ω
150
100
50
Rising
Falling
0
1
2
3
4
5
Differential VOUT (V)
6
7
VIN
VOUT
2
4
1
2
0
0
−2
−1
VS = 5 V
G = 2 V/V
RF = 2 kΩ
RL = 200 Ω
−2
−3
8
5
Figure 38. Single-Ended Slew Rate vs VOUT Step
250
Slew Rate (V/µs)
10M
Figure 36. Large-Signal Frequency Response
1.5
0
1M
Frequency (Hz)
G027
Figure 35. Small-Signal Frequency Response
−1.5
G = 1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
0
−4
−6
100 200 300 400 500 600 700 800 900 1000
Time (ns)
G054
Figure 39. Differential Slew Rate vs VOUT Step
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Figure 40. Overdrive Recovery
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Differential Output Voltage (V)
Gain (dB)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, VOCM = open, VOUT = 2 Vpp, RF = 2 kΩ, RL = 2 kΩ Differential, G
= 1 V/V, Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply, TA = 25°C unless otherwise
noted.
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Typical Characteristics: VS = 5 V (continued)
10
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
VS = 5 V
G = 1 V/V
RF = 2 kΩ
RL = 100 kΩ
VOUT = 8 Vpp
0
Harmonic Distortion (dBc)
Magnitude (dBV)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, VOCM = open, VOUT = 2 Vpp, RF = 2 kΩ, RL = 2 kΩ Differential, G
= 1 V/V, Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply, TA = 25°C unless otherwise
noted.
5k
10k
15k
Frequency (Hz)
20k
24k
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
Second Harmonic
Third Harmonic
1k
10k
G032
Figure 41. 10 kHz FFT On Audio Analyzer
100k
Frequency (Hz)
Second Harmonic
Third Harmonic
Harmonic Distortion (dBc)
−60
−70
−50
−55
−60
−65
−70
Second Harmonic
Third Harmonic
−75
1
2
3
4
5
VOUT (Vpp)
6
7
−80
8
2
4
6
8
10
Gain (V/V)
G035
Figure 44. Harmonic Distortion vs Gain at 1 MHz
0
0
−20
−30
Second Harmonic
Third Harmonic
VS = 5 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
VOUT = 2 Vpp
f = 1 MHz
−10
Harmonic Distortion (dBc)
VS = 5 V
G = 1 V/V
RF = 2 kΩ
VOUT = 2 Vpp
f = 1 MHz
−10
Harmonic Distortion (dBc)
0
G034
Figure 43. Harmonic Distortion vs Output Voltage at 1 MHz
−40
−50
−60
−70
−20
−30
−40
Second Harminc
Third Harmonic
−50
−60
−70
−80
0
200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k
Load (Ω)
2k
Figure 45. Harmonic Distortion vs Load at 1 MHz
20
G033
VS = 5 V
RF = 2 kΩ
RL = 2 kΩ
VOUT = 2 Vpp
f = 1 MHz
−45
−50
−80
10M
−40
VS = 5 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
f = 1 MHz
−40
−80
1M
Figure 42. Harmonic Distortion vs Frequency
−30
Harmonic Distortion (dBc)
VS = 5 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
VOUT = 2 Vpp
−90
0
G036
0.5
1
1.5
2
2.5
3
VOCM (V)
3.5
4
4.5
5
G037
Figure 46. Harmonic Distortion vs VOCM at 1 MHz
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Typical Characteristics: VS = 5 V (continued)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, VOCM = open, VOUT = 2 Vpp, RF = 2 kΩ, RL = 2 kΩ Differential, G
= 1 V/V, Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply, TA = 25°C unless otherwise
noted.
5
VS = 5 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
VOUT = 2 Vpp Envelope
−20
−30
−40
4.5
Single-Ended VOUT (V)
Intermodulation Distortion (dB)
−10
−50
−60
−70
Second Intermodulation
Third Intermodulation
−80
−90
1
1
0.8
VS = 5 V
G = 2 V/V
RF = 2 kΩ
0.4
0.2
0
0.1
1
10
Differential Load Current (mA)
100
1k
Load Resistance (Ω)
10k
G039
10
1
0.1
0
100
RO (Ω)
VS = 5 V, G = 1 V/V
RF = 2 kΩ, RL = 2 kΩ
VOUT = 100 mVpp
−9
−18
−21
100k
CL = 0 pF, RO = 0 Ω
CL = 15 pF, RO = 200 Ω
CL = 39 pF, RO = 100 Ω
CL = 120 pF, RO = 50 Ω
CL = 470 pF, RO = 20 Ω
CL = 1200 pF, RO = 12 Ω
1M
1M
Frequency (Hz)
10M
40M
G041
Figure 50. Main Amplifier Differential Output Impedance vs
Frequency
200
−15
100k
G040
3
−12
VS = 5 V
G = 1 V/V
RF = 2 kΩ
VOUT = 100 mVpp
0.01
10k
30
Figure 49. Single-Ended Output Saturation Voltage vs Load
Current
−6
50
100
VSAT High
VSAT Low
1
−3
VS = 5 V
G = 2 V/V
RF = 2 kΩ
Figure 48. Single-Ended Output Voltage Swing vs Load
Resistance
Differential Output Impedance (Ω)
Output Saturation Voltage (V)
2
1.5
G038
1.2
Gain (dB)
3
2.5
0
Figure 47. Two-Tone, 2nd and 3rdOrder Intermodulation
Distortion vs Frequency
0.6
VOUT MAX
VOUT MIN
0.5
10
Frequency (MHz)
4
3.5
10
VS = 5 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
10M
100M
Frequency (Hz)
1
1
G042
Figure 51. Frequency Response vs CLOAD
10
100
CLOAD (pF)
1k
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Figure 52. RO vs CLOAD
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Typical Characteristics: VS = 5 V (continued)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, VOCM = open, VOUT = 2 Vpp, RF = 2 kΩ, RL = 2 kΩ Differential, G
= 1 V/V, Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply, TA = 25°C unless otherwise
noted.
−50
−60
−70
−80
CMRR
PSRR
−90
−100
100k
1M
Frequency (Hz)
10M
1.5
2
1
1
0.5
0
0
200
G044
1.5
1
2
0.5
1
0
0
10
20
30
Time (ns)
40
50
0
10
1
1
0
−45
−90
−135
100
1k
10k
100k
Frequency (Hz)
10
100
1M
1k
10k
Frequency (Hz)
0.1
1M
100k
G047
10M
−30
−180
100M
VS = 5 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
−40
−50
−60
−70
−80
100k
G048
Figure 57. Main Amplifier Differential Open-Loop Gain and
Phase vs Frequency
22
10
Figure 56. Input-Referred Voltage Noise and Current Noise
Spectral Density
Magnitude
Phase
10
100
G046
Open Loop Gain Phase (deg)
Open Loop Gain Magnitude (dB)
40
30
20
10
0
G045
Voltage Noise
Current Noise
0.1
Figure 55. Turn-Off Time
120
110
100
90
80
70
60
50
0
1000
800
100
Output Balance Error (dB)
Power Down (V)
VS = 5 V
G = 1 V/V
RF = 2 kΩ
RL = 200 Ω
3
Input Referred Voltage Noise (nV/ Hz)
2
Differential Output Voltage (V)
2.5
4
400
600
Time (ns)
Figure 54. Turn-On Time
Figure 53. Rejection Ratio vs Frequency
Power Down
VOUT
2
3
30M
5
Power Down
VOUT
Differential Output Voltage (V)
VS = 5 V
G = 1 V/V
RF = 2 kΩ
RL = 200 Ω
4
Input Referred Current Noise (pA/ Hz)
−40
VS = 5 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
Power Down (V)
Rejection Ratio (dB)
−30
2.5
5
−20
1M
Frequency (Hz)
10M
30M
G049
Figure 58. Output Balance Error vs Frequency
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Typical Characteristics: VS = 5 V (continued)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, VOCM = open, VOUT = 2 Vpp, RF = 2 kΩ, RL = 2 kΩ Differential, G
= 1 V/V, Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply, TA = 25°C unless otherwise
noted.
3.2
Output Common-Mode Voltage (V)
3
0
Gain (dB)
−3
−6
−9
−12
−15
VS = 5 V
G = 1 V/V
RF = 2 kΩ
VOUT = 100 mVpp
−18
100k
1M
Frequency (Hz)
10M
3
2.8
2.6
2.4
2
1.8
50M
0.2-V Step
1-V Step
2.2
0
G050
Figure 59. VOCM Small-Signal Frequency Response
Figure 60. VOCM Large and Small-Signal Pulse Response
100k
600
VS = 5 V
THS4531ID
VS = 5 V
TA = 25°C
500
10k
400
Count
1k
300
200
100
100
100k
1M
Frequency (Hz)
10M
0
50M
−50
−45
−40
−35
−30
−25
−20
−15
−10
−5
0
5
10
15
20
25
30
35
40
45
50
VOCM Input Impedance (Ω)
100 200 300 400 500 600 700 800 900 1000
Time (ns)
G051
G052
Input Offset Current (nA)
Figure 61. VOCM Input Impedance vs Frequency
G061
Figure 62. Input Offset Current Histogram
50
14
THS4531ID
VS = 5V
10
Count
THS4531ID
VS = 5 V
40
Input Offset Current (nA)
12
0°C to +70°C
−40°C to +85°C
−40°C to +125°C
8
6
4
2
30
20
10
0
−10
−20
−30
−40
−50
−50
−200
−180
−160
−140
−120
−100
−80
−60
−40
−20
0
20
40
60
80
100
120
140
160
180
200
0
Input Offset Current Temperature Drift (pA/°C)
G062
−25
0
25
50
Temperature (°C)
75
100
125
G063
Figure 64. Input Offset Current vs Temperature
Figure 63. Input Offset Current Temperature Drift Histogram
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Typical Characteristics: VS = 5 V (continued)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, VOCM = open, VOUT = 2 Vpp, RF = 2 kΩ, RL = 2 kΩ Differential, G
= 1 V/V, Single-Ended Input, Differential Output, Input and Output Referenced to mid-supply, TA = 25°C unless otherwise
noted.
10
200
THS4531ID
VS = 5 V
TA = 25°C
8
Count
150
Count
0°C to +70°C
−40°C to +85°C
−40°C to +125°C
100
THS4531ID
VS = 5V
6
4
50
2
0
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
1
2
3
4
5
6
7
8
9
10
−1000
−900
−800
−700
−600
−500
−400
−300
−200
−100
0
100
200
300
400
500
600
700
800
900
1000
1100
0
Input Offset Voltage Temperature Drift (µV/°C)
Input Offset Voltage (µV)
G064
Figure 65. Input Offset Voltage Histogram
G065
Figure 66. Input Offset Voltage Temperature Drift Histogram
1000
THS4531ID
VS = 5 V
Input Offset Voltage (µV)
800
600
400
200
0
−200
−400
−600
−800
−1000
−50
−25
0
25
50
Temperature (°C)
75
100
125
G066
Figure 67. Input Offset Voltage vs Temperature
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9 Application Information
9.1 Typical Characteristics Test Circuits
Figure 68 shows the general test circuit built on the EVM that was used for testing the THS4531. For simplicity,
power supply decoupling is not shown – please see layout in the applications section for recommendations.
Depending on the test conditions, component values are changed per Table 4 and Table 5, or as otherwise
noted. Some of the signal generators used are ac coupled 50 Ω sources and a 0.22 µF cap and 49.9 Ω resistor
to ground are inserted across RIT on the un-driven or alternate input as shown to balance the circuit. Split-power
supply is used to ease the interface to common lab test equipment, but if properly biased, the amplifier can be
operated single-supply as described in the applications section with no impact on performance. For most of the
tests, the devices are tested with single ended input and a transformer on the output to convert the differential
output to single ended because common lab test equipment have single ended inputs and outputs. Performance
is the same or better with differential input and differential output.
VIN+
RG
Input From 50-Ω
Test Equipment
RIT
RF
PD
VS+
+
0.22 μF
VOCM
–
0.22 μF
VIN–
VS–
RO
VOUT–
THS4531
1:1
Output to 50-Ω
Test Equipment
ROT
VOUT+
RO
RG
No Connection
RF
0.22 μF
Installed to Balance
Amplifier
RIT
49.9 Ω
Figure 68. General Test Circuit
Table 4. Gain Component Values for Single-Ended Input (1)
(1)
GAIN
RF
RG
RIT
1 V/V
2 kΩ
2 kΩ
51.1 Ω
2 V/V
2 kΩ
1 kΩ
52.3 Ω
5 V/V
2 kΩ
392 Ω
53.6 Ω
10 V/V
2 kΩ
187 kΩ
57.6 Ω
Note components are chosen to achieve gain and 50-Ω input termination. Resistor values shown are closest standard values so gains
are approximate.
Table 5. Load Component Values For 1:1 Differential to Single-Ended Output Transformer (1)
(1)
RL
RO
ROT
100 Ω
25 Ω
open
ATTEN
6
200 Ω
86.6 Ω
69.8 Ω
16.8
499 Ω
237 Ω
56.2 Ω
25.5
1 kΩ
487 Ω
52.3 Ω
31.8
2 kΩ
976 Ω
51.1 Ω
37.9
Note the total load includes 50-Ω termination by the test equipment. Components are chosen to achieve load and 50-Ω line termination
through a 1:1 transformer. Resistor values shown are closest standard values so loads are approximate.
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Due to the voltage divider on the output formed by the load component values, the amplifier’s output is
attenuated. The column Atten in Table 5 shows the attenuation expected from the resistor divider. When using a
transformer at the output as shown in Figure 68, the signal will see slightly more loss due to transformer and line
loss, and these numbers will be approximate. The standard output load used for most tests is 2 kΩ with
associated 37.9 dB of loss.
9.1.1 Frequency Response and Output Impedance
The circuit shown in Figure 68 is used to measure the frequency response of the amplifier.
A network analyzer is used as the signal source and the measurement device. The output impedance of the
network analyzer is 50-Ω and is DC coupled. RIT and RG are chosen to impedance match to 50 Ω and maintain
the proper gain. To balance the amplifier, a 49.9 Ω resistor to ground is inserted across RIT on the alternate
input.
The output is routed to the input of the network analyzer via 50 Ω coax. For 2 k load, 37.9 dB is added to the
measurement to refer back to the amplifier’s output per Table 5.
For output impedance, the signal is injected at VOUT with VIN left open. The voltage drop across the 2x RO
resistors is measured with a high impedance differential probe and used to calculate the impedance seen looking
into the amplifier’s output.
9.1.2 Distortion
At 1 MHz and above, the circuit shown in Figure 68 is used to measure harmonic, intermodulation distortion, and
output impedance of the amplifier.
A signal generator is used as the signal source and the output is measured with a spectrum analyzer. The output
impedance of the signal generator is 50 Ω and is AC coupled. RIT and RG are chosen to impedance match to 50
Ω and maintain the proper gain. To balance the amplifier, a 0.22 µF cap and 49.9 Ω resistor to ground is inserted
across RIT on the alternate input. A low-pass filter is inserted in series with the input to reduce harmonics
generated at the signal source. The level of the fundamental is measured and then a high-pass filter is inserted
at the output to reduce the fundamental so it does not generate distortion in the input of the spectrum analyzer.
Distortion in the audio band is measured using an audio analyzer. Refer to audio measurement section for detail.
9.1.3 Slew Rate, Transient Response, Settling Time, Overdrive, Output Voltage, and Turn-On and TurnOff Time
The circuit shown in Figure 69 is used to measure slew rate, transient response, settling time, overdrive
recovery, and output voltage swing. Turn-on and turn-off times are measured with 50 Ω input termination on the
PD input, by replacing the 0.22 µF capacitor with 49.9 Ω resistor.
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VIN+
RG
Input From 50-Ω
Test Equipment
RF
PD
RIT
RO
VOUT–
RO
VOUT+
VS+
+
0.22 μF
VOCM
–
0.22 μF
VIN–
THS4531
VS–
RG
No Connection
RF
Output to
Test Equipment
RIT
0.22 μF
Installed to Balance
Amplifier
Output to
Test Equipment
49.9 Ω
Figure 69. Slew Rate, Transient Response, Settling Time, ZO, Overdrive Recovery, VOUT Swing, and TurnOn and Trun-Off Test Circuit
9.1.4 Common-Mode and Power Supply Rejection
The circuit shown in Figure 70 is used to measure the CMRR. The signal from the network analyzer is applied
common-mode to the input.
VIN+
RG
Input From 50-Ω
Test Equipment
RF
VS+
+
VOCM
–
0.22 μF
VS–
VIN–
RO
VOUT–
THS4531
ROT
Measure With
Diff Probe
VOUT+
RG
RO
No Connection
RIT
RF
Cal Diff Probe
Figure 70. CMRR Test Circuit
Figure 71 is used to measure the PSRR of VS+ and VS-. The power supply is applied to the network analyzer’s
DC offset input. For both CMRR and PSRR, the output is probed using a high impedance differential probe
across ROT.
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Power
Supply
Network
Analyzer
Cal Diff Probe
VIN+
RF
RG
RO
No Connection
VS+
RIT
VOUT–
+
VOCM
0.22 μF
VIN–
VS–
Measure With
Diff Probe
ROT
THS4531
–
VOUT+
RG
RO
No Connection
RF
RIT
Figure 71. PSRR Test Circuit
9.1.5 VOCM Input
The circuit shown in Figure 72 is used to measure the transient response, frequency response and input
impedance of the VOCM input. For these tests, the cal point is across the 49.9 Ω VOCM termination resistor.
Transient response and frequency response are measured with RCM = 0 Ω and using a high impedance
differential probe at the summing junction of the two RO resistors, with respect to ground. The input impedance is
measured using a high impedance differential probe at the VOCM pin and the drop across RCM is used to calculate
the impedance seen looking into the amplifier’s VOCM input.
VIN+
RG
RF
RO
No Connection
RIT
VS+
VOCM
RCM
From Network
Analyzer
+
VOCM
-
For ZIN
Measure With
Diff Probe Here
49.9
Cal Diff Probe
VIN±
VOUT±
For BW
Measure With
Diff Probe Here
THS4531
VOUT+
VS±
RG
RO
No Connection
RF
RIT
NC
Figure 72. VOCM Input Test Circuit
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9.1.6 Balance Error
The circuit shown in Figure 73 is used to measure the balance error of the main differential amplifier. A network
analyzer is used as the signal source and the measurement device. The output impedance of the network
analyzer is 50 Ω and is DC coupled. RIT and RG are chosen to impedance match to 50 Ω and maintain the
proper gain. To balance the amplifier, a 49.9 Ω resistor to ground is inserted across RIT on the alternate input.
The output is measured using a high impedance differential probe at the summing junction of the two RO
resistors, with respect to ground.
VIN+
RG
Input From 50-Ω
Test Equipment
RF
RIT
VS+
Cal Diff Probe
+
VOCM
–
0.22 μF
VS–
VIN-
RO
VOUT–
Measure With
Diff Probe Here
THS4531
VOUT+
RG
RO
No Connection
RF
49.9 Ω
RIT
Installed to Balance
Amplifier
Figure 73. Balance Error Test Circuit
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9.2 Application Circuits
The following circuits show application information for the THS4531. For simplicity, power supply decoupling
capacitors are not shown in these diagrams – please see the EVM and Layout Recommendations section for
recommendations. For more detail on the use and operation of fully differential op amps refer to application
report Fully-Differential Amplifiers SLOA054D.
9.2.1 Differential Input to Differential Output Amplifier
The THS4531 is a fully differential op amp and can be used to amplify differential input signals to differential
output signals. A basic block diagram of the circuit is shown in Figure 74 (VOCM and PD inputs not shown). The
gain of the circuit is set by RF divided by RG.
RF
RG
VIN+
VOUT±
Differential
Input
Differential
Output
VS+
+
THS4531
±
VS±
RG
RF
VIN±
VOUT+
Figure 74. Differential Input to Differential Output Amplifier
9.2.2 Single-Ended Input to Differential Output Amplifier
The THS4531 can also be used to amplify and convert single-ended input signals to differential output signals. A
basic block diagram of the circuit is shown in Figure 75 (VOCM and PD inputs not shown). The gain of the circuit
is again set by RF divided by RG.
RG
RF
VIN+
VOUT–
Single-Ended
Input
Differential
Output
VS+
+
THS4531
–
VS–
RG
RF
VOUT+
Figure 75. Single-Ended Input to Differential Output Amplifier
9.2.3 Differential Input to Single-Ended Output Amplifier
Fully differential op amps like the THS4531 are not recommended for differential to single-ended conversion.
This application is best performed with an instrumentation amplifier or with a standard op amp configured as a
classic differential amplifier. See application section of the OPA835 data sheet (SLOS713).
30
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Application Circuits (continued)
9.2.4 Input Common-Mode Voltage Range
The input common-model voltage of a fully differential op amp is the voltage at the + and – input pins of the op
amp.
It is important to not violate the input common-mode voltage range (VICR) of the op amp. Assuming the op amp is
in linear operation the voltage across the input pins is only a few millivolts at most. So finding the voltage at one
input pin will determine the input common-mode voltage of the op amp.
Treating the negative input as a summing node, the voltage is given by:
æ
RG
ç VOUT+ ´
R
G + RF
è
ö æ
RF ö
÷ + ç VIN- ´
÷
R
G + RF ø
ø è
(1)
To determine the VICR of the op amp, the voltage at the negative input is evaluated at the extremes of VOUT+.
As the gain of the op amp increases, the input common-mode voltage becomes closer and closer to the input
common-mode voltage of the source.
9.2.5 Setting the Output Common-Mode Voltage
The output common-model voltage is set by the voltage at the VOCM pin and the internal circuit works to maintain
the output common-mode voltage as close as possible to this voltage. If left unconnected, the output commonmode is set to mid-supply by internal circuitry, which may be over-driven from an external source. Figure 76 is
representative of the VOCM input. The internal VOCM circuit has about 24 MHz of -3 dB bandwidth, which is
required for best performance, but it is intended to be a DC bias input pin. Bypass capacitors are recommended
on this pin to reduce noise. The external current required to overdrive the internal resistor divider is given
approximately by the formula:
IEXT =
2VOCM - (VS+ - VS- )
1.25 MΩ
(2)
where VOCM is the voltage applied to the VOCM pin.
VS+
Internal
VOCM Circuit
625 kΩ
IEXT
VOCM
625 kΩ
VS–
Figure 76. Simplified VOCM Input Circuit
9.2.6 Single-Supply Operation
To facilitate testing with common lab equipment, the THS4531 EVM is built to allow for split-supply operation and
most of the data presented in this data sheet was taken with split-supply power inputs. But the device is
designed for use with single-supply power operation and can easily be used with single-supply power without
degrading the performance. The only requirement is to bias the device properly and the specifications in this data
sheet are given for single supply operation.
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Application Circuits (continued)
9.2.7 Low Power Applications and the Effects of Resistor Values on Bandwidth
The THS4531 is designed for the nominal value of RF to be 2 kΩ. This gives excellent distortion performance,
maximum bandwidth, best flatness, and best pulse response. It also loads the amplifier. For example, in gain of 1
with RF = RG = 2 kΩ, RG to ground, and VOUT+ = 4 V, 1 mA of current will flow through the feedback path to
ground. In low power applications, it is desirable to reduce this current by increasing the gain setting resistors
values. Using larger value gain resistors has two primary side effects (other than lower power) due to their
interaction with the device and PCB parasitic capacitance:
1. Lowers the bandwidth.
2. Lowers the phase margin
a. This will cause peaking in the frequency response.
b. And will cause over shoot and ringing in the pulse response.
Figure 77 shows the small signal frequency response for gain of 1 with RF and RG equal to 2 kΩ, 10 kΩ, and 100
kΩ. The test was done with RL = 2 kΩ. Due to loading effects of RL, lower values may reduce the peaking, but
higher values will not have a significant effect.
As expected, larger value gain resistors cause lower bandwidth and peaking in the response (peaking in
frequency response is synonymous with overshoot and ringing in pulse response).
9
VOUT = 100 mVPP
6
3
Gain (dB)
0
−3
−6
−9
−12
−15
−18
−21
100k
RF = 2 kΩ
RF = 10 kΩ
RF = 100 kΩ
1M
10M
Frequency (Hz)
100M
G067
Figure 77. THS4531 Frequency Response with Various Gain Setting Resistor Values
9.2.8 Driving Capacitive Loads
The THS4531 is designed for a nominal capacitive load of 2 pF (differentially). When driving capacitive loads
greater than this, it is recommended to use small resisters (RO) in series with the output as close to the device as
possible. Without RO, capacitance on the output will interact with the output impedance of the amplifier causing
phase shift in the loop gain of the amplifier that will reduce the phase margin resulting in:
1. Peaking in the frequency response.
2. Overshoot, undershoot, and ringing in the time domain response with a pulse or square-wave signal.
3. May lead to instability or oscillation.
Inserting RO will compensate the phase shift and restore the phase margin, but it will also limit bandwidth. The
circuit shown in Figure 69 is used to test for best RO versus capacitive loads, CL, with a capacitance placed
differential across the VOUT+ and VOUT- along with 2 kΩ load resistor, and the output is measure with a differential
probe. Figure 78 shows the optimum values of RO versus capacitive loads, CL, and Figure 79 shows the
frequency response with various values. Performance is the same on both 2.7 V and 5 V supply.
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Application Circuits (continued)
200
RO (Ω)
100
10
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
1
1
10
100
CLOAD (pF)
1k
2k
G068
Figure 78. Recommended Series Output Resistor vs Capacitive Load for Flat Frequency Response
3
0
Gain (dB)
−3
−6
−9
−12
−15
−18
−21
100k
VS = 2.7 V
G = 1 V/V
RF = 2 kΩ
RL = 2 kΩ
VOUT = 100 mVpp
CL = 0 pF, RO = 0 Ω
CL = 15 pF, RO = 200 Ω
CL = 39 pF, RO = 100 Ω
CL = 120 pF, RO = 50 Ω
CL = 470 pF, RO = 20 Ω
CL = 1200 pF, RO = 12 Ω
1M
10M
Frequency (Hz)
100M
G069
Figure 79. Frequency Response for Various RO and CL Values
9.2.9 Audio Performance
The THS4531 provides excellent audio performance with very low quiescent power. To show performance in the
audio band, the device was tested with an audio analyzer. THD+N and FFT tests were run at 1 Vrms output
voltage. Performance is the same on both 2.7 V and 5 V supply. Figure 80 is the test circuit used, and Figure 81
and Figure 82 show performance of the analyzer. In the FFT plot the harmonic spurs are at the testing limit of the
analyzer, which means the THS4531 is actually much better than can be directly measured. Because the
THS4531 distortion performance cannot be directly measured in the audio band it is estimated from
measurement in high noise gain configuration correlated with simulation.
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Application Circuits (continued)
RG
10
RF
VIN–
VOUT–
100 pF
VS+
+
From Analyzer
VOCM
THS4531
To Analyzer
–
0.22 μF
RG
10
VOUT+
VIN+
RF
100 pF
Figure 80. THS4531 Audio Analyzer Test Circuit
−95
VS = 5 V
G = 1 V/V
VOUT = 1 VRMS
RF = 2 kΩ
RL = 600 Ω
No Weighting
A−Weighting
−97
−99
THD+N (dB)
−101
−103
−105
−107
−109
−111
−113
−115
0
5k
10k
15k
Frequency (Hz)
20k
24k
G070
Magnitude (dBV)
Figure 81. THD+N on Audio Analyzer, 10 Hz to 24 kHz
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
VS = 5 V
G = 1 V/V
VOUT = 1 VRMS
RF = 2 kΩ
RL = 600 Ω
0
5k
10k
15k
Frequency (Hz)
20k
24k
G071
Figure 82. 1 kHz FFT Plot on Audio Analyzer
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Application Circuits (continued)
9.2.10 Audio On and Off Pop Performance
The THS4531 is tested to show on and off pop performance by connecting a speaker between the differential
outputs and switching on and off the power supply, and also by using the power down function of the THS4531.
Testing was done with and without tones. During these tests no audible pop could be heard.
5
2.5
4
2
VS = 5 V
G = 2 V/V
RF = 2 kΩ
RL = 200 Ω
3
1
2
1
0
1.5
0
50m
100m
Time (s)
Output Voltage (V)
Power Supply (V)
With no input tone, Figure 83 shows the voltage waveforms when switching power on to the THS4531 and
Figure 84 shows voltage waveforms when turning power off. The transients during power on and off show no
audible pop should be heard.
Power Supply 0.5
VOUT +
VOUT −
0
150m
200m
G072
Figure 83. Power Supply Turn On Pop Performance
Power Supply (V)
4
VS = 5 V
G = 2 V/V
RF = 2 kΩ
RL = 200 Ω
3
1.5
2
1
1
0.5
0
0
50m
100m
Time (s)
150m
Output Voltage (V)
2.5
Power Supply
VOUT +
VOUT −
2
5
0
200m
G073
Figure 84. Power Supply Turn Off Pop Performance
With no input tone, Figure 85 shows the voltage waveforms using the PD pin to enable and disable the
THS4531. The transients during power on and off show no audible pop should be heard.
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Application Circuits (continued)
Power Down (V)
4
VS = 5 V
G = 2 V/V
RF = 2 kΩ
RL = 200 Ω
3
1.5
2
1
1
0.5
0
0
50m
100m
Time (s)
150m
Output Voltage (V)
2.5
Power Down
VOUT +
VOUT −
2
5
0
200m
G074
Figure 85. PD Enable Pop Performance
9.3 Audio ADC Driver Performance: THS4531 AND PCM4204 Combined Performance
To show achievable performance with a high performance audio ADC, the THS4531 is tested as the drive
amplifier for the PCM4204. The PCM4204 is a high-performance, four-channel analog-to-digital (A/D) converter
designed for professional and broadcast audio applications. The PCM4204 architecture utilizes a 1-bit deltasigma modulator per channel incorporating an advanced dither scheme for improved dynamic performance, and
supports PCM output data. The PCM4204 provides flexible serial port interface and many other advanced
features. Please refer to its data sheet for more information.
The PCM4204 EVM is used to test the audio performance of the THS4531 as a drive amplifier. The standard
PCM4204 EVM is provided with 4x OPA1632 fully differential amplifiers, which use the same pin out as the
THS4531. For testing, one of these amplifiers is replaced with a THS4531 device in same package (MSOP), gain
changed to 1 V/V, and power supply changed to single supply +5 V. Figure 86 shows the circuit. With single
supply +5 V supply the output common-mode of the THS4531 defaults to +2.5 V as required at the input of the
PCM4204. So the resistor connecting the VOCM input of the THS4531 to the input common-mode drive from the
PCM4204 is optional and no performance change was noted with it connected or removed. The EVM power
connections were modified by connecting positive supply inputs, +15 V, +5 VA and +5 VD, to a +5 V external
power supply (EXT +3.3 was not used) and connecting -15 V and all ground inputs to ground on the external
power supply so only one external +5 V supply was needed to power all devices on the EVM.
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Audio ADC Driver Performance: THS4531 AND PCM4204 Combined Performance (continued)
2 kΩ
1 nF
2 kΩ
40.2 Ω
VIN–
100 pF
5V
+
From Analyzer
VOUT–
THS4531
VOCM
–
0.22 μF
2.7 nF
PCM4204
To Analyzer
VOUT+
1 nF
2 kΩ
40.2 Ω
VIN+
100 pF
2 kΩ
Figure 86. THS4531 and PCM4204 Test Circuit
An audio analyzer is used to provide an analog audio input to the EVM and the PCM formatted digital output is
read by the digital input on the analyzer. Data was taken at fS = 96 kHz, and audio output uses PCM format.
Other data rates and formats are expected to show similar performance in line with that shown in the data sheet.
Figure 87 shows the THD+N vs Frequency with no weighting and Figure 88 shows an FFT with 1 kHz input tone.
Input signal to the PCM4204 for these tests is -0.5 dBFS. Table 6 summarizes results of testing using the
THS4531 + PCM4204 versus typical Data Sheet performance, and show it make an excellent drive amplifier for
this ADC.
−95
−97
THD+N (dBFS)
−99
−101
−103
−105
−107
−109
−111
−113
−115
20
100
1k
Frequency (Hz)
10k
20k
G075
Figure 87. THS4531 + PCM4204 THD+N vs Frequency with No Weighting
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Magnitude (dBFS)
Audio ADC Driver Performance: THS4531 AND PCM4204 Combined Performance (continued)
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
20
100
1k
Frequency (Hz)
10k
24k
G076
Figure 88. THS4531 + PCM4204 1 kHz FFT
Table 6. 1 kHz AC Analysis: Test Circuit versus PCM4204 Data Sheet Typical Specifications (fS = 96
kSPS)
CONFIGURATION
TONE
THD + N
THS4531 + PCM4204
1 kHz
-106 dB
PCM4204 data sheet (typical)
1 kHz
-103 dB
9.4 SAR ADC Performance
9.4.1 THS4531 and ADS8321 Combined Performance
To show achievable performance with a high performance SAR ADC, the THS4531 is tested as the drive
amplifier for the ADS8321. The ADS8321 is a 16-bit, SAR ADC that offers excellent AC and DC performance,
with ultra-low power and small size. The circuit shown in Figure 89 is used to test the performance. Data was
taken using the ADS8321 at 100 kSPS with input frequency of 10 kHz and signal levels 0.5 dB below full scale.
The FFT plot of the spectral performance is in Figure 90. A summary of the FFT analysis results are in Table 7
along with ADS8321 typical data sheet performance at fS = 100 kSPS. Please refer to its data sheet for more
information.
The standard ADS8321 EVM and THS4531 EVM are modified to implement the schematic in Figure 89 and used
to test the performance of the THS4531 as a drive amplifier. With single supply +5 V supply the output commonmode of the THS4531 defaults to +2.5 V as required at the input of the ADS8321 so the VOCM input of the
THS4531 simply bypassed to GND with 0.22 µF capacitor. The summary of results of the FFT analysis versus
typical data sheet performance shown in Table 7 show the THS4531 will make an excellent drive amplifier for
this ADC.
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SAR ADC Performance (continued)
2 kȍ
No Input
121 ȍ
2 kȍ
VIN–
100 pF
5V
49.9 ȍ
+
VOCM
–
0.22 ȝF
Single-Ended
Signal from
V
Generator and IN+
10 kHz BPF
220 pF
VOUT–
To Data
Analysis
2.2 nF
THS4531
ADS8321
VOUT+
2 kȍ
121 ȍ
2 kȍ
100 pF
220 pF
49.9 ȍ
Magnitude (dBFS)
Figure 89. THS4531 and ADS8321 Test Circuit
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
VS = 5 V
G = 1 V/V
RF = 2 kΩ
VOUT = −0.5 dBFS
0
10k
20k
30k
Frequency (Hz)
40k
50k
G078
Figure 90. THS4531 + ADS8321 1-kHz FFT
Table 7. 10 kHz FFT Analysis Summary
CONFIGURATION
TONE
SIGNAL
SNR
THD
SINAD
SFDR
THS4531 + ADS8321
10 kHz
-0.5 dBFS
87 dBc
-96 dBc
87 dBc
100 dBc
ADS8321 data sheet (typical)
10 kHz
-0.5 dBFS
87 dBc
-86 dBc
84 dBc
86 dBc
9.4.2 THS4531 and ADS7945 Combined Performance
To show achievable performance with a high performance SAR ADC, the THS4531 is tested as the drive
amplifier for the ADS7945. The ADS7945 is a 14-bit, SAR ADC that offers excellent AC and DC performance,
with low power and small size. The circuit shown in Figure 91 is used to test the performance. Data was taken
using the ADS7945 at 2MSPS with input frequency of 10 kHz and signal level 0.5 dB below full scale. The FFT
plot of the spectral performance is in Figure 92. A summary of the FFT analysis results are in Table 8 along with
ADS7945 typical data sheet performance at fS = 2 MSPS. Please refer to its data sheet for more information.
The standard ADS7945 EVM and THS4531 EVM are modified to implement the schematic in Figure 91 and used
to test the performance of the THS4531 as a drive amplifier. With single supply +5 V supply the output commonmode of the THS4531 defaults to +2.5 V as required at the input of the ADS7945 so the VOCM input of the
THS4531 simply bypassed to GND with 0.22 µF capacitor. The summary of results of the FFT analysis versus
typical data sheet performance shown in Table 8 show the THS4531 will make an excellent drive amplifier for
this ADC.
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2 kȍ
www.ti.com
40.2 ȍ
2 kȍ
VIN–
100 pF
Differential
Signal from
Generator and
10 kHz BPF
5V
+
To Data
Analysis
THS4531
VOCM
–
0.22 ȝF
VOUT–
1 nF
ADS7945
VOUT+
2 kȍ
2 kȍ
40.2 ȍ
VIN+
100 pF
Magnitude (dBFS)
Figure 91. THS4531 and ADS7945 Test Circuit
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
VS = 5 V
G = 1 V/V
RF = 2 kΩ
VOUT = −0.5 dBFS
1k
10k
100k
Frequency (Hz)
1M
G077
Figure 92. THS4531 and ADS7945 Test Circuit
Table 8. 10 kHz FFT Analysis Summary
CONFIGURATION
TONE
SIGNAL
SNR
THD
SFDR
THS4531 + ADS7945
10 kHz
-0.5 dBFS
83 dBc
-93 dBc
96 dBc
ADS7945 Data sheet (typical)
10 kHz
-0.5 dBFS
84 dBc
-92 dBc
94 dBc
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9.5 EVM and Layout Recommendations
The THS4531 EVM (SLOU334) should be used as a reference when designing the circuit board. It is
recommended to follow the EVM layout of the external components near to the amplifier, ground plane
construction, and power routing as closely as possible. General guidelines are:
1. Signal routing should be direct and as short as possible into and out of the op amp.
2. The feedback path should be short and direct avoiding vias if possible.
3. Ground or power planes should be removed from directly under the amplifier’s input and output pins.
4. A series output resistor is recommended to be placed as near to the output pin as possible. See Figure 78
Recommended Series Output Resistor vs. Capacitive Load for recommended values given expected
capacitive load of design.
5. A 2.2 µF power supply decoupling capacitor should be placed within 2 inches of the device and can be
shared with other op amps. For split supply, a capacitor is required for both supplies.
6. A 0.1 µF power supply decoupling capacitor should be placed as near to the power supply pins as possible.
Preferably within 0.1 inch. For split supply, a capacitor is required for both supplies.
7. The PD pin uses TTL logic levels referenced to the negative supply voltage (VS-). When not used it should
tied to the positive supply to enable the amplifier. When used, it must be actively driven high or low and
should not be left in an indeterminate logic state. A bypass capacitor is not required, but can be used for
robustness in noisy environments.
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10 Device and Documentation Support
10.1 Device Support
10.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
10.2 Documentation Support
For related documentation see the following:
• ADS7945 and ADS7946 14-Bit, 2 MSPS, Dual-Channel, Differential/Single-Ended, Ultra low-Power Analogto-Digital Converters, SBAS539
• ADS8321 16-Bit, High Speed, Micro Power Sampling Analog-to-Digital converter, SBAS123
• Extending Rail-to-Rail Output Range for Fully Differential Amplifiers to Include True Zero Volts, TIDU187
• Fully-Differential Amplifiers, SLOA054
• OPAx835 Ultra Low-Power, Rail-to-Rail Out, Negative Rail In, VFB Op Amp, SLOS713
• PCM4204 High-Performance 24-Bit, 216 kHz Sampling Four-Channel Audio Analog-to-Digital Converter,
SBAS327
• SN74AVC1T45 Single-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation and 3-State
Outputs, SCES530
• THS4531ADGKEVM Evaluation Module, SLOU356
10.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
10.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
THS4531ID
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T4531
THS4531IDGK
ACTIVE
VSSOP
DGK
8
80
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
4531
THS4531IDGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
4531
THS4531IDR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
T4531
THS4531IRUNR
ACTIVE
QFN
RUN
10
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
4531
THS4531IRUNT
ACTIVE
QFN
RUN
10
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
4531
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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