THS4551IRUNT

THS4551 SBOS778D – APRIL 2016 – REVISED THS4551 APRIL 2021 SBOS778D – APRIL 2016 – REVISED APRIL 2021 www.ti.com THS4551 Low-Noise, Precision, 150-MHz, Fully Differential Amplifier 1 Features 3 Description • • • • The THS4551 fully differential amplifier offers an easy interface from single-ended sources to the differential output required by high-precision analogto-digital converters (ADCs). Designed for exceptional dc accuracy, low noise, and robust capacitive load driving, this device is well suited for data acquisition systems where high precision is required along with the best signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) through the amplifier and ADC combination. • • • • • • • • • • Bandwidth: 150 MHz (G = 1 V/V) Differential Output Slew Rate: 220 V/µs Gain Bandwidth Product: 135 MHz Negative Rail Input (NRI), Rail-to-Rail Output (RRO) Wide Output Common-Mode Control Range Single-Supply Operating Range: 2.7 V to 5.4 V Trimmed-Supply Current: 1.37 mA at 5 V 25°C Input Offset: ±175 µV (max) Input Offset Voltage Drift: ±1.8 µV/°C (max) Differential Input Voltage Noise: 3.3 nV/√ Hz HD2: –128 dBc at 2 VPP, 100 kHz HD3: –139 dBc at 2 VPP, 100 kHz < 50-ns Settling Time: 4-V Step to 0.01% 18-Bit Settling Time: 4-V Step, < 500 ns 2 Applications • • • • • 24-Bit, Delta-Sigma (ΔΣ) ADC Drivers 16- to 20-Bit, Differential, High-Speed SAR Drivers Differential Active Filters Differential Transimpedance Amplifiers Pin-Compatible Upgrade to the THS4521 (VSSOP-8 only) The THS4551 features the negative rail input required when interfacing a dc-coupled, ground-centered, source signal to a single-supply differential input ADC. Very low dc error and drift terms support the emerging 16- to 20-bit successive-approximation register (SAR) input requirements. A wide-range output commonmode control supports the ADC running from 1.8V to 5-V supplies with ADC common-mode input requirements from 0.7 V to greater than 3.0 V. The THS4551 device is characterized for operation over the wide temperature range of –40°C to +125°C, and is available in 8-pin VSSOP, 16-pin VQFN, and 10-pin WQFN packages. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) THS4551 VSSOP (8) 3.00 mm × 3.00 mm WQFN (10) 2.00 mm × 2.00 mm VQFN (16) 3.00 mm × 3.00 mm (1) See the orderable addendum at the end of the data sheet for all available packages. 1.2 k 270 pF 1.2 k 1 nF VOCM 470 pF 330 + ± 3V 5 + ± 1.2 k THS4551 330 10 AINN 22 nF ADS127L01 AINP 5 10 270 pF 1.2 k Copyright © 2016, Texas Instruments Incorporated Simplified Schematic: Gain of 1 V/V, Single-Ended Input to Differential Output, 500-kHz, Multiple Feedback Filter Interface to the ADS127L01 An©IMPORTANT NOTICEIncorporated at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyright 2021 Texas Instruments Submit Document Feedback intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: THS4551 1 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Companion Devices........................................................ 4 6 Pin Configuration and Functions...................................5 7 Specifications.................................................................. 6 7.1 Absolute Maximum Ratings........................................ 6 7.2 ESD Ratings............................................................... 6 7.3 Recommended Operating Conditions.........................6 7.4 Thermal Information....................................................6 7.5 Electrical Characteristics: (VS+) – (VS–) = 5 V.............7 7.6 Electrical Characteristics: (VS+) – (VS–) = 3 V...........10 7.7 Typical Characteristics: (VS+) – (VS–) = 5 V.............. 13 7.8 Typical Characteristics: (VS+) – (VS–) = 3 V.............. 16 7.9 Typical Characteristics: 3-V to 5-V Supply Range.... 19 8 Parameter Measurement Information.......................... 23 8.1 Example Characterization Circuits............................23 8.2 Output Interface Circuit for DC-Coupled Differential Testing.......................................................25 8.3 Output Common-Mode Measurements.....................25 8.4 Differential Amplifier Noise Measurements...............26 8.5 Balanced Split-Supply Versus Single-Supply Characterization.......................................................... 26 8.6 Simulated Characterization Curves.......................... 26 8.7 Terminology and Application Assumptions............... 27 9 Detailed Description......................................................28 9.1 Overview................................................................... 28 9.2 Functional Block Diagram......................................... 28 9.3 Feature Description...................................................29 9.4 Device Functional Modes..........................................38 10 Application and Implementation................................ 42 10.1 Application Information........................................... 42 10.2 Typical Applications................................................ 49 11 Power Supply Recommendations..............................55 11.1 Thermal Analysis.....................................................56 12 Layout...........................................................................57 12.1 Layout Guidelines................................................... 57 12.2 Layout Example...................................................... 58 12.3 EVM Board..............................................................59 13 Device and Documentation Support..........................61 13.1 Device Support....................................................... 61 13.2 Documentation Support.......................................... 63 13.3 Receiving Notification of Documentation Updates..63 13.4 Support Resources................................................. 64 13.5 Trademarks............................................................. 64 13.6 Electrostatic Discharge Caution..............................64 13.7 Glossary..................................................................64 14 Mechanical, Packaging, and Orderable Information.................................................................... 64 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (July 2017) to Revision D (April 2021) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Added the Device Information table to the Description section.......................................................................... 1 • Moved the Low-Power ADCs Supported by the THS4551 table to the Device Comparison section................. 4 • Removed the IIB input bias current (positive current out-of-node) minimum limits in the Electrical Characteristics: (VS+) – (VS–) = 5 V section........................................................................................................7 • Removed the IIB input bias current (positive current out-of-node) minimum limits in the Electrical Characteristics: (VS+) – (VS–) = 3 V section......................................................................................................10 Changes from Revision B (November 2016) to Revision C (July 2017) Page • Changed 47k Ohms , 1.3 pF to 150k Ohms , 7 pF in the Section 7.6 table ...................................................... 1 Changes from Revision A (August 2016) to Revision B (November 2016) Page • Added second row and footnote 2 to Voltage parameter of Absolute Maximum Ratings table.......................... 6 • Added package differences and footnote 3 to ESD Ratings table......................................................................6 • Changed footnotes 1 and 2 in 5-V Electrical Characteristics table.....................................................................7 • Added test conditions to AOL parameter in 5-V Electrical Characteristics table................................................. 7 • Changed Input offset voltage drift parameter .................................................................................................... 7 • Changed IIB parameter minimum and maximum specifications in last three rows ............................................ 7 • Changed Input bias current drift parameter test conditions and specifications ................................................. 7 • Added Input offset current drift parameter test conditions, minimum and maximum specifications, and test level value to second row................................................................................................................................... 7 • Changed test conditions of Common-mode input, low and Common-mode input, high parameters .................7 • Changed test conditions of Continuous output current and Linear output current parameters ......................... 7 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com • • • • • • • • • • • • • • • • • • • • SBOS778D – APRIL 2016 – REVISED APRIL 2021 Changed test conditions of Enable voltage threshold and Disable voltage threshold parameters..................... 7 Changed specifications of Power-down quiescent current parameter ...............................................................7 Changed Common-mode loop supply headroom to negative supply parameter test conditions........................7 Changed test conditions and maximum specifications of Common-mode loop supply headroom to positive supply parameter................................................................................................................................................ 7 Added test conditions to DC Performance, AOL parameter.............................................................................. 10 Changed Input offset voltage drift parameter test conditions in first row, added second row...........................10 Changed minimum and maximum specifications in last three rows of IIB parameter....................................... 10 Changed Input bias current drift parameter test conditions.............................................................................. 10 Added second row to Input offset current drift parameter ................................................................................10 Changed test conditions of Common-mode input, low and Common-mode input, high parameters................10 Changed test conditions of Continuous output current and Linear output current parameters ....................... 10 Changed test conditions of Enable voltage threshold and Disable voltage threshold parameters................... 10 Changed IQ(PD) parameter specifications..........................................................................................................10 Changed Common-mode loop supply headroom to negative supply parameter test conditions......................10 Changed Common-mode loop supply headroom to positive supply parameter test conditions and maximum specifications ................................................................................................................................................... 10 Changed conditions of Figure 7-49 to Figure 7-54 .......................................................................................... 19 Changed Single-Ended Source to a Differential Gain of a 1-V/V Test Circuit figure.........................................23 Changed main Device Functional Modes section: changed value of PD pin voltage ......................................38 Changed the minimum value for single-supply operation in the Operating the Power Shutdown Feature section.............................................................................................................................................................. 45 Added SBOS476, SBOC466, SBOC463, SBOC467, SBOS460, SBOC477, SBOC472, SLOC341, SBOC469, SBOC462, SBOC461, SBOC465, SBOC464, SBOC475, SBOC474, SBOC471, SBOC459, SBOC470, SBOC468, and SBOC473 to Related Documentation section ........................................................................ 63 Changes from Revision * (April 2016) to Revision A (August 2016) Page • Released to production ......................................................................................................................................1 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 3 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 5 Companion Devices Low-Power ADCs Supported by the THS4551 PART NUMBER 4 ADC TYPE RESOLUTION, SPEED ADS127L01 Delta sigma 24 bits, 0.512 MSPS ADS8881 SAR 18 bits, 1 MSPS ADS9110 SAR 18 bits, 2 MSPS ADC3241 Pipeline 14 bits, 25 MSPS Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 6 Pin Configuration and Functions VS+ IN- 8 1 10 IN+ OUT– 1 9 OUT+ VOCM 2 7 PD NC 2 8 NC VS+ 3 6 VS- PD 3 7 VOCM OUT+ 4 5 OUT- IN+ 4 6 IN– 5 VS– Figure 6-1. DGK Package 8-Pin VSSOP Top View VS– VS– VS– VS– Figure 6-2. RUN Package 10-Pin WQFN Top View 16 15 14 13 IN+ 2 11 OUT– IN– 3 10 OUT+ FB+ 4 9 VOCM 5 6 7 8 VS+ PD VS+ 12 VS+ 1 VS+ FB– Figure 6-3. RGT Package 16-Pin VQFN With Exposed Thermal Pad Top View Table 6-1. Pin Functions PIN NAME NO. I/O DESCRIPTION RGT(1) RUN DGK 1 — — O FB+ 4 — — O Noninverting (positive) output feedback IN– 3 6 1 I Inverting (negative) amplifier input Noninverting (positive) amplifier input FB– IN+ 2 4 8 I NC — 2, 8 — — Inverting (negative) output feedback No internal connection OUT– 11 1 5 O Inverting (negative) amplifier output OUT+ 10 9 4 O Noninverting (positive) amplifier output PD 12 3 7 I Power down. PD = logic low = power off mode; PD = logic high = normal operation. VOCM 9 7 2 I Common-mode voltage input VS– 13-16 5 6 I Negative power-supply input VS+ 5, 6, 7, 8 10 3 I Positive power-supply input (1) Solder the exposed thermal pad (RGT package) to a heat-spreading power or ground plane. This pad is electrically isolated from the die, but it must be connected to a power or ground plane and not floated. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 5 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT 5.5 V ±1 V/µs Supply voltage, (VS+) – (VS–) Supply turn-on/off maximum Voltage dV/dT(2) Input/output voltage range (VS+) + 0.5 Differential input voltage ±1 Continuous input current ±10 Continuous output Current (VS–) – 0.5 current(3) See the Section 7.4 and Section 11.1 sections Maximum junction (1) (2) (3) mA ±20 Continuous power dissipation Temperature V 150 Operating free-air, TA –40 125 Storage, Tstg –65 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Staying below this ± supply turn-on edge rate ensures that the edge-triggered ESD absorption device across the supply pins remains off. Long-term continuous current for electro-migration limits. 7.2 ESD Ratings VALUE UNIT A. THS4551 in DGK, RUN Pacakges V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1250 Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) (3) ±1000 V B. THS4551 in RGT Package V(ESD) (1) (2) (3) Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22-C101(2) V ±1250 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. ESD limit of ±1000 V for any pin to thermal pad. Pin-to-pin HBM ESD specifications are rated at ±2500 V. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX VS+ Single-supply positive voltage 2.7 5 5.4 UNIT V TA Ambient temperature –40 25 125 °C 7.4 Thermal Information THS4551 THERMAL METRIC(1) 6 RGT(2) (VQFN) RUN (WQFN) DGK (VSSOP) 16 PINS 10 PINS 8 PINS UNIT RθJA Junction-to-ambient thermal resistance 54 142 185 °C/W RθJC(top) Junction-to-case (top) thermal resistance 72 78 76 °C/W Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 THS4551 THERMAL METRIC(1) RGT(2) (VQFN) RUN (WQFN) DGK (VSSOP) 16 PINS 10 PINS 8 PINS UNIT RθJB Junction-to-board thermal resistance 28 97 106 °C/W ψJT Junction-to-top characterization parameter 3.2 9.7 13 °C/W ψJB Junction-to-board characterization parameter 28 97 105 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 12 N/A N/A °C/W (1) (2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal impedance for RGT reported with backside thermal pad soldered to heat spreading plane. 7.5 Electrical Characteristics: (VS+) – (VS–) = 5 V at TA ≈ 25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL(1) AC PERFORMANCE VOUT = 20 mVPP, G = 1, peaking (< 1.0 dB) SSBW Small-signal bandwidth 150 C MHz VOUT = 20 mVPP, G = 2 75 VOUT = 20 mVPP, G = 10 15 C 135 MHz C C GBP Gain-bandwidth product VOUT = 20 mVPP, G = 100 LSBW Large-signal bandwidth VOUT = 2 VPP, G = 1 37 MHz C Bandwidth for 0.1-dB flatness VOUT = 2 VPP, G = 1 15 MHz C 220 V/µs C rate(2) SR Slew tR, tF Rise and fall time tSETTLE Settling time Overshoot and undershoot HD2 HD3 Second-order harmonic distortion Third-order harmonic distortion VOUT = 4 VPP, full-power bandwidth (FPBW), RL = 1 kΩ VOUT = 0.5-V step, G = 1, input tR = 2 ns 6 To 0.1%, VOUT = 0.5-V step, input tR = 2 ns, G = 1 30 To 0.01%,VOUT = 0.5-V step, input tR = 2 ns, G = 1 50 VOUT = 0.5-V step G = 1, input tR = 2 ns ns ns C C C 8% C f = 100 kHz, VOUT = 2 VPP, G = 1, RL = 1 kΩ –128 C f = 100 kHz, VOUT = 8 VPP, G = 1, RL = 1 kΩ –124 f = 100 kHz, VOUT = 2 VPP, G = 1, RL = 1 kΩ –139 f = 100 kHz, VOUT = 8 VPP, G = 1, RL = 1 kΩ –131 dBc dBc C C C Input voltage noise f > 500 Hz, 1/f < 150 Hz 3.3 nV/√ Hz C Input current noise f > 20 kHz, 1/f 90-dB CMRR at input range limits TA = 25°C (VS–) – 0.2 (VS–) – 0.1 TA = –40°C to +125°C (VS–) – 0.1 Common-mode input, high > 90-dB CMRR at input range limits TA = 25°C (VS+) – 1.2 (VS+) – 1.1 TA = –40°C to +125°C (VS+) – 1.3 (VS+) – 1.2 Common-mode rejection ratio Input pins at [(VS+) – (VS–)] / 2 93 Input impedance differential mode Input pins at [(VS+) – (VS–)] / 2 VS– V V 110 100 || 1.2 A B A B dB A kΩ || pF C OUTPUT TA = 25°C (VS–) + 0.2 Output voltage, low TA = –40°C to +125°C Output voltage, high TA = –40°C to +125°C Linear output current (VS–) + 0.22 (VS+) – (VS+) – 0.2 0.23 TA = 25°C Continuous output current (VS–) + 0.2 (VS–) + 0.23 ±60 TA = –40°C to +125°C, ±2.1 V, RL= 40 Ω, VOCM offset < ±20 mV ±50 TA = 25°C, ±2.1 V, RL= 50 Ω, AOL > 80 dB ±40 B A V (VS+) – (VS+) – 0.2 0.22 TA = 25°C, ±2.5 V, RL= 40 Ω, VOCM offset < ±20 mV A V B ±65 A mA B ±45 A mA TA = –40°C to +125°C, ±1.6 V, RL= 50 Ω, AOL > 80 dB ±30 2.7 5 5.4 TA ≈ 25°C(7), VS+ = 5 V 1.28 1.37 1.44 TA = –40°C to +125°C, VS+ = 5 V 0.97 B POWER SUPPLY Specified operating voltage IQ Quiescent operating current dIQ/dT Quiescent current temperature coefficient ±PSRR Power-supply rejection ratio 1.92 VS+ = 5 V 2.4 3.9 Either supply pin to differential VOUT 93 110 5.4 V mA B A B µA/°C B dB A V A POWER-DOWN Enable voltage threshold Specified on above (VS–) + 1.15 V Disable voltage threshold Specified off below (VS–) + 0.55 V Disable pin bias current PD = VS– → VS+ Power-down quiescent current 8 (VS–) + 1.15 –100 –2 (VS–) + 0.55 V A ±10 100 nA B 1 5 µA A tON Turn-on time delay Time from PD = low to VOUT = 90% of final value 700 ns C tOFF Turn-off time delay Time from PD = low to VOUT = 10% of final value 100 ns C Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 7.5 Electrical Characteristics: (VS+) – (VS–) = 5 V (continued) at TA ≈ 25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL(1) OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL(4) (See Figure 8-5) SSBW Small-signal bandwidth VOCM = 100 mVPP at the control pin LSBW Large-signal bandwidth VOCM = 1 VPP at the control pin 40 MHz C 8 MHz C SR Slew rate(2) Output common-mode noise (≥ 2 kHz) From 1-VPP LSBW 18 V/µs C VOCM pin driven from low impedance 15 nV/√ Hz C Gain VOCM control pin input to output average voltage (see Figure 8-5) Input bias current DC output balance (differential mode to common-mode output) SSBW Output balance LSBW 0.997 0.999 1.001 V/V A –100 ±10 100 nA A dB C VOUT = ±1 V 85 VOUT = 100 mVPP (output balance drops –3 dB from the 85-dB dc level) 300 VOUT = 2 VPP (output balance drops –3 dB from the 85-dB dc level) 300 Input impedance (VOCM pin input) Default voltage offset from [(VS+) – (VS–)] / 2 C kHz C 150 || 7 VOCM pin open VOCM pin open, TA = –40°C to +125°C kΩ || pF C –12 ±2 12 mV A 15 35 55 µA/°C B –5.0 ±1 OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL (continued) TA = 25°C CM VOS Common-mode offset voltage VOCM pin driven to [(VS+) – (VS–)] / 2 Common-mode offset voltage drift(3) TA = –40°C to +125°C Common-mode loop supply headroom to negative supply < ±15-mV shift from midsupply CM VOS 5.0 A –5.25 5.5 B TA = –40°C to +85°C –5.7 5.6 TA = –40°C to +125°C –5.7 6.0 TA = 0°C to +70°C –10 TA = 25°C Common-mode loop supply headroom to positive supply (1) (2) (3) (4) (5) (6) (7) < ±15-mV shift from midsupply CM VOS TA = 0°C to +70°C ±2 10 mV B B µV/°C B 0.55 A 0.6 B V TA = –40°C to +85°C 0.65 TA = –40°C to +125°C 0.7 B TA = 25°C 1.2 A TA = 0°C to 70°C 1.25 TA = –40°C to +85°C 1.3 TA = –40°C to +125°C 1.3 V B B B B Test levels (all values set by characterization and simulation): (A) 100% tested at TA ≈ 25°C. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information. This slew rate is the average of the rising and falling time estimated from the sinusoidal large-signal bandwidth as: (VP / √ 2) × 2π × f–3dB. Input offset voltage drift, input bias current drift, and input offset current drift are the mean ±1-sigma values calculated by taking measurements at the maximum-range ambient temperature end points, computing the difference, and dividing by the temperature range. Maximum drift specifications are set by mean ±4 σ on the device distributions tested over a –40°̊C to +125°̊C ambient temperature range. Drift is not specified by final ATE testing or QA sample test. Specifications are from the input VOCM pin to the differential output average voltage. Currents out of pin are treated as a positive polarity (with the exception of the power-supply pins). Trace mismatch measurement is dominated by the variation in contactor resistance. Internal mismatch is less than 0.1 Ω. TA = 25°C and ICC ≈ 1.37 mA. The test limit is expanded for the ATE ambient range of 22°C to 32°C with a 4-µA/°C ICC temperature coefficient considered; see Figure 11-1. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 9 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 7.6 Electrical Characteristics: (VS+) – (VS–) = 3 V at TA ≈ 25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL(1) AC PERFORMANCE VOUT = 20 mVPP, G = 1, peaking (< 1.0 dB) SSBW Small-signal bandwidth 150 C VOUT = 20 mVPP, G = 2 80 MHz VOUT = 20 mVPP, G = 10 14 C 130 MHz C C C GPB Gain-bandwidth product VOUT = 20 mVPP, G = 100 LSBW Large-signal bandwidth VOUT = 1 VPP, G = 1 45 MHz Bandwidth for 0.1-dB flatness VOUT = 1 VPP, G = 1 14 MHz C SR Slew rate(2) VOUT = 1 VPP, FPBW, G = 1 110 V/µs C tR, tF Rise and fall time ns tSETTLE Settling time Overshoot and undershoot HD2 HD3 Second-order harmonic distortion Third-order harmonic distortion VOUT = 0.5-V step, G = 1, input tR = 4 ns 7.0 To 0.1%, VOUT = 0.5-V step, input tR = 4 ns, G = 1 35 To 0.01%, VOUT = 0.5-V step, input tR = 4 ns, G = 1 55 VOUT = 0.5-V step, G = 1, input tR = 4 ns ns C C C 7% C f = 100 kHz, VOUT = 2 VPP, G = 1, RL = 1 kΩ –128 C f = 100 kHz, VOUT = 4 VPP, G = 1, RL = 1 kΩ –127 f = 100 kHz, VOUT = 2 VPP, G = 1, RL = 1 kΩ –139 f = 100 kHz, VOUT = 4 VPP, G = 1, RL = 1 kΩ –125 dBc dBc C C C Input voltage noise f > 500 Hz, 1/f < 150 Hz 3.4 nV/√ Hz C Input current noise f > 20 kHz, 1/f < 10 kHz 0.5 pA/√ Hz C Overdrive recovery time G = 2, 2X output overdrive, dc coupled 100 ns C Closed-loop output impedance f = 100 kHz (differential), G = 1 0.02 Ω C DC PERFORMANCE(5) AOL Open-loop voltage gain Internal feedback trace resistance ±2-V differential to 1-kΩ differential load 100 120 TA = 25°C, RGT only (pins 11-1, 10-4) 3.0 3.45 –1 0.05 TA = 25°C –175 ±40 TA = 0°C to +70°C –225 265 TA = –40°C to +85°C –295 295 TA = –40°C to +125°C –295 375 TA = –40°C to +125°C, temperature drift (6) Internal feedback trace resistance TA = 25°C, RGT only (pins 11-1, 10-4) mismatch T = –40°C to +125°C, temperature drift 50 Input-referred offset voltage Input offset voltage drift(3) IIB Input bias current IOS drift(3) Input offset current Input offset current drift(3) 10 dB A Ω A mΩ/°C B Ω A µΩ/°C 175 B A µV B B B TA = –40°C to +125°C (DGK package) –2.0 ±0.45 2.0 TA = –40°C to +125°C (RUN package) –1.7 ±0.4 1.7 TA = –40°C to +125°C (RGT package) –1.8 ±0.4 1.8 1.0 1.5 A TA = 0°C to +70°C 1.73 B TA = –40°C to +85°C 1.80 TA = –40°C to +125°C 2.0 TA = 25°C Input bias current (positive current out of node) 1 50 A VIO 4.7 TA = –40°C to +125°C B µV/°C B B µA B B 2 3.3 5.5 TA = 25°C –50 ±10 50 A TA = 0°C to +70°C –57 63 B TA = –40°C to +85°C –68 67 TA = –40°C to +125°C –68 78 TA = –40°C to +125°C (DGK package) –280 ±70 280 TA = –40°C to +125°C (RGT and RUN package) –120 ±20 120 Submit Document Feedback nA/°C nA B B B pA/°C B B Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 7.6 Electrical Characteristics: (VS+) – (VS–) = 3 V (continued) at TA ≈ 25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL(1) INPUT CMRR Common-mode input, low > 87-dB CMRR at input range limits TA = 25°C (VS–) – 0.2 (VS–) – 0.1 TA = –40°C to +125°C (VS–) – 0.1 Common-mode input, high > 87-dB CMRR at input range limits TA = 25°C (VS+) – 1.2 (VS+) –1.1 TA = –40°C to +125°C (VS+) – 1.3 (VS+) –1.2 Common-mode rejection ratio Input pins at [(VS+) – (VS–)] / 2 90 Input impedance differential mode Input pins at [(VS+) – (VS–)] / 2 VS– V V 110 100 || 1.2 A B A B dB A kΩ || pF C OUTPUT TA = 25°C VOL (VS–) + 0.2 Output voltage, low TA = –40°C to +125°C (VS–) + 0.2 Output voltage, high Linear output current ±1.5 V, RL = 40 Ω, VOCM offset < ±20 mV TA = 25°C ±1.3 V, RL = 40 Ω, VOCM offset < ±20 mV TA = –40°C to +125°C ±30 ±1.5 V, RL = 50 Ω, AOL > 80 dB TA = 25°C ±28 ±1.1 V, RL = 50 Ω, AOL > 80 dB TA = –40°C to +125°C ±35 A V B A V (VS+) – (VS+) – 0.2 0.22 TA = –40°C to +125°C Continuous output current (VS–) + 0.22 (VS+) – (VS+) – 0.2 0.21 TA = 25°C VOH (VS–) + 0.21 B ±40 A mA B ±35 A mA ±20 B POWER SUPPLY Specified operating voltage IQ Quiescent operating current dIQ/dT Quiescent current temperature coefficient ±PSRR Power-supply rejection ratio TA ≈ 25°C(7), VS+ = 3 V TA = –40°C to +125°C, VS+ = 3 V 2.7 3 5.4 1.24 1.31 1.40 0.96 1.84 VS+ = 3 V 2.0 3.4 Either supply pin to differential VOUT 90 105 5.0 V mA B A B µA/°C B dB A V A POWER-DOWN Enable voltage threshold Specified on above (VS–) + 1.15 V Disable voltage threshold Specified off below (VS–) + 0.55 V Disable pin bias current PD = VS– → VS+ (VS–) + 1.15 –100 –2 (VS–) + 0.55 V A ±10 100 nA B 1 5 IQ(PD) Power-down quiescent current µA A tON Turn-on time delay Time from PD = low to VOUT = 90% of final value 750 ns C tOFF Turn-off time delay Time from PD = low to VOUT = 10% of final value 150 ns C OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL(4) (See Figure 8-5) SSBW Small-signal bandwidth VOCM = 100 mVPP at the control pin LSBW Large-signal bandwidth VOCM = 1 VPP at the control pin SR Slew rate(2) From 1-VPP LSBW Output common-mode noise VOCM pin driven from low impedance, f ≥ 2 kHz Gain VOCM control pin input to output average voltage (see Figure 8-5) DC output balance (differential mode to common-mode output) VOUT = ±1 V SSBW Output balance LSBW 0.997 40 MHz C 8 MHz C 12 V/µs C 15 nV/√ Hz 0.999 1.001 85 dB VOUT = 100 mVPP (output balance drops –3 dB from the 85-dB dc level) 300 VOUT = 1 VPP (output balance drops –3 dB from the 85-dB dc level) 300 V/V A C C kHz C Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 11 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 7.6 Electrical Characteristics: (VS+) – (VS–) = 3 V (continued) at TA ≈ 25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit PARAMETER TEST CONDITIONS Input bias current MIN TYP MAX UNIT TEST LEVEL(1) –100 ±10 100 nA A Input impedance Default voltage offset from [(VS+) – (VS–)] / 2 150 || 7 VOCM pin open VOCM pin open, TA = –40°C to +125°C kΩ || pF C –12 ±2 12 mV A 15 35 55 µA/°C B –5.0 ±1 OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL (continued) TA = 25°C CM VOS Common-mode offset voltage VOCM input driven to [(VS+) TA = 0°C to +70°C – (VS–)] / 2 T = –40°C to +85°C A TA = –40°C to +125°C Common-mode offset voltage drift(3) VOCM input driven to [(VS+) – (VS–)] / 2 TA = 25°C Common-mode loop supply headroom to negative supply < ±15-mV shift from midsupply CM VOS TA = 0°C to +70°C (1) (2) (3) (4) (5) (6) (7) 12 < ±15-mV shift from midsupply CM VOS A 5.5 B –5.7 5.6 –5.7 6.0 –10 ±2 10 0.6 TA = –40°C to +85°C 0.65 0.7 TA = 0°C to +70°C mV B B µV/°C 0.55 TA = –40°C to +125°C TA = 25°C Common-mode loop supply headroom to positive supply 5.0 –5.25 B A V B B B 1.2 A 1.25 B TA = –40°C to +85°C 1.3 TA = –40°C to +125°C 1.3 V B B Test levels (all values set by characterization and simulation): (A) 100% tested at TA ≈ 25°C. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information. This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (VPP / √ 2) × 2π × f–3dB. Input offset voltage drift, input bias current drift, and input offset current drift are the mean ±1-sigma values calculated by taking measurements at the maximum-range ambient temperature end points, computing the difference, and dividing by the temperature range. Maximum drift specifications are set by mean ±4 σ on the device distributions tested over a –40°̊C to +125°̊C ambient temperature range. Drift is not specified by final ATE testing or QA sample test. Specifications are from input VOCM pin to differential output average voltage. Currents out of pin are treated as a positive polarity (with exception of the power-supply pin currents). Trace mismatch measurement is dominated by the variation in contactor resistance. Internal mismatch is less than 0.1 Ω. TA = 25°C and ICC ≈ 1.31 mA. The test limit is expanded for the ATE ambient range of 22°C to 32°C with a 4-µA/°C ICC temperature coefficient considered; see Figure 11-1. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 7.7 Typical Characteristics: (VS+) – (VS–) = 5 V at TA ≈ 25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit 9 3 1 3 -1 0 Gain (dB) Normalized Gain (dB) 2 6 0 -3 -6 -9 100k -3 -4 VOUT = 20 mVpp VOUT = 200 mVpp VOUT = 1 Vpp VOUT = 2 Vpp VOUT = 4 Vpp VOUT = 8 Vpp -5 G = 0.1 V/V G = 1 V/V G = 2 V/V G = 5 V/V G = 10 V/V 1M -2 -6 -7 -8 10M Frequency (Hz) -9 100k 100M 1M D001 VOUT = 20 mVPP, see Figure 8-1 and Table 9-1 for resistor values 10M Frequency (Hz) 100M D002 See Figure 8-1 Figure 7-2. Frequency Response vs VOUT Figure 7-1. Small-Signal Frequency Response vs Gain 6 3 2 1 3 0 0 Gain (dB) Gain (dB) -1 -2 -3 -4 -5 -6 -7 -8 -9 100k VOCM = 0.8 V VOCM = 1 V VOCM = 1.5 V VOCM = 2 V VOCM = 3 V VOCM = 3.5 V 1M -3 -6 RL = 50 : RL = 100 : RL = 200 : RL = 500 : RL = 1000 : -9 10M Frequency (Hz) -12 100k 100M D003 VOUT = 20 mVPP , see Figure 8-1 with VOCM adjusted 1M 10M Frequency (Hz) 100M D004 VOUT = 20 mVPP, see Figure 8-1 with load resistance (RL) adjusted Figure 7-3. Small-Signal Frequency Response vs VOCM Figure 7-4. Small-Signal Frequency Response vs RL 3 100 2 90 -1 -2 -3 -4 -5 -6 -7 -8 -9 100k G = 1 V/V G = 2 V/V G = 5 V/V G = 10 V/V 80 0 RO in each output (:) Normalized Gain (dB) 1 CL = 10 pF, RO = 97.6 : CL = 47 pF, RO = 49.9 : CL = 100 pF, R O = 32.4 : CL = 470 pF, R O = 10.0 : CL = 1000 pF, R O = 4.7 : 70 60 50 40 30 20 10 0 1M 10M Frequency (Hz) 1 100M D005 VOUT = 20 mVPP at load, G = 1, two series RO added at output before capacitive load (CL) 10 100 Differential CL (pF) 1000 D006 Output resistance (RO) is two series output resistors to a differential CL in parallel with a 1-kΩ load resistance Figure 7-5. Small-Signal Frequency Response vs CL Figure 7-6. Recommended RO vs CL Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 13 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 7.7 Typical Characteristics: (VS+) – (VS–) = 5 V (continued) at TA ≈ 25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit 1.2 0.5 1 0.4 0.8 0.3 Differential Output (V) 0.6 Differential Output (V) RO = 0 : RO = 75 : 0.4 0.2 0 -0.2 -0.4 -0.6 0.2-V step, tR = 1 ns 0.5-V step, tR = 2 ns 1-V step, tR = 4 ns 2-V step, tR = 8 ns -0.8 -1 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -1.2 0 20 40 60 80 100 120 Time (ns) 140 160 180 0 200 20 40 60 80 D007 100 120 Time (ns) 140 180 200 D008 G = 1 V/V, VOUT = 500-mV step into 22-pF CL, see Figure 8-4 G = 1 V/V, 5-MHz input, single-ended to differential output Figure 7-8. Step Response Into Capacitive Load Figure 7-7. Small- and Large-Signal Step Response 0.5 1.5 RO = 0 : RO = 46.4 : 0.4 1 0.3 Differential Output (V) Differential Output (V) 160 0.5 0 -0.5 0.2-V step, tR = 1 ns 0.5-V step, tR = 1 ns 1-V step, tR = 2 ns 2-V step, tR = 5 ns -1 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -1.5 -0.5 0 20 40 60 80 100 120 Time (ns) 140 160 180 200 0 20 40 60 D009 G = 2 V/V, 5-MHz input, single-ended input to differential output 80 100 120 Time (ns) 140 160 180 200 D010 G = 2 V/V, VOUT = 500-mV step into 22-pF CL, see Figure 8-4 Figure 7-10. Step Response Into Capacitive Load Figure 7-9. Small- and Large-Signal Step Response 10 Error to Final Value (%) Input and Differential Output Voltage (V) 0.2 0.2-V step, tR = 1 ns 1-V step, tR = 4 ns 2-V step, tR = 8 ns 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 6 4 2 0 -2 -4 -6 -8 -10 -0.2 0 10 20 30 40 50 Time ' from 50% of Input Edge (ns) 60 70 0 D011 Simulated with G = 1 V/V 0.1 0.2 0.3 0.4 0.5 0.6 Time (Ps) 0.7 0.8 0.9 1 D012 Single-ended to differential gain of 2, 2X input overdrive Figure 7-11. Small- and Large-Signal Step Settling Time 14 Input Output 8 Figure 7-12. Overdrive Recovery Performance Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 7.7 Typical Characteristics: (VS+) – (VS–) = 5 V (continued) at TA ≈ 25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit -70 -50 HD2 HD3 -60 HD2, 100 kHz HD3, 100 kHz HD2, 1 MHz HD3, 1 MHz -80 -70 Distortion (dBc) Distortion (dBc) -90 -80 -90 -100 -110 -100 -110 -120 -120 -130 -130 -140 -140 -150 10k 100k 1M Frequency (Hz) -150 0.1 10M D013 1 Differential Output Voltage (Vpp) D014 G = 1 V/V G = 1 V/V, VOUT = 2 VPP Figure 7-14. Harmonic Distortion vs Output Swing Figure 7-13. Harmonic Distortion vs Frequency -40 -60 Max IMD3 Max IMD2 -45 HD2, 100 kHz HD3, 100 kHz HD2, 1 MHz HD3, 1 MHz -70 -50 -80 -55 Distortion (dBc) Spurious Level (dBc) 10 -60 -65 -70 -90 -100 -110 -75 -120 -80 -130 -85 -90 1M -140 50 10M Frequency (Hz) D015 1000 D016 G = 1 V/V, VOUT = 2 VPP, with RL adjusted G = 1 V/V, VOUT = 1 VPP each tone Figure 7-16. Harmonic Distortion vs RL Figure 7-15. Intermodulation Distortion (IMD2 and IMD3) vs Frequency -20 -105 HD2, 10 kHz HD2, 100 kHz HD2, 1 MHz HD3, 10 kHz HD3, 100 kHz HD3, 1 MHz -60 HD2, 100 kHz HD3, 100 kHz -110 -115 Distortion (dBc) -40 Distortion (dBc) 100 Differential Load Resistance (:) -80 -100 -120 -120 -125 -130 -135 -140 -140 -160 0.5 -145 1.5 2.5 VOCM - (VS-) (V) 3.5 4.5 1 G = 1 V/V, VOUT = 2 VPP, with VOCM adjusted Figure 7-17. Harmonic Distortion vs VOCM 10 Gain (V/V) D017 D018 VOUT = 2 VPP, seeTable 9-1 for gain setting Figure 7-18. Harmonic Distortion vs Gain Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 15 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 7.8 Typical Characteristics: (VS+) – (VS–) = 3 V at TA ≈ 25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit 9 3 1 3 -1 0 Gain (dB) Normalized Gain (dB) 2 6 0 -3 -6 -9 100k -3 -4 -5 G = 0.1 V/V G = 1 V/V G = 2 V/V G = 5 V/V G = 10 V/V 1M -2 VOUT = 20 mVpp VOUT = 200 mVpp VOUT = 1 Vpp VOUT = 2 Vpp VOUT = 4 Vpp -6 -7 -8 10M Frequency (Hz) -9 100k 100M 1M D019 VOUT = 20 mVPP, see Figure 8-1 and Table 9-1 for resistor values 10M Frequency (Hz) 100M D020 See Figure 8-1 Figure 7-20. Frequency Response vs VOUT Figure 7-19. Small-Signal Frequency Response vs Gain 6 3 2 1 3 0 0 Gain (dB) Gain (dB) -1 -2 -3 -4 -5 -3 -6 RL = 50 : RL = 100 : RL = 200 : RL = 500 : RL = 1000 : -6 -7 -8 -9 100k VOCM = 0.8 V VOCM = 1 V VOCM = 1.5 V 1M -9 10M Frequency (Hz) -12 100k 100M D021 D003 VOUT = 20 mVPP, see Figure 8-1 with VOCM adjusted 110 1 100 0 90 RO in each output (:) Normalized Gain (dB) 120 2 -1 -2 -3 -4 -7 -8 -9 100k CL = 10 pF, RO = 113 : CL = 47 pF, RO = 54.9 : CL = 100 pF, R O = 34.0 : CL = 470 pF, R O = 10.5 : CL = 1000 pF, R O = 5.1 : D022 G = 1 V/V G = 2 V/V G = 5 V/V G = 10 V/V 80 70 60 50 40 30 20 10 0 1M 10M Frequency (Hz) 1 100M 10 100 Differential CL (pF) D023 VOUT = 20 mVPP, G = 1 V/V, two series RO added at output before CL Figure 7-23. Small-Signal Frequency Response vs CL 16 100M Figure 7-22. Small-Signal Frequency Response vs RL 3 -6 10M Frequency (Hz) VOUT = 20 mVPP, see Figure 8-1 with RL adjusted Figure 7-21. Small-Signal Frequency Response vs VOCM -5 1M 1000 D024 Two RO at output to differential CL in parallel with a 1-kΩ load resistance Figure 7-24. Recommended RO vs CL Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 7.8 Typical Characteristics: (VS+) – (VS–) = 3 V (continued) at TA ≈ 25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit 0.5 1.5 RO = 0 : RO = 82.5 : 0.4 0.3 Differential Output (V) Differential Output (V) 1 0.5 0 -0.5 0.2-V step, tR = 2 ns 0.5-V step, tR = 4 ns 1-V step, tR = 8 ns 2-V step, tR = 12ns -1 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -1.5 -0.5 0 20 40 60 80 100 120 Time (ns) 140 160 180 200 0 20 40 60 80 D025 G = 1 V/V, 5-MHz input, single-ended input to differential output 100 120 Time (ns) 140 160 180 200 D026 G = 1 V/V, VOUT = 500-mV step into 22-pF CL, see Figure 8-4 Figure 7-26. Step Response Into Capacitive Load Figure 7-25. Small- and Large-Signal Step Response 0.5 1.5 0.4 0.3 Differential Output (V) Differential Output (V) 1 0.5 0 -0.5 0.2-V step, tR = 2 ns 0.5-V step, tR = 2 ns 1-V step, tR = 6 ns 2-V step, tR = 12 ns -1 0.2 0.1 0 -0.1 -0.2 -0.3 RO = 0 : RO = 51.1 : -0.4 -1.5 -0.5 0 20 40 60 80 100 120 Time (ns) 140 160 180 200 0 20 40 60 D027 G = 2 V/V, 5-MHz input, single-ended input to differential output. 80 100 120 Time (ns) 140 160 180 200 D028 G = 2 V/V, VOUT = 500-mV step into 22-pF CL, see Figure 8-4 Figure 7-28. Step Response Into Capacitive Load Figure 7-27. Small- and Large-Signal Step Response 6 0.2-V step, tR = 2 ns 1-V step, tR = 8 ns 2-V step, tR = 12 ns 0.15 Error to Final Value (%) Input and Differential Output Voltage (V) 0.2 0.1 0.05 0 -0.05 -0.1 -0.15 Input Output 4 2 0 -2 -4 -6 -0.2 0 10 20 30 40 50 Time ' from 50% of Input Edge (ns) 60 70 0 D029 Simulated with G = 1 V/V 0.1 0.2 0.3 0.4 0.5 0.6 Time (Ps) 0.7 0.8 0.9 1 D030 Single-ended to differential gain of 2, 2X input overdrive Figure 7-29. Small- and Large-Signal Step Settling Time Figure 7-30. Overdrive Recovery Performance Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 17 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 7.8 Typical Characteristics: (VS+) – (VS–) = 3 V (continued) at TA ≈ 25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit -70 -40 -50 HD2 HD3 HD2, 100 kHz HD3, 100 kHz HD2, 1 MHz HD3, 1 MHz -80 -60 -90 Distortion (dBc) Distortion (dBc) -70 -80 -90 -100 -110 -120 -100 -110 -120 -130 -130 -140 -140 -150 10k 100k 1M Frequency (Hz) -150 0.1 10M D031 Figure 7-31. Harmonic Distortion vs Frequency D032 Figure 7-32. Harmonic Distortion vs Output Swing -40 -60 Max IMD3 Max IMD2 HD2, 100 kHz HD3, 100 kHz HD2, 1 MHz HD3, 1 MHz -70 -50 -80 -55 Distortion (dBc) Spurious Level (dBc) 4 G = 1 V/V G = 1 V/V, VOUT = 2 VPP -45 1 Differential Output Voltage (Vpp) -60 -65 -70 -90 -100 -110 -75 -120 -80 -130 -85 -90 1M -140 50 10M Frequency (Hz) D033 HD2, 10 kHz HD2, 100 kHz HD2, 1 MHz HD3, 10 kHz HD3, 100 kHz HD3, 1 MHz -110 -130 -120 -125 -130 -135 -140 1 1.2 1.4 1.6 VOCM - (VS-) (V) 1.8 2 1 10 Gain (V/V) D035 VOUT = 2-VPP output, with VOCM adjusted D036 VOUT = 2-VPP output, see Table 9-1 for gain setting Figure 7-35. Harmonic Distortion vs VOCM 18 HD2, 100 kHz HD3, 100 kHz -115 Distortion (dBc) Distortion (dBc) -110 -90 -150 0.8 D034 Figure 7-34. Harmonic Distortion vs RL Figure 7-33. IMD2 and IMD3 vs Frequency -30 -70 1000 G = 1 V/V, VOUT = 2-VPP output, with RL adjusted G = 1 V/V, 1 VPP each tone -50 100 Differential Load Resistance (:) Figure 7-36. Harmonic Distortion vs Gain Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 7.9 Typical Characteristics: 3-V to 5-V Supply Range at TA ≈ 25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit Open-Loop Gain (dB) 100 70 -100 40 -150 10 -200 -20 10 100 1k 10k 100k 1M Frequency (Hz) 10M 100M 100 50 Output Impedance (:) 0 +5 V, Gain +5 V, Phase +3 V, Gain -50 +3 V, Phase Open-Loop Phase (deg) 130 20 10 5 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 10k -250 1G +5 V, G = 1 V/V +5 V, G = 2 V/V +5 V, G = 5 V/V +3 V, G = 1 V/V +3 V, G = 2 V/V +3 V, G = 5 V/V 100k D037 Simulated with a 1-kΩ differential load and 0.6-pF internal feedback capacitors removed 1M Frequency (Hz) 10M 100M D038 Simulated closed-loop differential output impedance Figure 7-38. Closed-Loop Output Impedance vs Frequency Figure 7-37. Main Amplifier Differential Open-Loop Gain and Phase vs Frequency 90 85 10 80 Output Balance (dB) Input Spot Voltage (nV/—Hz) and Current (pA/—Hz) Noise 20 1 +5 V, En +5 V, In +3 V, En +3 V, In 0.1 10 100 75 70 65 60 55 50 45 1k 10k Frequency (Hz) 100k +5 V, SSOB +5 V, 2-VPP OB +3 V, SSOB +3 V, 2-VPP OB 40 10k 1M 100k . 1M 10M Frequency (Hz) D039 D040 Differential mode output to common-mode output, simulated with G = 1 V/V Figure 7-39. Input Spot Noise vs Frequency Figure 7-40. Output Balance vs Frequency 120 120 +5 V +3 V 115 110 100 105 PSRR (dB) CMRR (dB) 110 100 95 90 80 90 70 85 80 1k 10k 100k Frequency (Hz) 1M 10M D041 Common-mode input to differential output, simulated with G = 1 V/V Figure 7-41. CMRR vs Frequency 60 1k +5 V, VS+ +5 V, VS+3 V, VS+ +3 V, VS10k 100k Frequency (Hz) 1M 10M D042 Single-ended to differential gain of 1, PSRR simulated to differential output Figure 7-42. Power-Supply Rejection Ratio vs Frequency Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 19 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 7.9 Typical Characteristics: 3-V to 5-V Supply Range (continued) at TA ≈ 25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit 0.6 3 Output Common Mode Voltage (V) 2 1 0 Gain (dB) -1 -2 -3 -4 -5 -6 +5 V, 100 mVpp +5 V, 1 Vpp +3 V, 100 mVpp +3 V, 1 Vpp -7 -8 1M 10M +5 V, 0.2-V step +5 V, 1-V step +3 V, 0.2-V step +3 V, 1-V step -0.4 0 0.1 0.2 0.3 0.4 0.5 0.6 Time(Ps) 0.7 0.8 0.9 1 D044 Figure 7-44. Common-Mode Voltage, Small- and Large-Step Response (VOCM Pin Driven) 1000 3 +3 V, VOCM Pin Driven +5 V, VOCM Pin Driven +3 V, VOCM Pin Floating +5 V, VOCM Pin Floating Output CM Voltage Offset (mV) Output Spot Common Mode Noise (nV/—Hz) -0.2 D043 Figure 7-43. Common-Mode Voltage, Small- and Large-Signal Response (VOCM Pin Driven) 100 +3 V +5 V 2 1 0 -1 1k 10k 100k Frequency (Hz) 1M 10M 0 0.5 1 D045 The VOCM pin is either driven to midsupply by low-impedance source or allowed to float and default to midsupply 1.5 2 2.5 VOCM - (VS-) (V) 3 3.5 4 D046 Average VOCM output offset of 39 units, standard deviation < 2 mV Figure 7-45. Output Common-Mode Noise vs Frequency Figure 7-46. VOCM Offset vs VOCM Setting 120 120 +5 V +3 V +5 V +3 V 115 Positive Supply PSRR (dB) 115 Negative Supply PSRR (dB) 0 100M Frequency (Hz) 110 105 100 95 90 85 110 105 100 95 90 85 80 80 0 1 2 3 VOCM - (VS-) (V) 4 5 0 D047 Simulated with single-ended to differential gain of 1 , PSRR for negative supply to differential output Figure 7-47. –PSRR vs VOCM Approaching VS– 20 0.2 -0.6 -9 100k 10 100 0.4 1 2 3 VOCM - (VS-) (V) 4 5 D048 Simulated with single-ended to differential gain of 1, PSRR for positive supply to differential output Figure 7-48. +PSRR vs VOCM Approaching VS+ Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 7.9 Typical Characteristics: 3-V to 5-V Supply Range (continued) at TA ≈ 25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit 60 80 +5 V +3 V +5 V +3 V 50 64 No. of Units in 5 nA Bins No. of units in 20 PV Bins 72 56 48 40 32 24 16 40 30 20 10 8 0 Input Offset Voltage (PV) -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 0 Input Offset Current (nA) D049 Total of 234 DGK units trimmed at a 5-V supply Total of 234 DGK units trimmed at a 5-V supply Figure 7-50. Input Offset Current (IOS) Figure 7-49. Input Offset Voltage (VIO) 100 50 80 40 60 30 Delta from 25°C IOS (nA) Delta from 25°C VIO (µV) D050 40 20 0 -20 -40 -60 -80 20 10 0 -10 -20 -30 -40 -100 -40 -20 0 20 40 60 80 Ambient Temperature (qC) 100 -50 -40 120 D051 -20 0 20 40 60 80 Ambient Temperature (qC) 100 120 D052 5-V and 3-V delta from 25°C VIO, 50 DGK units 5-V and 3-V delta from 25°C IOS, 50 DGK units Figure 7-51. Input Offset Voltage vs Temperature Figure 7-52. Input Offset Current vs Temperature 40 +5 V +3 V 12 No. of Units in Each 0.05 nA/°C Bin 10 8 6 4 2 +5 V +3 V 36 32 28 24 20 16 12 8 4 0 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 D053 Input Offset Voltage Drift (PV/qC) –40°C to +125°C endpoint drift, total of 62 DGK units Figure 7-53. Input Offset Voltage Drift Histogram -0.5 -0.45 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 No. of Units in Each 0.2 PV/qC Bin 14 Input Offset Current Drift (nA/qC) D054 –40°C to +125°C endpoint drift, total of 62 DGK units Figure 7-54. Input Offset Current Drift Histogram Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 21 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 7.9 Typical Characteristics: 3-V to 5-V Supply Range (continued) at TA ≈ 25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit 2.5 1.6 2 1.4 Supply Current (mA) Maximum VOUT (V) 1.5 1 0.5 r1.5 V, Pos r1.5 V, Neg r2.5 V, Pos r2.5 V, Neg 0 -0.5 -1 1.2 1 0.8 0.6 0.4 -1.5 0.2 -2 -2.5 50 +3 V +5 V 0 100 Differential Load Resistance (:) 1000 0 1 D055 2 3 Disable Pin Voltage (V) Maximum differential output swing, VOCM at midsupply +5 V +3 V No. of Units in 0.5 mV Bins No. of Units in 2 mV Bins 140 120 100 80 60 40 20 +3 V, PD +3 V, VOUT 5 4 3 2 1 0 -1 -2 0.2 0.4 0.6 0.8 1 1.2 Time (Ps) 1.4 1.6 1.8 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Figure 7-58. Common-Mode Output Offset from Driven VOCM Histogram Disable and Differential Output Voltage (V) Disable and Differential Output Voltage (V) 7 0 2 7 +5 V, PD +5 V, VOUT +3 V, PD +3 V, VOUT 6 5 4 3 2 1 0 -1 -2 0 D059 5 MHz, 2-VPP input, G = 1 V/V, see Figure 8-1 0.2 0.4 0.6 0.8 1 1.2 Time (Ps) 1.4 1.6 1.8 2 D060 5 MHz, 2-VPP input, G = 1 V/V, see Figure 8-1 Figure 7-59. PD Turn-On Waveform 22 D058 Common Mode Offset Voltage (mV) VOCM Input driven to midsupply, total of 240 units Figure 7-57. Common-Mode Output Offset from VS+ / 2 Default Value Histogram +5 V, PD +5 V, VOUT +5 V +3 V D057 VOCM input floating, total of 240 units 6 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 16 14 12 8 10 6 4 2 0 -2 -4 -6 -8 -10 -12 -14 -16 0 Common Mode Offset Voltage (mV) D056 Figure 7-56. Supply Current vs PD Voltage 200 160 5 . Figure 7-55. ±Maximum VOUT vs Differential Load Resistance 180 4 Figure 7-60. PD Turn-Off Waveform Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 8 Parameter Measurement Information 8.1 Example Characterization Circuits The THS4551 offers the advantages of a fully differential amplifier (FDA) design with the trimmed input offset voltage and very low drift of a precision op amp. The FDA is an extremely flexible device where the main aim is to provide a purely differential output signal centered on a user-configurable common-mode voltage usually matched to the input common-mode voltage required by an analog-to-digital converter (ADC) following this stage. The primary options revolve around the choices of single-ended or differential inputs, ac-coupled or dccoupled signal paths, gain targets, and resistor value selections. The characterizations described in this section focus on single-ended input to differential output designs as the more challenging application requirement. Differential sources can certainly be supported and are often simpler to both implement and analyze. The characterization circuits are typically operated with a single-ended, matched, 50-Ω, input termination to a differential output at the FDA output pins because most lab equipment is single-ended. The FDA differential output is then translated back to single-ended through a variety of baluns (or transformers), depending on the test and frequency range. DC-coupled step response testing used two 50-Ω scope inputs with trace math. Single-supply operation is most common in end equipment designs. However, using split balanced supplies allows simple ground referenced testing without adding further blocking capacitors in the signal path beyond those capacitors already within the test equipment. The starting point for any single-ended input to differential output measurements (such as any of the frequency response curves) is shown in Figure 8-1 (available as a TINA-TI™ simulation file). 50- Input Match, Gain of 1 V/V from RT, Single-Ended Source to Differential Output THS4551 Wideband, Fully Differential Amplifier RF1 1k RO1 487 VS+ RG1 1k Network Analyzer, 50- Source Impedance ADTL1-4-75+ ± RT1 52.3 VOCM FDA RG2 1k Termination RS1 50 RT2 52.3 N1 + VOPP ± + 50- 31.8-dB Insertion Loss from VOPP to a 50- Load PD VS- VS+ RF2 1k RO2 487 1-k Differential Load RM 52.3 N2 50Single-Ended Source Network Analyzer, 50- Load Copyright © 2016, Texas Instruments Incorporated Figure 8-1. Single-Ended Source to a Differential Gain of a 1-V/V Test Circuit Most characterization plots fix the RF (RF1 = RF2) value at 1 kΩ, as shown in Figure 8-1. This element value is completely flexible in application, but 1 kΩ provides a good compromise for the parasitic issues linked to this value, specifically: • • • Added output loading: the FDA functions similarly to an inverting op amp design with both feedback resistors appearing as an added load across the outputs (the approximate total differential load in Figure 8-1 is 1 kΩ || 2 kΩ = 667 Ω). The 1-kΩ value also reduces the power dissipated in the feedback networks. Noise contributions resulting from resistor values: these contributions are both the 4kTRF terms and the current noise times the RF value to the output (see Section 10.1.1). Parasitic feedback pole at the input summing nodes: this pole is created by the feedback resistor (RF) value and the 1.2-pF differential input capacitance (as well as any board layout parasitic) and introduces a zero in the noise gain, thus decreasing the phase margin in most situations. This effect must be managed for best frequency response flatness or step response overshoot. Internal 0.6-pF feedback capacitors on each side combine with these external feedback resistors to introduce a zero in the noise gain, thereby reducing the effect of the feedback pole to the differential input capacitance. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 23 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 The frequency domain characterization curves start with the selections of Figure 8-1. Some of the features in this test circuit include: • • • The elements on the non-signal input side exactly match the signal input resistors. This feature has the effect of more closely matching the divider networks on each side of the FDA. The three resistors on the non-signal input side can be replaced by a single resistor to ground using a standard E96 value of 1.02 kΩ with some loss in gain balancing between the two sides; see Section 9.3.4). Translating from a 1-kΩ differential load to a 50-Ω environment introduces considerable insertion loss in the measurements (–31.8 dB in Figure 8-1). The measurement path insertion loss is normalized out when reporting the frequency response curves to show the gain response to the FDA output pins. In the pass band for the output balun, the network analyzer 50-Ω load reflects to be in parallel with the 52.3-Ω shunt termination. These elements combine to show a differential 1-kΩ load at the output pins of the THS4551. The source impedance presented to the balun is a differential 50-Ω source. Figure 8-2 and Figure 8-3 show the TINA-TI™ model (available as a TINA-TI™ simulation file) and resulting response flatness for this relatively low-frequency balun providing 0.1-dB flatness through 100 MHz. L1's Inductance : 198.94 uH L2's Inductance : 198.94 uH Mutual Inductance : 198.92972 uH ADTL1-4-75 Model 198.94u R3 50 + N1 R1 25 VG1 N2 R2 25 + V VM1 Figure 8-2. Output Measurement Balun Simulation Circuit in TINA-TI™ 10 8 -6.02 6 -6.03 4 -6.04 2 -6.05 0 -6.06 -2 -6.07 -4 -6.08 -6.09 -6.1 1k Phase (deg) Gain (dB) -6 -6.01 -6 Gain (dB) Phase (deg) 10k -8 100k 1M Frequency (Hz) 10M -10 100M D061 Figure 8-3. Output Measurement Balun Flatness Test 24 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 Starting from the test circuit of Figure 8-1, various elements are modified to show the effect of these elements over a range of design targets, specifically: • • • • The gain setting is changed by adjusting the RT and the two RG elements to provide a 50-Ω input match and setting the feedback resistors to 1 kΩ. Output loading of both resistive and capacitive load testing. Changing to lower resistive loads is accomplished by adding parallel resistors across the output pins in Figure 8-1. Changing to capacitive loads adds series output resistors to a differential capacitance before the 1-kΩ sense path of Figure 8-1. Power-supply settings. Most often, a single 5-V test uses a ±2.5-V supply and a 3-V test uses ±1.5-V supplies with the VOCM input control at ground. The disable control pin ( PD) is tied to the positive supply (VS+) for any active channel test. 8.2 Output Interface Circuit for DC-Coupled Differential Testing The pulse response plots were taken using the output circuit of Figure 8-4. The two sides of this circuit present a 500-Ω load to ground (for a differential 1-kΩ load) with a 50-Ω source to the two scope inputs. Trace math is used to combine the two sides into the pulse response plots of Figure 7-7 to Figure 7-10 and Figure 7-25 to Figure 7-28. Using balanced bipolar supplies for this test ensures that the THS4551 outputs deliver a ground-centered differential swing. This setup produces no dc load currents using the circuit of Figure 8-4. RO1 475 RM1 56.2 THS4551 Output RM1 56.2 RO2 475 50Scope Input 50Scope Input Copyright © 2016, Texas Instruments Incorporated Figure 8-4. Output Interface for DC-Coupled Differential Outputs 8.3 Output Common-Mode Measurements The circuit of Figure 8-5 is a typical setup for common-mode measurements. THS4551 Wideband, Fully Differential Amplifier RG1 1k RF1 1k VS+ Signal Source 100 RS 49.9 VOCM Input ± FDA RT 49.9 + ± + RT 1k 50Measurement Equipment PD VS- VS+ 100 RF2 1k Copyright © 2016, Texas Instruments Incorporated Figure 8-5. Output Common-Mode Measurements Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 25 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 In Figure 8-5, the differential path is simply terminated back to ground on the two 1-kΩ input resistors and the VOCM control input is driven from a 50-Ω matched source for the frequency response and step response curves of Figure 7-43 and Figure 7-44. The outputs are summed to a center point (to obtain the average, or common-mode, output) through two 100-Ω resistors. These 100-Ω resistors form an equivalent 50-Ω source to the common-mode output for measurements. This common-mode test circuit is available as a TINA-TI™ simulation file. Figure 7-45 illustrates the common-mode output noise measurements with either a ground on the VOCM input pin or with the VOCM input pin floating. The higher noise in Figure 7-45 for a floated input can be reduced by including a capacitor to ground at the VOCM control input pin. 8.4 Differential Amplifier Noise Measurements To extract out the input-referred noise terms from the total output noise, a measurement of the differential output noise is required under two external conditions to emphasize the different noise terms. A high-gain, low resistor value condition is used to emphasize the differential input voltage noise and a higher RF at low gains is used to emphasize the two input current noise terms. The differential output noise must be converted to single-ended with added gain before being measured by a spectrum analyzer. At low frequencies, a zero 1/f noise, high-gain, differential to single-ended instrumentation amplifier (such as the INA188) is used. At higher frequencies, a differential to single-ended balun is used to drive into a high-gain, low-noise, op amp (such as the LMH6629). In this case, the THS4551 outputs drive 25-Ω resistors into a 1:1 balun where the balun output is terminated single-endedly at the LMH6629 input with 50 Ω. This termination provides a modest 6-dB insertion loss for the THS4551 differential output noise that is then followed by a 40-dB gain setting in the very wideband LMH6629. 8.5 Balanced Split-Supply Versus Single-Supply Characterization Although most end applications use a single-supply implementation, most characterizations are done on a split balanced supply. Using a split balanced supply keeps the I/O common-mode inputs near midsupply and provides the most output swing with no dc bias currents for level shifting. These characterizations include the frequency response, harmonic distortion, and noise plots. The time domain plots are in some cases done via single-supply characterization to obtain the correct movement of the input common-mode voltage. 8.6 Simulated Characterization Curves In some cases, a characteristic curve can only be generated through simulation. A good example of this scenario is the output balance plot of Figure 7-40. This plot shows the best-case output balance (output differential signal versus output common-mode signal) using exact matching on the external resistors in simulation using a single-ended input to differential output configuration. The actual output balance is set by resistor mismatch at low frequencies but intersects and follows the high-frequency portion of Figure 7-40. The remaining simulated plots include: • • • • • 26 AOL gain and phase, see Figure 7-37. Large- and small-signal settling times, see Figure 7-11 and Figure 7-29. Closed-loop output impedance versus frequency, see Figure 7-38. CMRR vs frequency, see Figure 7-41. PSRR vs frequency and output common-mode voltage, see Figure 7-42, Figure 7-47, and Figure 7-48. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 8.7 Terminology and Application Assumptions Numerous common terms that are unique to this type of device exist. This section identifies and explains these terms. • • • • Fully differential amplifier (FDA). This term is restricted to devices offering what appears similar to a differential inverting op amp design element that requires an input resistor (not a high-impedance input) and includes a second internal control loop that sets the output average voltage (VOCM) to a default or set point. This second common-mode control loop interacts with the differential loop in certain configurations. The desired output signal at the two output pins is a differential signal that swings symmetrically around a common-mode voltage, which is the average voltage for the two outputs. Single-ended to differential. The output must always be used differentially in an FDA; however, the source signal can be either a single-ended or a differential source with a variety of implementation details for either source. For an FDA operating in single-ended to differential, only one of the two input signals is applied to one of the input resistors. The common-mode control has limited bandwidth from the input VOCM pin to the common-mode output voltage. The internal loop bandwidth beyond the input VOCM buffer is a much wider bandwidth than the reported VOCM bandwidth, but is not directly discernable. A very wide bandwidth in the internal VOCM loop is required to perform an effective and low-distortion single-ended to differential conversion. Several features in the application of the THS4551 are not explicitly stated, but are necessary for correct operation. These features are: • • • • • Good power-supply decoupling is required. Often a larger capacitor (2.2 µF, typical) is used along with a high-frequency, 0.1-µF supply decoupling capacitor at the device supply pins (share this capacitor with the four supply pins in the RGT package). For single-supply operation, only the positive supply has these capacitors. Where a split supply is used, connect these capacitors to ground on both sides with the larger capacitor placed some distance from the package and shared among multiple channels of the THS4551, if used. A separate 0.1-µF capacitor must be provided to each device at the device power pins. With cascaded or multiple parallel channels, including ferrite beads from the larger capacitor to the local high-frequency decoupling capacitor is often useful. Although often not stated, the power disable pin ( PD) is tied to the positive supply when only an enabled channel is desired. Virtually all ac characterization equipment expects a 50-Ω termination from the 50-Ω source and a 50-Ω, single-ended source impedance from the device outputs to the 50-Ω sensing termination. This condition is achieved in all characterizations (often with some insertion loss) but is not necessary for most applications. Matching impedance is most often required when transmitting over longer distances. Tight layouts from a source, through the THS4551, and to an ADC input do not require doubly-terminated lines or filter designs. The only exception is if the source requires a defined termination impedance for correct operation (for example, mixer outputs). The amplifier signal path is flexible for use as single- or split-supply operation. Most applications are intended to be single supply, but any split-supply design can be used as long as the total supply voltage across the TH4551 is less than 5.5 V and the required input, output, and common-mode pin headrooms to each supply are taken into account. When left open, the VOCM pin defaults to near midsupply for any combination of split or single supplies used. The disable pin ( PD) is referenced to the negative rail. Using a negative supply requires that PD be pulled down to within 0.55 V of the negative supply to disable the amplifier. External element values are normally assumed to be accurate and matched. In an FDA, this assumption translates to equal feedback resistor values and a matched impedance from each input summing junction to either a signal source or a dc bias reference on each side of the inputs. Unbalancing these values introduces non-idealities in the signal path. For the signal path, imbalanced resistor ratios on the two sides creates a common-mode to differential conversion. Furthermore, mismatched RF values and feedback ratios create additional differential output error terms from any common-mode dc or ac signal or noise terms. Using standard 1% resistor values is a typical approach and generally leads to some nominal feedback ratio mismatch. Modestly mismatched resistors or ratios do not by themselves degrade harmonic distortion. Where there is a meaningful common-mode noise or distortion coming in that gets converted to differential via an element or ratio mismatch. For the best dc precision, use 0.1% accuracy resistors that are readily available in E96 values (1% steps). Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 27 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 9 Detailed Description 9.1 Overview In addition to the core differential I/O voltage feedback gain block, there are two 5.2-kΩ resistors internally across the outputs to sense the average voltage at the outputs. These resistors feed the average voltage back into a VCM error amplifier where the voltage is compared to either a default voltage divider across the supplies or an externally set VOCM target voltage. When the amplifier is disabled, the default midsupply bias string is disabled to save power. To achieve the very-low noise at the low power provided by the THS4551, the input stage transistors are relatively large, thus resulting in a higher differential input capacitance (1.2 pF in the Section 9.2). As a default compensation for the 1.2-pF differential input capacitance and the 1-kΩ feedback resistors used in characterization, internal 0.6-pF capacitors are placed between the two output and input pins. Adjust any desired external feedback capacitor value to account for these 0.6-pF internal elements. When using the 16-pin WQFN package and the internal feedback traces to the input side of the package, include the nominal trace impedance of 3.3 Ω in the design. These elements are not included in the TINA-TI™ model and must be added externally to a design intending to use the RGT package. 9.2 Functional Block Diagram VS+ 3.3 (RGT Package) FB+ 0.6 pF OUT+ IN± ± 5.2 k High-AOL + Differential I/O Amplifier ± 1.2 pF IN+ 5.2 k + OUT± 0.6 pF VS+ 3.3 (RGT Package) FB± 300 k VS± ± VCM Error Amplifier + PD VOCM CMOS Buffer 300 k VS± 28 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 9.3 Feature Description 9.3.1 Differential Open-Loop Gain and Output Impedance The most important elements to the closed-loop performance are the open-loop gain and open-loop output impedance. Figure 9-1 and Figure 9-2 show the simulated differential open-loop gain and phase from the differential inputs to the differential outputs with no load and with a 100-Ω load. Operating with no load removes any effect introduced by the open-loop output impedance to a finite load. This AOL simulation removes the 0.6-pF internal feedback capacitors to isolate the forward path gain and phase (see Figure 13-1). The 0.6-pF capacitance becomes part of the feedback network that sets the noise gain and phase combined with the external elements. The simulated differential open-loop output impedance is shown in Figure 9-3. -90 80 100 : Load No Load 70 -100 -110 Open-Loop Phase (deg) Open-Loop Gain (dB) 60 50 40 30 20 10 -120 -130 -140 -150 -160 -170 -180 0 -190 -10 -200 -20 100k 1M 10M Frequency (Hz) 100M No Load 100 : Load -210 100k 1G 1M 10M Frequency (Hz) D063 Figure 9-1. No-Load and 100-Ω Loaded AOL Gain 100M 1G D064 Figure 9-2. No-Load and 100-Ω AOL Phase Differential Output Impedance (:) 10000 1000 100 10 1 10 100 1k 10k 100k 1M Frequency (Hz) 10M 100M 1G D062 Figure 9-3. Differential Open-Loop Output Impedance This impedance combines with the load to shift the apparent open-loop gain and phase to the output pins when the load changes. The rail-to-rail output stage shows a very high impedance at low frequencies that reduces with frequency to a lower midrange value and then peaks again at higher frequencies. The maximum value at low frequencies is set by the common-mode sensing resistors to be a 10.5-kΩ dc value (see Section 9.2). This high impedance at a low frequency is significantly reduced in closed-loop operation by the loop gain, as shown in the closed-loop output impedance of Figure 7-38. Figure 9-1 compares the no load AOL gain to the AOL gain driving a 100-Ω load that shows the effect of the output impedance. The heavier loads pull the AOL gain down faster to lower crossovers with more phase shift at the lower frequencies. The much faster phase rolloff for the 100-Ω differential load explains the greater peaked response illustrated in Figure 7-4 and Figure 7-22 when the load decreases. This same effect happens for the RC loads common with converter interface designs. Use the TINA-TI™ model to verify loop phase margin in any design. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 29 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 9.3.2 Setting Resistor Values Versus Gain The THS4551 offers considerable flexibility in the configuration and selection of resistor values. The design starts with the selection of the feedback resistor value. The 1-kΩ feedback resistor value used for the characterization curves is a good compromise between power, noise, and phase margin considerations. With the feedback resistor values selected (and set equal on each side) the input resistors are set to obtain the desired gain with input impedance also set with these input resistors. Differential I/O designs provide an input impedance that is the sum of the two input resistors. Single-ended input to differential output designs present a more complicated input impedance. Most characteristic curves implement the single-ended to differential design as the more challenging requirement over differential-to-differential I/O. For single-ended, matched, input impedance designs, Table 9-1 illustrates the suggested standard resistors set to approximately a 1-kΩ feedback. This table assumes a 50-Ω source and a 50-Ω input match and uses a single resistor on the non-signal input side for gain matching. Better matching is possible using the same three resistors on the non-signal input side as on the input side. Figure 9-4 shows the element values and naming convention for the gain of 1-V/V configuration where the gain is defined from the matched input at RT to the differential output. 50- Input Match, Gain of 1 V/V from RT, Single-Ended Source to Differential Output 50Source Impedance THS4551 Wideband, Fully Differential Amplifier RF1 1k VS+ RG1 1k RS1 50 VOPP ± RT 52.3 VOCM FDA + + RG2 1.02 k RL 1k ± PD VS- VS+ RF2 1k Copyright © 2016, Texas Instruments Incorporated Figure 9-4. Single-Ended to Differential Gain of 1 V/V with Input Matching Using Standard Resistor Values Starting from a target feedback resistor value, the desired input matching impedance, and the target gain (AV), the required input RT value is given by solving the quadratic of Equation 1. RT 2 RS § · 2RS ¨ 2RF A V2 ¸ 2 © ¹ RT 2RF 2 A V RS A V (4 A V ) 2RF 2 2RFRS2 A V AV RS A V (4 0 AV ) (1) When this value is derived, the required input side gain resistor is given by Equation 2 and then the single value for RG2 on the non-signal input side is given by Equation 3: 2 RG1 RF AV 1 RS RS RT (2) RF AV RS 1 RT 2 RG2 30 (3) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 Using these expressions to generate a swept gain table of values results in Table 9-1, where the best standard 1% resistor values are shown to minimize input impedance and gain error to target. Table 9-1. Swept Gain 50-Ω Input Match with RF = 1-kΩ (±1 Standard Values) GAIN (V/V) RF RG1 RT RG2 ZIN AV 0.1 1000 10000 49.9 10000 49.66 0.09965 1 1000 976 51.1 1000 49.2 1.0096 2 1020 499 52.3 523 48.9 1.988 5 1000 187 59 215 50.2 5.057 10 1020 88.7 69.8 118 50.6 10.09 Where an input impedance match is not required, simply set the input resistor to obtain the desired gain without an additional resistor to ground (remove RT in Figure 9-4). This scenario is common when coming from the output of another single-ended op amp (such as the OPA192). This single-ended to differential stage shows a higher input impedance than the physical RG as given by the expression for ZA (active input impedance) shown as Equation 4. ZA RG1 § ¨1 © RG1 ·§ RF · ¸¨ 1 ¸ RG2 ¹© RG1 ¹ RF 2 RG2 (4) Using Equation 4 for the gain of 1 V/V with all resistors equal to 1-kΩ shows an input impedance of 1.33 kΩ. The increased input impedance comes from the common-mode input voltage at the amplifier pins moving in the same direction as the input signal. The common-mode input voltage must move to create the current in the non-signal input RG resistor to produce the inverted output. The current flow into the signal-side input resistor is impeded because the common-mode input voltage moves with the input signal, thus increasing the apparent input impedance in the signal input path. 9.3.3 I/O Headroom Considerations The starting point for most designs is to assign an output common-mode voltage for the THS4551. For ac-coupled signal paths, this voltage is often the default midsupply voltage to retain the most available output swing around the voltage centered at the VOCM voltage. For dc-coupled designs, set this voltage with consideration to the required minimum headroom to the supplies as described in the specifications of the Electrical Characteristics table for the VOCM control. For precision ADC drivers, this output VOCM becomes the input VCM to the ADC. Often, VCM is set to VREF / 2 to center the differential input on the available input when precision ADCs are being driven. From the target output VOCM, the next step is to verify that the desired output differential peak-to-peak voltage (VOPP) stays within the supplies. For any desired differential VOPP, make sure that the absolute maximum voltage at the output pins swings with Equation 5 and Equation 6 and confirm that these expressions are within the supply rails minus the output headroom required for the RRO device. VOmax VOCM VOPP 4 (5) VOmin VOCM VOPP 4 (6) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 31 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 For instance, when the THS4551 drives the ADC3223 with a 0.95-VCM control using a single 3.0-V supply, the negative-going signal sets the maximum output swing from 0.95 VCM to 0.2 V above ground. This 0.75-V, single-sided swing becomes an available 4 × 0.75 V = 3-VPP differential around the nominal 0.95-VCM output common-mode voltage. On the high side, the maximum output is equal to 1.7 V (0.95 V + 0.75 V), which is well within the allowed maximum range of 2.8 V (3.0 V – 0.2 V). This available 3-VPP maximum differential output is also well beyond the maximum value required for the 2-VPP input ADS3223. With the output headrooms confirmed, the input junctions must also stay within the operating range. The input range limitations only appear when approaching the positive supply where a maximum 1.3-V headroom is required over the full temperature range because the input range extends to the negative supply voltage over the full temperature range. The input pins operate at voltages set by the external circuit design, the required output VOCM, and the input signal characteristics. For differential-to-differential designs where there is no signal-related movement in the input VICM voltages, ac-coupled differential input designs have a VICM equal to the output VOCM. Going towards the positive supply, the output common-mode can be set to within 1.2 V of the supply. AC-coupled input designs violate the required 1.3-V headroom on the input pins in this case. Going towards the negative supply on the VOCM setting requires a minimum of 0.55 V above the supply. This extreme is always in range for the input pins that require a minimum 0-V headroom to the negative supply. DC-coupled differential input designs must check the voltage divider from the source common-mode input voltage to the THS4551 VOCM setting. This result must be equal to an input VICM within the specified range. If the source VCM can vary over some voltage range, validate this result over that range before proceeding. For single-ended input to differential output designs, the VICM is nominally at a voltage set by the external configuration with a small swing around the nominal value because of the common-mode loop. An ac-coupled, single-ended input to differential output design places an average input VICM equal to the output VOCM for the FDA with an ac-coupled swing around the VOCM voltage following the input voltage. A dc-coupled, single-ended input to differential design gets a nominal input VICM set by the source signal common-mode level and the VOCM output voltage with a small signal-related swing around the nominal VICM voltage. One approach to deriving the VICM voltage range for any single-ended input to differential output design is to observe the output voltage swing on the non-signal input side of the FDA outputs and simply take the voltage division on the input pin to ground or to the dc reference used on that side. An example analysis is shown in Figure 9-5 using a Thevenized version of the gain of 2 values listed in Table 9-1 for a 50-Ω matched impedance, ac-coupled design. In this example, a single 3.3-V supply is used with the VOCM defaulted to midsupply or 1.65 V as a commonmode output voltage. This value is also the common-mode voltage on the input pins for the ac-coupled input to the FDA. Targeting a 4-VPP differential output swing means each output pin swings ±1 V around this 1.65-V common-mode voltage. This output swing is in range because the full swing is 0.65 V to 2.65 V relative to ground, which is well within the 0.2-V output headroom requirements on a single 3.3-V supply. THS4551 Wideband, Fully Differential Amplifier VS+ Thevinized Source VS- RS1 25.6 1 µF RF1 1.02 k VS+ RG1 499 VOUT = 4-VPP Differential RL 1k ± + ± 3.3 V + ± VOCM 0V FDA VIN = ±1.022 V 1 µF + ± + 1 µF PD VSRG2 523 VS+ RF2 1.02 k Copyright © 2016, Texas Instruments Incorporated Figure 9-5. Input Swing Analysis Circuit with AC-Coupled, Single-Ended to Differential Signal Path 32 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 The output on the lower side of this design ranges from 0.65 V to 2.65 V. This 2-VPP swing (on just one side, the other output is an inverted version and gives the 4-VPP differential maximum) is divided back by the RF2 and RG2 divider to the input pins to form a common-mode input swing on top of the 1.65-V input common-mode voltage. This divider is 0.339 × 2 VPP = 0.678 VPP or ±0.34 V around the 1.65-V input common-mode voltage. The 1.31-V to 1.99-V common-mode input swing for this design is in range for the 0 V to 2.2 V available input range (the maximum headroom is 3.3 V – 1.1 V, which is equal to 2.2 V). These voltage swings can be directly observed using the SBOC460 TINA-TI™ simulation file. Shifting the VOCM down slightly (if allowed by the design requirements) is a good way to improve the positive-swinging input headroom for this low-voltage design. Taking a more complex example by using the THS4551 to attenuate a large bipolar input signal in a dc-coupled design for an ADC is shown in Figure 9-6. To remove the peaking for this low-noise gain design, the two CF elements and an input capacitor are added to shape the noise gain at high frequencies to a capacitive divider, as described in the Section 10.1.6. In this example (including the 1.2-pF internal differential capacitor at the inputs and the 0.6-pF internal feedback capacitors), the high-frequency noise gain is 3 V/V and a flat frequency response with approximately 45 MHz of –3-dB BW is delivered. 3.1 pF 10 k VOCM 4.096 V + THS4551 Wideband, Fully Differential Amplifier RF1 1k VOUT = 7.2 VPP Differential 1 µF 10 k ± Gain of 0.2 V/V, DC-Coupled, Single-Ended Source to Differential Output VS+ RG1 4.99 k ± VS+ 5V + ± VS0V VOCM VS = ±18 V 2.6 pF + FDA + RL 1k ± + PD VS- VS+ For Attenuator Design: NG1 = 1.2 NG2 = 3 GBP = 135 MHz Zo = 14.3 MHz ± RG2 4.99 k A 1-k load is very important to include because of high-frequency resonance; no load may oscillate. RF2 1k 3.1 pF Copyright © 2016, Texas Instruments Incorporated Figure 9-6. DC-Coupled, Single-Ended to Differential Attenuator Design In this example, the output VOCM is 4.096 V / 2, which equals 2.048 V and the source signal VCM is 0 V. These values set the nominal input pin VICM to 2.048 V × 4.99 kΩ / (4.99 kΩ + 1 kΩ) = 1.71 V. Applying a ±18-V input at the 4.99-kΩ input resistor produces a 7.2-VPP differential output. That is, a ±1.8-V swing on the lower output side around the 2.048-V common-mode voltage. This 0.248-V to 3.84-V relative-to-ground swing at the output is well within the 0.2-V output headrooms to the 0-V to 5-V supplies used in the example in Figure 9-6 (with the same swing inverted on the other output side). That output swing on the lower side produces an attenuated input common mode swing of (±1.8 V × (4.99 kΩ / (4.99 kΩ + 1 kΩ)) = ±1.5 V around the midscale input bias of 1.71 V. This 0.2-V to 3.2-V input common-mode swing is well within the available 0-V to 3.8-V input range. This ±18-V bipolar input signal is delivered to a SAR ADC with a 7.2-VPP differential output with all I/O nodes operating in range using a single 5-V supply design. The source must sink the 2.048 V / 5.99 kΩ = 0.34-mA common-mode level-shifting current to take the input 0-V common-mode voltage up to the midscale 1.71-V VICM operating voltage. Using the single-ended input impedance of Equation 4, the source must also drive an apparent input load of 5.44 kΩ. Most designs do not run into an input range limit. However, using the approach shown in this section can allow a quick assessment of the input VICM range under the intended full-scale output condition. The TINA-TI™ simulation file for Figure 9-6 can be used to plot the input voltages under the intended swings and application circuit to verify that there is no limiting from this effect. Driving the I/O nodes out of range in the TINA-TI™ model results in convergence problems. Increasing the positive and negative supplies slightly in simulation is an easy way to discover the simulated swings that might be going out of range. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 33 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 As a third example of arriving at the input pin voltage swings, use the design of Figure 10-17 (the ADC3241 design). Thevenize the source to just one input resistor to get an expression for the input VICM in terms of the input voltage to be derived. Figure 9-7 shows the gain of 5 V/V, dc-coupled, matched input impedance, single-ended to differential circuit of Figure 10-17 with both sides reduced to a single input resistor. In Figure 10-17, the design operates on a single 3.3-V supply with an output VOCM equal to 0.95 V to directly connect to TI’s line of low-power ADC3xxx series of 12- and 14-bit ADCs. This family accepts a 2-VPP maximum differential voltage, which (at the input-terminating resistor of Figure 10-17) is a ±0.2-V swing. Going back to the source through the matching resistor is then a ±0.4-V source swing. Thevenizing that source with the RT element provides the ±0.217 V shown in Figure 9-7 and the total R2 as the sum of RG1 and 50 Ω || 59 Ω. THS4551 Wideband, Fully Differential Amplifier RF1 1k VOUT VS+ 3.3 V + ± VOCM VS0V + ± Thevinized Source VS+ R2 215 ±1-V Differential Output Centered on 0.95 VCM ± 0.95 V + ± VOCM VTHEV ±0.217 V FDA + + R2 215 RL 1k ± PD VS- VS+ RF2 1k Copyright © 2016, Texas Instruments Incorporated Figure 9-7. Input VICM Analysis Circuit From the Design of Figure 10-17 For an input signal (VTHEV) that swings around ground as ±VTHEV, the input pins are within a range given by Equation 7, which is a superposition of the output VOCM divided back to the input nodes and half of the input ±VTHEV signal. VICM VOCM RG V RF r THEV u RG RF 2 RF RG (7) Using the values from the design of Figure 9-7, the computed input range for the THS4551 input pins is VICM = 0.168 V ± 0.89 mV or 0.079 V to 0.257 V at the input pins. These values are well within range for the negative rail input available in the THS4551. A simpler approach to arriving at the input common mode range for this DC coupled single supply design would be to take the output voltage swing range on the lower side (non – signal input side) and simply divide it back through its resistor divider to ground on that side. The output pin voltage swing is 0.95 V ± 0.5 V or 0.45 V to 1.45 V. This swing is divided back to the input VICM by a 215 / (215 + 1000) = 0.177 ratio. This ratio computes the input pin range as 79 mV to 0.256 V, matching the input source swing results in Equation 7. The TINA-TI™ model for Figure 9-7 (available as SBOC472) also provides these input swings as shown in the simplified circuit of Figure 9-8. The large centered swing is the differential output voltage at the THS4551 output pins (which is actually the two outputs swinging ±0.5 V around a 0.95 VCM), the small centered bipolar swing is the input swing for the thevenized source of Figure 9-8, and the smallest VPP swing on a dc offset is the input VICM voltage at the non-signal side input for the circuit of Figure 9-8. 34 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 1.2 1 0.8 0.6 Output (V) 0.4 0.2 0 -0.2 -0.4 -0.6 VIN+ VOUT VS -0.8 -1 -1.2 0 100 200 300 400 500 600 Time (ns) 700 800 900 1000 D069 Figure 9-8. I/O Swing Simulation Using the TINA-TI™ Model 9.3.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances The THS4551 offers a trimmed input offset voltage and extremely low offset drift over the full –40°C to +125°C operating range. This offset voltage combines with several other error contribution terms to produce an initial 25°C output offset error band and then a drift over temperature. For each error term, a gain must be assigned to that term. For this analysis, only dc-coupled signal paths are considered. One new source of output error (versus the typical op amp analysis) arises from the effect mismatched resistor values and ratios can have on the two sides of the FDA. Any common-mode error or drift creates a differential output error through the slight mismatches arising from the external feedback and gain setting resistor tolerances or standard value constraints. The error terms (25°C and drift), along with the gain to the output differential voltage, include input offset voltage and input offset current. Input offset voltage has a gain equal to the noise gain or 1 + RF / RG, where RG is the total dc impedance from the input pins back to the source or a dc reference (typically ground). Input offset current has a gain to the differential output through the average feedback resistor value. The remaining terms arise from an assumed range on both the absolute feedback resistor mismatch and the mismatch in the divider ratio on each side of the FDA. The first of these resistor mismatch terms is the input bias current that creates a differential output offset via RF mismatch. For simplicity, the upper RF and RG values are termed RF1 and RG1 with a ratio of RF1 / RG1 ≡ G1. The lower elements are defined as RF2 and RG2 with a ratio of RF2 / RG2 ≡ G2. To compute worst-case contributions, a maximum variation in the design resistor tolerance is used in the absolute and ratio mismatches. For instance, ±1% tolerance resistors are assumed, giving a worst-case G1 that is 2% higher than nominal and a G2 that is 2% lower than nominal with a worst-case RF value mismatch of 2% as well. Using a 0.1% precision resistor reduces the gain for the input bias current, but because these precision resistors are usually only available in 1% value steps, a gain mismatch term may still need to be considered. For matched impedance designs with RT and RG1 on a single-ended to differential stage, the standard value constraint imposes a fixed mismatch in the initial feedback ratios with the tolerance of the resistors around the ratio if the non-signal input side uses a single resistor for RG2. Define the selected external resistor tolerance as ±T (so for 1% tolerance resistors, T = 0.01). Input bias current times the feedback resistor mismatch gain is ±2 × T × RFnom. Anything that generates an output common-mode level or shift over temperature also generates an output differential error term if the two feedback ratios, G1 and G2, are not equal. An error trying to produce a shift in the output common-mode voltage is overridden by the common-mode control loop where the error becomes a balanced differential error around the output VOCM. The terms that create a differential error from a common-mode term and feedback ratio mismatch include the desired VOCM voltage, any source common-mode voltage, any drift on the reference bias to the VOCM control pin, any internal offset and drift in the VOCM control path, and the input average bias current and drift. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 35 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 Considering just the output common-mode control and the source common-mode voltage, the conversion to output differential offsets is through Equation 8. VOD VOCM G1 G2 VICM G1 G2 G1 G2 1 2 (8) Neglecting any G1 and G2 mismatch because of standard values constraint, the conversion gain for these two terms can be recast in terms of the nominal RF / RG ≡ G and the tolerance T, as shown in Equation 9. When G increases, this conversion gain approaches 4T. VOD VOCM G 4T ‡ (1 G) (1 T 2 ) (9) This conversion gain to differential output error is applied to two error terms: VOCM and the input bias current and drift. (The source common-mode voltage is assumed to be 0 V. If not, apply this gain to the source common-mode voltage and any resulting shift in application.) The output error is applied to VOCM, assuming that the input control pin is driven and not floating. The input bias current and drift are multiplied by the average RF value then by the conversion gain to differential output error to create an added output differential error. As an example of using these terms to estimate the worst-case output 25°C error band and then the worst-case drift (by adding all error terms together independently), use the gain of 1-V/V configuration with RF = 1 kΩ and assume a ±1% tolerance on the resistors with the standard values used in Figure 9-9. 50- Input Match, Gain of 1 V/V from RT, Single-Ended Source to Differential Output 50Source Impedance VS+ + ± VS- 5V + ± VOCM 0V + ± THS4551 Wideband, Fully Differential Amplifier RF1 1k VS+ RG1 1k RS1 50 VOPP ± 2.5 V RT1 52.3 VOCM FDA + + RG2 1.02 k RL 1k ± PD VS- VS+ RF2 1k Copyright © 2016, Texas Instruments Incorporated Figure 9-9. DC-Coupled Gain of 1 with RF = 1 kΩ and Single-to-Differential Matched Input 50-Ω Impedance The standard value constraint on the non-signal input side actually produces more gain mismatch than the resistor tolerances. For Figure 9-9, G2 = 1000 / 1020 = 0.9804 and G1 = 1000 / 1025.6 = 0.9751 nominally, then with a ±2% tolerance around the initial gain mismatch resulting from the standard values available if 1% resistors are used. 36 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 Using the maximum 25°C error terms and nominal resistor values with an exact 2.5-V input to the VOCM control pin gives Table 9-2, gains to the output differential error (VOD), and then the summed output error band at 25°C. The output error is clearly dominated by the VOCM voltage and the effect of the nominal feedback dividers being slightly mismatched. This analysis does not include resistor tolerances but the approach is the same with the wider error bands on the gain terms. Using 1% tolerance on the resistors setting the gain matching dominates the output error band through the VOCM input voltage. For the lowest output error, this analysis shows that an exact match on the feedback dividers with precision resistors is preferred. However, doing so would require duplicating the exact network on the non-signal input side and the signal input side. Where input impedance matching is not required, the two RG resistors are simply single equal resistors and the gain mismatch is just from the tolerance of the resistors. Table 9-2. Worst-Case Output VOD Error Band ERROR TERM 25°C MAX VALUE GAIN TO VOD OUTPUT ERROR (mV) GAIN COMMENT Input VIO ±0.175 mV 1.9777 ±0.346 Average noise gain Input IOS ±50 nA 1000 ±0.05 Feedback resistor Input IBCM 1.5 µA 20 Ω ±0.03 Feedback resistor mismatch Input IBCM 1.5 µA 1 kΩ × 0.00268 ±0.004 Converted to differential by gain mismatch VOCM input 2.5 V 0.00268 ±6.7 VOCM to differential by gain mismatch Total ±7.13 The 0.00268 conversion gain for the gain ratio mismatch is the worst-case ratio starting from the initially lower G1 value resulting from the standard value constraint and using a ±1% tolerance on the RF and RG elements of the ratio. Adding in the resistor tolerances to the gain mismatch term greatly increases the contribution of those terms. Normally, the expected drift in the output VOD is of more interest than an initial error band. Table 9-3 shows these terms for the RGT package and the summed results by adding all terms independently to obtain a worst-case drift. Table 9-3. Worst-Case Output VOD Drift Band ERROR TERM OUTPUT ERROR (µV/°C) GAIN COMMENT 1.9777 ±3.56 Average noise gain 1000 ±0.12 Feedback resistor MAX VALUE GAIN TO VOD Input VIO ±1.8 µV/°C Input IOS ±120 pA/°C Input IBCM 5.0 nA/°C 20 Ω ±0.10 Feedback resistor mismatch Input IBCM 5.0 nA/°C 1 kΩ × 0.00268 ±0.013 Converted to differential by gain mismatch VOCM input ±10 µV/°C 0.00268 ±0.027 VOCM to differential by gain mismatch Total ±3.82 In Table 9-3, the input offset voltage drift dominates the output drift. For the last term, the drift for the VOCM path is just for the internal offset drift of the common-mode path with a driven input. Any added external drift on the source of the VOCM input must also be considered. This type of calculation can be repeated for the exact application circuit considering each of these terms in the context of a specific design. The absolute accuracy and drift for the THS4551 are exceptionally good. Mismatched resistor feedback ratios combined with a high drift in the VOCM control input can actually dominate the output VOD drift. Where the output differential precision is more important than the input matching accuracy, consider matching the networks on the two sides of the input to obtain improved nominal G1 to G2 match. The gains for the input bias current error terms are relatively low when using the 1-kΩ feedback values. Higher RF values provide the input-current-related drift terms more gain. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 37 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 9.4 Device Functional Modes The wideband FDA requires external resistors for correct signal-path operation. When configured for the desired input impedance and gain setting with these external resistors, the amplifier can be either on with the PD pin asserted to a voltage greater than (VS–) + 1.15 V, or turned off by asserting PD low (within 0.55 V of the negative supply). Disabling the amplifier shuts off the quiescent current and stops correct amplifier operation. The signal path is still present for the source signal through the external resistors, which provides poor signal isolation from the input to output in power-down mode. Internal protection diodes remain present across the input pins in both operating and shutdown mode. Large input signals during disable can turn on the input differential protection diodes, thus producing a load current in the supply even in shutdown. The VOCM control pin sets the output average voltage. Left open, VOCM defaults to an internal midsupply value. Driving this high-impedance input with a voltage reference within the valid range sets a target for the internal VCM error amplifier. If floated to obtain a default midsupply reference for VOCM, an external decoupling capacitor is recommended to be added on the VOCM pin to reduce the otherwise high output noise for the internal high-impedance bias (see Figure 7-45). 9.4.1 Operation from Single-Ended Sources to Differential Outputs One of the most useful features supported by the FDA device is an easy conversion from a single-ended input to a differential output centered on a user-controlled, common-mode level. Although the output side is relatively straightforward, the device input pins move in a common-mode manner with the input signal. The common-mode voltage at the input pins, which moves with the input signal, increases the apparent input impedance to be greater than the RG value. The input active impedance issue applies to both ac- and dc-coupled designs, and requires somewhat more complex solutions for the resistors to account for this active impedance, as discussed in the Section 9.3.2. 9.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversions When the signal path can be ac-coupled, the dc biasing for the THS4551 becomes a relatively simple task. In all designs, start by defining the output common-mode voltage. The ac-coupling issue can be separated for the input and output sides of an FDA design. The input can be ac-coupled and the output dc-coupled, or the output can be ac-coupled and the input dc-coupled, or both can be ac-coupled. One situation where the output can be dc-coupled (for an ac-coupled input), is when driving directly into an ADC where the VOCM control voltage uses the ADC common-mode reference to directly bias the FDA output common-mode voltage to the required ADC input common-mode voltage. In any case, the design starts by setting the desired VOCM. When an ac-coupled path follows the output pins, the best linearity is achieved by operating VOCM at midsupply, which can be easily delivered by floating the VOCM pin. The VOCM voltage must be within the linear range for the common-mode loop, as specified in the headroom specifications (approximately 0.7 V greater than the negative supply and 1.3 V less than the positive supply for the full –40°C to +125°C operation). If the output path is also ac-coupled, simply letting the VOCM control pin float is usually preferred in order to obtain a midsupply default VOCM bias with minimal elements. To limit noise, place a 0.1-µF decoupling capacitor on the VOCM control pin to ground. After VOCM is defined, check the target output voltage swing to ensure that the VOCM plus the positive and negative output swing on each side does not clip into the supplies. If the desired output differential swing is defined as VOPP, divide by 4 to obtain the ±VP (peak voltage) swing around VOCM at each of the two output pins (each pin operates 180° out of phase with the other). Check that VOCM ±VP does not exceed the absolute supply rails for the rail-to-rail output (RRO) device. Common-mode current does not flow from the common-mode output voltage set by the VOCM pin towards the device input pins side, because both the source and balancing resistor on the non-signal input side are dc blocked (see Figure 9-5). The ac-coupled input path sets the input pin common-mode voltage equal to the output common-mode voltage. 38 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 The input pin positive headroom requirement (1.2 V) is less than the VOCM positive headroom (1.3 V). If the VOCM is in range, the input pins are also in range for the ac-coupled input configuration. This headroom requirement functions similarly for when the output VOCM voltage approaches the negative supply. The approximate minimum headroom of 0.6 V to the negative supply on the VOCM voltage is greater than the input pin voltage headroom of approximately 0 V for the negative rail input design. The input common-mode voltage is also in range if the output common-mode voltage is in range and above 0.6 V from the negative supply because the input common-mode voltage follows the output VOCM setting for ac-coupled input designs. The input pin voltages move in a common-mode manner with the input signal, as described in Section 9.3.3. Confirm that the VOCM voltage plus the input VPP common-mode swing also stays in range for the input pins. 9.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversions The output considerations remain the same as for the ac-coupled design. Again, the input can be dc-coupled when the output is ac coupled. A dc-coupled input with an ac-coupled output can have some advantages to move the input VICM down by adjusting the VOCM down if the source is ground referenced. When the source is dc-coupled into the THS4551 (see Figure 9-4), both sides of the input circuit must be dc-coupled to retain differential balance. Normally, the non-signal input side has an RG element biased to whatever the source midrange is expected to be, provided that this midscale reference gives a balanced differential swing around VOCM at the outputs. Often, RG2 is simply grounded for dc-coupled, bipolar-input applications. This configuration provides a balanced differential output if the source swings around ground. If the source swings from ground to some positive voltage, grounding RG2 gives a unipolar output differential swing from both outputs at VOCM (when the input is at ground) to one polarity of the swing. Biasing RG2 to an expected midpoint for the input signal creates a differential output swing around VOCM. One significant consideration for a dc-coupled input is that VOCM sets up a common-mode bias current from the output back through RF and RG to the source on both sides of the feedback. Without input balancing networks, the source must sink or source this dc current. After the input signal range and biasing on the other RG element is set, check that the voltage divider from VOCM to VIN through RF and RG (and possibly RS) establishes an input VICM at the device input pins that is in range. If the average source is at ground, the negative rail input stage for the THS4551 is in range for applications using a single positive supply and a positive output VOCM setting because this dc common-mode current lifts the average FDA input summing junctions up off of ground to a positive voltage (the average of the V+ and V– input pin voltages on the FDA). TINA-TI™ simulations of the intended circuit offer a good check for input and output pin voltage swings (see Figure 9-7). 9.4.2 Operation from a Differential Input to a Differential Output In many ways, this method is a much simpler way to operate the FDA from a design equations perspective. Again, assuming that the two sides of the circuit are balanced with equal RF and RG elements, the differential input impedance is now just the sum of the two RG elements to a differential inverting summing junction. In these designs, the input common-mode voltage at the summing junctions does not move with the signal but must be dc biased in the design range for the input pins and must take into account the voltage headroom required to each supply. Slightly different considerations apply to ac- or dc-coupled differential input to differential output designs, as described in the following sections. 9.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues The most common way to use the THS4551 with an ac-coupled differential source is to simply couple the input into the RG resistors through the blocking capacitors. Figure 9-10 shows a typical blocking capacitor approach to a differential input. An optional input differential termination resistor (RM) is included in this design. The RM element allows the input RG resistors to be scaled up and still delivers lower differential input impedance to the source. In this example, the RG elements sum to show a 1-kΩ differential impedance and the RM element combines in parallel to provide a net 500-Ω ac differential impedance to the source. Again, the design ideally proceeds by selecting the RF element values, then the RG to set the differential gain, and then an RM element (if needed) to achieve a target input impedance. Alternatively, the RM element can be eliminated, with the 2 × RG elements set to the desired input impedance and RF set to obtain the differential gain (equal to RF / RG). Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 39 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 THS4551 Wideband, Fully Differential Amplifier VS+ VS- + + Differential I/O with AC-Coupled Input 10 nF VS+ RG1 499 VOUT ± VOCM ± 3.3 V ± RF1 1.02 k 0V VIN RF1 1.02 k 1 µF 10 nF + FDA + PD VSRG2 499 RL 1k ± VS+ RF2 1.02 k Copyright © 2016, Texas Instruments Incorporated Figure 9-10. Example AC-Coupled Differential Input Design The dc biasing for an ac-coupled differential input design is very simple. The output VOCM is set by the input control voltage and, because there is no dc current path for the output common-mode voltage (as long as RM is only differential and not split and connected to ground for instance), the dc bias also sets the common-mode operating points for the input pins. For a purely differential input, the voltages on the input pins remain fixed at the output VOCM setting and do not move with the input signal (unlike the single-ended input configurations where the input pin common-mode voltages do move with the input signal). The SLOC341 TINA-TI™ simulation file is available for Figure 9-10. 9.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues Operating the THS4551 with a dc-coupled differential input source is very simple and only requires that the input pins stay in range for the dc common-mode operating voltage. The example in Figure 9-11 takes the output of a dual precision op amp (such as the OPA2192) where a high differential input signal is attenuated by the THS4551 down into the range of an 18-bit SAR ADC such as the 2-MSPS ADS9110. The input stage provides a differential gain of 21 V/V with a common-mode gain of 1 V/V. This example amplifies a small differential signal on top of a very-wide range common-mode voltage. The input common-mode voltage appears at the outputs of the OPA2192. The input common-mode voltage is level shifted by the FDA common-mode control to be at the required output common-mode voltage to drive the ADS9110 SAR ADC (with a 4.096-V reference, as shown in Figure 9-11); the FDA output common-mode voltage must be at the 2.048 V shown in Figure 9-11. This design offers a very high CMRR using the common-mode control loop of the FDA to reset the output common-mode voltage from that delivered to the inputs of the OPA2192. The actual CMRR from the OPA2192 inputs to the FDA outputs is dominated by the resistor mismatches in the FDA. The feedback and differential input capacitors are included to shape the noise gain as described in Section 10.1.6. This full example circuit is available as a TINA-TI™ simulation file. 40 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 Gain of 0.2 V/V, DC-Coupled, Differential Input to Differential Output 2k VOCM 4.096 V + 10 k ± 22 pF VCC 2.048 V 10 k THS4551 Wideband, Fully Differential Amplifier 1 µF RG1 4.99 k ± VIN1 RF1 1k 10 + ADS9110 Inputs VS+ VEE 200 VS+ VS- VCC VEE ± OPA2192 49 pF 2k VOCM FDA + 5V + ± 0V + ± 15 V + -15 V ± + 12 nF ± + PD VCC ± VS- ± VS+ 10 VIN2 + VEE RG2 4.99 k RF2 1k 22 pF Copyright © 2016, Texas Instruments Incorporated Figure 9-11. Example DC-Coupled Differential I/O Design from a Precision Dual Op Amp to an 18-Bit SAR 9.4.3 Input Overdrive Performance Figure 7-12 illustrates a 2X overdrive triangle waveform for the THS4551. The input resistor is driven with a ±9-V swing for the gain of 2-V/V configuration in the test circuit of Figure 8-1 using a single 5-V supply. When the output maximum swing is reached at approximately the supply values, the increasing input voltage turns on the internal protection diodes across the two input pins. The internal protection diodes are two diodes in series in both polarities. This feature clamps the maximum differential voltage across the inputs to approximately 1.5 V when the output is limited at the supplies but the input exceeds the available range. The input resistors on both sides limit the current flow in the internal diodes under these conditions. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 41 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 10 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 10.1 Application Information Most applications for the THS4551 strive to deliver the best dynamic range in a design that delivers the desired signal processing along with adequate phase margin for the amplifier itself. The following sections detail some of the design issues with analysis and guidelines for improved performance. 10.1.1 Noise Analysis The first step in the output noise analysis is to reduce the application circuit to the simplest form with equal feedback and gain setting elements to ground. Figure 10-1 shows the simplest analysis circuit with the FDA and resistor noise terms to be considered. enRg2 enRf2 RG RF r r In+2 + In±2 eno2 ± eni2 enRg2 enRf2 RG RF r r Figure 10-1. FDA Noise Analysis Circuit The noise powers are shown in Figure 10-1 for each term. When the RF and RG (or RI) terms are matched on each side, the total differential output noise is the root sum squared (RSS) of these separate terms. Using NG ≡ 1 + RF / RG, the total output noise is given by Equation 10. Each resistor noise term is a 4kT × R power (4kT = 1.6E-20J at 290K). eo eniNG 2 2 iNRF 2 2 4kTRFNG (10) The first term is simply the differential input spot noise times the noise gain, the second term is the input current noise terms times the feedback resistor (and because there are two uncorrelated current noise terms, the power is two times one of them), and the last term is the output noise resulting from both the RF and RG resistors, at again twice the value for the output noise power of each side added together. Running a wide sweep of gains when holding RF close to 1 kΩ and setting the input up for a 50-Ω match gives the standard values and resulting noise listed in Table 10-1. Note that when the gain increases, the input-referred noise approaches only the gain of the FDA input voltage noise term at 3.3 nV/√ Hz. 42 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 Table 10-1. Swept Gain of the Output- and Input-Referred Spot Noise Calculations GAIN (V/V) RF RG1 RT RG2 ZIN AV EO (nV/√ Hz) EI (nV/√ Hz) 0.1 1000 10000 49.9 10000 49.66 0.09965 7 70 1 1000 976 51.1 1000 49.2 1.0096 10.4 10.4 2 1020 499 52.3 523 48.9 1.988 13.9 6.95 5 1000 187 59 215 50.2 5.057 23 4.6 10 1020 88.7 69.8 118 50.6 10.09 36.4 3.64 10.1.2 Factors Influencing Harmonic Distortion As illustrated in the swept frequency harmonic distortion plots (Figure 7-13 and Figure 7-31), the THS4551 provides extremely low distortion at lower frequencies. In general, an FDA output harmonic distortion mainly relates to the open-loop linearity in the output stage corrected by the loop gain at the fundamental frequency. When the total load impedance decreases, including the effect of the feedback resistor elements in parallel for loading purposes, the output stage open-loop linearity degrades, thus increasing the harmonic distortion; see Figure 7-16 and Figure 7-34. When the output voltage swings increase, very fine scale open-loop output stage nonlinearities increase that also degrade the harmonic distortion; see Figure 7-14 and Figure 7-32. Conversely, decreasing the target output voltage swings drops the distortion terms rapidly. A nominal swing of 2 VPP is used for harmonic distortion testing where Figure 7-14 illustrates the effect of going up to an 8-VPP differential input that is more common with SAR converters. Increasing the noise gain functions to decrease the loop gain resulting in the increasing harmonic distortion terms; see Figure 7-18 and Figure 7-36. One advantage to the capacitive compensation for the attenuator designs is that the noise gain is shaped up with frequency to achieve a crossover at an acceptable phase margin at higher frequencies. This technique (see Section 10.1.6) holds the loop gain high at frequencies lower than the noise gain zero, thus improving distortion at lower frequencies. The THS4551 holds nearly constant distortion when the VOCM operating point is moved in the allowed range; see Figure 7-17 and Figure 7-35. Clipping into the supplies with any combination of VOCM and VOPP rapidly degrades distortion performance. The THS4551 does an exceptional job of converting from single-ended inputs to differential outputs with very low harmonic distortions. External resistors of 1% tolerance are used in characterization with good results. Unbalancing the feedback divider ratios does not degrade distortion directly. Imbalanced feedback ratios convert common-mode inputs to a differential mode at the outputs with the gain described in Section 9.3.4. 10.1.3 Driving Capacitive Loads The capacitive load of an ADC or some other next-stage device is commonly required to be driven. Directly connecting a capacitive load to the output pins of a closed-loop amplifier such as the THS4551 can lead to an unstable response; see the step response plots into a capacitive load (Figure 7-8, Figure 7-10, Figure 7-26, and Figure 7-28). One typical remedy to this instability is to add two small series resistors (RO) at the outputs of the THS4551 before the capacitive load. Figure 7-6 and Figure 7-24 illustrate parametric plots of recommended RO values versus differential capacitor load values and gains. Operating at higher noise gains requires lower RO values to obtain a ±0.5-dB flat response for the same capacitive load. Some direct parasitic loading is acceptable without a series RO that increases with gain setting (see Figure 7-8, Figure 7-10, Figure 7-26, and Figure 7-28 where the RO value is 0 Ω). Even when these plots suggest that a series RO is not required, good practice is to leave a place for the RO elements in a board layout (a 0-Ω value initially) for later adjustment in case the response appears unacceptable. The rail-to-rail output stage of the THS4551 has an inductive characteristic in the open-loop output impedance at higher frequencies; see Figure 9-3. This inductive open-loop output impedance introduces added phase shift at the output pins for direct capacitive loads and feedback capacitors. Larger values of feedback capacitors (greater than 100 pF) can risk a low phase margin. Including a 10-Ω to 15-Ω series resistor with a feedback capacitor can be used to reduce this effect. The TINA-TI™ simulation model does a good job of predicting these issues and illustrating the effect for different choices of capacitive load isolating resistors (RO) and different feedback capacitor configurations. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 43 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 10.1.4 Interfacing to High-Performance Precision ADCs The THS4551 provides a simple interface to a wide variety of precision SAR and delta-sigma (ΔΣ) ADCs. To deliver the exceptional distortion at the output pins, considerably wider bandwidth than what is typically required in the signal path to the ADC inputs is provided by the THS4551. This wide amplifier bandwidth provides the low broadband, closed-loop output impedance to supply the sampling glitches and to recover quickly for the best SFDR. A particularly challenging task is to drive the high-frequency modulator sample rates for a precision ΔΣ converter where the modulator frequency can be far higher than the final output data rate. Figure 10-2 shows a tested example circuit using the THS4551 in a 500-kHz, active multiple feedback (MFB) filter driving the 24-bit ADS127L01. This filter is designed for FO = 500 kHz and Q = 0.63 to give a linear phase response with the –3-dB frequency at 443 kHz. This example circuit is available as a TINA-TI™ simulation file. 1.2 k 270 pF VOCM 330 1 nF 470 pF 1.2 k + ± 3V 5 + ± 1.2 k THS4551 10 AINN ADS127L01 22 nF AINP 330 5 10 270 pF 1.2 k Copyright © 2016, Texas Instruments Incorporated Figure 10-2. 500-kHz Low-Pass Active Filter This 3-V supply example provides a low-power interface to the very low-power ADC. This circuit is available on the ADS127L01EVM board. The 5-Ω resistors inside the loop at the output pins and the 1-nF differential capacitor across the FDA input pins are not part of the filter design. These elements function to improve the loop-phase margin with minimal interaction with the active filter operation To observe the loop gain and phase margin, use the SBOC461 TINA-TI™ simulation file. Tested performance with the ADS127L01 at a 4-kHz input shows the exceptional THD and SNR of –114 dBc and 106 dB, respectively. Figure 10-3 uses the ADS127L01 at a modulator frequency of 16 MHz. 0 -20 -40 Amplitude (dB) -60 -80 -100 -120 -140 -160 -180 -200 0 20 40 60 80 Frequency (kHz) 100 120 D066 Figure 10-3. 4-kHz FFT Test for the Gain of 1 V/V Interface in Figure 10-2 44 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 10.1.5 Operating the Power Shutdown Feature The CMOS input pin must be asserted to the desired voltage for operation. An internal pullup resistor is not provided on the PD pin so that off-state quiescent current can be minimized. For applications simply requiring the device to be powered on when the supplies are present, tie the PD pin to the positive supply voltage. The disable operation is referenced from the negative supply, normally ground. For split-supply operation, with the negative supply below ground, a disable control voltage below ground is required to turn the THS4551 off. To assure an off state condition, the disable control pin must be below a voltage within 0.55 V of the negative supply. For single-supply operation, a minimum of 1.15 V above the negative supply (ground in this case) is required to assure on operation. This logic threshold range allows direct operation from a 1.8-V supply logic when the THS4551 operates with a single positive supply and ground. 10.1.6 Designing Attenuators Operating the THS4551 at a low-noise gain (or with higher feedback resistors) can cause a lower phase margin to exist, thus giving the response peaking illustrated in Figure 7-1 for the gain of a 0.1 (a 1/10 attenuator) condition. Although operating the THS4551 as an attenuator is often useful, taking a large input range to a controlled output common-mode voltage with a purely differential signal around the VOCM voltage, the response peaking illustrated in Figure 7-1 is usually undesirable. Several approaches can be used to reduce or eliminate this peaking, usually at the cost of higher output noise. DC attenuation at the input usually increases the output noise broadband, whereas using an ac noise gain shaping technique that peaks the noise gain only at higher frequencies is more desirable. This peaking output noise can then be filtered off with the typical passive RC filters often used after this stage. Figure 10-4 shows a simplified schematic for the gain of 0.1-V/V test from Figure 7-1. Gain of 0.1 V/V, DC-Coupled, Single-Ended Source to Differential Output VS+ RG1 10 k 2.5 V VS+ VS- + + ± -2.5 V THS4551 Wideband, Fully Differential Amplifier RF1 1k VOUT ± VOCM VIN FDA + + ± RL 1k ± PD VS- VS+ RF2 1k RG2 10 k Copyright © 2016, Texas Instruments Incorporated Figure 10-4. Divide-by-10 Attenuator Application for the THS4551 A 5-dB peaked response (see Figure 10-6) results from the configuration of Figure 10-4, which results from a nominal 32° phase margin. This peaking can be eliminated by placing two feedback capacitors across the RF elements and a differential input capacitor. Adding these capacitors provides a transition from a resistively set noise gain (NG1 = 1.1 in Figure 10-4) to a capacitive divider at high frequency, and flattening out to a higher noise gain (NG2). The key for this approach is to target a ZO where the noise gain begins to peak up. Using only the following terms, and targeting a closed-loop flat (Butterworth) response, gives this solution sequence (from Equation 11 to Equation 13) for ZO and then the capacitor values. See the OPA847 data sheet (page 12) for a discussion of this inverting noise gain shaping technique. • • • • Gain bandwidth product in Hz (135 MHz for the THS4551) Low-frequency noise gain, NG1 (equal to 1.1 in the attenuator gain of a 0.1-V/V design) The target high-frequency noise gain is selected to be higher than NG1 (NG2 = 5 V/V) in this example Feedback resistor value, RF (is assumed balanced for this differential design = 1 kΩ) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 45 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 From these elements, for any voltage feedback op amp or FDA, solve for ZO as shown in Equation 11: ZO GBP § ¨1 NG12 ¨© NG1 NG2 1 2 NG1 · ¸ NG2 ¸¹ (11) From this target zero frequency in the noise gain, the feedback capacitors can be solved as Equation 12: CF 1 2S ‡ RF ‡ ZO ‡ NG2 (12) The next step is to resolve the input capacitance on the summing junction. Equation 13 is for a single-ended op amp where the capacitor goes to ground. To use the capacitance (CS) resulting from Equation 13 for a voltage-feedback FDA, cut the target value in half and place the resulting CS across the two inputs (reducing the external value by the specified internal differential capacitance). CS NG2 1 CF (13) Using the computed capacitor values allows for an estimate of the resulting flat response bandwidth f–3dB frequency, as shown in Equation 14: f 3dB | GBP ‡ ZO (14) Running through these steps for the THS4551 in the attenuator circuit of Figure 10-4 provides the proposed compensation of Figure 10-5, where Equation 14 estimates a bandwidth of 22 MHz (the ZO target is 3.5 MHz). The solutions for CF gives 9 pF, where this value is reduced to 8.4 pF to account for the internal 0.6-pF feedback. The single-ended solution for CS gives 36 pF, which is reduced to 18 pF to be differential, and is then further reduced to 16.8 pF to account for the internal 1.2-pF differential input capacitance of the THS4551. CF1 8.4 pF Gain of 0.1 V/V, DC-Coupled, Single-Ended Source to Differential Output VS+ VS+ RG1 10 k VS- 2.5 V -2.5 V ± + ± VOUT ± VOCM + THS4551 Wideband, Fully Differential Amplifier RF1 1k Vin CS 16.8 pF FDA + RL 1k ± + PD VS- VS+ RF2 1k RG2 10 k CF2 8.4 pF Copyright © 2016, Texas Instruments Incorporated Figure 10-5. Compensated Attenuator Circuit Using the THS4551 The 16.8 pF across the inputs is really a total of 36 pF for a single-ended design from Equation 13 reduced by half and then the 1.2-pF internal capacitance is removed. These two designs (with and without the compensation capacitors) were both bench tested and simulated using the THS4551 TINA-TI™ model, which resulted in Figure 10-6. The TINA-TI™ simulation files used for Figure 10-6 are available both without the compensation capacitors and with the capacitors in place. 46 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 -12 -14 -16 Gain (dB) -18 -20 -22 -24 -26 -28 Bench, wo Capacitors Bench, with Capacitors TINA-TI•, wo Capacitors TINA-TI•, with Capacitors -30 1M 10M Frequency (Hz) 100M D067 Figure 10-6. Attenuator Response Shapes With and Without External Capacitors This approach does a good job of flattening the response for what starts out as a low phase margin attenuator application. The simulation model does a very good job of predicting the peaking and showing the same improvement with the external capacitors (both give a flat, approximately 24-MHz, closed-loop bandwidth for the gain of 0.1-V/V design). The output noise starts to peak up (because of the noise gain shaping of the capacitors) above 3.5 MHz in this example. These stages normally drive the RC filter at the input of a SAR ADC that filters off the noise peaking above 3.5 MHz. 10.1.7 The Effect of Adding a Feedback Capacitor Adding a feedback capacitor to band-limit the signal path is very common in lower frequency designs. This approach is very effective for the signal path gain but does create the potential for high-frequency peaking and oscillation for a wideband device such as the THS4551. The feedback capacitor by itself takes the noise gain to 1 V/V at high frequencies. Depending on the frequency where the noise gain goes to 1V/V, and what added phase margin reduction may already be in place resulting from the load RC, the feedback capacitors can cause instability. Figure 10-7 shows the starting point for a typical band-limited design. At lower frequencies, this example delivers a gain of 10 V/V with an intentional band limit in the feedback RC at 320 kHz. This single 5-V design targets a midsupply output common-mode voltage with only a noise reduction capacitor on the VOCM input control. CF1 250 pF High-Gain, Single-Ended to Differential Output Stage with Feedback Pole VS+ VS+ RG1 200 VS- + ± 0V + 10 ± VOCM 5V THS4551 Wideband, Fully Differential Amplifier RF1 2k VIN 10 nF ± FDA + 10 nF ± + SAR ADC Input PD VS- VS+ 10 RF2 2k RG2 200 CF2 250 pF Copyright © 2016, Texas Instruments Incorporated Figure 10-7. Single-Ended to Differential Stage with a Feedback Pole Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 47 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 Gain (dB) 20 15 200 Gain (dB) Phase (deg) 175 10 150 5 125 0 100 -5 75 -10 50 -15 25 -20 0 -25 -25 -30 100k Phase (deg) The response shape must be probed at the FDA output pins before the added RC pole to the SAR input. Running a wideband sweep with the THS4551 TINA-TI™ model using the SBOC475 simulation file shows a resonance at 50 MHz in Figure 10-8 resulting from the feedback capacitor. -50 1M 10M Frequency (Hz) 100M D070 Figure 10-8. Gain and Phase Plot with a Feedback Pole One approach to increasing the phase margin when there is a feedback capacitor is to include a differential input capacitor. This approach increases the noise gain at higher frequencies, thus creating a lower-frequency loop gain equal to a 0-dB crossover with more phase margin. Figure 10-9 shows a differential input capacitor equal to the feedback capacitor in the test circuit. This approach increases the noise gain from 1 V/V at higher frequencies (with only a feedback capacitor) to a noise gain of 3 V/V at higher frequencies. CF1 250 pF High-Gain, Single-Ended to Differential Output Stage with Feedback Pole VS+ RF1 2k VS+ RG1 200 VS- + ± 0V + ± 10 ± VOCM 5V THS4551 Wideband, Fully Differential Amplifier VIN 250 pF 10 nF FDA + 10 nF ± + SAR ADC Input PD VS- VS+ 10 RF2 2k RG2 200 CF2 250 pF Copyright © 2016, Texas Instruments Incorporated Figure 10-9. Single-Ended to Differential Stage with a Feedback Pole and Differential Input Capacitor Re-running the wideband response (using the SBOC474 TINA-TI™ simulation file) simulation illustrates in Figure 10-10 that the resonance is greatly reduced with the higher noise gain at the loop gain equal to a 0-dB crossover at a lower frequency. Although this example is only modestly peaking, good design practice is to include a place for a differential input capacitor (even if not used) for any design using a feedback capacitor across the feedback resistors. This recommendation applies to this simple example and to multiple feedback active filter designs. 48 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com Gain (dB) 20 10 200 Gain (dB) Phase (deg) 160 0 120 -10 80 -20 40 -30 0 -40 -40 -50 -80 -60 100k Phase (deg) SBOS778D – APRIL 2016 – REVISED APRIL 2021 -120 1M 10M Frequency (Hz) 100M D071 Figure 10-10. Gain and Phase Plot with a Differential Input Capacitor 10.2 Typical Applications 10.2.1 An MFB Filter Driving an ADC Application One common application for the THS4551 is to take a single-ended, high VPP voltage swing (from a high-voltage precision amplifier such as the OPA192) and deliver that swing to precision SAR ADC as a single-ended to differential conversion with output common-mode control and implement an active 2nd-order multiple feedback (MFB) filter design. Designing for a 40-VPP maximum input down to an 8-VPP differential swing requires a gain of 0.2 V/V. Targeting a 100-kHz Butterworth response with the RC elements tilted towards low noise gives the example design of Figure 10-11. Note that the VCM control is set to half of a 4.096-V reference, which is typical for 5-V differential SAR applications. OPA192 Output VS+ 5V + 2.96 k VS0V ± RG1 1.57 k 910 pF 20 ± 10 100 pF VS+ + VIN ± 1.5 nF 100 fF VOCM FDA + VS+ ± 20 2.96 k RG2 1.57 k RF2 592 8-VPP Differential SAR ADC Input PD VS- + 2.2 nF ± + VOCM 2.048 V THS4551 Wideband, Fully Differential Amplifier RF1 592 10 100 pF 910 pF Copyright © 2016, Texas Instruments Incorporated Figure 10-11. Example 100-kHz Butterworth Filter Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 49 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 10.2.1.1 Design Requirements The requirements for this application are: • • • • • Single-ended to differential conversion Attenuation by 0.2-V/V gain Active filter set to a Butterworth, 100-kHz response shape Output RC elements set by SAR input requirements (not part of the filter design) Filter element resistors and capacitors are set to limit added noise over the THS4551 and noise peaking 10.2.1.2 Detailed Design Procedure The design proceeds using the techniques and tools suggested in the Design Methodology for MFB Filters in ADC Interface Applications application note (SBOA114). The process includes: • • • • • • Scale the resistor values to not meaningfully contribute to the output noise produced by the THS4551 by itself Select the RC ratios to hit the filter targets when reducing the noise gain peaking within the filter design Set the output resistor to 10 Ω into a 2.2-nF differential capacitor Add 100-pF common-mode capacitors to the load capacitor to improve common noise filtering Inside the loop, add 20-Ω output resistors after the filter feedback capacitor to increase the isolation to the load capacitor Include a place for a differential input capacitor (illustrated as 100 fF in Figure 10-11) 10.2.1.3 Application Curves Probing the response to the output pins by using the THS4551 SBOC471 TINA-TI™ simulation model (before the RC filter to the SAR ADC) illustrates the expected response plus some peaking at higher frequencies. Any signal or noise peaking that appears at the output because of this peaking is rolled off by the RC filter between the FDA and SAR inputs. A place for a differential input capacitor is illustrated in Figure 10-11 (as 0.1 pF) but is not used for this simulation. This slight peaking is a combination of low phase margin and feedthrough via the feedback capacitor to the increasing open-loop output impedance of Figure 9-3. The loop gain and phase response are available as a TINA-TI™ simulation file. Obtaining the SNR to the ADC input pins, and assuming an 8-VPP full scale (2.83 VRMS), gives the result of Figure 10-13. The 113-dB SNR shown in Figure 10-13 does not limit the performance for any SAR application. -40 150 -60 0 -80 -150 -100 -300 -120 -450 -140 10k 100k 1M Frequency (Hz) 10M T -600 100M D072 150.00 Signal to Noise [dB] -20 450 Gain (dB) Phase (deg) 300 Phase (deg) Gain (dB) 0 140.00 130.00 120.00 110.00 10k 100k 1MEG 10MEG Frequency (Hz) 100MEG Figure 10-13. Signal-to-Noise Ratio Plot Figure 10-12. Gain and Phase Plot for a 100-kHz Butterworth Filter 50 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 10.2.2 Differential Transimpedance Output to a High-Grade Audio PCM DAC Application The highest-grade audio digital-to-analog converters (DACs) are a differential current-mode output. These devices normally suggest a two-amplifier transimpedance stage to hold the DAC output voltages fixed when the amplifiers produce a differential voltage swing at the outputs. Often, the differential voltage swing is then converted to single-ended in a differencing amplifier stage to drive headphone loads (see Figure 35 in the OPA1611). The emerging high-power class D audio amplifiers often require differential inputs. Applying the THS4551 as a differential transimpedance stage offers a simple solution for very low-distortion, differentialoutput audio channels. Starting with the output specifications for a very high-performance PCM1792A audio DAC, the requirements for the THS4551 interface can be extracted. The DAC is a current-sourcing device that requires its outputs to be held at ground when using a transimpedance amplifier. Using the DAC 3.3-V supply and the LM27762 low-noise, low-dropout (LDO) regulator and inverter provides a ±2.5-V supply to the THS4551. Operating the THS4551 on ±2.5-V supplies places all nodes in range for an input VCM equal to GND (and the DAC output voltages as well) and an FDA output VOCM also equal to GND. The center current in Table 10-2 is a fixed 6.2-mA dc current coming out of the DAC outputs regardless of the DAC code. This dc common-mode current can be absorbed by the –2.5-V supply at the input pins to hold the DAC compliance voltage and FDA input pins at ground. The FDA controls the output common-mode voltage, set to ground in this case, whereas the input pin voltage (which does not move with the DAC output differential current) is controlled with a resistor to the negative supply. Table 10-2. PCM1792A Analog Output Specification ANALOG OUTPUT TEST CONDITION Gain error Gain mismatch, channel-to-channel Bipolar zero (BPZ) error At BPZ Output current Full-scale (0 dB) Center current At BPZ MIN TYP MAX –6 ±2 6 % of FSR UNIT –3 ±0.5 3 % of FSR –2 ±0.5 2 % of FSR 7.8 mAPP –6.2 mA This bias is provided by the 402-Ω resistors to –2.5 V, as illustrated in Figure 10-14. This design takes the differential 7.8 mAPP from the DAC and produces a ±1.46-V swing on each output of the THS4551. This configuration gives a full-scale differential 5.85 VPP available on the ±2.5-V supply design centered at ground at both the inputs and outputs. Although the LM27762 provides a very-low noise, –2.5-V supply, using 0.1% resistors in the current sink path to the –2.5-V supply as well as the feedback resistors limits any common-mode noise on the –2.5-V supply to differential mode conversion at the FDA outputs. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 51 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 CF1 2.4 nF VS+ 4.4 VS- THS4551 Wideband, Fully Differential Amplifier VS2.5 V + ± -2.5 V + LM27762 Supplies RF1 750 6.2 mA ± 402 VS+ ± VOCM PCM1792A Complementary Current Output DAC + FDA ± + 20 nF PD VS+ VS- 6.2 mA RF2 750 402 VS- 4.4 CF2 2.4 nF Copyright © 2016, Texas Instruments Incorporated Figure 10-14. PCM1792A DAC Output Driver 10.2.2.1 Design Requirements To implement a differential transimpedance output interface to the PCM1792A DAC, the following requirements must be met: • • • • • The center current of the DAC must be considered to hold the DAC output voltage at ground. Using an FDA controls the output side common-mode voltage, but the input common-mode voltage must also be controlled to ground. A direct means of sinking the center current is to add a pulldown resistor at the DAC outputs to a negative supply. Generating a ±2.5-V supply for this current sink requirement and the THS4551 is accomplished with the LM27762. The transimpedance gain can be set using the feedback resistors of the THS4551 FDA. These resistors are very flexible, but when set, the bandwidth in this stage is set to 88 kHz using a feedback capacitor in parallel with the resistive gain element. When the feedback capacitor is set, a differential input capacitor is added to increase the high-frequency noise gain for the overall loop gain stability. These frequency response control capacitors interact with the inductive open-loop output impedance to form a high-frequency resonance. Adding a small series resistor to the feedback capacitor paths reduces this effect. 10.2.2.2 Detailed Design Procedure Proceed with this design using the techniques described in the Design for Wideband Differential Transimpedance DAC Output application note (SBAA150): • • • • • • • 52 Generate the bipolar balanced supplies using the LM27662. Set the THS4551 output common-mode voltage at midsupply by grounding the VOCM pin. Control the input pin operating voltage by sinking the center current out of the DAC to the –2.5-V supply with precision 402-Ω resistors. Set the gain for the complementary current output signal from the DAC by selecting the feedback resistor to be 750 Ω. Set this resistor to keep the resulting output swing to be less than the available 9-VPP differential swing. Control the bandwidth in this differential transimpedance stage to 88 kHz using the 2.4-nF feedback capacitor on each side. Increase the high-frequency noise gain to 17.7 V/V by adding a differential input capacitor of 20 nF. Isolate these feedback capacitors with a series 4.4-Ω resistor in series with the feedback capacitors. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 10.2.2.3 Application Curves Gain (dB) 70 65 240 Gain (dB) Phase (deg) 200 60 160 55 120 50 80 45 40 40 0 35 -40 30 -80 25 -120 20 1k 10k 100k 1M Frequency (Hz) Phase (deg) The bandwidth is controlled to 88 kHz by using the 2.4-nF feedback capacitors. Amplifier stability is controlled by the 20-nF differential capacitor across the DAC outputs. The added 4.4 Ω in series with the feedback 2.2-nF capacitor isolates this capacitance from the inductive open-loop output impedance. To observe the effect of adding these small resistors in series with the feedback capacitors, use the TINA-TI™ loop gain simulation circuit. Include the DAC source capacitance in any final design analysis. Running the frequency response for this circuit (available as a TINA-TI™ simulation file) provides this result. The 63.5-dBΩ gain is the 1.5-kΩ transimpedance gain provided in this design. -160 100M 10M D074 Figure 10-15. Gain and Phase Plot of DAC Output Driver Running a full-scale sine wave at 1 kHz with ±1.95 mA on each output from the DAC at 180° out of phase, and probing each THS4551 output pin separately results in the expected ±1.46 V on each output pin, as shown in Figure 10-16. More output swing is available for the RRO device using the ±2.5-V supplies provided by the LM27762 by simply increasing the feedback resistor values. 2.5 VOUTVOUT+ 2 Output Voltage (V) 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.2 0.4 0.6 0.8 1 1.2 Time (ms) 1.4 1.6 1.8 2 D075 Figure 10-16. Output Waveform of the DAC Output Driver Although this example is on the audio signal generation side, the THS4551 can also be used to convert a single-ended line input to a differential driver into an audio ADC. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 53 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 10.2.3 ADC3k Driver with a 2nd-Order RLC Interstage Filter Application The THS4551 is well suited to low-power, dc-coupled requirements driving low-power pipeline ADCs (such as the ADC3241 25-MSPS, 14-bit, dual device). Figure 10-17 shows an example design taking a bipolar input to a –1-dBFS swing at the ADC input of 1.8 VPP. In this case, a 50-Ω source and input matching is assumed with a gain of 5 V/V to the output pins with a 2nd-order interstage filter adding a –1-dB insertion loss. Full-scale voltage at the input of RT and RG1 is then ±0.2 V. The 0.95-V output common-mode voltage is provided by the ADC. The output filter provides a noise-power bandwidth limit with a low overshoot step response with no common-mode level shift from the 0.95-V voltage provided by the ADC. VS+ 3.3 V VS- + 0V ± ADC Output Common-Mode Voltage 50- Input Match, Gain of 5 V/V from RT, Single-Ended Source to Differential Output + RF1 1k 50- Source Impedance ± 10-MHz, Second-Order Bessel Filter VS+ RG1 187 RS1 50 40.2 390 nH 5.6 VOUT ± VOCM VIN 950 mV THS4551 Wideband, Fully Differential Amplifier + RT1 59 VOCM FDA + + ± RG2 215 360 pF ± ADC3241 Inputs 732 PD VS- VS+ 40.2 390 nH 5.6 RF2 1k Copyright © 2016, Texas Instruments Incorporated Figure 10-17. ADC3k Driver with a 2nd-Order RLC Interstage Filter 10.2.3.1 Design Requirements For this design example, the requirements include: • • • • • Provide a wideband, 50-Ω input impedance match for a single-ended source centered on ground. From the input termination, provide a gain of 5 V/V to the FDA output pins as a differential signal. Set the output common-mode operating point using the ADC common-mode output voltage as the VOCM input to the THS4551 FDA. Implement a low-overshoot, noise-band-limiting filter between the FDA and the ADC. Use only differential shunt elements in the filter to pass the FDA output common-mode voltage to the ADC with no level shifting. Design the filter as a –1-dB insertion loss filter with a low series resistor to limit the common-mode level shift resulting from the ADC input sample-rate-dependent common-mode current. 10.2.3.2 Detailed Design Procedure The design proceeds as follows: • • • • • • • 54 Select the feedback resistor to be 1 kΩ and use the values from Table 9-1 at a gain of 5 V/V to implement a 50-Ω input match with a gain of 5 V/V. Use a 3.3-V power supply and apply the ADC output common-mode voltage to the VOCM input pin of the THS4551. Design a –1-dB insertion loss, 2nd-order RLC filter using the approach described in the RLC Filter Design for ADC Interface Applications application note (SBAA108). Adjust the total resistive load target in the filter design to hit the standard value for the filter inductors. Convert the filter design to differential with only differential shunt elements. These elements must not be split and connected to a center-point ground. This technique passes the output common-mode voltage from the FDA to the ADC with no level shift error. Add a small series resistor at the ADC inputs. This resistor is not part of the filter design but spreads out the sampling glitch energy to provide improved SFDR. Check the common-mode level shift from the FDA outputs to the ADC resulting from the clock-ratedependent common-mode current. This common-mode current into the ADC shifts the common-mode voltage slightly, but can easily stay in range with a low series resistor in the filter design. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 10.2.3.3 Application Curve Driving a 2-MHz ±0.2-V square wave into this circuit (using a TINA-TI™ simulation file for the circuit of Figure 10-17) gives the response shown in Figure 10-18 at the ADC. The red trace is a –1-dBFS, 1.8-VPP square wave at the ADC input pins. The gray trace is the input signal at the RT termination resistor. The black trace is the common-mode voltage at the FDA input pins. Note that the input pin voltage swing stays above ground and in range for this bipolar input, single, 3.3-V supply design. 1.5 1 Voltage (V) 0.5 0 -0.5 VIN+ VOUT VIN -1 -1.5 0 100 200 300 400 500 600 Time (ns) 700 800 900 1000 D076 Figure 10-18. Time-Domain Waveform Unbuffered pipeline ADCs draw a clock-rate-dependent input common-mode current. For the ADC3241, this input current is specified as 1.5 µA per MSPS. Operating at 25 MSPS, the common-mode current drops the common-mode voltage from 0.95 V at the THS4551 outputs by 37.5 µA × 45.8 Ω = 1.7 mV to 0.9483 V. This value is well within the allowed ±25-mV common-mode deviation from the ADC VCM output. Consider this effect carefully when using higher resistor values in the interface at the ADC. 11 Power Supply Recommendations The THS4551 is principally intended to operate with a nominal single-supply voltage of 3 V to 5 V. Supply voltage tolerances are supported with the specified operating range of 2.7 V (10% low on a 3-V nominal supply) and 5.4 V (8% high on a 5-V nominal supply). Supply decoupling is required, as described in Section 8.7. Split (or bipolar) supplies can be used with the THS4551, as long as the total value across the device remains less than 5.5 V (absolute maximum). The thermal pad on the RGT package is electrically isolated form the die; connect the thermal pad (RGT package only) to any power or ground plane for reduced thermal impedance to the junction temperature. This pad must be connected to some power or ground plane and not floated. For the best input offset voltage drift, the THS4551 uses a proportional to absolute temperature (PTAT) quiescent current biasing scheme. This approach gives a positive over temperature variation in supply current. Figure 11-1 shows the 5-V supply current over a wide TJ range for a number of tested units. The Electrical Characteristics tables report the typical and range on this supply current temperature coefficient for both 5-V and 3-V supply operation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 55 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 1.8 Supply Current (mA) 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 -45 -30 -15 0 15 30 45 60 75 90 105 120 135 Junction Temperature (qC) D068 Figure 11-1. Linear Temperature Coefficient for Supply Current Using a negative supply to deliver a true swing to ground output when driving SAR ADCs can be desired. Although the THS4551 quotes a rail-to-rail output, linear operation requires approximately 200-mV headroom to the supply rails. One easy option for extending the linear output swing to ground is to provide the small negative supply voltage required using the LM7705 fixed –230-mV, negative-supply generator. This low-cost, fixed, negative-supply generator can accept the 3-V to 5-V positive supply input used by the THS4551 and provides a fixed –230-mV supply for the negative power supply. Using the LM7705 provides an effective solution, as discussed in the Extending Rail-to-Rail Output Range for Fully Differential Amplifiers to Include True Zero Volts TI design (TIDU187) 11.1 Thermal Analysis The very low internal quiescent power dissipation for the THS4551, combined with the excellent thermal impedance of the 16-pin VQFN package (RGT), limits the possibility of excessively high internal junction temperatures. A more detailed analysis may be warranted because the 10-pin WQFN (RUN) package has a much higher junction-to-ambient thermal impedance (θJA = 163°C/W). To estimate the internal TJ, an estimate of the maximum internal power dissipation is first required. There are two pieces to the internal power dissipation: quiescent current power and the power used in the output stage to deliver load current. To simplify the latter, the worst-case output stage power drives a dc differential voltage across a load using half the total supply voltage. Also assume a maximum ambient temperature of 125°C, giving the maximum quiescent current as shown in Figure 11-1. As an example: • • • Assume a maximum operating supply voltage of 5.4 V. This 5.4-V supply with a maximum ICC of 1.75 mA gives a quiescent power term of 9.45 mW. Assume a 200-Ω differential load with a static 2.7-V differential voltage established across the load. The 1.35 mA of dc load current generates a maximum output stage power of (5.4 V – 2.7 V) × 1.35 mA = 3.65 mW. From the worst-case total internal PD of 13.1 mW, multiplying the internal PD with a 163°C/W thermal impedance times the 163°C/W thermal impedance for the very small 10-pin WQFN package results in a 2.1°C rise from ambient. Even for this extreme condition and the maximum-rated ambient of 125°C, the junction temperature is a maximum of 127°C, which is less than the rated absolute maximum of 150°C. Follow this same calculation sequence for the exact application and package selected to predict the maximum TJ. 56 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 12 Layout 12.1 Layout Guidelines 12.1.1 Board Layout Recommendations Similar to all high-speed devices, best system performance is achieved with close attention to board layout. The THS4551DGKEVM user guide (SLOU447) shows a good example of high-frequency layout techniques as a reference. This EVM includes numerous extra elements and features for characterization purposes that may not apply to some applications. General high-speed signal path layout suggestions include: • • • • • Continuous ground planes are preferred for signal routing with matched impedance traces for longer runs; however, both ground and power planes must be opened up around the capacitive sensitive input and output device pins. When the signal goes to a resistor, parasitic capacitance becomes more of a band-limiting issue and less of a stability issue. Good high-frequency decoupling capacitors (0.1 µF) are required to a ground plane at the device power pins. Additional higher-value capacitors (2.2 µF) are also required but can be placed further from the device power pins and shared among devices. For best high-frequency decoupling, consider X2Y supply decoupling capacitors that offer a much higher self-resonance frequency over standard capacitors. Differential signal routing over any appreciable distance must use microstrip layout techniques with matched impedance traces. Higher-speed FDAs such as the THS4551 include a duplicate of the output pins on the input feedback side of the larger 16-pin VQFN (RGT) package. This feature is intended to allow the external feedback resistors to be connected with virtually no trace length on the input side of the package. This internal feedback trace also provides a second feedback path for connecting a feedback capacitor on the input pin sides for band-limited or multiple feedback filter designs. This internal trace shows an approximate 3.3-Ω series resistance that must be considered in any design using that path. The TINA-TI™ model does not include that element (to be generally applicable to all package styles) and must be added externally if the RGT package is used. Use this layout approach without extra trace length on the critical feedback path. The smaller 10-pin WQFN package lines up the outputs and the required inputs on the same side of the package where the feedback RF resistors must be placed immediately adjacent to the package with minimal trace length. The input summing junctions are very sensitive to parasitic capacitance. Any RG elements must connect into the summing junction with minimal trace length to the device pin side of the resistor. The other side of the RG elements can have more trace length if needed to the source or to GND. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 57 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 12.2 Layout Example Figure 12-1. Example Layout 58 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 12.3 EVM Board Figure 12-2 and Figure 12-3 show the layout of the top and bottom layers of the THS4551DGKEVM evaluation module, respectively. Figure 12-2. THS4551DGKEVM Top Layer Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 59 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 Figure 12-3. THS4551DGKEVM Bottom Layer 60 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 13 Device and Documentation Support 13.1 Device Support 13.1.1 TINA-TI™ Simulation Model Features The device model is available on the product folder under www.ti.com in a typical application circuit file. The model includes numerous features intended to speed designer progress over a wide range of application requirements. The following list shows the performance parameters included in the model: • • • • For the small-signal response shape with any external circuit: – Differential open-loop gain and phase – Parasitic input capacitance – Open-loop differential output impedance For noise simulations: – Input differential spot voltage noise and a 100-Hz 1/f corner – Input current noise on each input with a 6-kHz 1/f corner For time-domain, step-response simulations: – Differential slew rate – I/O headroom models to predict clipping – Input stage diodes to predict overdrive limiting Fine-scale, dc precision terms: – PSRR – CMRR The Section 7.9 provides more detail than the macromodels can provide; some of the unmodeled features include: • • • • Harmonic distortion Temperature drift in dc error terms (VIO and IOS) Overdrive recovery time Turn-on and turn-off times using the power-down feature Some unique simulation considerations come with the THS4551 TINA-TI™ model. This device (and model) include 0.6-pF internal feedback capacitors. These capacitors are intended to improve phase margin when using higher external feedback resistor values. Higher feedback resistors generate an in-band pole in the feedback signal with the differential input capacitance, and the internal 0.6 pF capacitors add a zero to the feedback response shape to shape the noise gain flat at the loop-gain crossover. In order to generate an accurate open-loop gain and phase simulation, these components must be removed because they are feedback elements, not forward path elements. Figure 13-1 illustrates a typical AOL gain and phase simulation (available as a TINA-TI™ software file) where external –0.6-pF capacitors cancel out the internal capacitors in the model (TINA-TI™ supports negative value elements). The inductors inside the loop close the loop for the dc operating point and open the loop immediately for an ac sweep. The input-coupling capacitors are open at dc, then couple in the differential input immediately on an ac sweep. The somewhat odd values help reduce numerical chatter in the simulation. When using the internal feedback traces from the outputs to the inputs on the RGT package, be sure to add the 3.3-Ω trace impedance to any simulation. This impedance is not included in the core model. VS± C2 -600 fF VS+ C3 9.97 kF - VM1 VOCM + + - - VG1 R5 10 M: C4 9.97 kF + VOCM + L2 999 H + U1 THS4551 VINV VIN+ R4 10 M: - VS± + VIN+ VCVS1 1 + - R3 100 k: V2 -2.5 VS+ V1 2.5 L1 999 H VS+ VOCM R1 10 m: V4 0 C1 -600 fF VINR2 10 m: Copyright © 2016, Texas Instruments Incorporated Figure 13-1. Open-Loop Gain and Phase TINA-TI™ Simulation Setup Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 61 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 This test is set up with a very light load to isolate the no load AOL curve. Adding a load brings in the open-loop ZOL response to the overall response of the output pins. Running this simulation gives the gain and phase of Figure 13-2 that closely matches the plot of Figure 7-37. Gain (dB) T 200.00 100.00 0.00 -100.00 Phase [deg] 0.00 -100.00 -200.00 -300.00 -400.00 10.00 100.00 1.00k 10.00k 100.00k 1.00MEG 10.00MEG 100.00MEG 1.00G Frequency (Hz) Figure 13-2. Open-Loop Gain and Phase Simulation Result 62 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 13.2 Documentation Support 13.2.1 Related Documentation For related documentation see the following: • Texas Instruments, THS4551 TINA-TI™ model • Texas Instruments, THS4551DGKEVM User Guide • Texas Instruments, THS452x Very Low Power, Negative Rail Input, Rail-To-Rail Output, Fully Differential Amplifier • Texas Instruments LMH6629 Ultra-Low Noise, High-Speed Operational Amplifier with Shutdown • Texas Instruments OPA847 Wideband, Ultra-Low Noise, Voltage-Feedback Operational Amplifier with Shutdown • Texas Instruments, INA188 Precision, Zero-Drift, Rail-to-Rail Out, High-Voltage Instrumentation Amplifier • Texas Instruments, OPAx192 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage, Low Input Bias Current Op Amp with e-trim™ • Texas Instruments, OPA161x SoundPlus™ High-Performance, Bipolar-Input Audio Operational Amplifiers • Texas Instruments, ADC322x Dual-Channel, 12-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converters • Texas Instruments, ADC324x Dual-Channel, 14-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converters • Texas Instruments, ADS127L01 24-Bit, High-Speed, Wide-Bandwidth Analog-to-Digital Converter • Texas Instruments, ADS127L01EVM User's Guide • Texas Instruments, ADS9110 18-Bit, 2-MSPS, 15-mW, SAR ADC with multiSPI™ Interface • Texas Instruments, REF6025EVM-PDK User's Guide (SBAU258) • Texas Instruments, 24-Bit, 192-kHz Sampling, Advanced Segment, Audio Stereo Digital-to-Analog Converter • Texas Instruments, LM27762 Low-Noise Regulated Switched-Capacitor Voltage Inverter • Texas Instruments, LM7705 Low-Noise Negative Bias Generator • Texas Instruments, Extending Rail-to-Rail Output Range for Fully Differential Amplifiers to Include True Zero Volts • Texas Isntruments, Design Methodology for MFB Filters in ADC Interface Applications • Texas Instruments, Design for Wideband Differential Transimpedance DAC Output • Texas Instruments, RLC Filter Design for ADC Interface Applications • Texas Instruments, TINA-TI Open Loop No Load Response • Texas Instruments, TINA-TI Basic Gain of 1 Test Circuit • Texas Instruments, TINA-TI ADTL1-4-75 Model Test • Texas Instruments, TINA-TI Common Mode Test CKT • Texas Instruments, TINA-TI AC Coupled Single to Differentiate Gain of 2 • Texas Instruments, TINA-TI Single to Differential Attenuator • Texas Instruments, TINA-TI Gain of 5 Single to Different Simplified • Texas Instruments, TINA-TI AC coupled different IO • Texas Instruments, TINA-TI Differential IO with OPA2192 to FDA to SAR • Texas Instruments, TINA-TI ADS127L01 MFB Driver • Texas Instruments, TINA-TI ADS127L01 MFB Driver LG Test • Texas Instruments, TINA-TI Attenuator With No Caps Gain of 0.1 • Texas Instruments, TINA-TI Attenuator With a Caps Gain of 0.1 • Texas Instruments, TINA-TI High Gain Single to Different with Feedback Pole • Texas Instruments, TINA-TI High Gain Single to Different with Feedback Pole and Input C • Texas Instruments, TINA-TI Gain of 0.2 100kHz Butterworth MFB Filter • Texas Instruments, TINA-TI 100kHz MFB filter LG test • Texas Instruments, TINA-TI Differential Transimpedance LG Sim • Texas Instruments, TINA-TI Differential Audio DAC ZT Design • Texas Instruments, TINA-TI Gain of 5 Single to Different with 10Mhz Bessel 13.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 63 THS4551 www.ti.com SBOS778D – APRIL 2016 – REVISED APRIL 2021 13.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 13.5 Trademarks TINA-TI™ are trademarks of Texas Instruments. TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 13.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 13.7 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 64 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: THS4551 PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) THS4551IDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG | SN Level-2-260C-1 YEAR -40 to 125 4551 Samples THS4551IDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAUAG | SN Level-2-260C-1 YEAR -40 to 125 4551 Samples THS4551IRGTR ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HS4551 Samples THS4551IRGTT ACTIVE VQFN RGT 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HS4551 Samples THS4551IRUNR ACTIVE QFN RUN 10 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 4551 Samples THS4551IRUNT ACTIVE QFN RUN 10 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 4551 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of