TLC072-Q1
www.ti.com ...................................................................................................................................................................................................... SLOS583 – JUNE 2008
WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE-SUPPLY OPERATIONAL AMPLIFIER
FEATURES
1
• Qualified for Automotive Applications
• Wide Bandwidth . . . 10 MHz
• High-Output Drive
– IOH . . . 57 mA at VDD – 1.5 V
– IOL . . . 55 mA at 0.5 V
• High Slew Rate
– SR+ . . . 16 V/µs
– SR– . . . 19 V/µs
• Wide Supply Range . . . 4.5 V to 16 V
• Supply Current . . . 1.9 mA/Channel
• Ultralow Power Shutdown Mode IDD . . . 125
mA/Channel
• Low Input Noise Voltage . . . 7 nV/Hz
• Input Offset Voltage . . . 60 µV
• Small 8-Pin SOIC Package
TLC072
D PACKAGE
(TOP VIEW)
23
1OUT
1IN−
1IN+
GND
1
8
2
7
3
6
4
5
VDD
2OUT
2IN−
2IN+
Operational Amplifier
−
+
DESCRIPTION/ORDERING INFORMATION
The first members of TI's new BiMOS general-purpose operational amplifier family are the TLC07x. The BiMOS
family concept is simple: provide an upgrade path for BiFET users who are moving away from dual-supply to
single-supply systems and demand higher AC and dc performance. With performance rated from 4.5 V to 16 V
across commercial (0°C to 70°C) and an extended industrial temperature range (–40°C to 125°C), BiMOS suits a
wide range of audio, automotive, industrial and instrumentation applications. Familiar features like offset nulling
pins enable higher levels of performance in a variety of applications.
Developed in TI's patented LBC3 BiCMOS process, the new BiMOS amplifiers combine a very high input
impedance low-noise CMOS front end with a high-drive bipolar output stage, thus providing the optimum
performance features of both. AC performance improvements over the TL07x BiFET predecessors include a
bandwidth of 10 MHz (an increase of 300%) and voltage noise of 7 nV/√Hz (an improvement of 60%). DC
improvements include a factor of 4 reduction in input offset voltage down to 1.5 mV (maximum) in the standard
grade, and a power supply rejection improvement of greater than 40 dB to 130 dB. Added to this list of
impressive features is the ability to drive ±50-mA loads comfortably from an ultrasmall-footprint MSOP
PowerPAD™ package, which positions the TLC07x as the ideal high-performance general-purpose operational
amplifier family.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 125°C
(1)
(2)
SOIC – D
Reel of 2500
ORDERABLE PART NUMBER
TLC072QDRQ1
TOP-SIDE MARKING
TC072Q
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TLC072-Q1
SLOS583 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VDD
Supply voltage (2)
17 V
VID
Differential input voltage range
±VDD
Continuous total power dissipation
See Dissipation Ratings Table
TA
Operating free-air temperature range
TJ
Maximum virtual-junction temperature
Tstg
Storage temperature range
Tlead
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
–40°C to 125°C
150°C
–65°C to 150°C
260°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to GND .
DISSIPATION RATINGS
PACKAGE
θJC (°C/W)
θJA (°C/W)
TA ≤ 25°C POWER RATING
D
38.3
176
710 mW
RECOMMENDED OPERATING CONDITIONS
VDD
Supply voltage
VICR
Common-mode input voltage
TA
Operating free-air temperature
2
Single supply
Split supply
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MIN
MAX
4.5
16
UNIT
±2.25
±8
+0.5
VDD – 0.8
V
–40
125
°C
V
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TLC072-Q1
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ELECTRICAL CHARACTERISTICS
VDD = 5 V, at specified free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
VDD = 5 V, VIC = 2.5 V, VO = 2.5 V, RS = 50 Ω
αVIO
Temperature coefficient of input
offset voltage
VDD = 5 V, VIC = 2.5 V, VO = 2.5 V, RS = 50 Ω
IIO
Input offset current
VDD = 5 V, VIC = 2.5 V, VO = 2.5 V, RS = 50 Ω
IIB
Input bias current
VDD = 5 V, VIC = 2.5 V, VO = 2.5 V, RS = 50 Ω
VICR
Common-mode input voltage
IOH = –20 mA
High-level output voltage
VIC = 2.5 V
IOH = –35 mA
IOH = –50 mA
IOL = 1 mA
IOL = 20 mA
VOL
Low-level output voltage
VIC = 2.5 V
IOL = 35 mA
IOL = 50 mA
MIN
25°C
TYP
MAX
390
1900
Full range
3000
25°C
1.2
25°C
0.7
Full range
25°C
1.5
0.5 to
4.2
Full range
0.5 to
4.2
25°C
4.1
Full range
3.9
25°C
3.7
Full range
3.5
25°C
3.4
Full range
3.2
25°C
3.2
Full range
50
50
700
25°C
UNIT
µV
µV/°C
700
Full range
RS = 50 Ω
IOH = –1 mA
VOH
TA (1)
pA
pA
V
4.3
4
V
3.8
3.6
3
25°C
0.18
Full range
0.25
0.35
25°C
0.35
Full range
0.39
0.45
25°C
0.43
Full range
0.55
V
0.7
25°C
0.48
Full range
0.63
0.7
Sourcing
25°C
100
Sinking
25°C
100
VOH = 1.5 V from positive rail
25°C
57
VOL = 0.5 V from negative rail
25°C
55
IOS
Short-circuit output current
IO
Output current
AVD
Large-signal differential voltage
amplification
ri(d)
Differential input resistance
25°C
1000
GΩ
CIC
Common-mode input capacitance f = 10 kHz
25°C
22.9
pF
zO
Closed-loop output impedance
25°C
0.25
Ω
CMRR Common-mode rejection ratio
VO(PP) = 3 V, RL = 10 kΩ
f = 10 kHz, AV = 10
VIC = 1 to 3 V, RS = 50 Ω
kSVR
Supply voltage rejection ratio
(ΔVDD/ΔVIO)
VDD = 4.5 V to 16 V, VIC = VDD/2, No load
IDD
Supply current (per channel)
VO = 2.5 V, No load
(1)
25°C
100
Full range
100
25°C
80
Full range
80
25°C
80
Full range
80
25°C
Full range
mA
mA
120
dB
95
dB
100
1.9
dB
2.5
3.5
mA
Full range is –40°C to 125°C.
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OPERATING CHARACTERISTICS
VDD = 5 V, at specified free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SR+
Positive slew rate at unity gain
VO(PP) = 0.8 V, CL = 50 pF, RL = 10 kΩ
SR–
Negative slew rate at unity gain
VO(PP) = 0.8 V, CL = 50 pF, RL = 10 kΩ
Vn
Equivalent input noise voltage
In
Equivalent input noise current
f = 1 kHz
THD + N
Total harmonic distortion plus
noise
VO(PP) = 3 V, RL = 10 kΩ and
250 Ω, f = 1 kHz
f = 100 Hz
TA (1)
MIN
TYP
25°C
10
16
Full range
9.5
25°C
12.5
Full range
25°C
f = 1 kHz
25°C
AV = 1
AV = 10
ts
Gain-bandwidth product
f = 10 kHz, RL = 10 kΩ
25°C
0.1%
V(STEP)PP = 1 V, AV = –1,
CL = 47 pF, RL = 10 kΩ
0.1%
Settling time
φm
Phase margin
RL = 10 kΩ
Gm
Gain margin
RL = 10 kΩ
(1)
4
0.01%
CL = 0 pF
CL = 50 pF
CL = 0 pF
0.6
V/µs
nV/
√Hz
fA/
√Hz
0.012
%
10
MHz
0.18
25°C
0.01%
CL = 50 pF
7
V/µs
0.085
25°C
V(STEP)PP = 1 V, AV = –1,
CL = 10 pF, RL = 10 kΩ
12
UNIT
0.002
AV = 100
GBWP
19
10
MAX
0.39
0.18
µs
0.39
25°C
25°C
32
40
2.2
3.3
°
dB
Full range is –40°C to 125°C.
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ELECTRICAL CHARACTERISTICS
VDD = 12 V, at specified free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
VDD = 12 V, VIC = 6 V, VO = 6 V, RS = 50 Ω
αVIO
Temperature coefficient of input
offset voltage
VDD = 12 V, VIC = 6 V, VO = 6 V, RS = 50 Ω
IIO
Input offset current
VDD = 12 V, VIC = 6 V, VO = 6 V, RS = 50 Ω
IIB
Input bias current
VDD = 12 V, VIC = 6 V, VO = 6 V, RS = 50 Ω
VICR
Common-mode input voltage
IOH = –20 mA
High-level output voltage
VIC = 6 V
IOH = –35 mA
IOH = –50 mA
IOL = 1 mA
IOL = 20 mA
VOL
Low-level output voltage
VIC = 6 V
IOL = 35 mA
IOL = 50 mA
MIN
25°C
TYP
MAX
390
1900
Full range
3000
25°C
1.2
25°C
0.7
Full range
25°C
1.5
0.5 to
11.2
Full range
0.5 to
11.2
25°C
11.1
Full range
50
50
700
25°C
UNIT
µV
µV/°C
700
Full range
RS = 50 Ω
IOH = –1 mA
VOH
TA (1)
pA
pA
V
11.2
11
25°C
10.8
Full range
10.7
25°C
10.6
Full range
10.3
25°C
10.4
Full range
10.3
25°C
109
V
10.7
10.5
0.17
Full range
0.25
0.35
25°C
0.35
0.45
0.4
0.52
Full range
0.5
25°C
Full range
V
0.6
25°C
0.45
Full range
0.6
0.65
Sourcing
25°C
150
Sinking
25°C
150
VOH = 1.5 V from positive rail
25°C
57
VOL = 0.5 V from negative rail
25°C
55
IOS
Short-circuit output current
IO
Output current
AVD
Large-signal differential voltage
amplification
ri(d)
Differential input resistance
25°C
1000
GΩ
CIC
Common-mode input capacitance f = 10 kHz
25°C
21.6
pF
zO
Closed-loop output impedance
25°C
0.25
Ω
CMRR Common-mode rejection ratio
VO(PP) = 8 V, RL = 10 kΩ
f = 10 kHz, AV = 10
VIC = 1 to 10 V, RS = 50 Ω
kSVR
Supply voltage rejection ratio
(ΔVDD/ΔVIO)
VDD = 4.5 V to 16 V, VIC = VDD/2, No load
IDD
Supply current (per channel)
VO = 7.5 V, No load
(1)
25°C
120
Full range
120
25°C
80
Full range
80
25°C
80
Full range
80
25°C
Full range
mA
mA
140
dB
100
dB
100
2.1
dB
2.9
3.5
mA
Full range is –40°C to 125°C.
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OPERATING CHARACTERISTICS
VDD = 12 V, at specified free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SR+
Positive slew rate at unity gain
VO(PP) = 2 V, CL = 50 pF, RL = 10 kΩ
SR–
Negative slew rate at unity gain
VO(PP) = 2 V, CL = 50 pF, RL = 10 kΩ
Vn
Equivalent input noise voltage
In
Equivalent input noise current
f = 1 kHz
THD + N
Total harmonic distortion plus
noise
VO(PP) = 8 V, RL = 10 kΩ and
250 Ω, f = 1 kHz
f = 100 Hz
TA (1)
MIN
TYP
25°C
10
16
Full range
9.5
25°C
12.5
Full range
25°C
f = 1 kHz
25°C
AV = 1
AV = 10
ts
Gain-bandwidth product
f = 10 kHz, RL = 10 kΩ
25°C
0.1%
V(STEP)PP = 1 V, AV = –1,
CL = 47 pF, RL = 10 kΩ
0.1%
Settling time
φm
Phase margin
RL = 10 kΩ
Gm
Gain margin
RL = 10 kΩ
(1)
6
0.01%
CL = 0 pF
CL = 50 pF
CL = 0 pF
0.6
V/µs
nV/
√Hz
fA/
√Hz
0.005
%
10
MHz
0.17
25°C
0.01%
CL = 50 pF
7
V/µs
0.022
25°C
V(STEP)PP = 1 V, AV = –1,
CL = 10 pF, RL = 10 kΩ
12
UNIT
0.002
AV = 100
GBWP
19
10
MAX
0.22
0.17
µs
0.29
25°C
25°C
37
42
3.1
4
°
dB
Full range is –40°C to 125°C.
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TYPICAL CHARACTERISTICS
Table 1. Table of Graphs
FIGURE
VIO
Input offset voltage
vs Common-mode input voltage
1, 2
IIO
Input offset current
vs Free-air temperature
3, 4
IIB
Input bias current
vs Free-air temperature
3, 4
VOH
High-level output voltage
vs High-level output current
5, 7
VOL
Low-level output voltage
vs Low-level output current
6, 8
Zo
Output impedance
vs Frequency
9
IDD
Supply current
vs Supply voltage
10
PSRR
Power supply rejection ratio
vs Frequency
11
CMRR
Common-mode rejection ratio
vs Frequency
12
Vn
Equivalent input noise voltage
vs Frequency
13
VO(PP)
Peak-to-peak output voltage
vs Frequency
14, 15
Crosstalk
vs Frequency
16
DIfferential voltage gain
vs Frequency
17, 18
Phase
vs Frequency
17, 18
Phase margin
vs Load capacitance
19, 20
Gain margin
vs Load capacitance
21, 22
Gain-bandwidth product
vs Supply voltage
23
vs Supply voltage
24
φm
SR
THD + N
Slew rate
Total harmonic distortion plus noise
vs Free-air temperature
25, 26
vs Frequency
27, 28
vs Peak-to-peak output voltage
29, 30
Large-signal follower pulse response
31, 32
Small-signal follower pulse response
33
Large-signal inverting pulse response
34, 35
Small-signal inverting pulse response
36
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INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
0
225
−25
VDD = 5 V
TA = 25° C
200
175
150
125
100
75
50
25
0
VDD = 12 V
TA = 25° C
−50
−75
−100
−125
−150
−175
−200
−225
−250
−25
0.0 0. 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
5 − Common-Mode Input Voltage − V
VICR
−275
0
1
2
3
4
5
6
7
8
9 10 11 12
VICR − Common-Mode Input Voltage − V
INPUT BIAS CURRENT AND
INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
I IB / I IO − Input Bias and Input Offset Current − pA
250
V IO − Input Offset Voltage − µ V
V IO − Input Offset Voltage − µ V
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
20
0
IIO
−20
−40
−60
−80
IIB
VDD = 5V
−100
−120
−55 −40 −25 −10 5 20 35 50 65 80 95 110 125
IIO
−20
−40
−60
−80
−100
IIB
−120
VDD = 12 V
−140
5.0
1.0
VDD = 5 V
4.5
TA = 70°C
TA = 25°C
4.0
TA = −40°C
3.5
TA = 125°C
3.0
2.5
2.0
−160
−55 −40 −25 −10 5 20 35 50 65 80 95 110 125
Figure 4.
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
TA = −40°C
TA = 25°C
10.0
9.5
VDD = 12 V
9.0
5 10 15 20 25 30 35 40 45 50
IOH - High-Level Output Current - mA
Figure 7.
0.6
TA = 125°C
TA = 70°C
TA = 25°C
0.5
0.4
0.3
TA = −40°C
0.2
0.1
10 15 20 25 30 35 40 45 50
IOH - High-Level Output Current - mA
0
5 10 15 20 25 30 35 40 45 50
IOL - Low-Level Output Current - mA
Figure 6.
OUTPUT IMPEDANCE
vs
FREQUENCY
1000
0.9
0.8
TA = 125°C
0.7
TA = 70°C
0.6
TA = 25°C
0.5
0.4
0.3
TA = −40°C
0.2
0.1
100
VDD = 5 V and 12 V
TA = 25°C
10
AV = 100
1
AV = 1
0.10
AV = 10
VDD = 12 V
0.0
0
8
VOL − Low-Level Output Voltage − V
V OH − High-Level Output Voltage − V
10.5
0.7
5
1.0
11.0
0.8
Figure 5.
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
12.0
11.5
VDD = 5 V
0.9
0.0
0
TA − Free-Air Temperature − °C
TA = 125°C
TA = 70°C
VOL − Low-Level Output Voltage − V
0
Figure 3.
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
Z o − Output Impedance − Ω
20
Figure 2.
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
V OH − High-Level Output Voltage − V
I IB / I IO − Input Bias and Input Offset Current − pA
TA − Free−Air Temperature − °C
Figure 1.
INPUT BIAS CURRENT AND
INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
0
5 10 15 20 25 30 35 40 45 50
IOL - Low-Level Output Current - mA
Figure 8.
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0.01
100
1k
100k
1M
10k
f - Frequency - Hz
10M
Figure 9.
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POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
I DD − Supply Current − mA
TA = 25°C
2.5
TA = −40°C
2.0
TA = 125°C
1.5
TA = 70°C
1.0
AV = 1
SHDN = VDD
Per Channel
0.5
0.0
4
5
6
140
120
VDD = 12 V
100
80
60
40
VDD = 5 V
20
0
0
7 8 9 10 11 12 13 14 15 16
VDD − Supply Voltage - V
VDD = 12 V
30
25
20
15
10
VDD = 5 V
5
0
10
100
1k
10k
100k
1k
10k
100k
1M
10M
100
80
60
40
20
0
100
f − Frequency − Hz
VDD = 12 V
8
6
VDD = 5 V
4
THD+N < = 5%
RL = 600 Ω
TA = 25°C
2
0
10k
Figure 13.
100k
1M
f - Frequency - Hz
1k
10k
100k
1M
f - Frequency - Hz
10M
Figure 12.
PEAK-TO-PEAK OUTPUT
VOLTAGE
vs
FREQUENCY
12
10
VDD = 5 V and 12 V
TA = 25°C
120
Figure 11.
PEAK-TO-PEAK OUTPUT
VOLTAGE
vs
FREQUENCY
V O(PP) − Peak-to-Peak Output Voltage − V
Hz
V n − Equivalent Input Noise Voltage − nV/
35
100
140
f − Frequency − Hz
Figure 10.
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
40
10
V O(PP) − Peak-to-Peak Output Voltage − V
3.0
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
CMRR − Common-Mode Rejection Ratio − dB
PSRR − Power Supply Rejection Ratio − dB
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
10M
Figure 14.
CROSSTALK
vs
FREQUENCY
12
10
VDD = 12 V
8
6
VDD = 5 V
4
2
0
10k
THD+N < = 5%
RL = 10 kΩ
TA = 25°C
100k
1M
f - Frequency - Hz
10M
Figure 15.
0
−20
Crosstalk − dB
−40
VDD = 5 V and 12 V
AV = 1
RL = 10 kΩ
VI(PP) = 2 V
For All Channels
−60
−80
−100
−120
−140
−160
10
100
1k
10k
100k
f − Frequency − Hz
Figure 16.
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DIFFERENTIAL VOLTAGE GAIN AND
PHASE
vs
FREQUENCY
DIFFERENTIAL VOLTAGE GAIN AND
PHASE
vs
FREQUENCY
80
80
Gain
A VD − Different Voltage Gain − dB
60
−45
50
Phase
40
−90
30
20
−135
10
0
−10
−20
1k
VDD = ±2.5 V
RL = 10 kΩ
CL = 0 pF
TA = 25°C
10k
−180
100k
1M
10M
0
70
Gain
60
Phase
40
20
−135
10
VDD = ±6 V
RL = 10 kΩ
CL = 0 pF
TA = 25°C
0
−10
45°
Rnull = 20 Ω
5°
VDD = 5 V
RL = 10 kΩ
TA = 25°C
Rnull = 100 Ω
25°
20°
Rnull = 20 Ω
15°
VDD = 12 V
RL = 10 kΩ
TA = 25°C
10°
5°
0°
10
GBWP - Gain Bandwidth Product - MHz
φ m − Phase Margin − dB
Rnull = 100 Ω
3.5
3
1
0.5
Rnull = 50 Ω
Rnull = 20 Ω
VDD = 12 V
RL = 10 kΩ
TA = 25°C
0
10
1
VDD = 5 V
RL = 10 kΩ
TA = 25°C
100
Figure 22.
Rnull = 20 Ω
100
Figure 21.
SLEW RATE
vs
SUPPLY VOLTAGE
22
CL = 11 pF
9.9
9.8
20
9.7
RL = 10 kΩ
9.6
9.5
9.4
RL = 600 Ω and 10 kΩ
CL = 50 pF
AV = 1
21
TA = 25°C
RL = 600 Ω
9.3
19
Slew Rate −
18
17
16
Slew Rate +
15
9.2
14
9.1
13
9.0
CL − Load Capacitance − pF
10
Rnull = 50 Ω
1.5
CL − Load Capacitance − pF
10.0
Rnull = 0 Ω
1.5
2
Figure 20.
GAIN BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
4.5
2
2.5
CL − Load Capacitance − pF
Figure 19.
GAIN MARGIN
vs
LOAD CAPACITANCE
2.5
Rnull = 100 Ω
3
0
10
100
CL − Load Capacitance − pF
4
Rnull = 0 Ω
0.5
0°
10
100
5
Rnull = 50 Ω
SR − Slew Rate − V/ µ s
15°
30°
G − Gain Margin − dB
φ m − Phase Margin
φ m − Phase Margin
20°
−225
100M
3.5
35°
30°
10°
4
Rnull = 0 Ω
40°
Rnull = 50 Ω
10M
Figure 18.
GAIN MARGIN
vs
LOAD CAPACITANCE
PHASE MARGIN
vs
LOAD CAPACITANCE
Rnull = 0 Ω
Rnull = 100 Ω
25°
1M
f − Frequency − Hz
Figure 17.
PHASE MARGIN
vs
LOAD CAPACITANCE
35°
−180
100k
10k
f − Frequency − Hz
40°
−90
30
−20
1k
−225
100M
−45
50
Phase − °
0
70
Phase − °
A VD − Different Voltage Gain − dB
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12
4
5
6
7 8 9 10 11 12 13 14 15 16
VDD - Supply Voltage - V
Figure 23.
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4
5
6
7 8 9 10 11 12 13 14 15 16
VDD - Supply Voltage - V
Figure 24.
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SLEW RATE
vs
FREE-AIR TEMPERATURE
SLEW RATE
vs
FREE-AIR TEMPERATURE
25
25
VDD = 5 V
RL = 600 Ω and 10 kΩ
CL = 50 pF
AV = 1
20
15
Slew Rate +
10
15
Slew Rate +
10
VDD = 12 V
RL = 600 Ω and 10 kΩ
CL = 50 pF
AV = 1
5
5
0
−55 −35 −15 5 25 45 65 85 105 125
TA - Free-Air Temperature - °C
0
−55 −35 −15 5 25 45 65 85 105 125
TA - Free-Air Temperature - °C
Total Harmonic Distortion + Noise − %
1
Slew Rate −
SR − Slew Rate − V/ µ s
Slew Rate −
20
SR − Slew Rate − V/ µ s
TOTAL HARMONIC DISTORTION
PLUS NOISE
vs
FREQUENCY
VDD = 5 V
RL = 10 kΩ
VO(PP) = 2 V
AV = 100
0.1
AV = 10
0.01
AV = 1
0.001
100
1k
10k
100k
f − Frequency − Hz
VDD = 12 V
RL = 10 kΩ
VO(PP) = 12 V
Total Harmonic Distortion + Noise − %
AV = 100
0.01
AV = 10
AV = 1
0.001
100
10k
1k
100k
Figure 27.
TOTAL HARMONIC DISTORTION
PLUS NOISE
vs
PEAK-TO-PEAK OUTPUT VOLTAGE
10
10
1
RL = 600 Ω
0.01
0.0001
0.25
1.25 1.75 2.25
2.75
3.25 3.75
RL = 250 Ω
0.1
RL = 600 Ω
0.01
0.001
VDD = 5 V
RL = 600 Ω
and 10 kΩ
CL = 8 pF
TA = 25°C
1.2 1.4 1.6 1.8
2
t − Time − µs
Figure 31.
1
6.5
8.5
10.5
VI(100mV/Div)
VDD = 12 V
RL = 600 Ω
and 10 kΩ
CL = 8 pF
TA = 25°C
0.2 0.4 0.6 0.8
4.5
Figure 30.
SMALL SIGNAL FOLLOWER PULSE
RESPONSE
VO (2 V/Div)
0
2.5
VO(PP) − Peak-to-Peak Output Voltage − V
VI (5 V/Div)
VO (500 mV/Div)
RL = 10 kΩ
0.0001
0.5
Figure 29.
LARGE SIGNAL FOLLOWER
PULSE RESPONSE
V O − Output Voltage − V
V O − Output Voltage − V
0.75
VDD = 12 V
AV = 1
f = 1 kHz
1
VO(PP) − Peak-to-Peak Output Voltage − V
VI (1 V/Div)
1
RL = 10 kΩ
0.001
Figure 28.
LARGE SIGNAL FOLLOWER
PULSE RESPONSE
0.2 0.4 0.6 0.8
RL = 250 Ω
0.1
f − Frequency − Hz
0
VDD = 5 V
AV = 1
f = 1 kHz
V O − Output Voltage − V
Total Harmonic Distortion + Noise − %
0.1
Figure 26.
TOTAL HARMONIC DISTORTION
PLUS NOISE
vs
PEAK-TO-PEAK OUTPUT VOLTAGE
Total Harmonic Distortion + Noise − %
Figure 25.
TOTAL HARMONIC DISTORTION
PLUS NOISE
vs
FREQUENCY
1.2 1.4 1.6 1.8
t − Time − µs
Figure 32.
2
VO(50mV/Div)
VDD = 5 V and 12 V
RL = 600 Ω and 10 kΩ
CL = 8 pF
TA = 25°C
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.10
t − Time − µs
Figure 33.
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LARGE SIGNAL INVERTING
PULSE RESPONSE
LARGE SIGNAL INVERTING
PULSE RESPONSE
VI (5 V/div)
VDD = 5 V
RL = 600 Ω
and 10 kΩ
CL = 8 pF
TA = 25°C
VI (100 mV/div)
V O − Output Voltage − V
V O − Output Voltage − V
VI (2 V/div)
V O − Output Voltage − V
SMALL SIGNAL INVERTING
PULSE RESPONSE
VDD = 12 V
RL = 600 Ω
and 10 kΩ
CL = 8 pF
TA = 25°C
VDD = 5 & 12 V
RL = 600 Ω and 10 kΩ
CL = 8 pF
TA = 25°C
VO (50 mV/Div)
VO (2 V/Div)
VO (500 mV/Div)
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
0
2
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
t − Time − µs
t − Time − µs
Figure 34.
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
t − Time − µs
Figure 35.
Figure 36.
PARAMETER MEASUREMENT INFORMATION
_
Rnull
+
RL
CL
Figure 37. Input Offset Voltage Null Circuit
12
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APPLICATION INFORMATION
Driving a Capacitive Load
When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device's
phase margin, leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10
pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as shown in
Figure 38. A minimum value of 20 Ω should work well for most applications.
RF
RG
_
Input
RNULL
Output
+
CLOAD
Figure 38. Driving a Capacitive Load
Offset Voltage
The output offset voltage (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula (see Figure 39) can be used to calculate the
output offset voltage:
RF
IIB−
RG
+
VI
RS
−
VO
+
IIB+
ǒ ǒ ǓǓ
VOO + VIO 1 )
R
F
RG
" IIB) RS
ǒ ǒ ǓǓ
1)
R
F
RG
" IIB– RF
Figure 39. Output Offset Voltage Model
High-Speed CMOS Input Amplifiers
The TLC072 is a high-speed low-noise CMOS input operational amplifier that has an input capacitance of the
order of 20 pF. Any resistor used in the feedback path adds a pole in the transfer function equivalent to the input
capacitance multiplied by the combination of source resistance and feedback resistance. For example, a gain of
–10, a source resistance of 1 kΩ, and a feedback resistance of 10 kΩ add an additional pole at approximately 8
MHz. This is more apparent with CMOS amplifiers than bipolar amplifiers due to their greater input capacitance.
This is of little consequence on slower CMOS amplifiers, as this pole normally occurs at frequencies above their
unity-gain bandwidth. However, the TLC07x with its 10-MHz bandwidth means that this pole normally occurs at
frequencies where there is on the order of 5-dB gain left and the phase shift adds considerably.
The effect of this pole is the strongest with large feedback resistances at small closed loop gains. As the
feedback resistance is increased, the gain peaking increases at a lower frequency and the 180° phase shift
crossover point also moves down in frequency, decreasing the phase margin.
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For the TLC072, the maximum feedback resistor recommended is 5 kΩ; larger resistances can be used but a
capacitor in parallel with the feedback resistor is recommended to counter the effects of the input capacitance
pole.
The TLC072 with a 1-V step response has an 80% overshoot with a natural frequency of 3.5 MHz when
configured as a unity gain buffer and with a 10-kΩ feedback resistor. By adding a 10-pF capacitor in parallel with
the feedback resistor, the overshoot is reduced to 40% and eliminates the natural frequency, resulting in a much
faster settling time (see Figure 40). The 10-pF capacitor was chosen for convenience only.
2
VIN
V O − Output Voltage − V
1
0
With
CF = 10 pF
1.5
−1
V I − Input Voltage − V
Load capacitance had little effect on these measurements due to the excellent output drive capability of the
TLC072.
10 pF
10 kΩ
_
1
0.5
VOUT
0
+
IN
VDD = ±5 V
AV = +1
RF = 10 kΩ
RL = 600 Ω
CL = 22 pF
600 Ω
50 Ω
22 pF
−0.5
0 0.2 0.4 0.6 0.8
t - Time - µs
1
1.2 1.4 1.6
Figure 40. 1-V Step Response
General Configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see
Figure 41).
RG
RF
−
VI
VO
+
R1
C1
f
V
O +
V
I
ǒ
R
1)
R
F
G
Ǔǒ
–3dB
+
1
2pR1C1
Ǔ
1
1 ) sR1C1
Figure 41. Single-Pole Low-Pass Filter
14
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If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task (see Figure 42). For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter
frequency bandwidth. Failure to do this can result in phase shift of the amplifier.
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
RG
RF
–3dB
RG =
+
(
1
2pRC
RF
1
2−
Q
)
Figure 42. Two-Pole Low-Pass Sallen-Key Filter
Circuit Layout Considerations
To achieve the levels of high performance of the TLC072, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
• Ground planes
A ground plane should be used on the board to provide all components with a low inductive ground
connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to
minimize the stray capacitance.
• Proper power supply decoupling
Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor on each supply terminal. It may be
possible to share the tantalum among several amplifiers depending on the application, but a 0.1-µF ceramic
capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-µF capacitor
should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the
connecting trace makes the capacitor less effective. The designer should strive for distances of less than
0.1 inch between the device power terminals and the ceramic capacitors.
• Sockets
Sockets can be used but are not recommended. The additional lead inductance in the socket pins often leads
to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best
implementation.
• Short trace runs/compact part placements
Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the
circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs.
Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as
possible. This will help to minimize stray capacitance at the input of the amplifier.
• Surface-mount passive components
Using surface-mount passive components is recommended for high performance amplifier circuits for several
reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with
stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally
leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded
components are used, it is recommended that the lead lengths be kept as short as possible.
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Macromodel Information
Macromodel information provided was derived using MicroSim Parts™, the model generation software used with
MicroSim PSpice™. The Boyle macromodel (1) and subcircuit in Figure 43 are generated using the TLC07x typical
electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the following
key parameters can be generated to a tolerance of 20% (in most cases):
• Maximum positive output voltage swing
• Maximum negative output voltage swing
• Slew rate
• Quiescent power dissipation
• Input bias current
• Open-loop voltage amplification
• Unity-gain frequency
• Common-mode rejection ratio
• Phase margin
• DC output resistance
• AC output resistance
• Short-circuit output current limit
(1)
16
G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, "Macromodeling of Integrated Circuit Operational Amplifiers," IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974).
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99
3
VDD +
9
RSS
10
J1
DP
VC
J2
IN +
11
VAD
DC
12
C1
RD1
R2
−
53
−
C2
6
−
−
+
VLN
+
GA
GCM
VLIM
8
−
RD2
RO1
DE
5
54
4
DLP
91
+
VLP
7
60
+
−
+
HLIM
−
+
90
RO2
VB
IN −
VDD −
92
FB
−
+
ISS
RP
2
1
DLN
EGND +
−
+
VE
OUT
*DEVICE=TLC07X_5V, OPAMP, PJF, INT
* TLC07X − 5V operational amplifier ”macromodel” subcircuit
* created using Parts release 8.0 on 12/16/99 at 08:38
* Parts is a MicroSim product.
*
* connections:
non-inverting input
*
inverting input
*
positive power supply
*
negative power supply
*
output
*
.subckt TLC07X_5V 1 2 3 4 5
*
c1
11 12 4.8697E−12
c2
6 7 8.0000E−12
css
10 99 4.0063E−12
dc
5 53 dy
de
54 5 dy
dlp
90 91 dx
dln
92 90 dx
dp
4 3 dx
egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5
fb
7 99 poly(5) vb vc ve vlp vln 0 6.9132E6 −1E3 1E3
6E6 −6E6
ga
gcm
iss
ioff
hlim
j1
j2
r2
rd1
rd2
ro1
ro2
rp
rss
vb
vc
ve
vlim
vlp
vln
.model
.model
.model
.model
.ends
6
0
3
0
90
11
12
6
4
4
8
7
3
10
9
3
54
7
91
0
dx
dy
jx1
jx2
0 11 12 457.42E−6
6 10 99 1.1293E−6
10 dc 183.67E−6
6 dc .806E−6
0 vlim 1K
2 10 jx1
1 10 jx2
9
100.00E3
11
2.1862E3
12
2.1862E3
5 10
99 10
4
2.4728E3
99
1.0889E6
0 dc 0
53 dc 1.5410
4 dc .84403
8 dc 0
0 dc 119
92 dc 119
D(Is=800.00E−18)
D(Is=800.00E−18 Rs=1m Cjo=10p)
PJF(Is=117.50E−15 Beta=1.1391E−3 Vto=−1)
PJF(Is=117.50E−15 Beta=1.1391E−3 Vto=−1)
Figure 43. Boyle Macromodel and Subcircuit
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLC072QDRQ1
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TC072Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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