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TLC6C598-Q1
SLIS142D – DECEMBER 2012 – REVISED SEPTEMBER 2016
TLC6C598-Q1 Power Logic 8-Bit Shift Register LED Driver
1 Features
3 Description
•
•
The TLC6C598-Q1 is a monolithic, medium-voltage,
low-current power 8-bit shift register designed for use
in systems that require relatively moderate load
power, such as LEDs.
1
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C3B
Wide Vcc From 3 V to 5.5 V
Output Maximum Rating of.40 V
Eight Power DMOS Transistor Outputs of 50-mA
Continuous Current With VCC = 5 V
Thermal Shutdown Protection
Enhanced Cascading for Multiple Stages
All Registers Cleared With Single Input
Low Power Consumption
Slow Switching Time (tr and tf), Which Helps
Significantly With Reducing EMI
16-Pin TSSOP-PW Package
16-Pin SOIC-D Package
2 Applications
•
•
•
Instrumentation Cluster
Tell-Tale Lamps
LED Illumination and Control
Typical Application Schematic
Battery 9 V–40 V
30 mA
4/3
MCU Serial I/F
8-Bit Shift Register
LED Driver
30 mA
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Data transfers through both the shift and
storage registers on the rising edge of the shiftregister clock (SRCK) and the register clock (RCK),
respectively. The storage register transfers data to
the output buffer when shift register clear (CLR) is
high. A low on CLR clears all registers in the device.
Holding the output enable (G) high, holds all data in
the output buffers low, and all drain outputs are off.
Holding G low makes data from the storage register
transparent to the output buffers. When data in the
output buffers is low, the DMOS transistor outputs are
off. When data is high, the DMOS transistor outputs
have sink-current capability. The serial output (SER
OUT) clocks out of the device on the falling edge of
SRCK to provide additional hold time for cascaded
applications. This provides improved performance for
applications where clock signals may be skewed,
devices are not located near one another, or the
system must tolerate electromagnetic interference.
The device contains built-in thermal shutdown
protection.
Outputs are low-side, open-drain DMOS transistors
with output ratings of 40 V and 50 mA continuous
sink-current capabilities when Vcc = 5 V. The current
limit decreases as the junction temperature increases
for additional device protection. The device also
provides up to 2000 V of ESD protection when tested
using the human-body model and 200 V when using
the machine model.
The TLC6C598-Q1 characterization is for for
operation over the operating ambient temperature
range of −40°C to 125°C.
Device Information(1)
PART NUMBER
TLC6C598-Q1
PACKAGE
BODY SIZE (NOM)
SOIC (16)
9.90 mm x 3.91 mm
TSSOP (16)
5.00 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLC6C598-Q1
SLIS142D – DECEMBER 2012 – REVISED SEPTEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
4
5
5
6
7
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Timing Waveforms ....................................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 16
12 Device and Documentation Support ................. 17
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
17
17
17
17
17
13 Mechanical, Packaging, and Orderable
Information ........................................................... 17
13.1 Package Option Addendum .................................. 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2015) to Revision D
Page
•
Added Receiving Notification of Documentation Updates section ....................................................................................... 17
•
Added new orderable part number to Package Option Addendum ..................................................................................... 18
Changes from Revision B (March 2013) to Revision C
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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SLIS142D – DECEMBER 2012 – REVISED SEPTEMBER 2016
5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
D Package
16-Pin SOIC
Top View
VCC
1
16
GND
VCC
1
16
GND
SER_IN
2
15
SRCK
SER_IN
2
15
SRCK
DRAIN0
3
14
DRAIN7
DRAIN0
3
14
DRAIN7
DRAIN1
4
13
DRAIN6
DRAIN1
4
13
DRAIN6
DRAIN2
5
12
DRAIN5
DRAIN2
5
12
DRAIN5
DRAIN3
6
11
DRAIN4
DRAIN3
6
11
DRAIN4
CLR
7
10
RCK
CLR
7
10
RCK
G
8
9
G
8
9
SER_OUT
SER_OUT
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
CLR
7
I
Shift register clear, active-low. The storage register transfers data to the output buffer
when CLR is high. Driving CLR low clears all the registers in the device.
DRAIN0
3
O
Open-drain output, LED current-sink channel, connect to LED cathode
DRAIN1
4
O
Open-drain output, LED current-sink channel, connect to LED cathode
DRAIN2
5
O
Open-drain output, LED current-sink channel, connect to LED cathode
DRAIN3
6
O
Open-drain output, LED current-sink channel, connect to LED cathode
DRAIN4
11
O
Open-drain output, LED current-sink channel, connect to LED cathode
DRAIN5
12
O
Open-drain output, LED current-sink channel, connect to LED cathode
DRAIN6
13
O
Open-drain output, LED current-sink channel, connect to LED cathode
DRAIN7
14
O
Open-drain output, LED current-sink channel, connect to LED cathode
G
8
I
Output enable, active-low. LED-channel enable and disable input pin. Having G low
enables all drain channels according to the output-latch register content. When high, all
channels are off.
GND
16
—
RCK
10
I
Register clock. The data in each shift register stage transfers to the storage register at the
rising edge of RCK.
SER IN
2
I
Serial data input. Data on SER IN loads into the internal register on each rising edge of
SRCK.
SER OUT
9
O
Serial data output of the 8-bit serial shift register. The purpose of this pin is to cascade
several devices on the serial bus.
SRCK
15
I
Serial clock input. On each rising SRCK edge, data transfers from SER IN to the internal
serial shift registers.
VCC
1
I
Power supply pin for the device. TI recommends adding a 0.1-μF ceramic capacitor close
to the pin.
Power ground, the ground reference pin for the device. This pin must connect to the
ground plane on the PCB.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCC
Logic supply voltage
–0.3
8
V
VI
Logic input-voltage range
–0.3
8
V
VDS
Power DMOS drain-to-source voltage
–0.3
42
V
Continuous total dissipation
See Thermal Information
TA
Operating ambient temperature
–40
125
°C
TJ
Operating junction temperature range
–40
150
°C
Tstg
Storage temperature range
–55
165
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged device model (CDM), per AEC
Q100-011
UNIT
±2000
All pins
±750
Corner pins (1, 8, 9, and
16)
±750
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN MAX
VCC
Supply voltage
VIH
High-level input voltage
3
VIL
Low-level input voltage
TA
Operating ambient temperature
5.5
2.4
–40
UNIT
V
V
0.7
V
125
°C
6.4 Thermal Information
TLC6C598-Q1
THERMAL METRIC
(1)
PW (TSSOP)
D (SOIC)
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
129.4
100
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
55.4
45
°C/W
RθJB
Junction-to-board thermal resistance
65.8
40
°C/W
ψJT
Junction-to-top characterization parameter
9.9
10
°C/W
ψJB
Junction-to-board characterization parameter
65.2
40
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
NA
NA
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
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SLIS142D – DECEMBER 2012 – REVISED SEPTEMBER 2016
6.5 Electrical Characteristics
VCC = 5 V, TC = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
DRAIN0 to DRAIN7. Drain-tosource voltage
High-level output voltage, SER
OUT
IOH = –20 μA
VOL
Low-level output voltage, SER
OUT
IOH = 20 μA
IIH
High-level input current
VCC = 5 V, VI = VCC
IIL
Low-level input current
VCC = 5 V, VI = 0
IOH = −4 mA
IOH = 4 mA
VCC = 5 V
0.001
0.01
0.25
0.4
V
V
μA
μA
0.1
1
All outputs on
88
160
200
Logic supply current at frequency
fSRCK = 5 MHz, CL = 30 pF
All outputs on
IDSX
Off-state drain current
VDS = 30 V
VCC = 5 V
VDS = 30 V, TC = 125°C
VCC = 5 V
Hysteresis
V
–0.2
ICC(FRQ)
Thermal shutdown trip point
V
4.69
All outputs off
VCC = 5 V, no clock signal
Thys
4.99
4.5
0.2
Logic supply current
TSHUTDOWN
V
4.9
VCC = 5 V
ICC
rDS(on)
UNIT
40
VOH
Static drain-source on-state
resistance
MAX
μA
μA
0.1
0.15
0.3
ID = 20 mA, VCC = 5 V, TA = 25°C,
Single channel ON
6
7.41
8.6
ID = 20 mA, VCC = 5 V, TA = 25°C,
All channels ON
6.7
8.3
9.6
ID = 20 mA, VCC = 3.3 V, TA = 25°C,
Single channel ON
7.9
9.34
11.2
ID = 20 mA, VCC = 3.3 V, TA = 25°C,
All channels ON
8.7
10.25
12.3
ID = 20 mA, VCC = 5 V, TA = 125°C,
Single channel ON
9.1
11.13
12.9
ID = 20 mA, VCC = 5 V, TA = 125°C,
All channels ON
10.3
12.28
14.5
ID = 20 mA, VCC = 3.3 V, TA = 125°C,
Single channel ON
11.6
13.69
16.4
ID = 20 mA, VCC = 3.3 V, TA = 125°C,
All channels ON
12.8
14.89
18.2
150
175
200
μA
Ω
ºC
15
ºC
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
tsu
Setup time, SER IN high before SRCK↑
15
ns
th
Hold time, SER IN high after SRCK↑
15
ns
tw
SER IN pulse duration
40
ns
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6.7 Switching Characteristics
VCC = 5 V, TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time, low-to-high-level output from G
220
ns
tPHL
Propagation delay time, high-to-low-level output from G
75
ns
tr
Rise time, drain output
210
ns
tf
Fall time, drain output
128
ns
tpd
Propagation delay time, SRCK↓ to SER OUT
CL = 30 pF, ID = 48 mA
49.4
ns
tor
SER OUT rise time (10% to 90%)
CL = 30 pF
20
ns
tof
SER OUT fall time (90% to 10%)
CL = 30 pF
20
ns
f(SRCK)
Serial clock frequency
CL = 30 pF, ID = 20 mA
tSRCK_WH
SRCK pulse duration, high
30
ns
tSRCK_WL
SRCK pulse duration, low
30
ns
6
CL = 30 pF, ID = 48 mA
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10
MHz
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6.8 Timing Waveforms
Figure 1 shows the SER IN to SER OUT waveform. The output signal appears on the falling edge of the shift
register clock (SRCK) because there is a phase inverter at SER OUT (see Figure 13). As a result, it takes seven
and a half periods of SRCK for data to transfer from SER IN to SER OUT.
8
7
5
6
3
4
2
1
SRCK
SER IN
CLR
1
SER OUT
0
Figure 1. SER IN to SER OUT Waveform
Figure 2 shows the switching times and voltage waveforms. Tests for all these parameters took place using the
test circuit shown in Figure 11.
5V
G
50%
50%
0V
tPHL
tPLH
90%
Output
10 V
90%
10%
10%
0.5 V
tf
tr
5V
SRCK
50%
0V
tsu
th
5V
SER IN
50%
50%
0V
tw
Switching Times, Input Setup and Hold Waveforms
SRCK
50%
50%
tpd
tpd
50%
SER OUT
50%
SER OUT Propagation Delay Waveform
Figure 2. Switching Times and Voltage Waveforms
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6.9 Typical Characteristics
Conditions for Figure 5 and Figure 6: Single channel on, conditions for Figure 7, Figure 8 and Figure 9: All channels on
500
350
T A = ±40ƒC
T A = 25ƒC
T A = 125ƒC
Supply Current ( A)
Supply Current ( A)
400
All Channels Off
All Channels On
300
300
200
250
200
150
100
100
50
VCC = 5V
0
0
0.1
1
10
100
Frequency (MHz)
3.0
5.0
5.5
6.0
C002
16
Drain-Source On-State Resistance (Ÿ
Drain-Source On-State Resistance (Ÿ
4.5
Figure 4. Supply Current vs Supply Voltage
12
10
8
6
4
TA = ±40ƒC
2
TA = 25ƒC
VCC = 5V
TA = 125ƒC
0
0
10
14
12
10
8
6
4
TA = ±40ƒC
TA = 25ƒC
2
20
30
40
50
60
0
10
20
30
40
50
Drain Current (mA)
C003
Figure 5. Drain-to-Source On-State Resistance vs Drain
Current
VCC = 3.3V
TA = 125ƒC
0
Drain Current (mA)
60
C004
Figure 6. Drain-to-Source On-State Resistance vs Drain
Current
14
18
Drain-Source On-State Resistance (Ÿ
Drain-Source On-State Resistance (Ÿ
4.0
Supply Voltage (V)
Figure 3. Supply Current vs Frequency
12
10
8
6
4
TA = ±40ƒC
2
TA = 25ƒC
VCC = 5V
TA = 125ƒC
0
0
10
16
14
12
10
8
6
4
TA = ±40ƒC
2
TA = 25ƒC
20
30
40
50
60
0
10
20
30
40
Drain Current (mA)
C005
Figure 7. Drain-to-Source On-State Resistance vs Drain
Current
VCC = 3.3V
TA = 125ƒC
0
Drain Current (mA)
8
3.5
C001
50
60
C006
Figure 8. Drain-to-Source On-State Resistance vs Drain
Current
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Typical Characteristics (continued)
Conditions for Figure 5 and Figure 6: Single channel on, conditions for Figure 7, Figure 8 and Figure 9: All channels on
350
16
300
tplh
tPLH
tPHL
tphl
250
trtr
tftf
14
Switching Time (ns)
Drain-Source On-State Resistance (Ÿ
18
12
10
8
6
4
TA = ±40ƒC
2
TA = 25ƒC
2.5
3.0
3.5
150
100
50
Ids = 20mA
TA = 125ƒC
0
200
0
4.0
4.5
5.0
5.5
6.0
Supply Voltage (V)
±60
6.5
±40
±20
0
20
40
60
80
100
120
Ambient Temperature (ƒC)
C007
Figure 9. Drain-to-Source On-State Resistance vs Drain
Current
140
C008
Figure 10. Switching Time vs Ambient Temperature
7 Parameter Measurement Information
Figure 11 and Figure 12 show the resistive-load test circuit and voltage waveforms. One can see from Figure 12
that with G held low and CLR held high, the status of each drain changes on the rising edge of the register clock,
indicating the transfer of data to the output buffers at that time.
5V
10 V
VCC
CLR
ID
RL = 200 W
SRCK
Output
MCU
DRAIN
SER IN
CL = 30 pF
(see Note A)
RCK
G
GND
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A.
CL includes probe and jig capacitance.
Figure 11. Resistive-Load Test Circuit
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Parameter Measurement Information (continued)
8
7
6
5
4
3
2
1
SRCK
SER IN
G
RCK
0
CLR
1
DRAIN0
0
DRAIN1
0
DRAIN6
0
DRAIN7
0
Figure 12. Voltage Waveforms
10
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8 Detailed Description
8.1 Overview
The TLC6C598-Q1 device is a monolithic, medium-voltage, low-current 8-bit shift register designed to drive
relatively moderate load power such LEDs. The device contains an 8-bit serial-in, parallel-out shift register that
feeds an 8-bit D-type storage register. Thermal shutdown protection is also built-into the device.
8.2 Functional Block Diagram
G
RCK
DRAIN0
CLR
D
D
C1
SRCK
C1
CLR
CLR
D
D
DRAIN1
SER IN
C1
C1
CLR
CLR
D
D
C1
C1
CLR
CLR
D
D
C1
CLR
D
D
C1
DRAIN4
C1
CLR
CLR
D
D
C1
DRAIN5
C1
CLR
CLR
D
D
C1
DRAIN6
C1
CLR
CLR
D
D
CLR
DRAIN3
C1
CLR
C1
DRAIN2
DRAIN7
C1
CLR
GND
D
C1
SER OUT
CLR
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Figure 13. Logic Diagram (Positive) of TLC6C598-Q1
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8.3 Feature Description
8.3.1 Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 175°C
(typical). The thermal shutdown forces the device to have an open state when the junction temperature exceeds
the thermal trip threshold. Once the junction temperature decreases below 160°C (typical), the device begins to
operate again.
8.3.2 Serial-In Interface
The TLC6C598-Q1 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register. Data transfer through the shift and storage registers is on the rising edge of the shift register clock
(SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when
shift register clear (CLR) is high.
8.3.3 Clear Registers
A logic low the CLR pin clears all registers in the device. TI suggests clearing the device during power up or
initialization.
8.3.4 Output Channels
DRAIN0–DRAIN7. These pins can survive up to 40-V LED supply voltage. This is quite helpful during automotive
load-dump conditions.
8.3.5 Register Clock
RCK is the storage-register clock. Data in the storage register appears at the output whenever the output enable
(G) input signal is high.
8.3.6 Cascade Through SER OUT
By connecting the SER OUT pin to the SER IN input of the next device on the serial bus to cascade, the data
transfers to the next device on the falling edge of SRCK. This can improve the cascade application reliability, as
it can avoid the issue that the second device receives SRCK and data input at the same rising edge of SRCK.
8.3.7
Output Control
Holding the output enable (pin G) high holds all data in the output buffers low, and all drain outputs are off.
Holding G low makes data from the storage register transparent to the output buffers. When data in the output
buffers is low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs are capable
of sinking current. This pin also can be used for global PWM dimming.
8.4 Device Functional Modes
8.4.1 Operation With VCC < 3 V
This device works normally within the range 3 V ≤ VCC ≤ 5.5 V. When the operating voltage is lower than 3 V,
correct behavior of the device, including communication interface and current capability, is not assured.
8.4.2 Operation With 5.5 V ≤ VCC ≤ 8 V
The device works normally in this voltage range, but reliability issues may occur if the device works for a long
time in this voltage range.
12
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLC6C598-Q1 device is a serial-in, parallel-out, power and logic, 8-bit shift register with low-side open-drain
DMOS output ratings of 40-V and 50-mA continuous sink-current capabilities when VCC = 5 V. The device is
designed to drive resistive loads and is particularly well-suited as an interface between a microcontroller and
LEDs or lamps. The device also provides up to 2000 V of ESD protection when tested using the human body
model and 200 V when using the machine model
9.2 Typical Application
Figure 14 shows a typical cascade application circuit with two TLC6C598-Q1 chips configured in cascade
topology. The MCU generates all the input signals.
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Typical Application (continued)
Battery 9 V–40 V
3 V–5.5 V
DRAIN0
DRAIN6
DRAIN1
DRAIN7
VCC
GND
SER IN
SRCK
MCU
G
SER OUT
CLR
RCK
DRAIN0
DRAIN1
DRAIN6
DRAIN7
VCC
SER IN
GND
SRCK
G
SER OUT
CLR
RCK
Copyright © 2016, Texas Instruments Incorporated
Figure 14. Typical Application Circuit
9.2.1 Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
VBattery
9 V to 40 V
VCC_1
3.3 V
I(D0), I(D1), I(D2), I(D3) , I(D4), I(D5), I(D6), I(D7)
30 mA
VCC_2
5V
I(D8), I(D9), I(D10), I(D11) , I(D12), I(D13), I(D14), I(D15)
50 mA
14
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SLIS142D – DECEMBER 2012 – REVISED SEPTEMBER 2016
9.2.2 Detailed Design Procedure
To
•
•
•
begin the design process, the designer must decide on a few parameters, as follows:
Vsupply: LED supply voltage
VDx: LED forward voltage
I: LED current
With these parameters determined, the resistor in series with the LED can be calculated by using the following
equation:
R X = (VSupply - VDx ) / I
(1)
9.2.3 Application Curve
Figure 15. TLC6C598-Q1 Application Waveform
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SLIS142D – DECEMBER 2012 – REVISED SEPTEMBER 2016
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10 Power Supply Recommendations
The TLC6C598-Q1 device is designed to operate with an input voltage supply range from 3 V to 5.5 V. This input
supply should be well regulated. TI recommends placing the ceramic bypass capacitors near the VCC pin.
11 Layout
11.1 Layout Guidelines
There are no special layout requirement for the digital signal pins. The only requirement is placing the ceramic
bypass capacitors near the corresponding pin.
Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat-flow
path from the package to the ambient is through the cooper on the PCB. Maximizing the copper coverage is
extremely important when the design does not include heat sinks attached to the PCB on the other side of the
package.
Add as many thermal vias as possible directly under the package ground pad to optimize the thermal conductivity
of the board.
All thermal vias should be either plated shut or plugged and capped on both sides of the board to prevent solder
voids. To ensure reliability and performance, the solder coverage should be at least 85%.
11.2 Layout Example
VCC
1
16
GND
SER IN
2
15
SRCK
DRAIN0
3
14
DRAIN7
DRAIN1
4
13
DRAIN6
DRAIN2
5
12
DRAIN5
DRAIN3
6
11
DRAIN4
CLR
7
10
RCK
G
8
9
SER OUT
Figure 16. TLC6C598-Q1 Example Layout
16
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SLIS142D – DECEMBER 2012 – REVISED SEPTEMBER 2016
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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SLIS142D – DECEMBER 2012 – REVISED SEPTEMBER 2016
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13.1 Package Option Addendum
13.1.1 Packaging Information
Orderable Device
(1)
(2)
(3)
(4)
(5)
(6)
Status
(1)
Package
Type
Package
Drawing
Pins
Package
Qty
Eco Plan
(2)
Lead/Ball
Finish (3)
MSL Peak Temp
(4)
Op Temp (°C)
Device Marking (5) (6)
TLC6C598QPWRQ1
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168
HR
-40 to 125
6C598
TLC6C598QDRQ1
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168
HR
-40 to 125
TLC6C598
TLC6C598CQDRQ1
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168
HR
-40 to 125
TLC6C598C
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
18
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SLIS142D – DECEMBER 2012 – REVISED SEPTEMBER 2016
13.1.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
TLC6C598QPWRQ1
TSSOP
PW
16
2000
330
12.4
TLC6C598QDRQ1
SOIC
D
16
2500
330
16.4
TLC6C598CQDRQ1
SOIC
D
16
2500
330
16.4
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
6.9
5.6
1.6
8
12
Q1
6.5
10.3
2.1
8
16
Q1
6.5
10.3
2.1
8
16
Q1
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SLIS142D – DECEMBER 2012 – REVISED SEPTEMBER 2016
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
L
W
20
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLC6C598QPWRQ1
TSSOP
PW
16
2000
367
367
38
TLC6C598QDRQ1
SOIC
D
16
2500
367
367
38
TLC6C598CQDRQ1
SOIC
D
16
2500
367
367
38
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PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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