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TLC59291
SLVSA96A – SEPTEMBER 2015 – REVISED MARCH 2016
TLC59291 8/16-Channel, Constant Current LED Driver with 7-bit Brightness Control Low
Quiescent Current and Full Self Diagnosis for LED Lamp
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8/16 Constant-Current Sink Output Channels with
On/Off Control
Current Capability:
– 1 - 40 mA (VCC ≤ 3.6 V)
– 1 - 50 mA (VCC > 3.6 V)
Global Brightness Control: 7-Bit (128 Steps)
Power-Supply Voltage Range: 3 V to 5.5 V
LED Power-Supply Voltage: Up to 10 V
Constant-Current Accuracy:
– Channel-to-Channel = ±3% (Typical)
– Device-to-Device = ±2% (Typical)
Low Quiescent Current
SOUT can be Configured for 8-Channel or 16Channel Output
LED Open Detection (LOD)/LED Short Detection
(LSD) with Invisible Detection Mode (IDM)
Output Leakage Detection (OLD) Detects 3 µA
Leak
Pre-Thermal Warning (PTW)
Thermal Shutdown (TSD)
Current Reference Terminal Short Flag (ISF)
Power-Save Mode with 10-µA Consumption
Undervoltage Lockout Sets the Default Data
2-ns Delayed Switching Between Each Channel
Minimizes Inrush Current
Operating Temperature: –40°C to 85°C
Industry LED Indicator
Illumination
LED Video Display
3 Description
The TLC59291 is a 8/16-channel constant current
sink LED driver. Each channel can be turned on-off
by writing data to an internal register. The constant
current value of all 16 channels is set by a single
external resistor and 128 steps for the global
brightness control (BC).
The TLC59291 has six type error flags: LED open
detection (LOD), LED short detection (LSD), output
leak detection (OLD), reference terminal short
detection (ISF), Pre thermal warning (PTW) and
thermal error flag (TEF). In addition, the LOD and
LSD functions have invisible detection mode (IDM)
that can detect those errors even when the output is
off. The error detection results can be read via a
serial interface port.
The TLC59291 has low quiescent current in normal
mode, it also has a power-save mode that sets the
total current consumption to 10 uA (typical) when all
outputs are off.
Device Information(1)
PART NUMBER
TLC59291
PACKAGE
VQFN (24)
BODY SIZE (NOM)
4.00mm x 4.00mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit (Multiple Daisy Chained TLC59291s)
VLED
OUT0 - - - - - - - - - - OUT15
DATA
SIN
Controller
SCLK
LAT
BLANK
SIN
VCC
SCLK
LAT
OUT0 - - - - - - - - - - OUT15
SOUT
TLC59291
IC1
SOUT
VCC
SCLK
VCC
LAT
BLANK
TLC59291
ICn
VCC
BLANK
GND
IREF
IREF
GND
RIREF
RIREF
GND
GND
GND
GND
3
SID read
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLC59291
SLVSA96A – SEPTEMBER 2015 – REVISED MARCH 2016
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
8
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Switching Characteristics .......................................... 8
Timing Diagrams ....................................................... 9
Typical Characteristics ............................................ 21
Parameter Measurement Information ................ 23
Detailed Description ............................................ 24
8.1 Overview ................................................................. 24
8.2 Functional Block Diagram ....................................... 24
8.3 Feature Description................................................. 25
8.4 Device Functional Modes........................................ 28
8.5 Register Maps ......................................................... 31
9
Application and Implementation ........................ 37
9.1 Application Information............................................ 37
9.2 Typical Application ................................................. 37
10 Power Supply Recommendations ..................... 38
11 Layout................................................................... 39
11.1 Layout Guidelines ................................................. 39
11.2 Layout Example .................................................... 39
12 Device and Documentation Support ................. 40
12.1
12.2
12.3
12.4
12.5
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
40
40
40
40
40
13 Mechanical, Packaging, and Orderable
Information ........................................................... 40
4 Revision History
Changes from Original (September 2015) to Revision A
Page
•
Changed Features From: Channel-to-Channel = ±1% (Typical) To: Channel-to-Channel = ±3% (Typical) .......................... 1
•
Deleted device number TLC5929 From the Electrical Characteristics table.......................................................................... 6
•
Changed ΔIOL(C0) Test Condition in Electrical Characteristics From: BC = 7Fh, RIREF = 1.6 kΩ To: BC = 0Eh, RIREF =
3.6 kΩ, ................................................................................................................................................................................... 7
•
Changed the ΔIOL(C1) values in Electrical Characteristics From: TYP = ±2%, MAX = ±4% To TYP = 1% , MAX =
÷3%: ....................................................................................................................................................................................... 7
•
Deleted device number TLC5929 From the Switching Characteristics table ......................................................................... 8
•
Changed text From: "with the 1-bit data" To: "with the 16-bit data" in the Function Control Data Writing section ............. 34
2
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SLVSA96A – SEPTEMBER 2015 – REVISED MARCH 2016
5 Pin Configuration and Functions
SCLK
SIN
GND
VCC
IREF
SOUT
24
23
22
21
20
19
RGE Package
24-Pin VQFN
(Top View)
LAT
1
18
BLANK
OUT0
2
17
OUT15
OUT1
3
16
OUT14
OUT2
4
15
OUT13
OUT3
5
14
OUT12
OUT4
6
13
OUT11
8
9
10
11
12
OUT6
OUT7
OUT8
OUT9
OUT10
OUT5
7
Thermal Pad
(Bottom Side)
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
BLANK PIN, has two configures:
When FC9(BLANK Mode) = 0, Blank pin worked as SOUT select pin:
a. When BLANK = Low, SOUT is connected to the bit 7 of the 16-bit shift register, worked as 8ch
device;
b. When BLANK = High, SOUT is connected to the bit 15 of the 16-bit shift register, worked as
16ch device;
When FC9(BLANK Mode) = 1, Blank pin worked as OUTPUT enable pin;
a. When BLANK = Low, all constant current outputs are controlled by the on/off control data in the
data latch.
b. When BLANK = High, all OUTx are forced off
BLANK
18
I
GND
22
—
Ground
IREF
20
I/O
Maximum current programming terminal.
A resistor connected between IREF and GND sets the maximum current for every constant-current
output. When this terminal is directly connected to GND, all outputs are forced off. The external
resistor should be placed close to the device and must be in the range of 1.32 kΩ to 66 kΩ.
LAT
1
I
Data latch.
The rising edge of LAT latches the data from the common shift register into the output on/off data
latch. At the same time, the data in the common shift register are replaced with SID, which is
selected by SIDLD. See the Output On/Off Data Latch section and Status Information Data (SID)
section for more details.
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
OUT0
2
O
OUT1
3
O
OUT2
4
O
OUT3
5
O
OUT4
6
O
OUT5
7
O
OUT6
8
O
OUT7
9
O
OUT8
10
O
OUT9
11
O
OUT10
12
O
OUT11
13
O
OUT12
14
O
OUT13
15
O
OUT14
16
O
OUT15
17
O
SCLK
24
I
Serial data shift clock.
Data present on SIN are shifted to the LSB of the 16-bit shift register with the SCKI rising edge. Data
in the shift register are shifted toward the MSB at each SCLK rising edge. The MSB data of the
common shift register appear on SOUT.
SIN
23
I
Serial data input for the 16-bit common shift register.
When SIN is high, a '1' is written to the LSB of the common shift register at the rising edge of SCLK.
Constant-current sink outputs.
Multiple outputs can be configured in parallel to increase the constant-current capability. Different
voltages can be applied to each output.
SOUT
19
O
Serial data output of the 16-bit common shift register.
When FC9(BLANK Mode) = 0 and BLANK = LOW;
SOUT is connected to the bit 7 of the 16-bit shift register. Data are clocked out at the SCLK rising
edge.
In other case:
SOUT is connected to the bit 15 of the 16-bit shift register. Data are clocked out at the SCLK rising
edge.
VCC
21
—
Power-supply voltage
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
MIN
MAX
–0.3
6
V
SIN, SCLK, LAT, BLANK, IREF
–0.3
VCC + 0.3
V
SOUT
–0.3
VCC + 0.3
V
OUT0 to OUT15
–0.3
11
V
65
mA
150
°C
150
°C
Supply voltage, VCC (2)
Input voltage
Output voltage
Output current (DC)
OUT0 to OUT15
Operating junction temperature, TJ (max)
Storage temperature, TSTG
(1)
(2)
4
–55
UNIT
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to device ground terminal.
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SLVSA96A – SEPTEMBER 2015 – REVISED MARCH 2016
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±2000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
At TA= –40°C to 85°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
3
3.3
5.5
V
10
V
DC Characteristics: VCC = 3 V to 5.5 V
VCC
Supply voltage
VO
Voltage applied to output
OUT0 to OUT15
VIH
High-level input voltage
SIN, SCLK, LAT, BLANK
0.7 × VCC
VCC
V
VIL
Low-level input voltage
SIN, SCLK, LAT, BLANK
GND
0.3 × VCC
V
IOH
High-level output current
SOUT
–2
mA
IOL
Low-level output current
SOUT
2
mA
OUT0 to OUT15
3 V ≤ VCC ≤ 3.6 V
40
mA
OUT0 to OUT15
3.6 V < VCC ≤ 5.5 V
50
mA
IOLC
Constant output sink current
TA
Operating free-air temperature range
–40
85
°C
TJ
Operating junction temperature range
–40
125
°C
33
MHz
AC Characteristics: VCC = 3 V to 5.5 V
fCLK
(SCLK)
Data shift clock frequency
SCLK
tWH0
SCLK
10
ns
tWL0
SCLK
10
ns
LAT
20
ns
tWH2
BLANK
40
ns
tWL2
BLANK
40
ns
tSU0
SIN to SCLK↑
5
ns
LAT↑ to SCLK↑
200
ns
SCLK ↓to LAT↑
10
ns
3
ns
LAT↑ to SCLK↑
10
ns
LAT↑ to SCLK ↓
40
ns
Pulse duration
(see Figure 1 and Figure 3)
tWH1
Setup time
(see Figure 1, Figure 3 and
Figure 4)
tSU1
tSU2
tH0
Hold time
(see Figure 1, Figure 3, and
Figure 13)
tH1
tH2
SIN to SCLK↑
6.4 Thermal Information
TLC59291
THERMAL METRIC
(1)
RGE (VQFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
38.1
RθJC(top)
Junction-to-case (top) thermal resistance
45.3
RθJB
Junction-to-board thermal resistance
16.9
ψJT
Junction-to-top characterization parameter
0.9
ψJB
Junction-to-board characterization parameter
16.9
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.2
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
At VCC = 3 V to 5.5 V and TA = –40°C to 85°C. Typical values at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = –2 mA at SOUT
VOL
Low-level output voltage
IOL = 2 mA at SOUT
VLOD
LED open detection threshold
All OUTn = on
MIN
TYP
MAX
VCC – 0.4
UNIT
VCC
V
0.4
V
0.25
0.30
0.35
V
VLSD0
All OUTn = on, detection voltage code = 0h
0.32 × VCC
0.35 × VCC
0.38 × VCC
V
VLSD1
All OUTn = on, detection voltage code = 1h
0.42 × VCC
0.45 × VCC
0.48 × VCC
V
All OUTn = on, detection voltage code = 2h
0.52 × VCC
0.55 × VCC
0.58 × VCC
V
All OUTn = on, detection voltage code = 3h
0.62 × VCC
0.65 × VCC
0.68 × VCC
V
1.175
1.205
1.235
V
1
μA
VLSD2
LED short detection threshold
VLSD3
VIREF
Reference voltage output
RIREF = 1.3 kΩ
IIN
Input current
VIN = VCC or GND at SIN, SCLK, LAT, and BLANK
–1
ICC0
SIN/SCLK/LAT = Low, BLANK = High, all OUTn = off,
VOUTn = 0.8 V, BC = 7Fh, RIREF = open
2
3
mA
ICC1
SIN/SCLK/LAT = Low, BLANK = High, all OUTn = off,
VOUTn = 0.8 V, BC = 7Fh, RIREF = 3.6 kΩ
(IOUT = 18.3 mA target)
5
7
mA
ICC2
SIN/SCLK/LAT/BLANK =Low, All OUTn = on,
VOUTn = 0.8 V, BC = 7Fh, RIREF = 3.6 kΩ
(IOUT = 18.3 mA target)
5
7
mA
ICC3
SIN/SCLK/LAT/BLANK =Low, All OUTn = on,
VOUTn = 0.8 V, BC = 0Eh, RIREF = 1.6 kΩ
(IOUT = 2 mA target)
3
4
mA
ICC4
SIN/SCLK/LAT/BLANK = Low, All OUTn = on,
VOUTn = 0.8 V, BC = 7Fh, RIREF = 1.6 kΩ
(IOUT = 41.3 mA target)
9
11
mA
ICC5
VCC = 5 V, SIN/SCLK/LAT/BLANK = Low,
All OUTn = on, VOUTn = 0.8 V, BC = 7Fh,
RIREF = 1.3 kΩ (IOUT = 50.8 mA target)
11
14
mA
ICC6
VCC = 5 V, SIN/SCLK/LAT/BLANK = Low,
VOUTn = 0.8 V, BC = 7Fh, RIREF = 1.3 kΩ
(IOUT = 50.8 mA target), all output data off with powersave mode enabled
10
40
µA
Supply current (VCC)
IOL(C0)
IOL(C1)
IOL(KG0)
IOL(KG1)
IOL(KG2)
(1)
6
Constant output sink current
(OUT0 to OUT15, see
Figure 28)
Output leakage current
(OUT0 to OUT15, see
Figure 28)
All OUTn = on, VOUTn = VOUTfix = 0.8 V, BC = 7Fh,
RIREF = 1.6 kΩ
38.5
41.3
44.1
mA
VCC = 5 V, All OUTn = on, VOUTn = VOUTfix = 1 V,
BC = 7Fh, RIREF = 1.3 kΩ
47.3
50.8
54.3
mA
0.1
μA
0.2
μA
0.8
μA
TJ = 25°C
BLANK = high, VOUTn = VOUTfix =
TJ = 85°C (1)
10 V, RIREF = 1.6 kΩ
TJ = 125°C (1)
0.3
Not tested; specified by design.
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Electrical Characteristics (continued)
At VCC = 3 V to 5.5 V and TA = –40°C to 85°C. Typical values at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ΔIO(LC0)
Constant-current error
(channel-to-channel, OUT0 to
OUT15) (2)
All OUTn = on, VOUTn = VOUTfix = 0.8 V, BC = 0Eh,
RIREF = 3.6 kΩ, TA = 25°C
±3%
±6%
ΔIOL(C1)
Constant-current error
(device-to-device, OUT0 to
OUT15) (3)
All OUTn = on, VOUTn = VOUTfix = 0.8 V, BC = 7Fh,
RIREF = 1.6 kΩ, TA = 25°C
±1%
±3%
ΔIOL(C2)
Line regulation (4)
All OUTn = on, VOUTn = VOUTfix = 0.8 V, BC = 7Fh,
RIREF = 1.6 kΩ
±0.1
±1
%/V
ΔIOL(C3)
Load regulation (5)
All OUTn = on, VOUTn = 0.8 V to 3 V, VOUTfix = 0.8 V,
BC = 7Fh, RIREF = 1.6 kΩ
±0.5
±3
%/V
TTEF
Thermal error flag threshold
Junction temperature (1)
150
165
180
°C
THYS
Thermal error flag hysteresis
Junction temperature (1)
5
10
20
°C
TPTW
Pre-thermal warning threshold
Junction temperature (1)
125
138
150
°C
(2)
(3)
(4)
(5)
The deviation of each output from the average of OUT0 to OUT15 constant-current. Deviation is calculated by the formula:
é
ù
ê
ú
ê
ú
IOLC( n )
D (%) = 100 x ê
- 1ú
êé I
+I
+...+ IOLC(14)+ IOLC(15) ù ú
ê ê OLC(0) OLC(1)
ú ú
êê
ú ú
16
ë
û û.
ë
The deviation of the OUT0 to OUT15 constant-current average from the ideal constant-current value. Deviation is calculated by the
formula:
éé I
ù
+I
+...+ IOLC(14) + IOLC(15) ù
ê ê OLC(0) OLC(1)
ú
ú
êê
ú
ú
16
û - (Ideal Output Current)ú
D (%) = 100 x ê ë
ê
ú
Ideal Output Current
ê
ú
ê
ú
ë
û
æ 1.20 ö
IO(LC _ IDEAL) = 54 x ç
÷
è RIREF ø
Ideal current is calculated by the formula:
Line regulation is calculated by the formula:
é IOLC(n) at VCC = 5.5 V - IOLC(n) at VCC = 3 V ù
ú
D (%) = 100 x ê
ê
ú
2.5 x IOLC(n) at VCC = 3 V
ë
û
Load regulation is calculated by the equation:
æ IOLC( n ) at VOUTn = 3 V - IOLC( n ) at VOUTn = 1 V ö
÷
D (%) = 100 x ç
ç
÷
2 x IOLC( n ) at VOUTn = 1 V
è
ø
(
)
(
)
(
(
(
(
) (
) (
)
)
)
)
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6.6 Switching Characteristics
At VCC = 3 V to 5.5 V, TA = –40°C to 85°C, CL = 15 pF, RL = 82 Ω, RIREF = 1.3 kΩ, and VLED = 5 V.
Typical values at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
PARAMETER
TYP
MAX
At SOUT
10
15
ns
At OUTn, BC = 7Fh
40
60
ns
At SOUT
10
15
ns
At OUTn, BC = 7Fh
40
60
ns
tD0
SCLK↑ to SOUT↑↓
8
22
ns
tD1
LAT↑ or BLANK↑↓ to OUT0 sink current on/off,
BC = 7Fh
35
65
ns
2
6
ns
tR0
Rise time
tR1
tF0
Fall time
tF1
tD2
Propagation delay
TEST CONDITIONS
MIN
OUTn on/off to OUTn + 1 on/off, BC = 7Fh
UNIT
tD3
LAT↑ to power-save mode by data writing for all output
off
400
ns
tD4
SCLK↑ to normal mode operation
100
µs
tD5
BLANK↑↓ to SOUT↑↓ when BLANK MODE=0
100
ns
20
ns
28
MHz
tON_ERR
Output on-time error (1)
fOSC
Internal oscillator
frequency
(1)
8
Output on/off data = all '1',
BLANK low pulse = 40 ns, BC = 7Fh
–30
12
20
Output on-time error (tON_ERR) is calculated by the formula: tON_ERR (ns) = tOUT_ON – 40 ns. tOUT_ON is the actual on-time of OUTn.
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6.7 Timing Diagrams
tWH0, tWL0, tWH1, tWH2, tWL2:
VIH
Input
(1)
50%
VIL
tWH
tWL
tSU0, tSU1, tH0, tH1:
VIH
SCLK Input
(1)
50%
VIL
tSU
tH
VIH
(1)
SIN/LAT Input
50%
VIL
(1)
Input pulse rise and fall time is 1 ns to 3 ns.
Figure 1. Input Timing
tR0, tR1, tF0, tF1, tD0, tD1, tD2:
VIH
Input
(1)
50%
VIL
tD
VOH or VOUTnH
90%
Output
50%
10%
VOL or VOUTnL
tR or tF
(1)
Input pulse rise and fall time is 1 ns to 3 ns.
Figure 2. Output Timing
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Timing Diagrams (continued)
SIN
DATA
0A
DATA
15B
DATA
13B
DATA
14B
DATA
12B
tH0
tSU0
DATA
3B
DATA
11B
DATA
2B
DATA
0B
DATA
1B
tH1
tWH0
DATA
15C
DATA
14C
1
2
DATA
13C
DATA
12C
DATA
11C
DATA
10C
3
4
5
6
tSU1
SCLK
1
2
3
4
5
13
14
15
16
tSU2
tWH1
tWL0
LAT
Shift Register
LSB Data
(Internal)
DATA
0A
Shift Register
LSB + 1 Data
(Internal)
DATA
1A
SID
0A
SID
1A
DATA
15B
SID
0A
DATA
14B
DATA
15B
DATA
13B
DATA
14B
DATA
3B
DATA
12B
DATA
13B
DATA
4B
DATA
2B
DATA
1B
Selected SID
0B
DATA
15C
DATA
14C
DATA
13C
DATA
12C
DATA
11C
DATA
3B
DATA
0B
DATA
2B
Selected SID
1B
SID
0B
DATA
15C
DATA
14C
DATA
13C
DATA
12C
Selected SID
14B
SID
13B
SID
12B
SID
11B
SID
10B
SID
9B
Selected SID
15B
SID
14B
SID
13B
SID
12B
SID
11B
SID
10B
SID
11B
SID
10B
DATA
1B
Shift Register
MSB - 1 Data
(Internal)
DATA
14A
SID
14A
SID
13A
SID
12A
SID
11A
SID
10A
SID
1A
SID
0A
Shift Register
MSB Data
(Internal)
DATA
15A
SID
15A
SID
14A
SID
13A
SID
12A
SID
11A
SID
2A
SID
1A
DATA
15B
DATA
14B
DATA
0A
DATA
15B
Output On/Off
Data Latch
(Internal)
DATA15A–0A
DATA15B–0B
Control
Data Latch
(Internal)
SOUT
Latest Control Data
DATA
15A
SID
15A
SID
14A
SID
13A
tD0
SID
12A
SID
11A
SID
2A
SID
0A
SID
1A
Selected
SID
SID
14B
SID
13B
SID
12B
DATA
15B
tR0/tF0
tWH2
BLANK
tWL2
tD1
tD1
OFF
(1)
OUTn
ON
ON
tOUTON
tD2
OFF
OUTn+1
(1)
tD1
(2)
OFF
ON
tF1 OFF
(3)
tD1
ON
OFF
OFF
OFF
ON
OFF
OUTn
OFF
ON
OFF
OUTn
tD2
ON
ON
OFF
OUTn
OFF
OFF
OFF
ON
tR1
(4)
ON
(1) On/off latched data is '1'.
(2) On/off latched data change from '1' to '0' at second LAT signal.
(3) On/off latched data change from '0' to '1' at second LAT signal.
(4) On/off latched data is '0'.
Figure 3. Write for ON/Off Data and Output Timing (BLANK Mode = 1)
10
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Timing Diagrams (continued)
SIN
DATA
0A
DATA
15B
DATA
13B
DATA
14B
DATA
2B
DATA
0B
DATA
1B
tH0
tWH0
tSU0
DATA
7C
DATA
6C
DATA
1C
DATA
0C
1
2
7
8
tH1
SCLK
1
2
3
14
15
16
6
tWH1
tSU2
LAT
Shift Register
LSB Data
(Internal)
DATA
0A
DATA
15B
DATA
14B
DATA
2B
DATA
1B
DATA
0B
DATA
7C
DATA
1C
DATA
0C
Shift Register
LSB + 1 Data
(Internal)
DATA
1A
DATA
0A
DATA
15B
DATA
3B
DATA
2B
DATA
1B
DATA
0B
DATA
2C
DATA
1C
Shift Register
MSB - 1 Data
(Internal)
DATA
14A
DATA
13A
DATA
12A
DATA
0A
DATA
15B
DATA
14B
DATA
14B
DATA
14B
DATA
14B
Shift Register
MSB Data
(Internal)
DATA
15A
DATA
14A
DATA
13A
DATA
1A
DATA
0A
DATA
15B
DATA
15B
DATA
15B
DATA
15B
DATA
0B
DATA
7C
Output On/Off
Data Latch
(Internal)
DATA15A–0A
DATA15B–0B
Control
Data Latch
(Internal)
SOUT
Latest Control Data
DATA
15A
DATA
14A
DATA
13A
tD0
DATA
1A
DATA
0A
DATA
7B
DATA
15B
DATA
6B
tD5
tR0/tF0
BLANK
tD1
tD1
OFF
OFF
(1)
OUT
ON
ON
tD2
OFF
OUTn+1
(1)
tD1
(2)
ON
ON
OFF
OFF
OUTn
tD1
OFF
tD1
(3)
ON
OFF
OFF
OUTn
OFF
ON
ON
OFF
OUTn
tD2
ON
OFF
(4)
ON
(1) If the on/off latched data is changed from “0” to “1” at 1’st LAT signal, changed from “1” to “0” at second LAT signal.
(2) If the on/off latched data is changed from “0” to “1” at 1’st LAT signal, changed from “1” to “1” at second LAT signal.
(3) If the on/off latched data is changed from “1” to “0” at 1’st LAT signal, changed from “0” to “1” at second LAT signal.
(4) if the on/off latched data is “0”.
Figure 4. Write for On/Off Data and Output Timing (BLANK Mode = 0)
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Timing Diagrams (continued)
SIN
Low
SCLK
1
2
3
14
15
16
1
2
3
4
5
6
LAT
BLANK
PSMODE Bit in
Control Data Latch
(Internal)
Don’t Care
1
On/Off Control
Data Latch
(Internal)
Previous On/Off Data
All Data are 0
OFF
OFF
OUT0
ON
OFF
OFF
OUT1
ON
OFF
OFF
OUT15
ON
Power-Save
Mode
Normal Mode
More Than 100 µA
ICC
(The Current
of VCC)
Normal Mode
Power-Save Mode
tD3
Normal Mode
tD4
Less Than 100 µA
Figure 5. Power-Save Mode
12
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SLVSA96A – SEPTEMBER 2015 – REVISED MARCH 2016
Timing Diagrams (continued)
SCLK
LAT
Common Shift
Register Bits[15:0]
(Internal)
LOD/TEF Data
These data are copied to the on/off data latch at LAT rising edge.
Common Shift
Register Bit 16
(Internal)
0
Output On/Off
Data (Internal)
SIDLD Data
(Internal)
Previous On/Off Data
New Latched GS Data
01 (LOD is selected)
High
BLANK
Low
OFF
All outputs are forced off
by TSD function.
OUTn
Device Junction
Temperature (TJ)
TJ < TPTW
TEF in SID
(Internal Data)
ON
ON
TJ ³ TTEF
TJ ³ TPTW
PTW is set to 1 when device
junction temperature is greater
than TPTW.
TJ < TTEF - THYST
PTW is not reset at LAT rising edge because SIDLD
does not select LOD. PTW is reset to 0 when the
device junction temperature is less than TPTW and
SIDLD selects LOD.
0
1
OFF
OFF
OFF
ON
1
PTW in SID
(Internal Data)
Resumed with TJ
going down.
TJ < TPTW
1
TEF is reset to 0at LAT riging edge for
on/off data writing when the device junction
temperature is less than TTEF and SIDLD
selects LOD.
0
TJ ³ TPTW
TJ ³ TTEF
1
1
0
TEF is set to 1 when device junction
temperture is grerater than TTEF.
Figure 6. PTW/TEF/TSD Timing (LOD Selected)
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Timing Diagrams (continued)
SIN
Low
SCLK
1
2
3
4
5
13
14
15
1
16
2
3
LAT
Don’t Care
BLANK
PSMODE bit
in Control Data
Latch (Internal)
1
Output On/Off
Control Data
Latch (Internal)
Previous On/Off Data
OFF
All Data are 0
OFF
OUT0
ON
OFF
OFF
OUT1
ON
OFF
OFF
OUT15
ON
Power-Save
Mode
Normal mode (No power save mode)
Depend on output on-off data
Normal mode
Power-Save mode (ICC = 30 µA,(typ))
When PSMODE bit is 0, the device does not into
the power save mode even if output on-off data is all "0".
Normal Mode
Because it takes about 50 µ s return to normal
mode, 1'st SCLK rising edge should be input
50 µ s or more before OUTn is turned on.
Figure 7. Power-Save Mode Timing
14
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Timing Diagrams (continued)
SIDLD in FC
data latch
(Internal)
01b
High
BLANK
Low
(working as enable pin)
Set current by external
resistor and BC data
When BLANK signal is High, all output is
forced off even if the IDM on time has not
been passed the selected time.
Programmed output current
OUTn current
for LED lighting
0mA
0mA
Selected output current by “IDMCUR”
bit in the function control latch
OUTn current
for IDM
0 µA
LOD data is held in SID holder while
BLANK is high level or the data is held in
SID holder when IDM working time has
passed.
Selected on time by IDMTIM bit
in the function control latch.
SID holder
data
(Internal)
2/10/20 µA
2/10/20 µA
0uA
LOD
Old data
LOD
XXXXh
LOD
XXXXh
LOD data goes through SID holder while BLANK is low level or IDM working time is not passed.
16 bit LOD
circuit output
data (Internal)
LOD
0000h
LOD
XXXXh
LOD
0000h
LOD
0000h
LOD data is not stable just after BLANK goes low.
LOD
XXXXh
LAT
17 bit common
shift register data
(Internal)
Latched output on-off data
SID is loaded into the shift register
Figure 8. IDM Operation Timing with LOD Selected and IDM Enabled
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Timing Diagrams (continued)
SIDLD in FC
data latch
(Internal)
01b
High
BLANK
Low
Set current by external
resistor and BC data
OUTn current
for LED lighting
When BLANK signal is “H” , all output is
forced off even if the IDM on time has not
been passed the selected time.
Programmed output current
0mA
0mA
The output for IDM is not turned on because
IDM is disabled by “IDMCUR” setting.
OUTn current
for IDM
0 µA
0 µA
0 µA
LOD data is held in SID holder while
BLANK is high level.
SID holder
data
(Internal)
LOD
Old data
LOD
XXXXh
LOD
XXXXh
LOD data goes through SID holder while BLANK is low level.
16 bit LOD
circuit output
data (Internal)
LOD
0000h
LOD
XXXXh
LOD
0000h
LOD
0000h
LOD data is not stable just after BLANK goes low.
LOD
XXXXh
LAT
17 bit common
shift register data
(Internal)
Latched on-off control data
SID is loaded into the shift register
Figure 9. IDM Operation Timing with LOD Selected and IDM Disabled
16
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Timing Diagrams (continued)
DATA
1A
SIN
DATA
0A
DATA DATA DATA DATA DATA
16B 15B
14B
13B 12B
Low
DATA DATA DATA
2B
3B
1B
High
DATA DATA DATA DATA
16C
15C 14C 13C
DATA
0B
SCLK
14
15
16
1
2
3
4
5
13
14
15
1
16
2
3
---
LAT
Shift register
LSB Data
(Internal)
Shift register
LSB +1 Data
(Internal)
Shift register
MSB -1 Data
(Internal)
DATA DATA
2A
1A
SID
0A
DATA
0A
SID
1A
DATA
1A
DATA DATA
3A
2A
DATA DATA
16A
0
DATA
15A
SID
15A
DATA DATA DATA DATA
16B
15B
14B
13B
0
DATA DATA DATA
3B
1B
2B
SID DATA DATA DATA
16B
15B
14B
0A
0
DATA DATA DATA
3B
4B
2B
SID
14A
DATA DATA DATA
13A
12A
11A
DATA
16A
DATA DATA
1
0
SID
15A
SID
14A
SID
13A
SID
12A
SID
1A
SID
0A
SID
2A
SID
1A
DATA
16B
0
DATA15A-0A
SIDLD in FC
data latch
(Internal)
SID
1B
SID
0B
DATA
16C
1
SID
15B
SID
14B
SID
13B
SID
15B
SID
14B
DATA
15B
DATA
16B
0
SID
0A
0
Output on-off
data latch
(Internal)
DATA DATA
16C 15C
1
DATA
1B
SID data selected by SIDLD bit is loaded into the common
shift register at LAT rising edge except SIDLD is 00b.
Shift register
MSB Data
(Internal)
SID
0B
DATA
0B
Old on-off data
XXb
LOD data is selected when SIDLD is 01h. LSD data is selected when SIDLD is set to 10b. OLD
data is selected when SID is set to 11b. No SID data is loaded when SIDLD is 00h.
SOUT
DATA DATA
1
0
DATA
16A
Low
SID
15A
SID
14A
SID
13A
SID
12A
SID
2A
SID
1A
SID
0A
DATA
16B
16 bit SID data
SID
15B
SID
14B
Low
BLANK
SID holder
data
(Internal)
Selected detector data by SIDLD is held in SID holder while BLANK is high level. Or the data is held in SID holder when IDM
working time is passed. The held data is loaded into the common shift register as SID except the case SIDLD is 00h.
Detector data
XXXXh
Detector data
XXXXh
LOD data goes through SID holder while BLANK is low level or IDM working time is not passed.
16 bit LOD or
LSD or OLD
data (Internal)
Detector
XXXXh
Detector data
0000h
Detector data
XXXXh
Detector data
0000h
The detectors data are not stable just after BLANK signal goes low.
Figure 10. SID Read Timing
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Timing Diagrams (continued)
SIN
DATA DATA DATA DATA DATA DATA
13B
12B 11B
0A
15B 14B
DATA DATA DATA
3B
1B
2B
DATA
0B
DATA DATA DATA DATA DATA DATA
15C
14C 13C 12C 11C 10C
SCLK
1
2
3
4
5
DATA
16B
0
DATA DATA DATA
14B
13B
15B
13
14
15
1
16
2
3
4
5
6
LAT
Shift register
LSB Data DATA
(Internal) 0A
Shift register
LSB +1Data DATA
1A
(Internal)
Shift register
MSB -1Data DATA
15A
(Internal)
Shift register
MSB Data
(Internal)
SID
0A
SID
1A
SID
15A
DATA
16A
0
SID
15A
Output on-off
data latch
(Internal)
DATA DATA DATA DATA DATA
16C 15C
14C
13C 12C
1
DATA
0B
SID DATA DATA DATA
16B
15B
0A
14B
0
SID
14A
SID
0B
DATA DATA DATA
3B
1B
2B
DATA DATA DATA
13A
12A
11A
SID
14A
SID
13A
SID
12A
DATA DATA DATA
4B
2B
3B
SID
0B
SID
15B
SID
14B
SID
13B
SID
12B
SID
11B
SID
10B
SID
15B
SID
14B
SID
13B
SID
12B
SID
11B
DATA
1B
SID
1A
SID
2A
SID
0A
DATA
16B
0
SID
1A
DATA
15B
DATA
16B
0
SID
0A
DATA DATA DATA DATA
16C
15C
14C 13C
1
SID
1B
DATA15B-0B
DATA15A-0A
Control data
Latch
(Internal)
Control data is not changed from previous data
DATA
16A
Low
SOUT
SID
15A
SID
14A
SID
13A
SID
12A
SID
2A
SID
1A
SID
0A
DATA
16B
SID
15B
SID
14B
SID
13B
SID
12B
SID
11B
Low
BLANK
OUTn
(1)
OUTn
(2)
OUTn
ON
ON
(3)
(4)
ON
OFF
OFF
ON
ON
OUTn
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
OFF
ON
OFF
OFF
These dotted lines are output pulse timing for IDM
ON
(1) On/off latch data is '1'.
(2) On/off latch data change from '1' to '0' at second LAT signal.
(3) On/off latch data is change from '0' to '1' at second LAT signal.
(4) On/off latch data is '0'.
Figure 11. On-Off Control Data Write Timing (BLANK Mode = 1)
18
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Timing Diagrams (continued)
SIN
DATA DATA DATA DATA
13B
0A
15B 14B
DATA DATA
1B
2B
DATA
0B
DATA DATA
7C
6C
DATA
1C
DATA
0C
SCLK
1
2
3
14
15
1
16
2
7
8
LAT
Shift register
LSB Data
(Internal)
DATA DATA DATA
0A
15B 14B
DATA DATA DATA
0B
1B
2B
DATA
7C
DATA DATA
0C
1C
Shift register
LSB +1Data
(Internal)
DATA DATA DATA
1A
0A
15B
DATA DATA DATA
1B
2B
3B
DATA
0B
DATA DATA
1C
2C
Shift register
MSB -1Data
(Internal)
DATA DATA DATA
14A
13A 12A
DATA DATA DATA
14B
15B
0A
DATA
14B
DATA DATA
14B
14B
Shift register
MSB Data
(Internal)
DATA DATA DATA
15A
14A 13A
DATA DATA DATA
0A
1A
15B
DATA
15B
DATA DATA
15B
15B
Output on-off
data latch
(Internal)
DATA 7C-0C
DATA15B-0B
DATA15A-0A
Control data
Latch
(Internal)
Latest control data
DATA
15A
SOUT
DATA DATA
14A
13A
DATA DATA DATA
1A
0A
15B
DATA
7B
DATA
6B
DATA DATA
0B
7C
BLANK
OFF
OUTn
OUTn+1
OUTn
(1)
OFF
ON
ON
(1)
OFF
OFF
ON
ON
(2)
OFF
ON
ON
OFF
OUTn
(3)
OFF
OFF
ON
OUTn
(4)
ON
OFF
OFF
OFF
ON
(1)
If the on/off latched data is changed from “0” to “1” at 1’st LAT signal, changed from “1” to “0” at 2’nd LAT signal.
(2)
If the on/off latched data is changed from “0” to “1” at 1’st LAT signal, changed from “1” to “1” at 2’nd LAT signal.
(3)
If the on/off latched data is changed from “1” to “0” at 1’st LAT signal, changed from “0” to “1” at 2’nd LAT signal.
(4)
If the on/off latched data is “0”.
Figure 12. On-Off Control Data Write Timing (BLANK Mode = 0)
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Timing Diagrams (continued)
SIN
DATA DATA DATA DATA DATA DATA
13B
12B 11B
0A
14B
15B
DATA DATA DATA
3B
1B
2B
DATA DATA DATA DATA DATA DATA
15C
14C 13C 12C 11C 10C
DATA
0B
SCLK
1
2
3
4
5
13
14
15
1
16
2
3
4
5
6
tH2
LAT
Shift register
LSB Data DATA
(Internal) 0A
SID
0A
Shift register
LSB +1 Data DATA
(Internal) 1A
SID
1A
Shift register
MSB -1 Data DATA
(Internal) 15A
SID
15A
Shift register
MSB Data
(Internal)
DATA
16A
DATA DATA DATA DATA
16B 15B
14B
13B
1
DATA DATA DATA
3B
1B
2B
DATA
0B
DATA DATA DATA DATA DATA
14C
13C 12C
16C 15C
0
SID
0A
DATA DATA DATA
14B
16B
15B
1
DATA DATA DATA
4B
2B
3B
DATA
1B
DATA DATA DATA DATA DATA
0B
16C
15C
14C 13C
0
SID
14A
DATA DATA DATA
13A
12A
11A
SID
15A
SID
14A
SID
13A
SID
12A
SID
1A
SID
0A
DATA
16B
1
DATA
15B
DATA DATA DATA DATA DATA
14B 13B
12B
11B
10B
SID
2A
SID
1A
SID
0A
DATA
16B
DATA DATA DATA DATA DATA
15B 14B
13B
12B 11B
0
1
Output Oo-off
data
(Internal)
DATA15A-0A
DATA15A-0A
Function control
Latch Data
(Internal)
SOUT
Old function control data
DATA
16A
Low
SID
15A
SID
14A
SID
13A
SID
12A
SID
2A
SID
1A
SID
0A
DATA15B-0B
DATA
16B
High
DATA DATA DATA DATA DATA
14B
13B
12B
11B
15B
Figure 13. Function Control Data Write Timing
20
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SLVSA96A – SEPTEMBER 2015 – REVISED MARCH 2016
6.8 Typical Characteristics
At TA = 25°C, unless otherwise noted.
100
60
66.0
50
Output Current (mA)
RIREF (kΩ)
33.0
13.2
10
6.60
4.40
3.30
2.64
2.20
1.89
1.65
0
10
20
30
IOLCMax = 30 mA
30
IOLCMax = 20 mA
20
IOLCMax = 2 mA
10
1.47
1.32
1
IOLCMax = 40 mA
40
40
IOLCMax = 5 mA
0
50
0.5
0
1.0
IOLCMax (V)
Figure 14. Reference Resistor vs Output Current
2.5
3.0
BC = 7Fh
VOUTn = 0.8 V
Figure 15. OUTn Current vs Output Voltage
46
60
45
50
44
Output Current (mA)
Output Current (mA)
2.0
1.5
Output Voltage (V)
VCC = 3.3 V
43
42
41
40
TA = -40°C
TA = +25°C
TA = +85°C
39
IOLCMax = 50 mA
IOLCMax = 40 mA
40
IOLCMax = 30 mA
30
IOLCMax = 20 mA
20
IOLCMax = 2 mA
10
38
IOLCMax = 10 mA
IOLCMax = 1 mA
IOLCMax = 5 mA
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0.5
0
Output Voltage (V)
VCC = 3.3 V
VOUTn = 0.8 V
BC = 7Fh
1.0
2.0
1.5
2.5
3.0
Output Voltage (V)
RIREF = 1.58 kΩ
VCC = 5 V
50 mA = 1 V
Figure 16. OUTn Current vs Output Voltage
BC = 7Fh
VOUTn = 0.8 V
Figure 17. OUTn Current vs Output Voltage
56
3
55
2
54
1
53
ΔIOLC (%)
Output Current (mA)
IOLCMax = 10 mA
IOLCMax = 1 mA
52
51
0
-1
50
TA = -40°C
TA = +25°C
TA = +85°C
49
48
0
0.5
1.0
1.5
2.0
2.5
3.0
-2
VCC = 3.3 V
VCC = 5 V
-3
0
10
Output Voltage (V)
VCC = 5 V
VOUTn = 1 V
BC = 7Fh
20
30
40
50
Output Current (mA)
RIREF = 1.28 kΩ
Figure 18. OUTn Current vs Output Voltage
BC = 7Fh
VOUTn = 0.8 V
50 mA = 1 V
Figure 19. Constant-Current Error
vs Output CurrenT set by RIREF or BC Data (Channel-toChannel)
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Typical Characteristics (continued)
At TA = 25°C, unless otherwise noted.
60
2
50
Output Current (mA)
3
ΔIOLC (%)
1
0
-1
-2
-40
-20
0
20
40
60
80
IO = 2 mA
IO = 5 mA
40
IO = 10 mA
IO = 20 mA
30
IO = 40 mA
20
IO = 50 mA
10
VCC = 3.3 V
VCC = 5 V
-3
VCC = 3.3 V
VCC = 5 V
0
100
0
16
32
48
Temperature (°C)
RIREF = 1.28 kΩ
80
112
96
128
VOUTn = 0.8 V
Figure 20. Constant-Current Error
vs Ambient Temperature (Channel-to-Channel)
Figure 21. Global Brightness
Control Linearity
16
14
14
12
12
10
10
ICC (mA)
ICC (mA)
64
BC Data (Decimal)
8
8
6
6
4
4
VCC = 3.3 V
VCC = 5 V
2
0
10
0
20
40
30
50
2
VCC = 3.3 V
VCC = 5 V
0
-40
-20
Output Current (mA)
BC = 7Fh
SCLK = 35 MHz
0
20
40
60
80
100
Ambient Temperature (°C)
RIREF = 1.6 kΩ
All Outpts on
SIN = 17.5 MHz
BC = 7Fh
SCLK = 35 MHz
Figure 22. Supply Current
vs Output Current Set by RIREF
RIREF = 1.6 kΩ
All Outpts on
SIN = 17.5 MHz
Figure 23. Supply Current
vs Ambient Temperature
30
CH1 (5 V/div)
CH1-BLANK
CH2 (2 V/div)
25
I CC ( µ A)
20
CH3 (2 V/div)
CH3-OUT1
15
CH4-OUT15
CH4 (2 V/div)
10
5
VCC = 3.3 V
VCC = 5 V
0
-40
-20
0
20
40
60
80
BC = 7Fh
Power-Save Mode
RIREF = 1.6 kΩ
Time (20 ns/div)
100
Ambient Temperature (°C)
SIN = SCLK = Low
VCC = 3.3 V
VLED = 5 V
Figure 24. Supply Current in Power-Save Mode
vs Ambient Temperature
22
CH2-OUT0
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BC = 7Fh
RL = 100 Ω
RIREF = 1.6 kΩ
CL = 15 pF
Figure 25. Constant-Current Output
Voltage Waveform
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7 Parameter Measurement Information
RL
VCC
VCC
OUTn
IREF
RIREF
CL
GND
VLED
(1)
(1) CL includes measurement probe and jig capacitance.
Figure 26. Rise Time and Fall Time Test Circuit for OUTn
VCC
SOUT
VCC
CL
GND
(1)
(1) CL includes measurement probe and jig capacitance.
Figure 27. Rise Time and Fall Time Test Circuit for SOUT
VCC
OUT0
¼
VCC
IREF
¼
RIREF
OUTn
GND OUT15
VOUTfix
VOUTn
Figure 28. Constant-Current Test Circuit for OUTn
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8 Detailed Description
8.1 Overview
The TLC59291 is a 8/16-channel constant current sink LED driver. Each channel can be turned on-off by writing
data to an internal register. The constant current value of all 16 channels is set by a single external resistor and
128 steps for the global brightness control (BC).
The TLC59291 has six type error flags: LED open detection (LOD), LED short detection (LSD), output leak
detection (OLD), reference terminal short detection (ISF), Pre thermal warning (PTW) and thermal error flag
(TEF). In addition, the LOD and LSD functions have invisible detection mode (IDM) that can detect those errors
even when the output is off. The error detection results can be read via a serial interface port.
8.2 Functional Block Diagram
VCC
VCC
UVLO
16 bit LOD or 16 bit LSD data or 16 bit OLD data
RESET
LSB
MSB
SIN
0
SCLK
Bit 7/15
Select
LOAD
SELECT
Common shift register
SOUT
15
2
16
LSB
MSB
All off
Output On-Off data Latch
0
16
15
16
LSB
MSB
16
Control data latch
(Global brightness control, LSD voltage select,
loaded error select, other function control)
LAT
0
3
1
Blank
Mode
4
15
2
ERROR
SELECT
1
BLANK
To all
analog
circuit
Power
save
control
2
7
OSC
IDM timing
control
Temp
Error
Status
BC
138C
16
2
SID
Holder
On-Off control with output delay
Reference
current
control
IREF
ISF
16
16channels constant current sink driver
with 7bit global brightness control
Detection
Voltage
16
ERROR
SELECT
VLSD
SELECT
GND
ISF
RESET
165C
Thermal
Detector
SID
Selector
2
LED Open Detection (LOD) / LED Short Detection (LSD)
/Output Leak Detection (OLD)
GND
OUT0
24
OUT1 OUT2
OUT13 OUT14 OUT15
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8.3 Feature Description
8.3.1 Maximum Constant Sink Current
The maximum output current of each channel (IO(LCmax)) is programmed by a single resistor (RIREF) that is placed
between the IREF and GND pins. The current value can be calculated by Equation 1:
RIREF (KW) =
VIREF (V)
x 54.8
IO(CL max) (mA)
Where:
VIREF = the internal reference voltage on IREF (typically 1.205 V when the global brightness control
data are at maximum.
IO(LCmax) = 1 mA to 40 mA ( VCC ≤ 3.6 V), or 1 mA to 50 mA (VCC > 3.6 V) at OUT0 to OUT15 (BC =
7Fh)
(1)
IO(LCmax) is the highest current for each output. Each output sinks IO(LCmax) current when it is turned on with the
maximum global brightness control (BC) data. Each output sink current can be reduced by lowering the global
brightness control value. RIREF must be between 1.32 kΩ and 66 kΩ to hold IO(LCmax) between 50 mA (typical) and
1 mA (typical). Otherwise, the output may be unstable. Output currents lower than 1 mA can be achieved by
setting IO(LCmax) to 1 mA or higher and then using the global brightness control to lower the output current.
Figure 14 and Table 1 show the characteristics of the constant-current sink versus the external resistor, RIREF.
Table 1. Maximum Constant Current Output versus
External Resistor Value
IO(LCmax) (mA)
RIREF (kΩ, typ)
50 (VCC > 3.6 V only)
1.32
45 (VCC > 3.6 V only)
1.47
40
1.65
35
1.89
30
2.20
25
2.64
20
3.30
15
4.40
10
6.60
5
13.2
2
33
1
66
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8.3.2 Global Brightness Control (BC) Function
The TLC59291 has the ability to adjust the output current of all constant current outputs simultaneously. This
function is called global brightness control (BC). The global BC for all outputs (OUT0 to OUT15) can be set with
a 7-bit word. The global BC adjusts all output currents in 128 steps from 0% to 100%. where 100% corresponds
to the maximum output current set by RIREF. Equation 2 calculates the actual output current. BC data can be set
via the serial interface.
IO(LCn) (mA) =
IO(LCmax) (mA) x BC
127d
Where:
IO(LCmax) = the maximum constant-current value for each output determined by RIREF.
BC = the global brightness control value in the control data latch (0h to 127d)
(2)
Table 2 shows the BC data versus the constant-current ratio against IO(LCmax).
Table 2. BC Data versus Constant-Current Ratio Against IO(LCmax)
BC DATA
RATIO OF OUTPUT
CURRENT TO IO(LCmax)
(%)
IO(LC)
(mA, IO(LCmax)= 40mA,
typ)
IO(LC)
(mA, IO(LCmax)= 1mA, typ)
BINARY
DECIMAL
HEX
000 0000
0
00
0
0
0
000 0001
1
01
0.8
0.31
0.01
000 0010
2
02
1.6
0.63
0.02
∙∙∙
∙∙∙
∙∙∙
∙∙∙
∙∙∙
∙∙∙
111 1101
125
7D
98.4
39.4
0.98
111 1110
126
7E
99.2
39.7
0.99
111 1111
127
7F
100.0
40.0
1.00
8.3.3 Thermal Shutdown (TSD) and Thermal Error Flag (TEF)
The thermal shutdown (TSD) function turns off all constant-current outputs when the junction temperature (TJ)
exceeds the threshold (TTEF = 165°C, typical) and sets all LOD data bit to ‘1’. When the junction temperature
drops below (TTEF – THYST), the output control starts. The TEF is remains ‘1’ until LAT is input even if low
temperature. Figure 6 shows a timing diagram and Table 3 shows a truth table for TEF.
8.3.4 Pre-Thermal Warning (PTW)
The PTW function indicates that the IC junction temperature is high. The PTW is set and all LSD data bit are set
to “1” while the IC junction temperature exceeds the temperature threshold (TPTW = 138 °C, typical). Then OUTn
are not forced off. When the PTW is set, the IC temperature should be reduced by lowering the power dissipated
in the driver to avoid a forced shutdown by the thermal shutdown circuit. This reduction can be accomplished by
lowering the values of the BC data. When the IC junction temperature decreases below the temperature of TPTW,
PTW is reset. Figure 6 shows a timing diagram and Table 3 shows a truth table for PTW.
26
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8.3.5 Current Reference Terminal – IREF Terminal - Short Flag (ISF)
The ISF function indicates that IREF terminal is short to GND with low impedance. When IREF is set, all OLD
data bit is set to “1”. Then all outputs (OUTn) are forced off and remain off until the short is removed. Table 3
shows the truth table for ISF.
Table 3. TEF/PTW/ISF Truth Table
TEF
PTW
ISF
CORRESPONDING DATA BITS
IN SID
Device temperature is lower than
high-side detect temperature
(temperature ≤ TTEF)
Device temperature is lower than
pre-thermal warning temperature
(temperature ≤ TPTW)
IREF terminal is not shorted
Depends on LOD/LSD/OLD
Device temperature is higher
than high-side detect
temperature and all outputs are
forced off (temperature >TTEF)
Device temperature is higher
than pre-thermal warning
temperature
(temperature > TPTW)
IREF terminal is shorted to GND
with low impedance and all
outputs (OUT0 to OUT15) are
forced off
SID is all 1s for TEF when SIDLD
bit = '01'. SID is all 1s for PTW
when SIDLD = '10'. SID is all 1s
for ISF when SIDLD = '11'.
8.3.6 Noise Reduction
Large surge currents may flow through the IC and the board on which the device is mounted if all 16 outputs turn
on simultaneously when BLANK goes low or on-off data changes at LAT rising edge with BLANK low. These
large current surges could induce detrimental noise and electromagnetic interference (EMI) into other circuits.
The TLC59291 turns the outputs on in 2ns series delay for each output to provide a circuit soft-start feature.
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8.4 Device Functional Modes
8.4.1 Blank Mode Selection (BLKMS)
The device has two configuration for BLANK pin, which is decided by BIT[9] in FC register. When BLANK mode
= 1, the device is in ENABLE mode, BLANK pin is worked as OUTPUT enable pin: when BLANK=Low, all
constant current outputs are controlled by the on/off control data in the data latch; when BLANK=High, all OUTx
are forced off.
When BLANK mode = 0, the device is in SOUT mode, BLANK pin is worked as SOUT select pin; when BLANK=
Low, SOUT is connected to the bit7 of the 16-bit shift register, worked as 8 channel device; when BLANK= High,
SOUT is connected to the bit15 of the 16-bit shift register, worked as 16ch device. If device is already in
ENABLE mode and we want to switch to SOUT mode, the new FC data with BIT[9]=0 must be input. Then it
enter SOUT mode.
If device is already in SOUT mode and the user wants to switch to ENABLE mode. First make sure BLANK pin is
high, SOUT is connected with bit15 of common shift register. Then input the new FC data with BIT[9] = 1. The
device enters ENABLE mode
When the IC is powered on, SOUT mode is selected as default value. Refer to table 7 for detail.
8.4.2 Power-Save Mode
In this mode, the device dissipation current becomes 30 µA (typical). When “PSMODE” bit is ‘1’, the power save
mode is enabled. Then if LAT rising edge is input to write all ‘0’ data into the output on-off data latch or to write
any data into the control data latch when the on-off data latch are all ‘0’, TLC5929 goes into the power save
mode. When SCLK rising edge is input, the device returns to normal operation. The power-save mode timing is
shown in Figure 7.
8.4.3 LED Open Detection (LOD)
LOD detects the fault caused by LED open circuit or a short from OUTn to ground by comparing the OUTn
voltage to the LOD detection threshold voltage level (VLOD = 0.3 V typical). If the OUTn voltage is lower than
VLOD, that output LOD bit is set to '1' to indicate an open LED. Otherwise, the LOD bit is set to '0'. LOD data are
only valid for outputs programmed to be on. LOD data for outputs programmed to be off are always '0' (Table
11).
The LOD data are stored into a 16-bit register called SID holder at BLANK rising edge when “SIDLD” bits is set
to ‘01b’ (Table6) or when Invisible Detection Mode (IDM) is enabled, the LOD data are stored to SID holder at
the end timing of IDM working time.
The stored LOD data can be read out through the common shift register as Status Information Data (SID) from
SOUT pin. LOD/LSD data are not valid until 0.5 µs after the falling edge of BLANK.
8.4.4 LED Short Detection (LSD)
LSD data detects the fault caused by a shorted LED by comparing the OUTn voltage to the LSD detection If the
OUTn voltage is higher than the programmed voltage, that output LSD bit is set to '1' to indicate a shorted LED.
Otherwise, the LSD bit is set to'0'. LSD data are only valid for outputs programmed to be on. LSD data for
outputs programmed to be off are always '0' (Table 4).
The LSD data are stored into a 16-bit register called SID holder at BLANK rising edge when “SIDLD” bits is set to
‘10b’ (Table6) or when Invisible Detection Mode (IDM) is enabled, the LSD data are stored to SID holder at the
end timing of IDM working time. The stored LSD data can be read out through the common shift register as
Status Information Data (SID) from SOUT pin. LOD/LSD data are not stabled until 0.5 µs after the falling edge of
BLANK. Therefore, BLANK must be low for at least that time.
The LSD need to be executed after propagation delay, “td4” or more from the device operation resumed from the
power save mode because LOD does not work during the power save mode.
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Device Functional Modes (continued)
8.4.5 Invisible Detection Mode (IDM)
Invisible Detection Mode (IDM) is the mode which can detect LOD and LSD when output on-off data is set to off
state. When “IDMCUR” bit in the control data latch are set any data except “00b”, OUTn start to sink the current
set by the “IDMCUR” bit at BLANK falling edge and OUTn stop to sink the current at BLANK rising signal or the
time set by “IDMTIM” has passed. When OUTn is stopped, the selected SID data by “SIDLD” bit are latched to
into SID holder.
When IDM mode is enabled, OLD is always set to disable. When “IDMCUR” bit in the control data latch is set
“00b”, OUTn doesn’t start to sink the current set. Figure 29 shows LOD/LSD/OLD/IDM circuit. Figure 8 shows
IDM operation timing and Table 5 shows a truth table for LOD/LSD/OLD.
IDM can only be working when FC[9] = 1.
8.4.6 Output Leakage Detection (OLD)
Output leak detection (OLD) detects a fault caused by OUTn is short to GND with high resistance by comparing
the OUTn voltage to the LSD detection threshold voltage when output on-off data is set to off state. Also OLD
can detect the short between adjacent pins. Small current is sourced from OUTn turned off to LED to detect LED
leaking when “SIDLD” bit are ‘11b’ and BLANK is low. OLD operation is disabled when SIDLD bit are set any
data except “11b” and then the sourced current is stopped. Also OLD is disabled when Invisible Detection Mode
(IDM) is enabled. If the OUTn voltage is lower than the programmed LSD threshold voltage, that output OLD bit
is set to '1' to indicate a leaking LED. Otherwise, the OLD bit is set to '0'. OLD result is valid for outputs
programmed to off only. The OLD data is latched into SID holder when BLANK goes high. OLD data for outputs
not programmed to off are always '0'. The OLD need to be executed after propagation delay, “td4” or more from
the device operation resumed from the power save mode because OLD does not work during the power save
mode.
VCC
OLD
Control
LSD/OLD Data
‘1’ = Error
VLED
2 mA (typ)
LED Lamp
OUTn
On/Off
Control
VLSD
Up to
50 mA
IDM
Control
2 mA/10 mA/20 mA
(typ)
LOD Data
‘1’ = Error
GND
VLOD
Figure 29. LOD/LSD/OLD/IDM Circuit
8.4.7 Status Information Data (SID)
The status information data (SID) contains the status of the LED Open Detection (LOD), LED Short Detection
(LSD), Output Leakage Detection (OLD), Pre-Thermal Warning (PTW), Thermal Shutdown (TSD) and Thermal
Error Flag (TEF) and Current Reference Terminal – IREF Terminal - Short Flag (ISF). The loaded SID data can
be selected by “SIDLD” bits in the control data latch. When the MSB of the common shift register is set to '0', the
selected SID overwrites lower 16-bit data in the common shift register data at the rising edge of LAT after the
data in the common shift register are copied to the output on-off data latch. If the common shift register MSB is
'1', the selected SID does not overwrite the 16-bit data in the common shift register
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Device Functional Modes (continued)
After being copied into the common shift register, new SID data are not available until new data are written into
the common shift register. If new data are not written, the LAT signal is ignored. To recheck SID without
changing the on-off control data, reprogram the common shift register with the same data currently programmed
into the on-off data latch. When LAT goes high, the output on-off data is not changed, but new SID data are
loaded into the common shift register. LOD, LSD, OLD, PTW, TEF, ISF are shifted out of SOUT with each rising
edge of SCLK. The SID need to be read out after td4 or more from the device operation resumed from the power
save mode.
The SID reading must be delayed for a duration of tD4 or more after the device resumes operation from the
power-save mode because SID does not indicate correct data during the power-save mode. The SID load
configuration and SID read timing are shown in Figure 10 and Figure 30, respectively.
Selected SID (16 bits) by SIDLD Data in the Control Data Latch
MSB
LSB
Selected Selected Selected Selected Selected
SID for SID for SID for SID for SID for
OUT0
OUT1
OUT2
OUT3
OUT4
Selected Selected Selected Selected Selected
SID for SID for SID for SID for SID for
OUT15 OUT14 OUT13 OUT12 OUT11
15
14
13
12
11
4
3
2
1
0
SID are loaded to the
common shift register
at the rising edge of
LAT when the common
shift register MSB is 0.
No data are loaded
into the MSB of the
common shift register
MSB = ‘0’
SOUT
Latch
Select
Bit
16
LSB
Common Common Common Common Common
Data Bit Data Bit Data Bit Data Bit Data Bit
0
1
2
3
4
Common Common Common Common Common
Data Bit Data Bit Data Bit Data Bit Data Bit
11
12
13
14
15
15
14
13
12
11
4
3
2
1
SIN
SLCK
0
Common Shift Register (17 Bits)
Figure 30. SID Load Configuration
Table 4. SID Load Assignment
SIDLD
1/0 BIT
SELECTED
DETECTOR
00b
No detector selected
01b
10b
11b
30
CHECKED OUTn
BIT NUMBER
LOADED INTO
COMMON SHIFT
REGISTER
—
No data loaded
OUT0
0
OUT1
1
∙∙∙
∙∙∙
OUT14
14
OUT15
15
OUT0
0
OUT1
1
LED open detection
(LOD)
LED short detection
(LSD)
∙∙∙
∙∙∙
OUT14
14
OUT15
15
OUT0
0
OUT1
1
Output leakage
detection (OLD)
∙∙∙
∙∙∙
OUT14
14
OUT15
15
DESCRIPTION
The data in the common shift register are not changed.
The data in the common shift register are updated with LOD or TEF data.
All bits '1' = device junction temperature (TJ) is high (TJ > TTEF) and all
outputs are forced off by the thermal shutdown function.'1 = OUTn shows
lower voltage than the LED open detection threshold (VLOD).
0 = normal operation.
The data in the common shift register are updated with LSD or PTW data.
All bits '1' = device junction temperature (TJ) is high (TJ > TPTW).
1 = OUTn shows higher voltage than the LED short detection threshold
(VLSD) selected by LSDVLT.
0 = normal operation.
The data in the common shift register are updated with OLD or ISF data.
All bits '1' = IREF pin is shorted to GND with low impedance.
1 = OUTn is leaking to GND with greater than 3µA.
0 = normal operation.
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Table 5. LOD/LSD/OLD Truth Table
LOD
LSD
OLD
CORRESPONDING BIT IN SID
LED is not opened
(VOUTn > VLOD)
LED is not shorted (VOUTn ≤ VLSD)
OUTn does not leak to GND (VOUTn >
VLSD when constant-current output off
and OUTn source current on)
0
LED is open or shorted to GND
(VOUTn ≤ VLOD)
LED is shorted between anode and
cathode, or shorted to higher voltage
side (VOUTn > VLSD)
Current leaks from OUTn to internal
GND, or OUTn is shorted to external
GND with high impedance (VOUTn ≤
VLSD when constant-current output off
and OUTn source current on)
1
8.5 Register Maps
8.5.1 Register and Data Latch Configuration
The TLC59291 has one common shift register and two control data latch. The common shift register is 16-bits in
length and two control data latch is 16-bits length. When SCLK is '0' at LAT rising edge, the 16-bits common shift
register are copied into the output on-off data latch. Also when SCLK is '1' at LAT rising edge the 16-bits data are
copied into the control data latch. Figure 31 shows the common shift register and two control data latches
configuration.
SID 16 bit
Common shift register (16 bits)
LSB
MSB
SOUT
Common Common Common
Data bit
Data bit Data bit
15
14
13
15
14
13
Common Common Common Common Common
Data bit
Data bit
Data bit Data bit Data bit
3
4
2
1
0
Common Common
Data bit
Data bit
12
11
12
11
---
4
3
2
1
SIN
SCLK
0
16 bit
Output on - off data latch (16 bits)
MSB
15
14
13
12
11
OUTON
15
OUTON
14
OUTON
13
OUTON
12
OUTON
11
---
LSB
0
4
3
2
1
OUTON
4
OUTON
3
OUTON
2
OUTON
1
OUTON
0
0
The latch pulse
comes from LAT
pin when SCLK
signal = 0.
16 bit
To output on-off control circuit
16 bit
Control data latch (16 bits)
MSB
15
Power
save
enable
1 bit
To power
save mode
control
circuit
14
IDM
working
time 1
13
12
11
10
9
8
IDM
working
time 0
IDM
current
select 1
IDM
current
select 0
LSD
detect
voltage1
LSD
detect
voltage0
SID load
control
1
2 bit
To IDM
working time
control
circuit
2 bit
To IDM
current
control
circuit
2 bit
To LSD
circuit
7
6
SID load Brightness
control
control
(BC) 6
0
2 bit
To SID
data load
control
circuit
LSB
0
---
Brightness
control
(BC) 0
The latch pulse
comes from LAT
pin when SCLK
signal = 1.
7 bit
To output constant current
control circuit
Figure 31. Common Shift Register and Control Data Latches Configuration
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Register Maps (continued)
8.5.1.1 Common Shift Register
The 16-bit common shift register is used to shift data from the SIN pin into the TLC59291. The data shifted into
the register are used for the data writing for output on-off control, global brightness control, and some functions
control. The register LSB is connected to SIN. On each SCLK rising edge, the data on SIN are shifted into the
register LSB and all bits are shifted towards the MSB.
SOUT can be connected to either bit 15 or bit 7 of common shift register depending on BLANK signal and control
data setting.
Also Status Information Data (SID) selected by the load select data in the control data latch are loaded to the
common shift register when LAT rising edge is input with SCLK is “0” of the shift register.
When the device powered up, the data in the 16-bit common shift register is set to all “0”.
8.5.1.2 Output On/Off Data Latch
The output on/off data latch is 16 bits long and sets the on or off status for each constant-current output.
When FC[9] = 1 and BLANK is high, all outputs are forced off. But then the data in the latch are not changed. In
other case, the corresponding output is turned on if the data in the output on-off data latch are '1' and remains off
if the data are '0'.
When the IC is initially powered on, the data in the data latch is set to all “0”.
The output on/off data latch configuration is shown in Figure 32 and the data bit assignment is shown in Table 6.
From common shift register
16 bit
Output on-off data latch (16 bits)
MSB
15
14
13
12
11
OUTON
15
OUTON
14
OUTON
13
OUTON
12
OUTON
11
---
4
3
2
1
OUTON
4
OUTON
3
OUTON
2
OUTON
1
LSB
0
OUTON
0
16 bit
To output on off control circuit
Figure 32. Output On/Off Data Latch Configuration
Table 6. On/Off Control Data Latch Bit Assignment
32
BIT NUMBER
BIT NAME
CONTROLLED CHANNEL
0
OUTON0
OUT0
1
OUTON1
OUT1
OUT2
2
OUTON2
∙∙∙
∙∙∙
∙∙∙
13
OUTON13
OUT13
14
OUTON14
OUT14
15
OUTON15
OUT15
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Figure 33. Output On/Off Data Latch
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. Output On/Off Data Latch
Bit
Field
Type
Reset
[15]
OUTON15
R/W
00
[14]
OUTON14
R/W
00
[13]
OUTON13
R/W
00
[12]
OUTON12
R/W
00
[11]
OUTON11
R/W
00
[10]
OUTON10
R/W
00
[9]
OUTON9
R/W
00
[8]
OUTON8
R/W
00
[7]
OUTON7
R/W
00
[6]
OUTON6
R/W
00
[5]
OUTON5
R/W
00
[4]
OUTON4
R/W
00
[3]
OUTON3
R/W
00
[2]
OUTON2
R/W
00
[1]
OUTON1
R/W
00
[0]
OUTON0
R/W
00
Description
When IC is powered up, these all data are set to “0”
0 = output OFF (default)
1 = output ON
8.5.1.3 Control Data Latch
The control data latch is 16-bit in length and contains the Global Brightness Control (BC) Function data, Status
Information Data (SID) load select data, Blank Mode Selection (BLKMS) data, the current value for Invisible
Detection Mode (IDM), IDM working time, and Power-Save Mode enable control data.
When the device is powered up, the data in this data latch are set to the default values shown in Table 8.
The function control data latch configuration is shown in Figure 34.
From common shift register
16 bit
Control data latch (16bits)
MSB
15
Power
save
enable
1 bit
To power
save mode
control
circuit
14
IDM
working
time 1
13
12
11
10
9
8
IDM
working
time 0
IDM
current
select 1
IDM
current
select 0
BLANK
Mode
Select1
BLANK
Mode
Select0
SID load
control
1
2 bit
To IDM
working
time control
circuit
2 bit
To IDM
current
control
circuit
6
SID load Brightness
control
control
(BC) 6
0
2 bit
2 bit
To BLANK
Mode
select
circuit
7
To SID
data load
control
circuit
LSB
0
---
Brightness
control
(BC) 0
7 bit
To output constant current
control circuit
Figure 34. Function Control Data Latch Configuration
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Figure 35. Control Data Latch
15
1
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
1
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. Control Data Latch
Bit
Field
Type
Reset
Description
[15]
PSMODE
R/W
1b
Power save mode enable (Default value = ‘1b’)
The data selects power save mode enable or disable. When the
mode is enabled, the device goes into power save mode if all
data in the on/off data latch are “0”. Table 15 shows the power
save mode truth table. Figure 7 shows the power save mode
operation timing.
[14:13]
IDMTIM
R/W
00b
IDM working time select (Default value = ‘00b’)
The data selects the time of output current sink at OUTn for IDM
to detect LED open detection (LOD) or LSD without visible
lighting. Table 15 shows the work time truth table.Figure 9
shows the IDM operation timing.
[12:11]
IDMCUR
R/W
00b
IDM current select (Default value = ‘00b’)
The data selects the sink current at OUTn for IDM to detect LED
open detection (LOD) or LSD without visible lighting. Table 14
shows the current value truth table. Figure 9 shows the IDM
operation timing.
[10]
LSDVLT
R/W
1b
LSD detection voltage select. (Default value = ‘1b’)
These two bits select the detection threshold voltage for the LED
short detection (LSD). Table 12 shows the detect voltage truth
table.
[9]
BLKMS
R/W
0b
BLANK Mode Select (Default value = ‘0b’)
The data selects the working mode for BLANK pin. Table 11
shows the truth table.
[8:7]
SIDLD
R/W
00b
SID load control (Default value = ‘00b’)
The data selects the SID data loaded to the common register
when LAT pulse is input for on-off data writing. Table 10 shows
the selected data truth table.
[6:0]
BCALL
R/W
1111111b
Global brightness control (Default value = ‘1111111b’)
The 7-bit data controls the current of all output with 128 steps
between 0~100% of the maximum current value set by a
external resistor. Table 13 shows the current value truth table.
8.5.1.4
Output On/Off Data Write Timing and Output Control
When SCLK = “0” at LAT rising edge, the output on-off data can be updated with the 16-bit data in the shift
register after the data are stored to the shift register using SIN and SCLK signals. When the on-off data latch is
updated, SID is loaded into the shift register except SID load control is “00b”. See Figure 11.
When BLANK = SOUT mode, the timing is show in Figure 12.
8.5.1.5 Function Control Data Writing
When SCLK = “1” at LAT rising edge, the control data latch can be updated with the 16-bit data in the shift
register after the data are stored to the shift register using SIN and SCLK signals. When the control data latch is
updated, SID is not loaded into the shift register.
If the device is in SOUT mode (FC[9] = 0) and BLANK = Low, SOUT is connected with BIT 7 of common shift
register. Then FC data can’t be input and not valid. See Figure 13
34
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8.5.1.6 Function Control (FC) Data
The FC data latch is 16 bits long and is used to adjust output current values for LED brightness, select the SID,
BLANK mode select, the output current for IDM, the output on time for IDM, and power-save mode
enable/disable. When the IC is powered on, the control data latch is set to the default value (E67Fh).The control
data latch truth tables are shown in Table 9 through Table 14.
Table 9. Global Brightness Control (BC) Truth Table
BCALL (BIT 6:0)
Brightness Control for all Output with Output Current
0000000
Output current of OUTn is set to IO(LCmax) × 0%
0000001
IO(LCmax) × 0.8%
∙∙∙
∙∙∙
1111110
IO(LCmax) × 99.2%
1111111
IO(LCmax) × 100%
Table 10. SID Load Control Truth Table
SIDLD
SID LOADED TO THE COMMON SHIFT REGISTER
BIT 8
BIT 7
0
0
0
1
LED open detection (LOD) or thermal error flag (TEF) data are loaded
1
0
LED short detection (LSD) or pre-thermal warning (PTW) data are loaded
1
1
Output leakage detection (OLD) or IREF pin short flag (ISF) data are loaded
No data is loaded (default value)
Table 11. BLANK Mode Selection Table
BLKMS (BIT 9)
BLANK MODE SELECTION
0
SOUT mode, BLANK pin worked as SOUT 8/16 select signal (default)
1
Enable mode, BLANK pin worked as OUTPUT enable
Table 12. LSD Threshold Voltage Truth Table
LSDVLT (BIT 10)
LED SHORT DETECTION (LSD) THRESHOLD VOLTAGE
0
VLSD0 (0.35 × VCC typ)
1
VLSD3 (0.65 × VCC typ, default value)
Table 13. Current Select for IDM
IDMCUR
SINK CURRENT AT OUTn FOR INVISIBLE DETECTION MODE (IDM)
BIT 12
BIT 11
0
0
0
1
2 µA (typ)
1
0
10 µA (typ)
1
1
20 µA (typ)
IDM is disabled (default value)
Table 14. IDM Work-Time Truth Table
IDMTIM
INVISIBLE DETECTION MODE (IDM) WORKING TIME
BIT 14
BIT 13
0
0
All outputs are turned on for 17 OSC clocks (0.85 µs typ)
0
1
All outputs are turned on for 33 OSC clocks (1.65 µs typ)
1
0
All outputs are turned on for 65 OSC clocks (3.25 µs typ)
1
1
All outputs are turned on for 129 OSC clocks (6.45 µs tyicalp, default value)
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Table 15. Power-Save Mode Truth Table
PSMODE (BIT 15)
36
POWER-SAVE MODE FUNCTION
0
Power-save mode is disabled.
The device does not go into power-save mode even if the bits in the output on/off data latch
are all '0'.
1
Power save mode is enabled (default value).
The device goes into power-save mode when the bits in the output on/off data latch are all
'0'.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The device is a 8/16-channel, constant sink current, LED driver. This device is typically connected in series to
drive many LED lamps with only a few controller ports. On/Off control data and FC control data can be written
from the SIN input terminal. The device has six type error flags: LED open detection (LOD), LED short detection
(LSD), output leak detection (OLD), reference terminal short detection (ISF), Pre themal warning (PTW) and
thermal error flag (TEF).
9.2 Typical Application
In this application, the device VCC and LED lamp anode voltages are supplied from different power supplies.
VLED
OUT0 - - - - - - - - - - OUT15
DATA
SIN
Controller
SCLK
TLC59291
IC1
LAT
BLANK
SIN
VCC
SCLK
LAT
OUT0 - - - - - - - - - - OUT15
SOUT
SOUT
VCC
SCLK
VCC
LAT
BLANK
TLC59291
ICn
VCC
BLANK
GND
IREF
GND
IREF
RIREF
RIREF
GND
GND
GND
GND
3
SID read
Figure 36. Multiple Daisy-chained TLC59291 Devices
9.2.1 Design Requirements
The parameters for the design example are shown in Table 16.
Table 16. Design Parameters
PARAMETER
VALUE
VCC input voltage range
3 V to 5.5 V
LED lamp (VLED) input voltage range
Maximum LED forward voltage (VF) + 0.3 V (knee voltage)
SIN, SCLK, LAT, and GSCLK voltage range
Low level = GND, High level = VCC
9.2.2 Detailed Design Procedure
To begin the design process, a few parameters must be decided upon. The designer needs to know the
following:
• Maximum output constant-current value for each color LED lamp.
• Maximum LED forward voltage (VF).
• Which error flags are used.
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Ch2 - 2 V/div
Ch2 - 2 V/div
Ch1 - 1 V/div
Ch1 - 1 V/div
9.2.3 Application Curves
Time = 400 ns/div
Time = 400 ns/div
Figure 37. Output Waveform When BLANK_Mode = 0
Figure 38. Output Waveform When BLANK_Mode = 1
10 Power Supply Recommendations
The VCC power supply voltage should be decoupled by placing a 0.1-µF ceramic capacitor close to the VCC pin
and GND plane. Depending on the panel size, several electrolytic capacitors must be placed on the board
equally distributed to get a well regulated LED supply voltage (VLED). The VLED voltage ripple must be less than
5% of it nominal value. Futhremore, the VLED must be set to the voltage calculated by Equation 3.
VLED > VF + 0.4 V (10-mA constant-current example)
(3)
Where
• VF = maximum forward voltage of all LEDs.
38
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11 Layout
11.1 Layout Guidelines
•
•
•
•
•
Place the decoupling capacitor near the VCC pin and GND plane
Place the current programming resistor RIREF close to the IREF pin an the IREFGND pin.
Route the GND pattern as widely as possible for large GND currents.
The routing wire between the LED cathode side and the device OUTXn pin must be as short and straight as
possible to reduce wire inductance.
When several ICs are chained, symmetric placements are recommended.
11.2 Layout Example
Figure 39. Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
40
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLC59291RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TLC
59291
TLC59291RGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TLC
59291
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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