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TLC5941-Q1
SLDS165A – DECEMBER 2008 – REVISED DECEMBER 2014
TLC5941-Q1 16-Channel LED Driver With Dot Correction and Grayscale PWM Control
1 Features
2 Applications
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Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level 2
– Device CDM ESD Classification Level C4B
16 Channels
12-Bit (4096 Steps) Grayscale PWM Control
Dot Correction: 6 Bit (64 Steps)
Drive Capability (Constant-Current Sink):
0 mA to 60 mA
LED Power Supply Voltage up to 17 V
VCC = 3.0 V to 5.5 V
Serial Data Interface
Controlled In-Rush Current
30-MHz Data Transfer Rate
CMOS Level I/O
Error Information
– LOD: LED Open Detection
– TEF: Thermal Error Flag
Monocolor, Multicolor, Full-Color LED Displays
LED Signboards
Display Back-Lighting
3 Description
The TLC5941-Q1 device is a 16-channel, constantcurrent sink, LED driver. Each channel has an
individually adjustable 4096-step grayscale PWM
brightness control and a 64-step constant-current sink
(dot correction), which both are accessible via a serial
interface. This device features two fault diagnostic
circuits. The LED open detection (LOD) indicates a
broken or disconnected LED at an output terminal.
The thermal error flag (TEF) indicates an over
temperature condition.
The TLC5941-Q1 features two error information
circuits. The LED open detection (LOD) indicates a
broken or disconnected LED at an output terminal.
The thermal error flag (TEF) indicates an
overtemperature condition.
Device Information(1)
PART NUMBER
TLC5941-Q1
PACKAGE
HTSSOP (28)
BODY SIZE (NOM)
9.70 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Functional Block Diagram
VCC
GND
SCLK
XLAT
SIN
CNT
MODE
1 0
IREF
Max. OUTn
Current
V REF
=1.24 V
GS Register
MODE
1 0
11
0
GSCLK
BLANK
0
DC Register
5
GS Counter
0
Status
Information:
LOD,
TED,
DC DATA
191
0
CNT
96
12−Bit Grayscale
PWM Control
Constant-Current
Driver
OUT0
Delay
x0
6−Bit Dot Correction
LED Open Detection
Input
Shift
Register
CNT
192
192
GS Register
23
96
95
1 0
96
12
DC Register
11
12−Bit Grayscale
PWM Control
Constant-Current
Driver
OUT1
Delay
x1
6−Bit Dot Correction
6
MODE
LED Open Detection
96
Temperature
Error Flag
(TEF)
LED Open
Detection
(LOD)
CNT
Input
Shift
Register
GS Register
191
XERR
180
DC Register
95
12−Bit Grayscale
PWM Control
Constant-Current
Driver
OUT15
Delay
x15
6−Bit Dot Correction
90
191
LED Open Detection
SOUT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLC5941-Q1
SLDS165A – DECEMBER 2008 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
7.1 Pin Equivalent Input and Output Schematic
Diagrams.................................................................... 9
7.2 Test Parameter Equations ...................................... 10
8
Detailed Description ............................................ 11
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
17
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application ................................................. 18
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................ 22
11.2 Layout Example .................................................... 23
12 Device and Documentation Support ................. 23
12.1 Trademarks ........................................................... 23
12.2 Electrostatic Discharge Caution ............................ 23
12.3 Glossary ................................................................ 23
13 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
Changes from Original (December 2008) to Revision A
•
2
Page
Added the ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 4
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SLDS165A – DECEMBER 2008 – REVISED DECEMBER 2014
5 Pin Configuration and Functions
PWP Package
28-Pin HSSOP With Thermal Pad
Top View
GND
1
28
VCC
BLANK
2
27
IREF
XLAT
3
26
TEST
SCLK
4
25
GSCLK
SIN
5
24
SOUT
MODE
6
23
XERR
OUT0
7
22
OUT15
OUT1
8
21
OUT14
OUT2
9
20
OUT13
OUT3
10
19
OUT12
OUT4
11
18
OUT11
OUT5
12
17
OUT10
OUT6
13
16
OUT9
OUT7
14
15
OUT8
Thermal
Pad
Pin Functions
PIN
I/O
DESCRIPTION
2
I
Blank all outputs. When BLANK = H, all OUTn outputs are forced OFF. GS counter is also reset. When BLANK = L, OUTn
are controlled by grayscale PWM control. This pin should be pull up to high before micro-controller or digital signal processor
sending control signal to device. A pull-up resistor to VCC is needed.
GND
1
G
Ground
GSCLK
25
I
Reference clock for grayscale PWM control
IREF
27
I/O
MODE
6
I
Input mode-change pin. When MODE = GND, the device is in GS mode. When MODE = VCC, the device is in DC mode.
OUT0
7
O
Constant-current output
OUT1
8
O
Constant-current output
OUT2
9
O
Constant-current output
OUT3
10
O
Constant-current output
OUT4
11
O
Constant-current output
OUT5
12
O
Constant-current output
OUT6
13
O
Constant-current output
OUT7
14
O
Constant-current output
OUT8
15
O
Constant-current output
OUT9
16
O
Constant-current output
OUT10
17
O
Constant-current output
OUT11
18
O
Constant-current output
OUT12
19
O
Constant-current output
OUT13
20
O
Constant-current output
OUT14
21
O
Constant-current output
OUT15
22
O
Constant-current output
SCLK
4
I
Serial data shift clock
NAME
NO.
BLANK
Reference current terminal
SIN
5
I
Serial data input
SOUT
24
O
Serial data output
TEST
26
I
Test. Must be connected to VCC.
VCC
28
I
Power supply voltage. This pin should be powered up before micro-controller or digital signal processor sending control
signal to device.
XERR
23
O
Error output. Open-drain. Goes L when LOD or TEF is detected.
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Pin Functions (continued)
PIN
NAME
NO.
XLAT
3
I/O
DESCRIPTION
I
Level triggered latch signal. When XLAT = high, the TLC5941-Q1 writes data from the input shift register to either GS register
(MODE = low) or DC register (MODE = high). When XLAT = low, the data in the GS or DC registers is held constant and
does not change.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Input voltage, VI (2)
Output voltage, VO
MIN
MAX
VCC
–0.3
6
V(BLANK), V(SCLK), V(XLAT), V(MODE), V(SIN), V(GSCLK), V(IREF), V(TEST)
–0.3
VCC + 0.3
V(SOUT), V(XERR)
–0.3
VCC + 0.3
V(OUT0) to V(OUT15)
–0.3
18
Output current (DC), IO
90
Operating junction temperature, TJ(max)
150
Storage temperature, Tstg
(1)
(2)
–55
UNIT
V
V
mA
°C
150
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
Human body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic discharge
Charged device model (CDM), per
AEC Q100-011
UNIT
±2000
Corner pins (1, 14, 15, and 28)
±750
Other pins
±500
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
MIN
MAX
UNIT
3
5.5
V
DC CHARACTERISTICS
VCC
Supply voltage
VO
Voltage applied to output (OUT0–OUT15)
17
V
VIH
High-level input voltage
0.8 VCC
VCC
V
VIL
Low-level input voltage
GND
0.2 VCC
IOH
High-level output current
VCC = 5 V at SOUT
IOL
Low-level output current
VCC = 5 V at SOUT, XERR
IOLC
Constant output current
OUT0 to OUT15
TJ
Operating junction temperature
–40
V
–1
mA
1
mA
60
mA
125
°C
AC CHARACTERISTICS
f(SCLK)
Data shift clock frequency
SCLK
30
MHz
f(GSCLK)
Grayscale clock frequency
GSCLK
30
MHz
twh0/twl0
SCLK pulse duration
SCLK = H/L (see Figure 12)
16
ns
twh1/twl1
GSCLK pulse duration
GSCLK = H/L (see Figure 12)
16
ns
twh2
XLAT pulse duration
XLAT = H (see Figure 12)
20
ns
twh3
BLANK pulse duration
BLANK = H (see Figure 12)
20
ns
tsu0
Setup time
SIN to SCLK↑ (see Figure 12)
5
ns
tsu1
Setup time
SCLK↓ to XLAT↑ (see Figure 12)
10
ns
4
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Recommended Operating Conditions (continued)
MIN
MAX
UNIT
tsu2
Setup time
MODE↑↓ to SCLK↑ (see Figure 12)
10
ns
tsu3
Setup time
MODE↑↓ to XLAT↑ (see Figure 12)
10
ns
tsu4
Setup time
BLANK↓ to GSCLK↑ (see Figure 12)
10
ns
tsu5
Setup time
XLAT↑ to GSCLK↑ (see Figure 12)
30
ns
th0
Hold time
SCLK↑ to SIN (see Figure 12)
3
ns
th1
Hold time
XLAT↓ to SCLK↑ (see Figure 12)
10
ns
th2
Hold time
SCLK↑ to MODE↑↓ (see Figure 12)
10
ns
th3
Hold time
XLAT↓ to MODE↑↓ (see Figure 12)
10
ns
th4
Hold time
GSCLK↑ to BLANK↑ (see Figure 12)
10
ns
6.4 Thermal Information
TLC5941-Q1
THERMAL METRIC
(1)
PWP
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance (2) (3)
36.7
RθJC(top)
Junction-to-case (top) thermal resistance
18.9
RθJB
Junction-to-board thermal resistance
15.9
ψJT
Junction-to-top characterization parameter
0.6
ψJB
Junction-to-board characterization parameter
15.8
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.3
(1)
(2)
(3)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The package thermal impedance is calculated in accordance with JESD 51-7.
With PowerPAD soldered on PCB with 2-oz trace of copper. For further information see the TI application report, PowerPAD™
Thermally Enhanced Package, SLMA002.
6.5 Electrical Characteristics
VCC = 3 V to 5.5 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = –1 mA, SOUT
VOL
Low-level output voltage
IOL = 1 mA, SOUT
II
Input current
MIN
TYP
VCC – 0.5
Supply current
IO(LC)
Ilkg
ΔIO(LC0)
VI = VCC or GND,
BLANK, TEST, GSCLK, SCLK, SIN, XLAT
–1
1
VI = GND, MODE pin
–1
1
(1)
V
μA
50
No data transfer, all output OFF, VO = 1 V,
R(IREF) = 10 kΩ
0.9
6
No data transfer, all output OFF, VO = 1 V,
R(IREF) = 1.3 kΩ
5.2
12
Data transfer 30 MHz, all output ON, VO = 1 V,
R(IREF) = 1.3 kΩ
16
25
Data transfer 30 MHz, all output ON, VO = 1 V,
R(IREF) = 640 Ω
30
60
61
69
mA
0.1
μA
Constant output current
All output ON, VO = 1 V, R(IREF) = 640 Ω
Leakage output current
All output OFF, VO = 15 V, R(IREF) = 640 Ω,
OUT0 to OUT15
Constant sink current error
UNIT
V
0.5
VI = VCC, MODE pin
ICC
MAX
mA
54
All output ON, VO = 1 V, R(IREF) = 640 Ω,
OUT0 to OUT15, TA = –20°C to 85°C (1)
±1%
±4%
All output ON, VO = 1 V, R(IREF) = 640 Ω,
OUT0 to OUT15 (1)
±1%
±8%
The deviation of each output from the average of OUT0-15 constant current. It is calculated by Equation 1 in Test Parameter Equations.
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Electrical Characteristics (continued)
VCC = 3 V to 5.5 V, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.4%
±4%
UNIT
ΔIO(LC1)
Constant sink current error
Device to device, averaged current from
OUT0 to OUT15,R(IREF) = 1920 Ω (20 mA) (2)
ΔIO(LC2)
Line regulation
All output ON, VO = 1 V, R(IREF) = 640 Ω,
OUT0 to OUT15, VCC = 3 V to 5.5 V (3)
±1
±4
%/V
ΔIO(LC3)
Load regulation
All output ON, VO = 1 V to 3 V, R(IREF) = 640 Ω,
OUT0 to OUT15 (4)
±2
±6
%/V
170
°C
0.3
0.4
V
1.25
1.29
V
T(TEF)
Thermal error flag threshold
V(LED)
LED open detection threshold
V(IREF)
Reference voltage output
(2)
(3)
(4)
(5)
Junction temperature
(5)
150
RI(REF) = 640 Ω
1.20
The deviation of average of OUT0–OUT15 constant current from the ideal constant-current value. It is calculated by Equation 2 in Test
Parameter Equations. The ideal current is calculated by Equation 3 in Test Parameter Equations.
The line regulation is calculated by Equation 4 in Test Parameter Equations.
The load regulation is calculated by Equation 5 in Test Parameter Equations.
Not tested. Specified by design.
6.6 Switching Characteristics
VCC = 3 V to 5.5 V, CL = 15 pF, TJ = –40°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tr0
Rise time
SOUT
tr1
Rise time
OUTn, VCC = 5 V, TA = 60°C, DCn = 3Fh
tf0
Fall time
SOUT
tf1
Fall time
OUTn, VCC = 5 V, TA = 60°C, DCn = 3Fh
tpd0
Propagation delay time
tpd1
MIN
TYP
MAX
UNIT
16
ns
30
ns
16
ns
30
ns
SCLK to SOUT (see Figure 12)
30
ns
Propagation delay time
BLANK to OUT0 (see Figure 12)
60
ns
tpd2
Propagation delay time
OUTn to XERR (see Figure 12)
1000
ns
tpd3
Propagation delay time
GSCLK to OUT0 (see Figure 12)
60
ns
tpd4
Propagation delay time
XLAT to IOUT (dot correction) (see Figure 12)
1000
ns
td
Output delay time
OUTn to OUT(n+1) (see Figure 12)
20
30
ns
ton_err
Output on-time error
touton – tgsclk (see Figure 12), GSn = 01h, GSCLK = 11 MHz
–50
–90
ns
10
10
10
6.7 Typical Characteristics
4000
10 k
3.84 k
1.92 k
1.28 k
1k
0.96 k
0.79 k
0.64 k
0.55 k
0.48 k
100
0
10
20
30
40
50
60
IO(LC) − Output Current − mA
70
3000
2000
TLC5941PWP-
1000
0
–40
80
–20
0
20
40
60
80
TA – Free-Air Temperature – °C
Figure 1. Reference Resistor vs Output Current
6
Power Dissipation Rate – mW
R(IREF) − Reference Resistor − W
TLC5941PWP+
Figure 2. Power Dissipation Rate vs Free-Air Temperature
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Typical Characteristics (continued)
90
TA = 25°C,
VCC = 3.3 V
80
65
IO = 80 mA
IO - Output Current - mA
IO = 60 mA
60
50
IO = 40 mA
40
30
TA = 25°C
TA = 85°C
63
70
IO - Output Current - mA
IO = 60 mA,
VCC = 3.3 V
64
62
61
60
TA = -40°C
59
58
IO = 20 mA
57
20
56
IO = 5 mA
10
55
0
0
0
0.5
1
1.5
2
VO - Output Voltage - V
2.5
1.5
2
2.5
3
Figure 4. Output Current vs Output Voltage
8
8
IO = 60 mA
6
6
4
VCC = 3.3 V
TA = 25°C,
VCC = 3.3 V
4
VCC = 5 V
Max
2
ΔIOLC - %
2
ΔIOLC - %
1
VO - Output Voltage - V
Figure 3. Output Current vs Output Voltage
0
0
-2
-2
-4
-4
-6
-6
-8
-40
-20
0
20
40
60
80
TA - Ambient Temperature - °C
Min
-8
0
100
Figure 5. Delta Output Current vs Free-Air Temperature
20
40
60
IO - Output Current - mA
80
Figure 6. Delta Output Current vs Output Current
70
90
TA = 25°C,
VCC = 3.3 V
80
70
IO = 60 mA,
VCC = 3.3 V
IO = 80 mA
60
IO = 60 mA
IO - Output Current - mA
IO - Output Current - mA
0.5
3
60
50
40
IO = 30 mA
30
TA = 85°C
50
TA = 25°C
40
30
TA = -40°C
20
20
IO = 5 mA
10
10
0
0
10
20
30
40
50
Dot Correction Data - dec
60
70
Figure 7. Dot Correction Linearity (ABS Value)
0
0
10
20
30
40
50
Dot Correction Data - dec
60
70
Figure 8. Dot Correction Linearity (ABS Value)
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Typical Characteristics (continued)
70
60
TA = 25°C,
IO = 60 mA
IO - Output Current - mA
VCC = 3.3 V
50
40
30
VCC = 5 V
20
10
0
0
10
20
30
40
50
Dot Correction Data - dec
60
70
Figure 9. Dot Correction Linearity (ABS Value)
8
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7 Parameter Measurement Information
7.1 Pin Equivalent Input and Output Schematic Diagrams
Resistor values are equivalent resistance and not tested.
INPUT EQUIVALENT CIRCUIT
(BLANK, XLAT, SCLK, SIN, GSCLK, TEST)
OUTPUT EQUIVALENT CIRCUIT (SOUT)
VCC
23
400
INPUT
SOUT
23
GND
GND
INPUT EQUIVALENT CIRCUIT (IREF)
OUTPUT EQUIVALENT CIRCUIT (XERR)
VCC
23
_
400
INPUT
Amp
XERR
+
100
GND
GND
INPUT EQUIVALENT CIRCUIT (VCC)
OUTPUT EQUIVALENT CIRCUIT (OUT)
OUT
INPUT
GND
GND
INPUT EQUIVALENT CIRCUIT (MODE)
INPUT
GND
Figure 10. Input and Output Equivalent Circuits
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Pin Equivalent Input and Output Schematic Diagrams (continued)
t who , t wIO, twh1, twl1, tsu0
t su4, th4
V(LED) = 4 V
SOUT
Test Point
RL = 51
CL = 15 pF
OUTn
Test Point
CL = 15 pF
IOLC, IOLC3, IOLC4
V(LED) = 1 V
OUT0
VCC = 0 V ~ 7 V
OUTn
+ _
OUT15
IREF
Test Point
RIREF = 640
Figure 11. Parameter Measurement Circuits
7.2 Test Parameter Equations
D(%) =
D(%) =
I OUTn - I OUTavg _ 0 -15
IOUTavg _ 0 -15
IOUTavg - I OUT (IDEAL )
I OUT (IDEAL )
´ 100
(1)
´ 100
(2)
æ 1.24 V ö
÷÷
IOUT (IDEAL ) = 31.5 ´ çç
è R IREF ø
(3)
(I
at VCC = 5.5 V ) - (I OUTn at VCC = 3.0 V ) 100
D(% / V ) = OUTn
´
(I OUTn at VCC = 3.0 V )
2.5
(4)
(I
at VOUTn = 3.0 V ) - (IOUTn at VOUTn = 1.0 V ) 100
D(% / V ) = OUTn
´
(IOUTn at VOUTn = 1.0 V )
2 .0
(5)
10
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8 Detailed Description
8.1 Overview
The TLC5941-Q1 device is a 16-channel constant-current sink LED driver with individual PWM dimming and dot
correction, designed for LEDs in automotive indicator application. Each channel has up to 60-mA capability,
giving a combined 960-mA current capability when paralleled. A single external resistor sets the maximum
current value of all 16 channels.
The TLC5941-Q1 device can adjust 4096-step grayscale brightness of each channel OUTn individually, using a
PWM control scheme. As well, the TLC5941-Q1 device has the capability to fine-adjust 64-step the output
current of each channel independently. The dot correction adjusts the brightness variations between LED
channels and other LED drivers. Both grayscale control and dot correction are accessible via a serial interface,
which can be connected to microcontrollers or digital signal processors in various ways.
The integrated diagnostic circuit is used to detect device working condition, normal operation, LOD or TEF. The
LED open detection (LOD) indicates a broken or disconnected LED at an output terminal. The thermal error flag
(TEF) indicates an over temperature condition.
8.2 Functional Block Diagram
VCC
GND
SCLK
XLAT
SIN
CNT
MODE
1 0
IREF
Max. OUTn
Current
V REF
=1.24 V
GS Register
MODE
1 0
11
0
GSCLK
BLANK
0
DC Register
5
GS Counter
0
Status
Information:
LOD,
TED,
DC DATA
191
0
CNT
96
12−Bit Grayscale
PWM Control
Constant-Current
Driver
OUT0
Delay
x0
6−Bit Dot Correction
LED Open Detection
Input
Shift
Register
CNT
192
192
GS Register
23
96
96
95
1 0
12
DC Register
11
12−Bit Grayscale
PWM Control
Constant-Current
Driver
OUT1
Delay
x1
6−Bit Dot Correction
6
MODE
LED Open Detection
96
Temperature
Error Flag
(TEF)
LED Open
Detection
(LOD)
CNT
Input
Shift
Register
GS Register
191
XERR
180
DC Register
95
12−Bit Grayscale
PWM Control
Constant-Current
Driver
OUT15
Delay
x15
6−Bit Dot Correction
90
191
LED Open Detection
SOUT
8.3 Feature Description
8.3.1 Serial Interface
The TLC5941-Q1 device has a flexible serial interface, which can be connected to microcontrollers or digital
signal processors in various ways. Only 3 pins are needed to input data into the device. The rising edge of SCLK
signal shifts the data from the SIN pin to the internal register. After all data is clocked in, a high-level pulse of
XLAT signal latches the serial data to the internal registers. The internal registers are level-triggered latches of
XLAT signal. All data are clocked in with the MSB first. The length of serial data is 96 bit or 192 bit, depending on
the programming mode. Grayscale data and dot correction data can be entered during a grayscale cycle.
Although new grayscale data can be clocked in during a grayscale cycle, the XLAT signal should only latch the
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Feature Description (continued)
grayscale data at the end of the grayscale cycle. Latching in new grayscale data immediately overwrites the
existing grayscale data. Figure 12 shows the timing chart. More than two TLC5941-Q1 devices can be connected
in series by connecting an SOUT pin from one device to the SIN pin of the next device. An example of cascading
two TLC5941-Q1 devices is shown in Figure 13. The SOUT pin can also be connected to the controller to
receive status information from TLC5941-Q1 device as shown in Figure 18.
MODE
DC Data Input Mode
GS Data Input Mode
th3
tsu3
twh2
XLAT
1st GS Data Input Cycle
SIN
DC
MSB
GS2
MSB
GS2
LSB
th1
tsu1
1
96
1
GS1
LSB
tsu2
th2
SCLK
2nd GS Data Input Cycle
GS1
MSB
DC
LSB
GS3
MSB
tsu0
twh0
192
193
th0
193
192
1
tpd0
twl0
-
SOUT
DC
MSB
-
GS1
MSB
-
1
SID1 SID1
MSB MSB-1
SID2 SID2
MSB MSB-1
SID1 GS2
LSB MSB
twh3
BLANK
1st GS Data Output Cycle
1
tpd4
1
4096
tpd3
tpd1
tpd3 + td
td
tpd1 + td
twl1
Tgsclk
tpd3
OUT0
(current)
twh1
tsu4
th4
tsu5
GSCLK
2nd GS Data Output Cycle
touton
OUT1
(current)
15 x td
tpd1 + 15 x td
OUT15
(current)
tpd2
XERR
Figure 12. Serial Data Input Timing Chart
SIN(a)
SIN
SOUT
TLC5941 (a)
SIN
SOUT
SOUT(b )
TLC5941 (b)
SCLK, XLAT,
BLANK,
GSCLK,
MODE
Figure 13. Cascading Two TLC5941-Q1 Devices
12
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Feature Description (continued)
MODE
XLAT
SIN(a)
SCLK
DCb
MSB
GSb1
MSB
DCa
LSB
1
192
1
GSa1
LSB
384
96X2
-
SOUT(b)
GSb2
MSB
385
GSa2
LSB
GSb3
MSB
385
384
1
1
192X2
DCb
MSB
-
GSb1
MSB
-
SIDb1 SIDb1
MSB MSB-1
SIDa1
LSB
SIDb2 SIDb2
MSB MSB-1
GSb2
MSB
BLANK
1
GSCLK
1
4096
OUT0
(current)
OUT1
(current)
OUT15
(current)
XERR
Figure 14. Timing Chart for Two Cascaded TLC5941-Q1 Devices
8.3.2 Error Information Output
The open-drain output XERR is used to report both of the TLC5941-Q1 error flags, TEF and LOD. During normal
operating conditions, the internal transistor connected to the XERR pin is turned off. The voltage on XERR is
pulled up to VCC through an external pullup resistor. If TEF or LOD is detected, the internal transistor is turned
on, and XERR is pulled to GND. Because XERR is an open-drain output, multiple ICs can be ORed together and
pulled up to VCC with a single pullup resistor which reduces the number of signals needed to report a system
error (see Figure 18).
To differentiate LOD and TEF signal from XERR pin, LOD can be masked out with BLANK = HIGH.
Table 1. XERR Truth Table
ERROR CONDITION
ERROR INFORMATION
TEMPERATURE
OUTn VOLTAGE
TEF
LOD
TJ < T(TEF)
Don't Care
L
X
TJ > T(TEF)
Don't Care
H
X
OUTn > V(LED)
L
L
OUTn < V(LED)
L
H
OUTn > V(LED)
H
L
OUTn < V(LED)
H
H
TJ < T(TEF)
TJ > T(TEF)
SIGNALS
BLANK
H
XERR
H
L
H
L
L
L
L
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8.3.3 TEF: Thermal Error Flag
The TLC5941-Q1 device provides a temperature error flag (TEF) circuit to indicate an overtemperature condition
of the IC. If the junction temperature exceeds the threshold temperature (160°C typical), the TEF flag becomes H
and XERR pin goes to low level. When the junction temperature becomes lower than the threshold temperature,
the TEF flag becomes L and the XERR pin becomes high impedance. The TEF status can also be read out from
the TLC5941-Q1 status register.
8.3.4 LOD: LED Open Detection
The TLC5941-Q1 device has an LED-open detection circuit that detects broken or disconnected LEDs. The LED
open detector pulls the XERR pin to GND when an open LED is detected. The XERR pin and the corresponding
error bit in the Status Information Data is only active under the following open LED conditions:
1. OUTn is on and the time tpd2 (1 μs typical) has passed.
2. The voltage of OUTn is < 0.3V (typical)
The LOD status of each output can be also read out from the SOUT pin. See the Status Information Output
section for details. The LOD error bits are latched into the Status Information Data when the XLAT pin returns to
a low after a high. Therefore, the XLAT pin must be pulsed high then low while the XERR pin is active in order to
latch the LOD error into the Status Information Data for subsequent reading via the serial shift register.
8.3.5 Delay Between Outputs
The TLC5941-Q1 device has graduated delay circuits between outputs. These circuits can be found in the
constant current driver block of the device (see the functional block diagram). The fixed-delay time is 20 ns
(typical), the OUT0 output has no delay, the OUT1 output has 20-ns delay, the OUT2 output has 40-ns delay,
and so on. The maximum delay is 300 ns from the OUT0 output to the OUT15 output. The delay works during
switch on and switch off of each output channel. These delays prevent large inrush currents which reduces the
bypass capacitors when the outputs turn on.
8.3.6 Output Enable
All OUTn channels of the TLC5941-Q1 device can be switched off with one signal. When the BLANK signal is set
high, all OUTn channels are disabled, regardless of logic operations of the device. The grayscale counter is also
reset. When the BLANK signal is set low, all OUTn channels work under normal conditions. If BLANK goes low
and then back high again in less than 300 ns, all outputs programmed to turn on still turn on for either the
programmed number of grayscale clocks, or the length of time that the BLANK signal was low, which ever is
lower. For example, if all outputs are programmed to turn on for 1 ms, but the BLANK signal is only low for 200
ns, all outputs still turn on for 200 ns, even though some outputs are turning on after the BLANK signal has
already gone high.
Table 2. BLANK Signal Truth Table
BLANK
OUT0 to OUT15
LOW
Normal condition
HIGH
Disabled
8.3.7 Status Information Output
The TLC5941-Q1 device does have a status information register, which can be accessed in grayscale mode
(MODE = GND). After the XLAT signal latches the data into the GS register, the input shift register data is
replaced with status information data (SID) of the device (see Figure 22). The LOD, TEF, and dot-correction
register data can be read out at the SOUT pin. The status information data packet is 192 bits wide. Bits 0
through 15 contain the LOD status of each channel. Bit 16 contains the TEF status. Bits 24 through 119 contain
the data of the dot-correction register. The remaining bits are reserved. The complete status information data
packet is shown in Figure 15.
The SOUT pin outputs the MSB of the SID at the same time the SID are stored in the SID register, as shown in
Figure 16. The next SCLK pulse, which is the clock for receiving the MSB of the next grayscale data, transmits
MSB-1 of SID. If output voltage is < 0.3 V (typical) when the output sink current turns on, the LOD status flag
becomes active. The LOD status flag is an internal signal which pulls the XERR pin down to low when the LOD
status flag becomes active. The delay time, tpd2 (1 μs, maximum), is from the time of turning on the output sink
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current to the time the LOD status flag becomes valid. The timing for each channels LOD status to become valid
is shifted by the 30-ns (maximum), channel-to-channel turn-on time. After the first GSCLK pin goes high, the
OUT0 LOD status is valid; tpd3 + tpd2 = 60 ns + 1 μs = 1.06 μs. The OUT1 LOD status is valid; tpd3 + td + tpd2 = 60
ns + 30 ns + 1 μs = 1.09 μs. The OUT2 LOD status is valid; tpd3 + 2td + tpd2 = 1.12 μs, and so on. The total time
from the first GSCLK rising edge until all LOD become valid is about 1.51 μs maximum (tpd3 + 15td + tpd2); tsuLOD
must be > 1.51 μs (see Figure 16) to ensure that all LOD data are valid.
MSB
LSB
0
15
16
LOD 15
LOD 0
TEF
23
X
LOD Data
24
X
DC 15.5
TEF
119
120
191
DC 0.0
X
X
DC Values
Reserved
Figure 15. Status Information Data Packet Format
MODE
GS Data Input Mode
tsuLOD > tpd3 + td ´ 15 + tpd2
tsuLOD
XLAT
1st GS Data Input Cycle
2nd GS Data Input Cycle
SIN
GS1
MSB
GS1
LSB
SCLK
1
192
SOUT
-
-
GS2
MSB
193
GS1
MSB
GS2
LSB
192
1
SID1
MSB
SID1
MSB-1
SID1
LSB
GS2
MSB
(1st GS Data Output Cycle)
BLANK
GSCLK
4096
1
tpd3
OUT0
(current)
td
OUT1
(current)
15 x td
OUT15
(current)
tpd2
XERR
tpd3 + 15 x td + tpd2
Figure 16. Readout Status Information Data (SID) Timing Chart
The LOD status of each output can be read out from the SOUT pin. The LOD error bits are latched into the
Status Information Data when the XLAT pin returns to a low after a high. Therefore, the XLAT pin must be pulsed
high then low while the XERR pin is active in order to latch the LOD error into the Status Information Data for
subsequent reading through the serial shift register.
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8.3.8 Grayscale PWM Operation
The grayscale PWM cycle begins with the falling edge of BLANK. The first GSCLK pulse after the BLANK pin
goes low increases the grayscale counter by one and switches on all OUTn pins with grayscale value not zero.
Each following rising edge of the GSCLK pin increases the grayscale counter by one. The TLC5941-Q1 device
compares the grayscale value of each output, OUTn, with the grayscale counter value. All OUTn pins with
grayscale values equal to the counter values are switched off. A BLANK = H signal after 4096 GSCLK pulses
resets the grayscale counter to zero and completes the grayscale PWM cycle (see Figure 17). When the counter
reaches a count of FFFh, the counter stops counting and all outputs turn off. Pulling the BLANK pin high before
the counter reaches FFFh immediately resets the counter to zero.
GS PWM
Cycle n
BLANK
t wl1
t wh1
t h4
GSCLK
1
OUT0
(Current)
OUT1
(Current)
t pd1
t pd1 + td
GS PWM
Cycle n+1
2
t pd3
4096
3
t wl1
t wh3
t su4
1
t pd3
nxt d
t pd3+ n x t d
t pd1 + 15 x td
OUT15
(Current)
t pd2
XERR
Figure 17. Grayscale PWM Cycle Timing Chart
8.3.8.1 Output On Time
The amount of time that each output is turned on is a function of the grayscale clock frequency and the
programmed grayscale PWM value. The on-time of each output can be calculated using Equation 6.
GSn
T _ on n =
+ t on _ err
f( GSCLK )
where
•
•
•
•
T_onn is the time that the OUTn pin turns on and sinks current
GSn is the programmed grayscale PWM value of the OUTn pin between 0 and 4095
ton_err is the output on time error defined in the Switching Characteristics table
(6)
When using Equation 6 with very high GSCLK frequencies and very low grayscale PWM values, the resulting
T_on time may be negative. If T_on is negative, the output does not turn on. For example, using f(GSCLK) = 30
MHz, GSn = 1, and the typical ton_err = 50 nS, Equation 6 calculates that OUTn turns on for –16.6 ns. This output
may not turn on under these conditions. Increasing the PWM value or reducing the GSCLK clock frequency
ensures turn-on.
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8.4 Device Functional Modes
8.4.1 Operating Modes
The TLC5941-Q1 device has two operating modes defined by MODE as shown in Table 3. The GS and DC
registers are set to random values that are not known just after power on. The GS and DC values must be
programmed before turning on the outputs.
NOTE
When initially setting GS and DC data after power on, the GS data must be set before the
DC data is set. Failure to set GS data before DC data may result in the first bit of GS data
being lost. The XLAT pin must be low when the MODE pin goes high-to-low or low-to-high
to change back and forth between GS mode and DC mode.
Table 3. TLC5941-Q1 Operating Modes Truth Table
MODE
INPUT SHIFT REGISTER
OPERATING MODE
GND
192 bit
Grayscale PWM Mode
VCC
96 bit
Dot Correction Data Input Mode
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLC5941-Q1 device can be used for LED lighting, such as signboards and automotive dashboard backlighting.
9.2 Typical Application
VCC
100 k
VLED
VCC
VLED
VLED
100 k
OUT0
Controller
VLED
SIN
XERR
SCLK
XLAT
GSCLK
MODE
BLANK
SOUT
VCC
SIN
XERR
SCLK
XLAT
GSCLK
MODE
BLANK
TEST
OUT15
OUT0
SOUT
VCC
VCC
TLC5941-Q1
GND
IREF
VCC
SIN
XERR
SCLK
XLAT
GSCLK
MODE
BLANK
TEST
OUT15
SOUT
VCC
VCC
TLC5941-Q1
GND
IREF
Figure 18. Cascading Devices
9.2.1 Design Requirements
For the design example, use the following as the input parameter.
• VCC = 5 V
• VLED = 5 V – 16 V
• IMAX = 30 mA
9.2.2 Detailed Design Procedure
9.2.2.1 Setting Maximum Channel Current
The maximum output current per channel is programmed by a single resistor, R(IREF), which is placed between
the IREF pin and the GND pin. The voltage on the IREF pin is set by an internal band gap V(IREF) with a typical
value of 1.24 V. The maximum channel current is equivalent to the current flowing through R(IREF) multiplied by a
factor of 31.5. The maximum output current can be calculated by Equation 7.
V
(IREF)
I max =
× 31.5
R
(IREF)
where
•
•
V(IREF) = 1.24 V
R(IREF) = User-selected external resistor.
(7)
The value of Imax must be set between 5 mA and 60 mA. The output current may be unstable if Imax is set lower
than 5 mA. Output currents lower than 5 mA can be achieved by setting Imax to 5 mA or higher and then using
dot correction.
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Typical Application (continued)
Figure 1 shows the maximum output current IO versus R(IREF). R(IREF) is the value of the resistor between IREF
terminal to GND, and IO is the constant output current of OUT0 to OUT15. A variable power supply may be
connected to the IREF pin through a resistor to change the maximum output current per channel. The maximum
output current per channel is 31.5 times the current flowing out of the IREF pin.
9.2.2.2 Power Dissipation Calculation
The device power dissipation must be below the power dissipation rate of the device package to ensure correct
operation. Equation 8 calculates the power dissipation of device.
P
D
ǒ
+ V
CC
I
Ǔ ) ǒVOUT
CC
I
MAX
N
DCn
63
d
PWM
Ǔ
where
•
•
•
•
•
•
•
VCC: device supply voltage
ICC: device supply current
VOUT: TLC5941-Q1 OUTn voltage when driving LED current
IMAX: LED current adjusted by R(IREF) resistor
DCn: maximum dot correction value for OUTn
N: number of OUTn driving LED at the same time
dPWM: duty cycle defined by BLANK pin or GS PWM value
(8)
9.2.2.3 Setting Dot Correction
The TLC5941-Q1 device has the capability to fine-adjust the output current of each channel (OUT0 to OUT15)
independently which is also called dot correction. This feature is used to adjust the brightness deviations of LEDs
connected to the output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 6-bit
word. The channel output can be adjusted in 64 steps from 0% to 100% of the maximum output current Imax. The
TEST pin must be connected to VCC to ensure proper operation of the dot correction circuitry. Equation 9
calculates the output current for each output n.
DCn
I
I
OUTn = max × 63
where
•
•
•
Imax = the maximum programmable output current for each output.
DCn = the programmed dot correction value for output n (DCn = 0 to 63)
n = 0 to 15
(9)
Figure 19 shows the dot correction data packet format which consists of 6 bits x 16 channel, total 96 bits. The
format is Big-Endian format. This means that the MSB is transmitted first, followed by the MSB-1 and so on. The
DC 15.5 in Figure 19 stands for the 5th-most significant bit for output 15.
MSB
LSB
0
5
6
89
90
95
DC 15.5
DC 15.0
DC 14.5
DC 1.0
DC 0.5
DC 0.0
DC OUT15
DC OUT0
DC OUT14 − DC OUT1
Figure 19. Dot Correction Data Packet Format
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Typical Application (continued)
When the MODE pin is set to VCC, the TLC5941-Q1 device enters the dot correction data input mode. The length
of input shift register becomes 96bits. After all serial data are shifted in, the TLC5941-Q1 device writes the data
in the input shift register to DC register when the XLAT pin is high, and holds the data in the DC register when
the XLAT pin is low. The DC register is a level triggered latch of the XLAT signal. Because the XLAT pin is a
level-triggered signal, SCLK and SIN must not be changed while the XLAT pin is high. After the XLAT pin goes
low, data in the DC register is latched and does not change. The BLANK signal does not need to be high to latch
in new data. When the XLAT pin goes high, the new dot-correction data immediately becomes valid and changes
the output currents if the BLANK pin is low. the XLAT pin has setup time (tsu1) and hold time (th1) to SCLK as
shown in Figure 12.
To input data into the dot correction register, the MODE pin must be set to VCC. The internal input shift register is
then set to 96-bit width. After all serial data are clocked in, a rising edge of the XLAT pin is used to latch the data
into the dot correction register. Figure 20 shows the DC-data input-timing chart.
DC Mode Data
Input Cycle n
DC Mode Data
Input Cycle n+1
VCC
MODE
SIN
DC n−1
LSB
DC n
MSB
DC n
MSB−1
DC n
MSB−2
DC n
LSB+1
DC n
LSB
DC n+1
MSB
DC n+1
MSB−1
twh0
SCLK
1
2
3
95
96
1
2
twl0
DC n−1
MSB
SOUT
DC n−1
MSB−1
DC n−1
MSB−2
DC n−1
LSB+1
DC n−1
LSB
DC n
MSB
DC n
MSB−1
DC n
MSB−2
twh2
tsu1
th1
XLAT
Figure 20. Dot-Correction Data Input-Timing Chart
9.2.2.4 Setting Grayscale
The TLC5941-Q1 device can adjust the brightness of each channel, OUTn, using a PWM control scheme. The
use of 12 bits per channel results in 4096 different brightness steps, from 0% to 100% brightness. Equation 10
calculates the brightness level for each output n.
Brightness in % = GSn × 100
4095
where
•
•
•
GSn = the programmed grayscale value for output n (GSn = 0 to 4095)
n = 0 to 15
Grayscale data for all OUTn
(10)
The input shift register enters grayscale data into the grayscale register for all channels simultaneously. The
complete grayscale data format consists of 16 × 12 bit words, which forms a 192-bit wide data packet (see
Figure 21). The data packet must be clocked in with the MSB first.
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Typical Application (continued)
MSB
0
11
12
179
180
LSB
191
GS 15.11
GS 15.0
GS 14.11
GS 1.0
GS 0.11
GS 0.0
GS OUT15
GS OUT14 − GS OUT1
GS OUT0
Figure 21. Grayscale Data Packet Format
When the MODE pin is set to GND, the TLC5941-Q1 device enters the grayscale data input mode. The device
switches the input shift register to 192-bit width. After all data is clocked in, a rising edge of the XLAT signal
latches the data into the grayscale register (see Figure 22). New grayscale data immediately becomes valid at
the rising edge of the XLAT signal; therefore, new grayscale data should be latched at the end of a grayscale
cycle when BLANK is high. The first GS data input cycle after dot correction requires an additional SCLK pulse
after the XLAT signal to complete the grayscale update cycle. All GS data in the input shift register is replaced
with status information data (SID) after updating the grayscale register.
DC Mode Data
Input Cycle
Following GS Mode Data
Input Cycle
First GS Mode Data
Input Cycle After DC Data Input Cycle
MODE
t h3
t h3
t su3
XLAT
t wh2
GS
MSB
DC
LSB
SIN
GS n + 1
LSB
t h1
t h2
t su1
t su2
1
96
SCLK
GS + 1
MSB
GS
LSB
192
193
1
192
t pd0
DC
MSB
n
SOUT DC
LSB
X
GS
MSB
X
SID
MSB
SID
MSB−1
SID
LSB
SID n + 1
MSB
Figure 22. Grayscale Data Input Timing Chart
9.2.2.5 Serial Data Transfer Rate
Figure 18 shows a cascading connection of n TLC5941-Q1 devices connected to a controller, building a basic
module of an LED display system. The TLC5941-Q1 device has no limit to the maximum number of ICs that can
be cascaded. The maximum number of cascading TLC5941-Q1 devices depends on the application system and
is in the range of 40 devices. Equation 11 calculates the minimum frequency needed:
f
+ 4096
f
(GSCLK)
(update)
f
(SCLK)
+ 193
f
(update)
n
where
•
•
•
•
f(GSCLK): minimum frequency needed for GSCLK
f(SCLK): minimum frequency needed for SCLK and SIN
f(update): update rate of whole cascading system
n: number cascaded of TLC5941-Q1 device
(11)
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Typical Application (continued)
9.2.3 Application Curves
CH1 DC=63
CH2 DC=31
CH3 DC=15
Figure 23. Current with Dot Correction
CH1 GS=512
CH2 GS=256
CH3 GS=64
Figure 24. Current with Grayscale PWM Brightness
Control
10 Power Supply Recommendations
The TLC5941-Q1 devices is qualified for automotive applications. The normal power supply connection is
therefore an automotive electrical system that provides a voltage within the range specified in the Recommended
Operating Conditions.
VCC pin and BLANK pin should be powered up before micro-controller or digital signal processor sends the
control signal to the device.
11 Layout
11.1 Layout Guidelines
In order to prevent thermal shutdown, TJ must be less than 150ºC. If the input voltage is very high, the power
dissipation might be large. Currently there is the HTSSOP package which has good thermal impedance, but at
the same time, the PCB layout is also very important. Good PCB design can optimize heat transfer, which is
absolutely essential for the long-term reliability of the device.
• Maximize the copper coverage on the PCB to increase the thermal conductivity of the board, because the
major heat-flow path from the package to the ambient is through the copper on the PCB. Maximum copper is
extremely important when there are not any heat sinks attached to the PCB on the other side of the package.
• Add as many thermal vias as possible directly under the package ground pad to optimize the thermal
conductivity of the board.
• All thermal vias should be either plated shut or plugged and capped on both sides of the board to prevent
solder voids. To ensure reliability and performance, the solder coverage should be at least 85 percent.
22
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TLC5941-Q1
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SLDS165A – DECEMBER 2008 – REVISED DECEMBER 2014
11.2 Layout Example
Power ground both on top and bottom
GND
BLANK
XLAT
SCLK
SIN
MODE
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
Thermal
Pad
TLC5941-Q1
VCC
IREF
TEST
GSCLK
SOUT
XERR
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
Figure 25. PCB Layout Example
12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLC5941QPWPRQ1
ACTIVE
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TLC5941Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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