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TLV62095
SLVSDD3A – MARCH 2016 – REVISED JANUARY 2017
TLV62095 4-A High Efficiency Step Down Converter with DCS-Control™
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
•
•
The TLV62095 device is a high frequency
synchronous step-down converter optimized for small
solution size, high efficiency and suitable for battery
powered applications. To maximize efficiency, the
converter operates in PWM mode with a nominal
switching frequency of 1.4MHz and it automatically
enters Power Save Mode operation at light load
currents. When used in distributed power supplies
and point of load regulation, the device allows voltage
tracking to other voltage rails and tolerates output
capacitors ranging from 10 µF to 150 µF and beyond.
Using the DCS-Control™ topology, the device
achieves excellent load transient performance and
accurate output voltage regulation.
1
•
•
2.5 V to 5.5 V Input Voltage Range
DCS-Control™
Up to 95% Efficiency
Power Save Mode
20 µA Operating Quiescent Current
100% Duty Cycle for Lowest Dropout
1.4 MHz Typical Switching Frequency
0.8 V to VIN Adjustable Output Voltage
Output Discharge Function
Adjustable Soft Startup
Hiccup Short Circuit Protection
Output Voltage Tracking
Pin-to-Pin Compatible with TLV62090 and
TPS62095
For Improved Feature Set, See TPS62095
Create a Custom Design Using the TLV62095
With the WEBENCH® Power Designer
The output voltage start-up ramp is controlled by the
soft startup pin, which allows operation as either a
standalone power supply or in tracking configurations.
Power sequencing is also possible by configuring the
EN and PG pins. In Power Save Mode, the device
operates with typically 20-µA quiescent current.
Power Save Mode is entered automatically and
seamlessly maintaining high efficiency over the entire
load current range.
2 Applications
•
•
•
•
The device is available in a 3 mm x 3 mm 16-pin
VQFN package.
TV, STB, Computers
Solid State Drives (SSD)
Hard Disk Drives (HDD)
Battery Powered Applications
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TLV62095
VQFN (16)
3.00 mm × 3.00 mm
1.8 V Output Application
TLV62095
12
11
C1
22mF
10
3
C5
10nF
13
7
8
PVIN
SW
PVIN
SW
AVIN
VOS
1
100
C2
2 x 22mF
16
DEF
EN
PG 4
CP
SS
CN
AGND 6
14
Vout
1.8V
R1
200k
2
FB 5
PGND PGND
1.8 V Output Application Efficiency
L1
1mH
R2
160k
Power Good
9
C4
10nF
90
R3
500k
Efficiency (%)
Vin
2.5V to 5.5V
80
15
70
60
0.001
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
0.01
0.1
Load (A)
1
5
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV62095
SLVSDD3A – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommend Operating Conditions...........................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 7
7.1
7.2
7.3
7.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
7
7
8
8
8
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Applications ................................................ 11
9 Power Supply Recommendations...................... 16
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 17
10.3 Thermal Consideration.......................................... 17
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
19
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
Changes from Original (March 2016) to Revision A
Page
•
Added WEBENCH® information to Features, Detailed Design Procedure, and Development Support sections .................. 1
•
Added SW (AC, less than 10 ns) to the Abolute Maximum Rating table ............................................................................... 4
•
Added Table 1, Power Good Pin Logic ................................................................................................................................ 10
2
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5 Pin Configuration and Functions
PG
4
EN
14
13
12
11
Exposed
Thermal Pad
10
5
6
7
8
CN
3
PGND
DEF
15
CP
2
PGND
SW
16
AGND
1
FB
SW
VOS
16-Pin VQFN with Thermal PAD
RGT
(Top View)
9
PVIN
PVIN
AVIN
SS
Pin Functions
PIN
DESCRIPTION
NAME
NO.
SW
1, 2
DEF
3
This pin is used for internal logic and needs to be pulled high. This pin must be connected to the AVIN
pin.
PG
4
Power good open drain output. A pull up resistor can not be connected to any voltage higher than the
input voltage.
FB
5
Feedback pin for regulating the output voltage.
AGND
6
Analog ground.
CP
7
Internal charge pump's flying capacitor. Connect a 10nF capacitor between CP and CN.
CN
8
Internal charge pump's flying capacitor. Connect a 10nF capacitor between CP and CN.
SS
9
Soft-start control pin. A capacitor is connected to this pin and sets the soft startup time. Leaving this pin
floating sets the minimum start-up time.
AVIN
10
Analog supply input voltage pin.
PVIN
11,12
Power supply input voltage pin.
EN
PGND
VOS
Exposed
Thermal Pad
13
14,15
16
Switch pin of the power stage.
Enable pin. This pin has an active pull down resistor of typically 400kΩ, which is active when EN is low.
To enable the device, this pin needs to be pulled high. Pulling this pin low disables the device.
Power ground.
Output voltage sense pin. This pin must be directly connected to the output voltage.
The exposed thermal pad must be connected to AGND. It must be soldered for mechanical reliability.
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6 Specifications
6.1 Absolute Maximum Ratings (1)
MIN
MAX
PVIN, AVIN, FB, SS, EN, DEF, VOS
– 0.3
7
SW (DC), PG
– 0.3
VIN+0.3
SW (AC, less than 10 ns) (3)
– 3.0
10
CN, CP
– 0.3
VIN+7.0
1.0
mA
Operating junction temperature range, TJ
– 40
150
°C
Storage temperature, Tstg
– 65
150
°C
Voltage at pins (2)
Sink current
(1)
(2)
(3)
PG
UNIT
V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground pin.
While switching.
6.2 ESD Ratings
MAX
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommend Operating Conditions
MIN
MAX
UNIT
VIN
Input voltage range
2.5
5.5
V
TJ
Operating junction temperature
-40
125
°C
6.4 Thermal Information
THERMAL METRIC (1)
TLV62095
VQFN (16 PINS)
RθJA
Junction-to-ambient thermal resistance
47
RθJC(top)
Junction-to-case (top) thermal resistance
60
RθJB
Junction-to-board thermal resistance
20
ψJT
Junction-to-top characterization parameter
1.5
ψJB
Junction-to-board characterization parameter
20
RθJC(bot)
Junction-to-case (bottom) thermal resistance
5.3
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
VIN = 3.6V and TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VIN
Input voltage range
IQ
Quiescent current into PVIN
and AVIN
EN = High, Not switching, FB = FB +5%
20
µA
ISD
Shutdown current Into PVIN
and AVIN
EN = Low
0.6
µA
Undervoltage lockout threshold
VIN falling
VUVLO
TSD
2.5
2.1
Undervoltage lockout hysteresis
Thermal shutdown
Temperature rising
Thermal shutdown hysteresis
5.5
2.2
2.3
V
V
200
mV
150
ºC
20
ºC
CONTROL SIGNAL EN
VH
High level input voltage
VIN = 2.5 V to 5.5 V
VL
Low level input voltage
VIN = 2.5 V to 5.5 V
Ilkg
Input leakage current
EN = GND or VIN
RPD
Pull down resistance
EN = Low
1
0.65
V
0.60
0.4
V
10
100
nA
400
kΩ
7.5
µA
SOFT STARTUP
ISS
Softstart current
POWER GOOD
VTH_PG
Power good threshold
VL
Low level voltage
Output voltage rising
95%
Output voltage falling
90%
I(sink) = 1 mA
0.4
V
POWER SWITCH
RDS(on)
High side FET on-resistance
ISW = 500 mA
50
mΩ
Low side FET on-resistance
ISW = 500 mA
40
mΩ
5.5
A
1.4
MHz
ILIM
High side FET switch current
limit
fSW
Switching frequency
4.7
IOUT = 3 A
OUTPUT
VOUT
Output voltage range
RDIS
Output discharge resistor
EN = GND, VOUT = 1.8 V
0.8
VIN
VFB
Feedback regulation voltage
IOUT = 1 A, PWM mode
Line regulation
VOUT = 1.8 V, PWM operation
0.016
%/V
Load regulation
VOUT = 1.8 V, PWM operation
0.04
%/A
792
800
808
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V
Ω
200
mV
5
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SLVSDD3A – MARCH 2016 – REVISED JANUARY 2017
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80
80
70
70
60
60
50
50
Rdson (m:)
Rdson (m:)
6.6 Typical Characteristics
40
30
20
Tj
Tj
Tj
Tj
10
0
2.5
=
=
=
=
30
20
-40°C
25°C
85°C
125°C
3.0
40
10
3.5
4.0
4.5
Input Voltage (V)
5.0
0
2.5
5.5
Tj
Tj
Tj
Tj
=
=
=
=
-40°C
25°C
85°C
125°C
3.0
3.5
D003
Figure 1. High-Side FET On Resistance
4.0
4.5
Input Voltage (V)
5.0
5.5
D004
Figure 2. Low-Side FET On Resistance
1
30
Shutdown Current (PA)
Quiescent Current (PA)
0.8
20
10
Tj
Tj
Tj
Tj
0
2.5
=
=
=
=
-40°C
0°C
25°C
85°C
3.0
0.6
0.4
0.2
3.5
4.0
4.5
Input Voltage (V)
5.0
5.5
Tj
Tj
Tj
Tj
0
2.5
D005
-40°C
0°C
25°C
85°C
3.0
3.5
4.0
4.5
Input Voltage (V)
5.0
5.5
D006
Figure 4. Shutdown Current
Figure 3. Quiescent Current
6
=
=
=
=
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7 Detailed Description
7.1 Overview
The TLV62095 synchronous step down converter is based on DCS-Control™ (Direct Control with Seamless
transition into Power Save Mode). This is an advanced regulation topology that combines the advantages of
hysteretic and voltage mode control.
The DCS-Control™ topology operates in PWM (Pulse Width Modulation) mode for medium to heavy load
conditions and in Power Save Mode at light load currents. In PWM mode, the converter operates with its nominal
switching frequency of 1.4 MHz having a controlled frequency variation over the input voltage range. As the load
current decreases, the converter enters Power Save Mode, reducing the switching frequency and minimizing the
current consumption of the IC to achieve high efficiency over the entire load current range. DCS-Control™
supports both operation modes using a single building block and therefore has a seamless transition from PWM
to Power Save Mode without effects on the output voltage. The TLV62095 offers excellent DC voltage regulation
and load transient regulation, combined with low output voltage ripple, minimizing interference with RF circuits.
7.2 Functional Block Diagram
PG
CP
PVIN
CN
Charge Pump
for
Gate driver
VFB
Hiccup
current limit
#32 counter
VREF
High Side
Current
Sense
AVIN
Bandgap
Undervoltage
Lockout
Thermal shutdown
EN
PVIN
M1
400kW (1)
SW
MOSFET Driver
Anti Shoot Through
Converter Control
Logic
AGND
SW
DEF
M2
PGND
PGND
Comparator
ramp
Timer
ton
Direct Control
and
Compensation
VOS
Error Amplifier
FB
Vref
0.8V
Vin
DCS - Control™
200Ω
Iss
Voltage clamp
Vref
SS
÷1.56
EN
Output voltage
discharge
logic
M3
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(1) The resistor is disconnected when EN is high.
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7.3 Feature Description
7.3.1 PWM Operation
At medium to heavy load currents, the device operates with pulse width modulation (PWM) at a nominal
switching frequency of 1.4 MHz. As the load current decreases, the converter enters power save mode operation
reducing its switching frequency. The device enters power save mode at the boundary to discontinuous
conduction mode (DCM).
7.3.2 Power Save Mode Operation
As the load current decreases, the converter enters Power Save Mode operation. During Power Save Mode, the
converter operates with reduced switching frequency to maintain high efficiency. Power Save Mode is based on
a fixed on-time architecture following Equation 1.
V
OUT × 360ns × 2
V
IN
2×I
OUT
f =
æ
ö V -V
V
V
OUT ÷ x IN
OUT
ton2 ç 1 + IN
ç
÷
V
L
OUT
è
ø
ton =
(1)
In Power Save Mode, the output voltage rises slightly above the nominal output voltage in PWM mode. This
effect is reduced by increasing the output capacitance or the inductor value. This effect is also reduced by
programming the output voltage of the TLV62095 lower than the target value.
7.3.3 Low Dropout Operation (100% Duty Cycle)
The device offers low input to output voltage difference by entering 100% duty cycle mode. In this mode the high
side MOSFET switch is constantly turned on. This is particularly useful in battery powered applications to achieve
longest operation time by taking full advantage of the whole battery voltage range. The minimum input voltage
where the output voltage falls below its set point is given by:
VIN(min) = VOUT + IOUT x ( RDS(on) + RL )
(2)
Where
RDS(on) = High side FET on-resistance
RL = DC resistance of the inductor
7.4 Device Functional Modes
7.4.1 Enable (EN)
The device is enabled by setting the EN pin to a logic high. Accordingly, shutdown mode is forced if the EN pin is
pulled low with a shutdown current of typically 0.6 μA. In shutdown mode, the internal power switches as well as
the entire control circuitry are turned off. An internal resistor of 200 Ω discharges the output through the VOS pin
smoothly. An internal pull-down resistor of 400 kΩ is connected to the EN pin when the EN pin is low. The pulldown resistor is disconnected when the EN pin is high.
7.4.2 Soft Startup (SS) and Hiccup Current Limit During Startup
To minimize inrush current during startup, the device has an adjustable startup time depending on the capacitor
value connected to the SS pin. The device charges the SS capacitor with a constant current of typically 7.5 µA.
The feedback voltage follows this voltage divided by 1.56, until the internal reference voltage of 0.8 V is reached.
The soft startup operation is completed once the voltage at the SS capacitor has reached typically 1.25 V. The
soft startup time is calculated using Equation 3. The larger the SS capacitor, the longer the soft startup time. The
relation between the SS pin voltage and the FB pin voltage is estimated using Equation 4.
1.25V
tSS = CSS x
7.5μA
(3)
VFB =
8
VSS
1.56
(4)
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Device Functional Modes (continued)
During startup the switch current limit is reduced to 1/3 of its typical current limit of 5.5A when the output voltage
is less than 0.6V. Once the output voltage exceeds typically 0.6V, the switch current limit is released to its
nominal value. Thus, the device provides a reduced load current of 1.8A when the output voltage is below 0.6V.
Due to this, a small or no startup time may trigger this reduced switch current limit during startup, especially for
larger output capacitor applications. This is avoided by using a larger soft start up capacitance which extends the
soft startup time. See Short Circuit Protection (Hiccup-Mode) for details of the reduced current limit during
startup. Leaving the SS pin floating sets the minimum startup time (around 50 μs).
7.4.3 Voltage Tracking (SS)
The SS pin is externally driven by another voltage source to achieve output voltage tracking. The application
circuit is shown in Figure 5. The internal reference voltage follows the voltage at the SS pin with a fraction of 1.56
until the internal reference voltage of 0.8 V is reached. The device achieves ratiometric or coincidental
(simultaneous) output tracking, as shown in Figure 6.
VOUT1
VOUT2
TLV62095
R3
R1
SS
FB
R2
R4
Figure 5. Output Voltage Tracking
The R2 value should be set properly to achieve accurate voltage tracking by taking 7.5 μA soft startup current
into account. 1 kΩ or smaller is a sufficient value for R2.
Voltage
Voltage
1+
VOUT1
VOUT1
VOUT2
VOUT2
R3 æ
R1 ö
1
< ç1 +
÷´
R 4 è R 2 ø 1.56
1+
R3 æ
R1 ö
1
= ç1 +
÷´
R 4 è R 2 ø 1.56
t
t
a) Ratiometric Tracking
b) Coincidental Tracking
Figure 6. Voltage Tracking Options
For decreasing the SS pin voltage, the device doesn't sink current from the output when the device is in power
save mode. So the resulting decrease of the output voltage may be slower than the SS pin voltage if the load is
light. When driving the SS pin with an external voltage, do not exceed the voltage rating of the SS pin which is 7
V.
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Device Functional Modes (continued)
7.4.4 Short Circuit Protection (Hiccup-Mode)
The device is protected against hard short circuits to GND and over-current events. This is implemented by a two
level short circuit protection. During start-up and when the output is shorted to GND, the switch current limit is
reduced to 1/3 of its typical current limit of 5.5 A. Once the output voltage exceeds typically 0.6 V the current limit
is released to its nominal value. The full current limit is implemented as a hiccup current limit. Once the internal
current limit is triggered 32 times, the device stops switching and starts a new start-up sequence after a typical
delay time of 66 µs passed by. The device repeats these cycles until the high current condition is released.
7.4.5 Output Discharge Function
To make sure the device starts up under defined conditions, the output gets discharged via the VOS pin with a
typical discharge resistor of 200 Ω whenever the device shuts down. This happens when the device is disabled
or if thermal shutdown, undervoltage lockout or short circuit hiccup-mode is triggered.
7.4.6 Power Good Output
The power good output is low when the output voltage is below its nominal value. The power good becomes high
impedance once the output is within 5% of regulation. The PG pin is an open drain output and is specified to sink
up to 1mA. This output requires a pull-up resistor to be monitored properly. The pull-up resistor cannot be
connected to any voltage higher than the input voltage of the device. The PG output can be left floating if
unused. Table 1 shows the PG pin logic.
Table 1. Power Good Pin Logic
PG Logic Status
Device State
Enable (EN=High)
High Impedance
VFB ≥ VTH_PG
Low
√
VFB ≤ VTH_PG
√
√
Shutdown (EN=Low)
UVLO
0.7 V < VIN ≤ VUVLO
Thermal Shutdown
TJ > TSD
Power Supply Removal
VIN ≤ 0.7 V
√
√
√
7.4.7 Undervoltage Lockout
To avoid mis-operation of the device at low input voltages, an undervoltage lockout is included. UVLO shuts
down the device at input voltages lower than typically 2.2 V with a 200 mV hysteresis.
7.4.8 Thermal Shutdown
The device goes into thermal shutdown once the junction temperature exceeds typically 150°C with a 20°C
hysteresis.
7.4.9 Charge Pump (CP, CN)
The CP and CN pins must attach to an external 10 nF capacitor to complete a charge pump for the gate driver.
This capacitor must be rated for the input voltage. It is not recommended to connect any other circuits to the CP
or CN pins.
10
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV62095 is a 4-A high frequency synchronous step-down converter optimized for small solution size, high
efficiency and suitable for battery powered applications.
8.2 Typical Applications
8.2.1
1.8-V Output Converter
L1
1mH
TLV62095
Vin
2.5V to 5.5V
12
11
C1
22mF
10
3
C5
10nF
13
7
8
PVIN
SW
PVIN
SW
AVIN
VOS
1
Vout
1.8V
R1
200k
2
C2
2 x 22mF
16
DEF
FB 5
EN
PG 4
CP
SS
CN
AGND 6
R2
160k
R3
500k
Power Good
9
C4
10nF
PGND PGND
14
15
Figure 7. TLV62095 Typical Application Circuit
8.2.1.1 Design Requirements
The design guideline provides a component selection to operate the device within the recommended operating
conditions. For the typical application example, the following input parameters are used.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
2.5 V to 5.5 V
Output voltage
1.8 V
Output ripple voltage
< 30 mV
Output current rating
4A
Table 3 shows the list of components for the Application Characteristic Curves.
Table 3. List of Components
REFERENCE
TLV62095
L1
C1, C2
DESCRIPTION
High efficiency step-down
converter
Inductor: 1 µH
Ceramic capacitor: 22 μF
MANUFACTURER
Texas Instruments
Coilcraft XAL4020-102
(6.3V, X5R, 0805)
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Table 3. List of Components (continued)
REFERENCE
DESCRIPTION
C4, C5
R1, R2, R3
MANUFACTURER
Ceramic capacitor, 10 nF
Standard
Resistor
Standard
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TLV62095 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2.2 Output Filter
The first step is the selection of the output filter components. To simplify this process, Table 4 outlines possible
inductor and capacitor value combinations.
Table 4. Output Filter Selection
INDUCTOR VALUE [µH] (1)
OUTPUT CAPACITOR VALUE [µF] (2)
10
22
2 x 22
100
150
√ (3)
√
√
0.47
1.0
2.2
(1)
(2)
(3)
Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by +20% and
–30%.
Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary by
+20% and –50%.
Typical application configuration. Other check mark indicates alternative filter combinations
8.2.1.2.3 Inductor Selection
The inductor selection is affected by several parameters like inductor ripple current, output voltage ripple,
transition point into Power Save Mode, and efficiency. See Table 5 for typical inductors.
Table 5. Inductor Selection
(1)
INDUCTOR VALUE
COMPONENT SUPPLIER (1)
SIZE (LxWxH mm)
Isat / DCR
1 µH
Coilcraft XAL4020-102
4.0 x 4.0 x 2.1
8.75A / 13.2 mΩ
0.47 µH
TOKO DFE322512C
3.2 x 2.5 x 1.2
5.9A / 21 mΩ
See Third-Party Products disclaimer
In addition, the inductor has to be rated for the appropriate saturation current and DC resistance (DCR). The
inductor needs to be rated for a saturation current as high as the typical switch current limit of 5.5A or according
to Equation 5 and Equation 6. Equation 5 and Equation 6 calculate the maximum inductor current under static
load conditions. The formula takes the converter efficiency into account. The converter efficiency can be taken
from the data sheet graphs or 80% can be used as a conservative approach. The calculation must be done for
the maximum input voltage where the peak switch current is highest.
12
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I =I
+
L
OUT
ΔI
L
2
(5)
æ
ö
V
V
OUT x ç 1 - OUT ÷
ç
η
V x η÷
IN
è
ø
I =I
+
L
OUT
2x f xL
(6)
where
ƒ = Converter switching frequency (typically 1.4MHz)
L = Inductor value
η = Estimated converter efficiency (use the number from the efficiency curves or 0.80 as a conservative
assumption)
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current. A margin of 20% should be added to cover for load transients during operation.
8.2.1.2.4
Input and Output Capacitor Selection
For best output and input voltage filtering, low ESR (X5R or X7R) ceramic capacitors are recommended. The
input capacitor minimizes input voltage ripple, suppresses input voltage spikes and provides a stable system rail
for the device. A 22-μF or larger input capacitor is recommended. The output capacitor value can range from 10
μF up to 150 μF and beyond. Load transient testing and measuring the bode plot are good ways to verify stability
with larger capacitor values.
The recommended typical output capacitor value is 2 x 22 μF (nominal) and can vary over a wide range as
outline in the output filter selection table. Ceramic capacitor have a DC-Bias effect, which has a strong influence
on the final effective capacitance. Choose the right capacitor carefully in combination with considering its
package size and voltage rating.
8.2.1.2.5 Setting the Output Voltage
The output voltage is set by an external resistor divider according to the following equations:
R1 ö
R1 ö
æ
æ
VOUT = VFB ´ ç 1 +
= 0.8 V ´ ç 1 +
÷
R2 ø
R2 ÷ø
è
è
R2 =
VFB
0.8 V
=
» 160 kΩ
IFB
5 μA
(7)
(8)
æV
ö
æV
ö
R1 = R2 ´ ç OUT - 1÷ = R2 ´ ç OUT - 1÷
è 0.8V
ø
è VFB
ø
(9)
When sizing R2, in order to achieve low quiescent current and acceptable noise sensitivity, use a minimum of 5
µA for the feedback current IFB. Larger currents through R2 improve noise sensitivity and output voltage
accuracy.
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8.2.1.3 Application Performance Curves
100
100
90
90
Efficiency (%)
Efficiency (%)
TA = 25°C, VIN = 3.6 V, VOUT = 1.8 V, unless otherwise noted.
80
70
70
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
60
0.001
0.01
80
0.1
Load (A)
1
VIN = 2.5 V
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
60
0.001
5
0.01
D001
100
100
90
90
80
70
D017
70
60
0.001
0.01
VIN = 3.6 V
VIN = 4.2 V
VIN = 5.0 V
0.1
Load (A)
1
60
0.001
5
0.01
D018
Figure 10. Efficiency, VOUT = 2.6 V
0.5
0.5
0.4
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
TA = 40qC
TA = 25qC
TA = 85qC
-0.4
-0.5
0.001
0.01
1
1
5
D019
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
TA = -40°C
TA = 25°C
TA = 85°C
-0.4
0.1
Load (A)
0.1
Load (A)
Figure 11. Efficiency, VOUT = 3.3 V
Output Voltage Accuracy (%)
Output Voltage Accuracy (%)
5
80
VIN = 3.3 V
VIN = 4.2 V
VIN = 5.0 V
5
-0.5
2.5
3.0
3.5
4.0
4.5
Input Voltage (V)
5.0
5.5
D007
D002
Figure 12. Load Regulation, VOUT = 1.8 V, VIN = 3.3 V
14
1
Figure 9. Efficiency, VOUT = 1.2 V
Efficiency (%)
Efficiency (%)
Figure 8. Efficiency, VOUT = 1.8 V
0.1
Load (A)
Figure 13. Line Regulation, VOUT = 1.8 V, IOUT = 1.0 A
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5000
Switching Frequency (kHz)
SW = 5V/div
1000
VOUT = 20 mV/div, AC
100
ICOIL = 0.5 A/div
10
VIN = 2.5 V
VIN = 3.6 V
VIN = 5.5 V
1
0.001
Time = 1 µs/div
0.01
0.1
Load (A)
1
5
D008
Figure 14. Switching Frequency, VOUT = 1.8 V
Figure 15. Output Ripple, VOUT = 1.8 V, IOUT = 100 mA
SW = 5V/div
VIN = 2V/div
VOUT = 20mV/div, AC
VOUT = 1V/div
ICOIL = 1A/div
ICOIL = 0.5A/div
Time = 0.5 µs/div
Time = 500 µs/div
Figure 16. Output Ripple, VOUT = 1.8 V, IOUT = 3.5 A
EN = 5V/div
Figure 17. Startup, Relative to VIN, RLOAD = 1.5 Ω
LOAD = 2A/div
0.1A to 2A load step
VIN = 2V/div
VOUT = 0.1V/div, AC
VOUT = 1V/div
ICOIL = 2A/div
ICOIL = 0.5A/div
Time = 500 µs/div
Time = 10 µs/div
Figure 18. Startup, Relative to EN, RLOAD = 1.5 Ω
Figure 19. Load Transient, VOUT = 1.8 V
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LOAD = 2A/div
VOUT = 1V/div
1A to 3.5A load step
VOUT = 0.1V/div, AC
ICOIL = 2A/div
ICOIL = 2A/div
Time = 10 µs/div
Time = 250 µs/div
Figure 20. Load Transient, VOUT = 1.8 V
Figure 21. Short Circuit, HICCUP Protection Entry
VOUT = 1V/div
ICOIL = 2A/div
Time = 250 µs/div
Figure 22. Short Circuit, HICCUP Protection Exit
9 Power Supply Recommendations
The TLV62095 device has no special requirements for its input power supply. The input power supply's output
current needs to be rated according to the supply voltage, output voltage and output current of the TLV62095.
10 Layout
10.1 Layout Guidelines
•
•
•
•
•
16
It is recommended to place the input capacitor as close as possible to the IC pins PVIN and PGND.
The VOS connection is noise sensitive and needs to be routed short and direct to the output terminal of the
inductor.
The exposed thermal pad of the package, analog ground (pin 6) and power ground (pin 14, 15) should have a
single point connection at the exposed thermal pad of the package. This minimizes switch node jitter.
The charge pump capacitor connected to CP and CN should be placed close to the IC to minimize coupling of
switching waveforms into other traces and circuits.
Refer to Figure 23 for an example of component placement, routing and thermal design.
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R2x1
R1
AGND
R2
L1x1
10.2 Layout Example
L1
C2
PGND
EN
PVIN
PGND
CP
CN
SS
AGND
AVIN
VOS
PVIN
FB
C4
VOUT
SW
PG
SW
DEF
C5
VIN
GND
C1
Figure 23. TLV62095 PCB Layout
10.3 Thermal Consideration
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component. The Thermal Information table provides the thermal metric of the device
and its package based on JEDEC standard. For more details on how to use the thermal parameters in real
applications, see the application notes: SZZA017 and SPRA953.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
11.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TLV62095 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
DCS-Control, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
18
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11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TLV62095RGTR
ACTIVE
VQFN
RGT
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
13O
TLV62095RGTT
ACTIVE
VQFN
RGT
16
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
13O
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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