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TMUX1072
SCDS382C – APRIL 2018 – REVISED AUGUST 2019
TMUX1072 2-Channel 2:1 Analog Multiplexer with Overvoltage Detection and Protection
1 Features
3 Description
•
•
The TMUX1072 is a high-speed, 2-channel, 2:1,
analog switch with integrated overvoltage detection
and powered off protection. The device is
bidirectional and can be used as a 2:1 or 1:2 switch
while supporting signals beyond VCC up to 5.5 V.
1
•
•
•
•
•
•
•
•
•
•
Supply range 2.3 V to 5.5 V
Powered off protection: I/O pins Hi-Z when
VCC = 0 V
6-V Overvoltage and overtemperature detection
with fault indicator pin
18-V Overvoltage protection (OVP) on common
pins
Support signals beyond VCC up to 5.5 V
Low RON of 6 Ω
BW of 1.2 GHz typical
CON of 4.5 pF typical
Low power disable mode
1.8-V Compatible logic inputs
ESD protection exceeds JESD22
– 2000-V Human body model (HBM)
Small 2.00 mm x 1.70 mm QFN package available
The protection on the I/O pins of the TMUX1072
tolerates a maximum of 18 V with automatic shutoff
circuitry to prevent damage to system components
behind the switch. This protection is used for power
sequencing. Some boards in the system may be
powered up before others are ready to receive
signals. The device detects overvoltage and
overtemperature events, and provides an open drain
output signal through the FLT pin.
Device Information(1)
PART NUMBER
TMUX1072
BODY SIZE (NOM)
2.00 mm × 1.70 mm
VSSOP (10)
3.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
PACKAGE
UQFN (12)
Data acquisition (DAQ)
Field instrumentation
Video surveillance
HVAC systems
Rear camera
Simplified Schematic
TMUX1072
VCC
OVP
NC1
COM1
NO1
NC2
COM2
NO2
SEL1
SEL2
OE
Logic
Control
FLT
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUX1072
SCDS382C – APRIL 2018 – REVISED AUGUST 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
5
5
8
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Dynamic Characteristics ...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 16
9
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application .................................................. 17
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2019) to Revision C
Page
•
Added Typical Characteristics curves for AC parameters ..................................................................................................... 9
•
Added the Application Curves section.................................................................................................................................. 18
Changes from Revision A (August 2018) to Revision B
•
Changed Feature From: 0-V to 18-V Overvoltage Protection (OVP) on Common Pins To: 0-V to 6-V Overvoltage
protection (OVP) on common pins ......................................................................................................................................... 1
Changes from Original (April 2018) to Revision A
•
2
Page
Page
Changed the device status From: Advanced Information To Production data ...................................................................... 1
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SCDS382C – APRIL 2018 – REVISED AUGUST 2019
5 Pin Configuration and Functions
RUT Package
12-Pin UQFN
Top View
FLT
DGS Package
10-Pin VSSOP
Top View
SEL1
1
11
NO1
2
12 10
NC1
GND
3
9
VCC
NO2
4
SEL2
5
6
COM1
8
NC2
7
COM2
SEL1
1
10
COM1
NO1
2
9
NC1
GND
3
8
VCC
NO2
4
7
NC2
SEL2
5
6
COM2
OE
Not to scale
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
RUT
DGS
SEL1
1
1
I
NO1
2
2
I/O
GND
3
3
GND
NO2
4
4
I/O
SEL2
5
5
I
Switch select 2
OE
6
-
I
Output enable (Active low)
COM2
7
6
I/O
Common signal path 2
Switch select 1
Signal path NO1
Ground
Signal path NO2
NC2
8
7
I/O
Signal path NC2
VCC
9
8
PWR
Supply Voltage
NC1
10
9
I/O
Signal path NC1
COM1
11
10
I/O
Common signal path 1
FLT
12
-
O
Fault indicator output pin (Active low) - open drain. If feature is unused, pin may be
left floating or connected to ground
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SCDS382C – APRIL 2018 – REVISED AUGUST 2019
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
(2)
Supply voltage (3)
VCC
Input/Output DC voltage (COM1, COM2)
VI/O
(3)
Input/Output DC voltage (NC1, NO1, NC2, NO2)
(3)
MIN
MAX
UNIT
–0.5
6
V
–0.5
20
V
–0.5
6
V
VI
Digital input voltage (SEL1, SEL2, OE)
–0.5
6
V
VO
Digital output voltage (FLT)
–0.5
6
V
IK
Input-output port diode current (COM1,
COM2,NC1, NO1, NC2, NO2)
VIN < 0
–50
mA
IIK
Digital logic input clamp current (SEL1,
SEL2, OE) (3)
VI < 0
–50
mA
ICC
Continuous current through VCC
IGND
Continuous current through GND
–100
Tstg
Storage temperature
–65
150
°C
TJ
Operating Junction Temperature
–65
150
°C
(1)
(2)
(3)
100
mA
mA
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
All voltages are with respect to ground, unless otherwise specified.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
VCC
Supply voltage
MIN
MAX
2.3
5.5
UNIT
V
V
VI/O
COM1, COM2
0
18
VI/O
(NC1, NO1, NC2, NO2)
0
5.5
V
COM1, COM2
-50
50
mA
(NC1, NO1, NC2, NO2)
II/O
Analog input/output
II/O
-50
50
mA
VI
Digital input voltage
SEL1, SEL2, OE
0
5.5
V
VO
Digital output voltage
FLT
0
5.5
V
Analog input/output port continuous current
(COM1, COM2, NC1, NO1,
NC2, NO2)
-50
50
mA
II/O
IOL
Digital output current
3
mA
TA
Operating free-air temperature
–40
125
ºC
TJ
Junction temperature
–40
125
ºC
4
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6.4 Thermal Information
TMUX1072
THERMAL METRIC
(1)
RUT (UQFN)
DGS (VSSOP)
12 PINS
10 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
127
175
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
55.5
61.2
°C/W
RθJB
Junction-to-board thermal resistance
67.7
96.9
°C/W
ψJT
Junction-to-top characterization parameter
1.6
8.2
°C/W
ψJB
Junction-to-board characterization parameter
67.3
95.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TA = –40°C to +125°C , VCC = 2.3 V to 5.5 V, GND = 0V, Typical values are at VCC = 3.3 V, TA = 25°C, (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VCC
Power supply voltage
2.3
5.5
V
75
110
µA
65
98
µA
3
10
µA
Active supply current
OE = 0 V
SEL1, SEL2 = 0 V, 1.8 V or VCC
0 V < VI/O < 3.6 V
Supply current during OVP
condition
OE = 0 V
SEL1, SEL2 = 0 V, 1.8 V or VCC
VI/O > VPOS_THLD
ICC_PD (1)
Standby powered down
supply current
OE = 1.8 V or VCC
SEL1 = 0 V, 1.8 V, or VCC
SEL2 = 0 V, 1.8 V, or VCC
UVLO
Under Voltage Lock Out
VCC = rising and falling
RON
ON-state resistance
VI/O = 0 V to VCC
ISINK = 8 mA
Refer to ON-State Resistance Figure
6
18
Ω
ΔRON
ON-state resistance match
between channels
VI/O = 0 V to VCC
ISINK = 8 mA
Refer to ON-State Resistance Figure
0.07
0.5
Ω
RON (FLAT)
ON-state resistance flatness
VI/O = 0 V to VCC
ISINK = 8 mA
Refer to ON-State Resistance Figure
2.5
7
Ω
ICC
1.65
V
DC Characteristics
(1)
Not tested for DGS package due to absence of FLT and OE pin.
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Electrical Characteristics (continued)
TA = –40°C to +125°C , VCC = 2.3 V to 5.5 V, GND = 0V, Typical values are at VCC = 3.3 V, TA = 25°C, (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
3.6
10
µA
VCOM1/2 = 5.5 V (2)
VCC = 5.5 V
VNC1/2 or VNO1/2 = 5.5 V
Refer to Off Leakage Figure
3
µA
VCOM1/2 = 3.6 V (2)
VCC = 3.3 V
VNC1/2 or VNO1/2 = 3.6 V
Refer to Off Leakage Figure
2
µA
VCOM1/2 = 5.5 V
VCC = 0 V
VNC1/2 or VNO1/2 = 5.5 V
Refer to Off Leakage Figure
15
µA
VCOM1/2 = 3.6 V
VCC = 0 V
VNC1/2 or VNO1/2 = 3.6 V
Refer to Off Leakage Figure
10
uA
VCOM1/2 = 1 V
VCC = 0 V
VNC1/2 or VNO1/2 = 1 V
Refer to Off Leakage Figure
2
uA
165
185
µA
1.2
3.5
µA
11.5
µA
VCOM1/2 = 0 V to 5.5 V (2)
VCC = 2.3 V to 5.5 V
VNC1/2 or VNO1/2 = 5.5 V or 0 V
Refer to Off Leakage Figure
IOFF
I/O pin OFF leakage current
VCOM1/2 = 18 V
VCC = 0 V, 5.5 V
VNC1/2 or VNO1/2 = 0 V
Refer to Off Leakage Figure
UNIT
VCOM1/2 = 5.5 V
ION
ON leakage current
VCC = 5.5 V
VNC1/2 and VNO1/2 = high-Z
Refer to On Leakage Figure
VCOM1/2 = 0 V to 5.5 V
VCC = 2.3-5.5 V
VNC1/2 and VNO1/2 = high-Z
Refer to On Leakage Figure
Digital Characteristics
VIH
Input logic high
SEL1, SEL2, OE
VIL
Input logic low
SEL1, SEL2, OE
0.5
V
VOL
Output logic low
FLT
IOL = 3 mA
0.3
V
IIH
Input high leakage current
SEL1, SEL2, OE = 1.8 V, VCC
-1
2
5
μA
IIL
Input low leakage current
SEL1, SEL2, OE = 0 V
-1
±0.2
1
μA
RPD
Internal pull-down resistor on SEL1, SEL2
digital input pins
OE
6
12
MΩ
3
6
MΩ
CI
(3)
Digital input capacitance
1.45
SEL1, SEL2 = 0 V, 1.8 V or VCC
f = 1 MHz
V
8
pF
Protection and Detection
VOVP_TH
VOVP_HYST
(2)
(3)
6
OVP positive threshold
(3)
OVP threshold hysteresis
5.55
5.8
6.0
V
40
100
300
mV
Not tested on COM1/2 pins for DGS package due to the absence of OE pin
Specified by design, not tested in production.
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Electrical Characteristics (continued)
TA = –40°C to +125°C , VCC = 2.3 V to 5.5 V, GND = 0V, Typical values are at VCC = 3.3 V, TA = 25°C, (unless otherwise
noted)
PARAMETER
TSD_HYST (3)
Thermal Shutdown
Hysteresis
TOTD_TH (3)
Overtemperature detection
threshold
VCLAMP_V (3)
tEN_OVP
(3)
tREC_OVP (3)
TEST CONDITIONS
Maximum voltage to appear
on NC1/2 and NO1/2 pins
during OVP scenario
MIN
TYP
MAX
UNIT
3
8
°C
135
165
°C
VCOM1/2 = 0 to 18 V
tRISE and tFALL(10% to 90 %) = 100 ns
RL = Open
Switch on or off
OE = 0 V
0
9.6
V
VCOM1/2 = 0 to 18 V
tRISE and tFALL(10% to 90 %) = 100 ns
RL = 50Ω
Switch on or off
OE = 0 V
0
9.0
V
OVP enable time
RPU = 10 kΩ to VCC (FLT)
CL = 35 pF
Refer to OVP Timing Diagram Figure
0.6
3
μs
OVP recovery time
RPU = 10 kΩ to VCC (FLT)
CL = 35 pF
Refer to OVP Timing Diagram Figure
1.5
5
μs
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6.6 Dynamic Characteristics
TA = –40°C to +125°C , VCC = 2.3 V to 5.5V, GND = 0V, Typical values are at VCC = 3.3 V, TA = 25°C, (unless otherwise
noted)
PARAMETER (1)
TEST CONDITIONS
OISO
TYP
MAX
UNIT
1.2
4.0
6.2
pF
COM1, COM2 off capacitance
NC1, NO1, NC2, NO2 off
capacitance
VCOM1/2 = 0 or 3.3 V,
OE = VCC or OE = 0V with SEL1, Switch OFF or
SEL2 (switch not selected)
not selected
f = 240 MHz
1.2
4.0
6.2
pF
COM1, COM2, NC1, NO1, NC2,
NO2 on capacitance
VCOM1/2 = 0 or 3.3 V,
f = 240 MHz
Switch ON
1.4
4.0
6.2
pF
RL = 50 Ω
CL = 5 pF
f = 100 kHz
Refer to Off Isolation Figure
Switch OFF
-80
dB
RL = 50 Ω
CL = 5 pF
f = 240 MHz
Refer to Off Isolation Figure
Switch OFF
-22
dB
Switch ON
-90
dB
COFF
CON
MIN
VCOM1/2 = 0 or 3.3 V,
OE = VCC
f = 240 MHz
Differential off isolation
Switch OFF
XTALK
Channel to Channel crosstalk
RL = 50 Ω
CL = 5 pF
f = 100 kHz
Refer to Crosstalk Figure
BW
Bandwidth
RL = 50 Ω; Refer to BW and
Insertion Loss Figure
Switch ON
1.2
GHz
ILOSS
Insertion loss
RL = 50 Ω
f = TBD MHz; Refer to BW and
Insertion Loss Figure
Switch ON
-0.8
dB
(1)
Specified by design, not tested in production.
6.7 Timing Requirements
TA = –40°C to +125°C , VCC = 2.3 V to 5.5V, GND = 0V, Typical values are at VCC = 3.3 V, TA = 25°C, (unless otherwise
noted)
PARAMETER (1)
TEST CONDITIONS
tswitch
Switching time between channels
(SEL1, SEL2 to output)
VNC = 0.8 V
Refer to Tswitch Timing Figure
ton
Device turn on time (OE to output)
VNC = 0.8 V
Refer to Ton and Toff Figure
VNC = 0.8 V
Refer to Ton and Toff Figure
MIN
RL = 50 Ω,
CL = 5 pF,
VCC = 2.3 V to 5.5 V
NOM
MAX
UNIT
0.9
1
µs
200
250
µs
1
10
µs
250
µs
toff
Device turn off time (OE to output)
toff_Vcc
Device turn off time VCC to Switch
off
tSK(P)
Skew of opposite transitions of
same output (between COM1 and
COM2) (1)
VCOM1/2 = VCC
Refer to Tsk Figure
RL = 50 Ω,
CL = 1 pF,
VCC = 2.3 V to 5.5 V
9
50
ps
tpd
Propagation delay (1)
VCOM1/2 = VCC
Refer to Tpd Figure
RL = 50 Ω,
CL = 5 pF,
VCC = 2.3 V to 5.5 V
130
200
ps
(1)
8
VNC = 0.8 V
Refer to Ton and Toff Figure
Ramp rate VCC = 2.3 V to 0 V
250µs
Specified by design, not tested in production.
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10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
100k
-60
-65
Magnitude (dB)
Magnitude (dB)
6.8 Typical Characteristics
-70
-75
-80
1M
10M
100M
Frequency (Hz)
1G
10G
-85
1M
10M
Frequency (Hz)
TMUX
D003
Figure 1. Off-Isolation vs Frequency
TMUX
D001
Figure 2. Xtalk vs Frequency
0
-1
Gain (dB)
-2
-3
-4
-5
-6
1M
10M
100M
Frequency (Hz)
1G
TMUX
D001
Figure 3. Bandwidth and Insertion Loss vs Frequency
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7 Parameter Measurement Information
V
VI/O
ISINK
Switch
Channel ON, RON = V/ISINK
Figure 4. ON-State Resistance (RON)
VCOM
VNC/NO
A
A
Switch
Figure 5. Off Leakage
VCOM
A
Switch
Figure 6. On Leakage
VNC
VCOM
CL
RL
VNO
SEL
VSEL
1.8 V
VSEL
0.8 V
1.2 V
0V
tSWITCH
tSWITCH
VCOM
90 %
VNC
10 %
0V
(1)
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 500
ps, tf < 500 ps.
(2)
CL includes probe and jig capacitance.
Figure 7. tSWITCH Timing
10
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Parameter Measurement Information (continued)
VNC
VCOM
CL
2.3 V
VCC
VNO
1.8 V
0.8 V
VOE
RL
1.2 V
0V
OE
tOFF
tON
90 %
VOE
VCOM
10 %
VNC/NO
0V
(1)
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 500
ps, tf < 500 ps.
(2)
CL includes probe and jig capacitance.
Figure 8. tON, tOFF for OE
Network Analyzer
50 O
Switch
VCOM1
50 O
Source
Signal
50 O
VCOM2
50 O
Source
Signal
50 O
50 O
Figure 9. Off Isolation
Network Analyzer
50
Switch
VCOM1
50
Source
Signal
50
VCOM2
50
50
50
Figure 10. Cross Talk
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Parameter Measurement Information (continued)
Network Analyzer
Switch
50
VCOM1
50
Source
Signal
50
VCOM2
50
Source
Signal
50
50
Figure 11. BW and Insertion Loss
VCOM
VPOS_THLD
VCOM
18 V
0V
CL
OE
RL
tEN_OVP
tREC_OVP
VOE
VCC
FLT
10 %
10 %
0V
Figure 12. tEN_OVP and tDIS_OVP Timing Diagram
Switch
VCOM
0.4 V
50
50 %
VCOM
50 %
0V
50
tPD
tPD
VNC/NO
50 %
0.4 V
50 %
0V
(1)
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 500
ps, tf < 500 ps.
(2)
CL includes probe and jig capacitance.
Figure 13. tPD
12
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Parameter Measurement Information (continued)
Switch
VCOM1
VNC1
50 O
0.4 V
VCOM1/2
0V
0.4 V
50 O
VCOM2
VNC2
VNC1
VNC2
50 %
0V
tSK
50 O
50 O
50 %
tSK
50 %
0.4 V
50 %
0V
(1)
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 500
ps, tf < 500 ps.
(2)
CL includes probe and jig capacitance.
Figure 14. tSK
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8 Detailed Description
8.1 Overview
The TMUX1072 is a high speed, 2-channel 2:1 analog switch with overvoltage protection. The device is
bidirectional and can be used as a dual 2:1 or 1:2 switch, but OVP only applies to the COM pins. The device also
contains a fault indicator pin which can signal to the system of either an over voltage or over temperature event.
The device maintains excellent signal integrity through the optimization of both RON and BW while protecting the
system with up to 18 V OVP protection. The OVP implementation is designed to protect sensitive system
components behind the switch that cannot survive fault conditions.
8.2 Functional Block Diagram
VCC
SEL1
6M
SEL2
Control
Logic
6M
FLT
OE
3M
VOVP
OVP
VNC1
VCOM1
VNC2
VNO1
VCOM2
VNO2
Switches
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8.3 Feature Description
8.3.1 Powered-off Protection
When the TMUX1072 is powered off the I/Os of the device remain in a high-Z state. The crosstalk, off-isolation,
and leakage remain within the Electrical Specifications
This prevents errant voltages from reaching the rest of the system and maintains isolation when the system is
powering up.
8.3.2 Overvoltage Detection
When a voltage on the COM pin exceeds the VOVP_TH, the open drain output FLTpin pulls the pin low to indicate
an overvoltage event has been detected. The open drain output will release the FLT pin when the voltage on the
COM pin returns below the VOVP_TH.
8.3.3 Overtemperature Detection
When the junction temperature of the device exceeds the overtemperature detection threshold TOTD_TH, the open
drain output FLT pin pulls the pin low to indicate an overtemperature event has been detected. The open drain
output releases the FLT pin when the junction temperature returns below the TOTD_TH.
8.3.4 Overvoltage Protection
The OVP of the TMUX1072 is designed to protect the system from overvoltage conditions up to 18 V on the
COM1 and COM2 pins. This protection is valid even if Vcc = 0V. Figure 15 depicts an event where up to 18 V
could appear on COM1 and COM2 that could pass through the device and damage components behind the
device.
Device 1
Existing Solutions
COM1
NC1
NO1
COM2
NC2
NO2
Device 2
Figure 15. Existing Solution Being Damaged by a Short, 18 V
The TMUX1072 opens the switches and protect the rest of the system by blocking the 18 V as depicted in
Figure 16.
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Feature Description (continued)
18 V does not reach
rest of system
Device 1
NC1
COM1
NO1
NC2
COM2
NO2
USB
Device
2
Figure 16. Protecting During a 18-V Short
Figure 17 is a waveform showing the voltage on the pins during an overvoltage scenario.
18 V
VOVP_THLD
COM1/COM2
0V
NO1/NO2 or
NC1/NC2
0V
FLT
Figure 17. Overvoltage Protection Waveform, 18 V
8.4 Device Functional Modes
8.4.1 Pin Functions
Table 1. Function Table
16
OE
SEL1
SEL2
COM1 Connection
H
X
X
High-Z
High-Z
L
L
L
COM1 to NC1
COM2 to NC2
L
L
H
COM1 to NC1
COM2 to NO2
L
H
L
COM1 to NO1
COM2 to NC2
L
H
H
COM1 to NO1
COM2 to NO2
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COM2 Connection
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
There are many applications in which processors and microcontrollers have a limited number of I/Os. This IC can
effectively expand the limited number of I/Os by switching between multiple signal paths in order to interface
them to a single processor or microcontroller. The device can also be used to connect a single microcontroller to
two signal paths. With independent control of the two switches using SEL1 and SEL2, TMUX1072 can be used
to cross switch single ended signals.
9.2 Typical Application
The TMUX1072 is used to switch signals between the high speed signal paths that may be exposed to a
connector or near a bus which could experience an overvoltage condition. The TMUX1072 has internal pull-down
resistors on SEL1, SEL2, and OE. The pull-down on SEL1 and SEL2 pins ensure the NC1/NC2 channel is
selected by default. The pull-down on OE enables the switch when power is applied.
TMUX1072
Device 1
VCC
OVP
NC1
COM1
NO1
NC2
COM2
NO2
SEL1
Device 2
SEL2
OE
Logic
Control
FLT
GND
Figure 18. Typical TMUX1072 Application
9.2.1 Design Requirements
The TMUX1072 has internal pull-down resistors on SEL1, SEL2, and OE, so no external resistors are required
on the logic pins. The internal pull-down resistor on SEL1 and SEL2 pins ensures the NC1 and NC2 channels
are selected by default. The internal pull-down resistor on OE enables the switch when power is applied to VCC.
The FLT indicator output pin is an open drain output that will require an external pull-up resistor for the
overvoltage and overtemperature condition to be detected. If feature is unused, FLT pin may be left floating or
connected to ground
9.2.2 Detailed Design Procedure
The TMUX1072 can be properly operated without any external components. However, TI recommends that
unused signal pins must be connected to ground through a 50-Ω resistor to prevent signal reflections back into
the device. TI does recommend a 100-nF bypass capacitor placed close to TMUX1072 VCC pin.
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Typical Application (continued)
9.2.3 Application Curves
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin of an on-channel, and the output is measured at the drain pin of the TMUX1072. Figure 19
shows the bandwidth of TMUX1072.
0
-1
Gain (dB)
-2
-3
-4
-5
-6
1M
10M
100M
Frequency (Hz)
1G
TMUX
D001
Figure 19. Bandwidth and Insertion Loss vs Frequency
10 Power Supply Recommendations
Power to the device is supplied through the VCC pin. TI recommends placing a 100-nF bypass capacitor as
close to the supply pin VCC as possible to help smooth out lower frequency noise to provide better load
regulation across the frequency spectrum.
11 Layout
11.1 Layout Guidelines
1. Place supply bypass capacitors as close to VCC pin as possible and avoid placing the bypass caps near the
signal traces.
2. The high-speed traces should always be of equal length and must be no more than 4 inches; otherwise, the
eye diagram performance may be degraded.
3. Route the high-speed signals using a minimum of vias and corners which will reduce signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the transmission line of the signal and increases the
chance of picking up interference from the other layers of the board. Be careful when designing test points
on twisted pair lines; through-hole pins are not recommended.
4. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
5. Do not route signal traces under or near crystals, oscillators, clock signal generators, switching regulators,
mounting holes, magnetic devices, or IC’s that use or duplicate clock signals.
6. Avoid stubs on the high-speed signals because they cause signal reflections.
7. Route all high-speed signal traces over continuous planes (VCC or GND), with no interruptions.
8. Avoid crossing over anti-etch, commonly found with plane splits.
9. For high frequency systems, a printed circuit board with at least four layers is recommended: two signal
layers separated by a ground layer and a power layer. The majority of signal traces should run on a single
layer, preferably Signal 1. Immediately next to this layer should be the GND plane, which is solid with no
cuts. Avoid running signal traces across a split in the ground or power plane. When running across split
planes is unavoidable, sufficient decoupling must be used. Minimizing the number of signal vias reduces EMI
by reducing inductance at high frequencies. For more information on layout guidelines, see High Speed
Layout Guidelines (SCAA082)
18
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11.2 Layout Example
LEGEND
VIA to Power Plane
Polygonal Copper Pour
VIA to GND Plane
12
1 SEL1
FLT
COM1 11
2 NO1
NC1 10
3 GND
VCC 9
4 NO2
NC2 8
Vcc
5 SEL2
COM2
Bypass Capacitor
7
OE
6
Not to scale
Figure 20. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• High-Speed Layout Guidelines Application Report
• High-Speed Interface Layout Guidelines
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMUX1072DGSR
ACTIVE
VSSOP
DGS
10
2500
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1A9
TMUX1072RUTR
ACTIVE
UQFN
RUT
12
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1BU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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