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TMUX6104
SCDS376A – FEBRUARY 2018 – REVISED SEPTEMBER 2018
TMUX6104 36-V, Low-Capacitance, Low-Leakage-Current,
Precision, 4:1 Analog Multiplexer
1 Features
3 Description
•
•
•
•
•
The TMUX6104 is a modern complementary metaloxide semiconductor (CMOS) analog multiplexer
(MUX) that offers 4:1 single-ended multiplexing. The
devices work well with dual supplies (±5 V to ±16.5
V), a single supply (10 V to 16.5 V), or unsymmetric
supplies (such as VDD = 12 V, VSS = –5 V). All digital
inputs
have
transistor-transistor
logic
(TTL)
compatible thresholds, ensuring both TTL and CMOS
logic compatibility.
1
•
•
•
•
•
•
•
•
Low On-Capacitance: 5 pF
Low Input Leakage: 5 pA
Low Charge Injection: 0.35 pC
Rail-to-Rail Operation
Wide Supply Range: ±5 V to ±16.5 V (Dual
Supplies) or 10 V to 16.5 V (Single Supply)
Low On-Resistance: 125 Ω
Transition Time: 88 ns
Break-Before-Make Switching Action
EN Pin Connectable to VDD With Integrated Pulldown
Logic Levels: 2 V to VDD
Low Supply Current: 17 µA
ESD Protection HBM: 2000 V
Industry-Standard TSSOP Package
2 Applications
•
•
•
•
•
•
Factory Automation and Industrial Process
Controls
Programmable Logic Controllers (PLC)
Analog Input Modules
ATE Test Equipment
Digital Multimeters
Battery Monitoring Systems
The TMUX6104 multiplexes one of four inputs (Sx) to
a common output (D), depending on the status of the
address pins (A0/ A1) and the enable pin (EN). Each
switch conducts equally well in both directions in the
ON position and supports input signal range up to the
supplies. In the OFF condition, signal levels up to the
supplies are blocked. All switches exhibit breakbefore-make (BBM) switching action.
The TMUX6104 device is part of Texas Instruments
Precision Switches and Multiplexers family. The
family of devices have very low leakage current and
charge injection, allowing them to be used in highprecision measurement applications. Low supply
current of 17 μA enables the device's usage in
portable applications.
Device Information(1)
PART NUMBER
TMUX6104
PACKAGE
TSSOP (14)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Simplified Schematic
Bridge Sensor
Thermocouple
+
GND
PGA
...
Multiplexer
Gain / Filter
Network
ADC
-
Current
Sensing
TMUX6104
Photo
LED Detector
Optical Sensor
Analog Inputs
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUX6104
SCDS376A – FEBRUARY 2018 – REVISED SEPTEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
4
5
6
6
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Thermal Information ..................................................
Recommended Operating Conditions.......................
Electrical Characteristics (Dual Supplies: ±15 V) .....
Switching Characteristics (Dual Supplies: ±15 V).....
Electrical Characteristics (Single Supply: 12 V)........
Switching Characteristics (Single Supply: 12 V).......
Typical Characteristics ..............................................
7
Parameter Measurement Information ................ 11
8
Detailed Description ............................................ 12
7.1 Truth Table.............................................................. 11
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 18
8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 20
9
Application and Implementation ........................ 21
9.1 Application Information............................................ 21
9.2 Typical Application ................................................. 21
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 Device and Documentation Support ................. 25
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (February 2018) to Revision A
•
2
Page
Changed the device status From: Advanced Information To: Production data...................................................................... 1
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SCDS376A – FEBRUARY 2018 – REVISED SEPTEMBER 2018
5 Pin Configuration and Functions
PW Package
14-Pin TSSOP
Top View
A0
1
14
A1
EN
2
13
GND
VSS
3
12
VDD
S1
4
11
S3
S2
5
10
S4
D
6
9
NC
NC
7
8
NC
Not to scale
Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
A0
1
I
Address line 0
A1
14
I
Address line 1
D
6
I/O
EN
2
I
Active high digital input. When this pin is low, all switches are turned off. When this pin is
high, the A0 and A1 logic inputs determine which switch is turned on.
GND
Drain pin. Can be an input or output.
13
P
Ground (0 V) reference
NC
7, 8, 9
No Connect
No internal connection
S1
4
I/O
Source pin 1. Can be an input or output.
S2
5
I/O
Source pin 2. Can be an input or output.
S3
11
I/O
Source pin 3. Can be an input or output.
S4
10
I/O
Source pin 4. Can be an input or output.
VDD
12
P
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and
GND.
VSS
3
P
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a
decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
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TMUX6104
SCDS376A – FEBRUARY 2018 – REVISED SEPTEMBER 2018
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VDD to VSS
VDD to GND
Supply voltage
VSS to GND
UNIT
36
V
–0.3
18
V
–18
0.3
V
GND –0.3
VDD+0.3
V
VDIG
Digital input pin (EN, A0, A1) voltage
IDIG
Digital input pin (EN, A0, A1) current
–30
30
VANA_IN
Analog input pin (Sx) voltage
VSS–0.3
VDD+0.3
IANA_IN
Analog input pin (Sx) current
–30
30
VANA_OUT
Analog output pin (D) voltage
VSS–0.3
VDD+0.3
IANA_OUT
Analog output pin (D) current
–30
30
mA
TA
Ambient temperature
–55
125
°C
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
–65
mA
V
mA
V
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Thermal Information
TMUX6104
THERMAL METRIC (1)
PW (TSSOP)
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
122.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
52.0
°C/W
RθJB
Junction-to-board thermal resistance
65.4
°C/W
ΨJT
Junction-to-top characterization parameter
8.1
°C/W
ΨJB
Junction-to-board characterization parameter
64.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD to VSS
(1)
NOM
MAX
UNIT
Power supply voltage differential
10
33
V
VDD to GND
Positive power supply voltage (singlle supply, VSS = 0 V)
10
16.5
V
VDD to GND
Positive power supply voltage (dual supply)
5
16.5
V
VSS to GND
Negative power supply voltage (dual supply)
–5
–16.5
V
(1)
4
VDD and VSS can be any value as long as 10 V ≤ (VDD – VSS) ≤ 33 V.
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SCDS376A – FEBRUARY 2018 – REVISED SEPTEMBER 2018
Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
VS
(2)
NOM
MAX
UNIT
Source pins voltage
VSS
VDD
V
VD
Drain pin voltage
VSS
VDD
V
VDIG
Digital input pin (EN, A0, A1) voltage
0
VDD
V
ICH
Channel current (TA = 25°C )
–25
25
mA
TA
Ambient temperature
–40
125
°C
MAX
UNIT
VDD
V
125
170
Ω
145
200
Ω
TA = –40°C to +85°C
230
Ω
TA = –40°C to +125°C
250
Ω
(2)
VS is the voltage on all the S pins.
6.5 Electrical Characteristics (Dual Supplies: ±15 V)
at TA = 25°C, VDD = 15 V, and VSS = -15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
ANALOG SWITCH
VA
Analog signal range
TA = –40°C to +125°C
VSS
VS = 0 V, IS = 1 mA
RON
On-resistance
VS = ±10 V, IS = 1 mA
1.5
ΔRON
On-resistance mismatch
between channels
VS = ±10 V, IS = 1 mA
6
Ω
TA = –40°C to +85°C
9
Ω
TA = –40°C to +125°C
11
Ω
45
Ω
53
Ω
58
Ω
26
RON_FLAT
RON_DRIFT
IS(OFF)
ID(OFF)
ID(ON)
On-resistance flatness
On-resistance drift
Source off leakage current (1)
Drain off leakage current (1)
Drain on leakage current
VS = –10 V, 0 V, +10 V, IS
TA = –40°C to +85°C
= 1 mA
TA = –40°C to +125°C
VS = 0 V
Ω/°C
0.5
–0.02
Switch state is off, VS =
+10 V/ –10 V, VD = –10
V/ + 10 V
TA = –40°C to +85°C
Switch state is off, VS =
+10 V/ –10 V, VD = –10
V/ +10 V
TA = –40°C to +85°C
Switch state is on, VS =
+10 V/ –10 V, VD = –10
V/ +10 V
TA = –40°C to +85°C
TA = –40°C to +125°C
0.02
nA
–0.13
0.05
nA
–1
0.5
nA
–0.05
TA = –40°C to +125°C
0.005
0.05
nA
–0.14
0.1
nA
–1
0.5
nA
0.07
nA
0.15
nA
–0.07
0.01
0.01
–0.27
TA = –40°C to +125°C
–2
2
1
nA
DIGITAL INPUT (EN, Ax pins)
VIH
Logic voltage high
TA = –40°C to +125°C
VIL
Logic voltage low
TA = –40°C to +125°C
RPD(EN)
Pull-down resistance on EN pin
V
0.8
6
V
MΩ
POWER SUPPLY
17
IDD
VDD supply current
VA = 0 V or 3.3 V, VS = 0
V, VEN = 3.3 V
24
µA
25
µA
27
µA
12
µA
TA = –40°C to +85°C
13
µA
TA = –40°C to +125°C
15
µA
TA = –40°C to +85°C
TA = –40°C to +125°C
7
ISS
(1)
VSS supply current
VA = 0 V or 3.3 V, VS = 0
V, VEN = 3.3 V
When VS is positive, VD is negative, and vice versa.
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6.6 Switching Characteristics (Dual Supplies: ±15 V)
at TA = 25°C, VDD = 15 V, and VSS = -15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VS = ±10 V, RL = 300 Ω , CL = 35 pF
tON
Enable turn-on time
Enable turn-off time
Transition time
130
ns
VS = ±10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
140
ns
65
ns
VS = ±10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+85°C
70
ns
VS = ±10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
75
ns
125
ns
VS = 10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+85°C
135
ns
VS = 10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
145
ns
53
88
VS = 10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
Break-before-make time delay
QJ
Charge injection
OISO
Off-isolation
RL = 50 Ω , CL = 5 pF, f = 1 MHz
XTALK
Channel-to-channel crosstalk
RL = 50 Ω , CL = 5 pF, f = 1 MHz, non-adjacent
channels
IL
Insertion loss
30
50
ns
VS = 0 V, RS = 0 Ω , CL = 1 nF
–0.35
pC
VS = –15 V to 15 V, RS = 0 Ω , CL = 1 nF
–0.41
pC
–86
dB
–105
dB
–87
dB
–7
dB
RL = 10 kΩ , CL = 5 pF, VPP= 0.62 V on VDD, f= 1
MHz
–52
dB
RL = 10 kΩ , CL = 5 pF, VPP= 0.62 V on VSS, f= 1
MHz
–49
dB
RL = 50 Ω , CL = 5 pF, f = 1 MHz, adjacent channels
AC Power Supply Rejection
Ratio
85
ns
tBBM
ACPSRR
UNIT
120
VS = 10 V, RL = 300 Ω , CL = 35 pF
tTRAN
MAX
VS = ±10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+85°C
VS = ±10 V, RL = 300 Ω , CL = 35 pF
tOFF
TYP
RL = 50 Ω , CL = 5 pF, f = 1 MHz
BW
-3dB Bandwidth
RL = 50 Ω , CL = 5 pF
500
MHz
THD + N
Total harmonic distortion +
noise
RL = 10k Ω , CL = 5 pF, f= 20Hz to 20kHz
0.08
%
CIN
Digital input capacitance
VIN = 0 V or VDD
1.2
pF
CS(OFF)
Source off-capacitance
VS = 0 V, f = 1 MHz
1.6
2.3
pF
CD(OFF)
Drain off-capacitance
VS = 0 V, f = 1 MHz
3.8
4.2
pF
CS(ON),
CD(ON)
Source and drain oncapacitance
VS = 0 V, f = 1 MHz
5.0
6.5
pF
TYP
MAX
6.7 Electrical Characteristics (Single Supply: 12 V)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
UNIT
ANALOG SWITCH
VA
Analog signal range
TA = –40°C to +125°C
TA = –40°C to +125°C
VSS
VDD
V
345
Ω
TA = –40°C to +85°C
400
Ω
TA = –40°C to +125°C
440
Ω
12
Ω
TA = –40°C to +85°C
19
Ω
TA = –40°C to +125°C
23
235
RON
On-resistance
VS = 10 V, IS = 1 mA
2.4
On-resistance mismatch
between channels
ΔRON
RON_DRIFT
6
On-resistance drift
VS = 10 V, IS = 1 mA
VS = 0 V
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0.47
Ω
%/°C
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SCDS376A – FEBRUARY 2018 – REVISED SEPTEMBER 2018
Electrical Characteristics (Single Supply: 12 V) (continued)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
IS(OFF)
Source off leakage current (1)
TEST CONDITIONS
Switch state is off, VS =
T = –40°C to +85°C
10 V/ 1 V, VD = 1 V/ 10 V A
TA = –40°C to +125°C
MIN
TYP
MAX
UNIT
–0.02
0.005
0.02
nA
–0.1
0.05
nA
–0.8
0.4
nA
–0.03
ID(OFF)
Drain off leakage current (1)
Switch state is off, VS =
T = –40°C to +85°C
10 V/ 1 V, VD = 1 V/ 10 V A
TA = –40°C to +125°C
0.03
nA
–0.1
0.08
nA
–0.8
0.4
nA
0.05
nA
–0.05
ID(ON)
Drain on leakage current
Switch state is on, VS =
floating, VD = 1 V/ 10 V
0.01
0.01
TA = –40°C to +85°C
–0.2
0.15
nA
TA = –40°C to +125°C
–1.6
0.8
nA
2
DIGITAL INPUT (EN, Ax pins)
VIH
Logic voltage high
TA = –40°C to +125°C
VIL
Logic voltage low
TA = –40°C to +125°C
RPD(EN)
Pull-down resistance on EN pin
V
0.8
6
V
MΩ
POWER SUPPLY
12
IDD
(1)
VDD supply current
VA = 0 V or 3.3 V, VS = 0
V , VEN = 3.3 V
18
µA
TA = –40°C to +85°C
19
µA
TA = –40°C to +125°C
21
µA
When VS is positive, VD is negative, and vice versa.
6.8 Switching Characteristics (Single Supply: 12 V)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VS = 8 V, RL = 300 Ω , CL = 35 pF
tON
Enable turn-on time
Enable turn-off time
Transition time
UNIT
91
125
ns
135
ns
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
145
ns
60
ns
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+85°C
52
70
ns
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
77
ns
127
ns
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+85°C
140
ns
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
150
ns
VS = 8 V, RL = 300 Ω , CL = 35 pF
tTRAN
MAX
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+85°C
VS = 8 V, RL = 300 Ω , CL = 35 pF
tOFF
TYP
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
tBBM
Break-before-make time delay
QJ
Charge injection
OISO
Off-isolation
XTALK
Channel-to-channel crosstalk
RL = 50 Ω , CL = 5 pF, f = 1 MHz, non-adjacent
channels
IL
Insertion loss
94
30
55
ns
VS = 6 V, RS = 0 Ω , CL = 1 nF
–0.2
pC
VS = 0 V to 12 V, RS = 0 Ω , CL = 1 nF
–0.2
pC
RL = 50 Ω , CL = 5 pF, f = 1 MHz
–86
dB
–107
dB
RL = 50 Ω , CL = 5 pF, f = 1 MHz, adjacent channels
–87
dB
RL = 50 Ω , CL = 5 pF, f = 1 MHz
–14
dB
ACPSRR
AC Power Supply Rejection
Ratio
RL= 10 kΩ , CL = 5 pF, VPP= 0.62 V, f= 1 MHz
–51
dB
BW
-3dB Bandwidth
RL = 50 Ω , CL = 5 pF
400
MHz
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TMUX6104
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www.ti.com
Switching Characteristics (Single Supply: 12 V) (continued)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CIN
Digital input capacitance
VIN = 0 V or VDD
1.2
CS(OFF)
Source off-capacitance
VS = 6 V, f = 1 MHz
1.9
2.3
pF
CD(OFF)
Drain off-capacitance
VS = 6 V, f = 1 MHz
4.6
5.3
pF
CS(ON),
CD(ON)
Source and drain oncapacitance
VS = 6 V, f = 1 MHz
6.3
7.5
pF
8
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6.9 Typical Characteristics
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
700
250
600
VDD= 12V
VSS = -12V
VDD= 13.5V
VSS = -13.5V
On Resistance (:)
On Resistance (:)
200
150
100
VDD= 15V
VSS = -15V
50
0
-20
-15
VDD= 16.5V
VSS = -16.5V
-10
-5
0
5
10
Source or Drain Voltage (V)
15
VDD= 5V
VSS = -5V
500
VDD= 6V
VSS = -6V
400
300
200
VDD= 7V
VSS = -7V
100
0
-8
20
-6
-4
D001
TA = 25°C
-2
0
2
4
Source or Drain Voltage (V)
6
8
D002
TA = 25°C
Figure 1. On-Resistance vs Source or Drain Voltage
Figure 2. On-Resistance vs Source or Drain Voltage
700
250
TA= 125qC
TA= 85qC
200
VDD= 10V
VSS = 0V
500
On Resistance (:)
On Resistance (:)
600
VDD= 12V
VSS = 0V
400
300
200
150
100
TA= 25qC
50
VDD= 14V
VSS = 0V
100
TA= -40qC
0
0
2
4
6
8
10
Source or Drain Voltage (V)
12
0
-20
14
-15
D003
TA = 25°C
15
20
D004
VDD = 15 V, VSS = –15 V
Figure 3. On-Resistance vs Source or Drain Voltage
Figure 4. On-Resistance vs Source or Drain Voltage
700
800
TA = 125qC
600
600
TA = 85qC
500
Leakage Current (pA)
On Resistance (:)
-10
-5
0
5
10
Source or Drain Voltage (V)
400
300
200
TA = -40qC
100
0
2
4
6
8
Source or Drain Voltage (V)
10
12
ID(OFF)+
IS(OFF)+
200
0
-200
IS(OFF)-
-400
ID(OFF)-
-600
TA = 25qC
0
ID(ON)+
400
ID(ON)-
-800
-50
-25
D005
VDD = 12 V, VSS = 0 V
0
25
50
75
100
Ambient Temperature (qC)
125
150
D006
VDD = 15 V, VSS = –15 V
Figure 5. On-Resistance vs Source or Drain Voltage
Figure 6. Leakage Current vs Temperature
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Typical Characteristics (continued)
600
2
Leakage Current (pA)
200
IS(OFF)_10V
ID(ON)_10V
0
IS(OFF)_1V
-200
Charge Injection (pC)
ID(OFF)_10V
400
ID(OFF)_1V
1
VDD= 12V
VSS = 0V
VDD= 10V
VSS = -10V
0
-1
VDD= 15V
VSS = -15V
-400
ID(ON)_1V
-600
-50
-25
0
25
50
75
100
Ambient Temperature (qC)
125
-2
-15
150
-10
VDD = 12 V, VSS = 0 V
10
15
D008
Source-to-drain, TA = 25°C
Figure 7. Leakage Current vs Temperature
Figure 8. Charge Injection vs Source Voltage
9
150
6
VDD= 10V
VSS = -10V
3
CS (5 V/div)
Enable Turn On/Off Time (ns)
Charge Injection (pC)
-5
0
5
Source Voltage (V)
D007
0
-3
VOUT (5 V/div)
VDD= 15V
VSS = -15V
-6
-9
-15
-10
-5
VDD= 12V
VSS = 0V
tON(VDD= 15V, VSS= -15V)
90
60
30
tOFF(VDD= 15V, VSS= -15V)
0
5
Drain Voltage (V)
10
0
-50
15
tON(VDD= 12V, VSS= 0V)
120
-25
D009
0
tOFF(VDD= 12V, VSS= 0V)
25
50
75
100
Ambient Temperature (qC)
125
150
D010
Drain-to-source, TA = 25°C
Figure 10. Turn-On and Turn-Off Times vs Temperature
0
-20
-20
-40
-40
-60
Crosstalk (dB)
Off Isolation (dB)
Figure 9. Charge Injection vs Drain Voltage
0
Adjacent Channel to D
-80
Adjacent Channels
-80
-100
-100
Non-Adjacent Channel to D
-120
-140
1E+5
-60
1E+6
1E+7
Frequency (Hz)
1E+8
5E+8
-140
1E+5
D011
VDD = 15 V, VSS = –15 V, TA = 25°C
1E+6
1E+7
Frequency (Hz)
1E+8
5E+8
D012
VDD = 15 V, VSS = –15 V, TA = 25°C
Figure 11. Off Isolation vs Frequency
10
Non-Adjacent Channels
-120
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Figure 12. Crosstalk vs Frequency
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Typical Characteristics (continued)
-5
100
-10
Insertion Loss (dB)
THD + N (%)
VDD= 15V
VSS= -15V
VDD= 5V
VSS= -5V
10
1
-15
-20
0.1
-25
0.01
1E+1
1E+2
1E+3
Frequency (Hz)
1E+4
-30
1E+5
1E+5
1E+6
1E+7
Frequency(Hz)
D013
TA = 25°C
1E+9
D014
VDD = 15 V, VSS = –15 V, TA = 25°C
Figure 13. THD+N vs Frequency
Figure 14. On Response vs. Frequency
10
10
CD(ON), CS(ON)
9
CS(ON), CD(ON)
8
Capactiance (pF)
8
Capactiance (pF)
1E+8
7
CD(OFF)
6
5
4
CS(OFF)
3
CD(OFF)
6
4
CS(OFF)
2
2
1
-15
0
-12
-9
-6
-3
0
3
6
Source Voltage (V)
9
12
15
0
2
4
D015
VDD = 15 V, VSS = –15 V, TA = 25°C
6
8
Source Voltage (V)
10
12
D016
VDD = 12 V, VSS = 0 V, TA = 25°C
Figure 15. Capacitance vs Source Voltage
Figure 16. Capacitance vs Source Voltage
7 Parameter Measurement Information
7.1 Truth Table
Table 1. TMUX6104 Truth Table
(1)
EN
A1
A0
STATE
0
X (1)
X (1)
All channels are off
1
0
0
Channel 1
1
0
1
Channel 2
1
1
0
Channel 3
1
1
1
Channel 4
X denotes don't care..
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8 Detailed Description
8.1 Overview
8.1.1 On-Resistance
The on-resistance of the TMUX6104 is the ohmic resistance across the source (Sx) and drain (D) pins of the
device. The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote onresistance. The measurement setup used to measure RON is shown in Figure 17. Voltage (V) and current (ICH)
are measured using this setup, and RON is computed as shown in Equation 1:
V
D
S
ICH
VS
Figure 17. On-Resistance Measurement Setup
RON = V / ICH
(1)
8.1.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF).
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF).
The setup used to measure both off-leakage currents is shown in Figure 18
ID (OFF)
Is (OFF)
A
S
D
VS
A
VD
Figure 18. Off-Leakage Measurement Setup
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Overview (continued)
8.1.3 On-Leakage Current
On-leakage current is defined as the leakage current that flows into or out of the drain pin when the switch is in
the on state. The source pin is left floating during the measurement. Figure 19 shows the circuit used for
measuring the on-leakage current, denoted by ID(ON).
ID (ON)
D
S
A
NC
NC = No Connection
VD
Figure 19. On-Leakage Measurement Setup
8.1.4 Transition Time
Transition time is defined as the time taken by the output of the TMUX6104 to rise (to 90% of the transition) or
fall (to 10% of the transition) after the digital address signal has fallen or risen to 50% of the transition. Figure 20
shows the setup used to measure transition time, denoted by the symbol tTRAN.
VDD
VSS
VSS
VDD
S1
VS1
S2
3V
SW
SW
Output
D
tr < 20 ns
VIN
50%
tf < 20 ns
50%
0V
VS
Output
S3
S4
VS4
0.9 VS
SW
300 Ÿ
EN
0.1 VS
tTRAN = max ( tTRAN 1, tTRAN 2)
35 pF
Ax
tTRAN 2
tTRAN 1
SW
2.0V
VIN
GND
Figure 20. Transition-Time Measurement Setup
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Overview (continued)
8.1.5 Break-Before-Make Delay
Break-before-make delay is a safety feature that prevents two inputs from connecting when the TMUX6104 is
switching. The TMUX6104 output first breaks from the on-state switch before making the connection with the
next on-state switch. The time delay between the break and the make is known as break-before-make delay.
Figure 21 shows the setup used to measure break-before-make delay, denoted by the symbol tBBM.
VDD
VSS
VSS
VDD
SW
S1
VS
3V
SW
S2
Output
D
VIN
SW
S3
0V
VS
Output
SW
S4
300 Ÿ
35 pF
Ax
0.8 VS
EN
tBBM 2
tBBM 1
2.0V
VIN
0V
GND
tBBM = min ( tBBM 1, tBBM 2)
Figure 21. Break-Before-Make Delay Measurement Setup
8.1.6 Turn-On and Turn-Off Time
Turn-on time is defined as the time taken by the output of the TMUX6104 to rise to a 90% final value after the
enable signal has risen to a 50% final value. Figure 22 shows the setup used to measure turn-on time. Turn-on
time is denoted by the symbol tON (EN).
Turn off time is defined as the time taken by the output of the TMUX6104 to fall to a 10% initial value after the
enable signal has fallen to a 50% initial value. Figure 22 shows the setup used to measure turn-off time. Turn-off
time is denoted by the symbol tOFF (EN).
VDD
VSS
VSS
VDD
VS
3V
S2
50%
VIN
Output
SW
Output
D
50%
S3
0V
VS
S1
SW
S4
SW
SW
300 Ÿ
35 pF
0.9 VS
tOFF (EN)
tON (EN)
Ax
0.1 VS
EN
GND
VIN
Figure 22. Turn-On and Turn-Off Time Measurement Setup
14
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Overview (continued)
8.1.7 Charge Injection
The TMUX6104 have a simple transmission-gate topology. Any mismatch in capacitance between the NMOS
and PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the
gate signal. The amount of charge injected into the source or drain of the device is known as charge injection,
and is denoted by the symbol QINJ. Figure 23 shows the setup used to measure charge injection from source
(Sx) to drain (D).
VDD
VSS
3V
VSS
VDD
VIN
S1
VS
0V
SW
SW
S2
NC
Output
VS
QINJ = CL ×
VOUT
NC
VOUT
D
Output
SW
S3
1 nF
SW
S4
NC
Ax
EN
2.0V
VIN
GND
Figure 23. Charge-Injection Measurement Setup
8.1.8 Off Isolation
Off isolation is defined as the voltage at the drain pin (D) of the TMUX6104 when a 1-VRMS signal is applied to
the source pin (Sx) of an off-channel. Figure 24 shows the setup used to measure off isolation. Use Equation 2
to compute off isolation.
VDD
VSS
Network Analyzer
VSS
VDD
S1
S2
SW
SW
NC
50 Ÿ
NC
VS
S3
S4
SW
SW
NC
VOUT
50 Ÿ
D
VIN
Ax
EN
2.0V
GND
Figure 24. Off Isolation Measurement Setup
Off Isolation
§V
·
20 ˜ Log ¨ OUT ¸
© VS ¹
(2)
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Overview (continued)
8.1.9 Channel-to-Channel Crosstalk
Channel-to-channel crosstalk is defined as the voltage at the source pin (Sx) of an off-channel, when a 1-VRMS
signal is applied at the source pin (Sx) of an on-channel. Figure 25 shows the setup used to measure, and
Equation 3 is the equation used to compute, channel-to-channel crosstalk.
VDD
VSS
Network Analyzer
VSS
VDD
SW
S1
SW
S2
VOUT
D
NC
VS
SW
S3
50 Ÿ
SW
S4
50 Ÿ
NC
Ax
VIN
EN
2.0V
GND
Figure 25. Channel-to-Channel Crosstalk Measurement Setup
Channel-to-Channel Crosstalk
§V
·
20 ˜ Log ¨ OUT ¸
© VS ¹
(3)
8.1.10 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied to the
source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the TMUX6104. Figure 26
shows the setup used to measure bandwidth of the mux. Use Equation 4 to compute the attenuation.
VDD
VSS
Network Analyzer
VSS
VDD
S1
S2
SW
SW
NC
NC
VS
S3
S4
SW
SW
NC
VOUT
50 Ÿ
D
VIN
Ax
EN
2.0V
GND
Figure 26. Bandwidth Measurement Setup
8176
)
85
#PPAJQ=PEKJ = 20 × .KC (
(4)
16
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Overview (continued)
8.1.11 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as the
ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the mux
output. The on-resistance of the TMUX6104 varies with the amplitude of the input signal and results in distortion
when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as
THD+N.
VDD
VSS
VSS
VDD
Audio Precision
SW
S1
SW
S2
NC
RS
SW
S3
NC
SW
S4
VS
NC
VOUT
D
10N Ÿ
Ax
VIN
EN
2.0V
GND
Figure 27. THD+N Measurement Setup
8.1.12 AC Power Supply Rejection Ratio (AC PSRR)
AC PSRR measures the ability of a device to prevent noise and spurious signals that appear on the supply
voltage pin from coupling to the output of the switch. The DC voltage on the device supply is modulated by a sine
wave of 620 mVPP. The ratio of the amplitude of signal on the output to the amplitude of the modulated signal is
the AC PSRR.
VDD
Network Analyzer
DC Bias
Injector
VSS
VSS
VDD
VBIAS
620 mVPP
S1
S2
SW
SW
NC
NC
VIN
S3
S4
SW
SW
NC
VOUT
50 Ÿ
D
10N Ÿ
5 pF
VIN
Ax
EN
2.0V
GND
VBIAS = 0 V
PSRR= 20 × Log (VOUT/ VIN)
Figure 28. AC PSRR Measurement Setup
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Overview (continued)
The Functional Block Diagram section provides a top-level block diagram of the TMUX6104. The TMUX6104 is a
4-channel, single-ended, analog multiplexer. Each channel is turned on or turned off based on the state of the
address lines and enable pin.
8.2 Functional Block Diagram
TMUX6104
S1
S2
D
S3
S4
1-of-4
Decoder
A0
A1
EN
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8.3 Feature Description
8.3.1 Ultralow Leakage Current
The TMUX6104 provide extremely low on- and off-leakage currents. The TMUX6104 is capable of switching
signals from high source-impedance inputs into a high input-impedance op amp with minimal offset error
because of the ultralow leakage currents. Figure 29 shows typical leakage currents of the TMUX6104 versus
temperature.
800
600
ID(ON)+
ID(OFF)+
Leakage Current (pA)
400
IS(OFF)+
200
0
-200
IS(OFF)-
-400
ID(OFF)-
-600
-800
-50
ID(ON)-25
0
25
50
75
100
Ambient Temperature (qC)
125
150
D006
Figure 29. Leakage Current vs Temperature
8.3.2 Ultralow Charge Injection
The TMUX6104 is implemented with simple transmission gate topology, as shown in Figure 30. Any mismatch in
the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch
is opened or closed.
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Feature Description (continued)
OFF ON
CGSN
CGDN
S
D
CGSP
CGDP
OFF ON
Figure 30. Transmission Gate Topology
The TMUX6119 utilizes special charge-injection cancellation circuitry that reduces the source (Sx) to drain (D)
charge injection to as low as –0.35 pC at VS = 0 V, and –0.41 pC in the full signal range, as shown in Figure 31.
Charge Injection (pC)
2
1
VDD= 12V
VSS = 0V
VDD= 10V
VSS = -10V
0
-1
VDD= 15V
VSS = -15V
-2
-15
-10
-5
0
5
Source Voltage (V)
10
15
D008
Figure 31. Source-to-Drain Charge Injection vs Source Voltage
The drain (D)-to-source (Sx) charge injection becomes important when the device is used as a demultiplexer
(demux), where the drain (D) becomes the input and the source (Sx) becomes the output. Figure 32 shows the
drain-to-source charge injection across the full signal range.
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Feature Description (continued)
Charge Injection (pC)
9
6
VDD= 10V
VSS = -10V
3
CS (5 V/div)
0
-3
VOUT (5 V/div)
-6
-9
-15
VDD= 15V
VSS = -15V
-10
-5
VDD= 12V
VSS = 0V
0
5
Drain Voltage (V)
10
15
D009
Figure 32. Drain-to-Source Charge Injection vs Drain Voltage
8.3.3 Bidirectional and Rail-to-Rail Operation
The TMUX6104 conducts equally well from source (Sx) to drain (D) or from drain (D) to source (Sx). Each
TMUX6104 channel has very similar characteristics in both directions. The valid analog signal for TMUX6104
ranges from VSS to VDD. The input signal to the TMUX6104 swings from VSS to VDD without any significant
degradation in performance.
8.4 Device Functional Modes
When the EN pin of the TMUX6104 is pulled high, one of the four switches is closed based on the state of the
address pins (A0 and A1). When the EN pin is pulled low, all four switches remain open irrespective of the state
of the address pins. The EN pin is weakly pull-down internally through a 6 MΩ resistor; thereby, setting each
channel to the open state if the EN pin is not actively driven. The address pins are also weakly pulled-down
through an internal 6 MΩ resistor, allowing channel 1 (S1 to D) to be selected by default when EN pin is driven
high. Both the EN pin and the address pins can be connected to VDD (as high as 16.5 V).
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TMUX6104 offers outstanding input/output leakage currents and ultralow charge injection. These devices
operate up to 33 V, and offer true rail-to-rail input and output. The on-capacitance of the TMUX6104 is very low.
These features makes the TMUX6104 a precision, robust, high-performance analog multiplexer for high-voltage,
industrial applications.
9.2 Typical Application
Figure 33 shows a 16-bit, differential, 4-channel, multiplexed, data-acquisition system. This example is typical in
industrial applications that require low distortion and a high-voltage input. The circuit uses the ADS8864, a 16-bit,
400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along with a precision,
high-voltage, signal-conditioning front end, and a 4-channel single-ended mux. This TI Precision Design details
the process for optimizing the precision, high-voltage, front-end drive circuit using the TMUX6104 and OPA192 to
achieve excellent dynamic performance and linearity with the ADS8864.
Bridge Sensor
Thermocouple
+
GND
...
Multiplexer
OPA192
Gain / Filter
Network
ADS8864
-
Current
Sensing
TMUX6104
Photo
LED Detector
Optical Sensor
Analog Inputs
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Figure 33. 16-Bit Precision Multiplexed Data-Acquisition System for High-Voltage Inputs With Lowest
Distortion
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Typical Application (continued)
9.2.1 Design Requirements
The primary objective is to design a ±15 V, single-ended, 4-channel, multiplexed, data-acquisition system with
lowest distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10-kHz, full-scale, pure, sine-wave
input. The design requirements for this block design are:
• System supply voltage: ±15 V
• ADC supply voltage: 3.3 V
• ADC sampling rate: 400 kSPS
• ADC reference voltage (REFP): 4.096 V
• System input signal: A high-voltage differential input signal with a peak amplitude of 15 V and frequency
(fIN) of 10 kHz are applied to each differential input of the mux.
9.2.2 Detailed Design Procedure
The purpose of this precision design is to design an optimal, high-voltage, multiplexed, data-acquisition system
for highest system linearity and fast settling. The overall system block diagram is illustrated in Figure 33. The
circuit is a multichannel, data-acquisition signal chain consisting of an input low-pass filter, mux, mux output
buffer, and attenuating SAR ADC driver. The architecture allows fast sampling of multiple channels using a single
ADC, providing a low-cost solution. This design systematically approaches each analog circuit block to achieve a
16-bit settling for a full-scale input stage voltage and linearity for a 10-kHz sinusoidal input signal at each input
channel.
9.2.3 Application Curve
1.0
Integral Non-Linearity (LSB)
0.8
0.6
0.4
0.2
0.0
±0.2
±0.4
±0.6
±0.8
±1.0
±20
±15
±10
±5
0
5
10
ADC Differential Peak-to-Peak Input (V)
15
20
C030
Figure 34. ADC 16-Bit Linearity Error for the Multiplexed Data-Acquisition Block
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10 Power Supply Recommendations
The TMUX6104 operates across a wide supply range of ±5 V to ±16.5 V (10 V to 16.5 V in single-supply mode).
The device also perform well with unsymmetric supplies such as VDD = 12 V and VSS= –5 V. For reliable
operation, use a supply decoupling capacitor ranging between 0.1 µF to 10 µF at both the VDD and VSS pins to
ground.
The on-resistance of the TMUX6104 varies with supply voltage, as illustrated in Figure 35
250
On Resistance (:)
200
VDD= 12V
VSS = -12V
VDD= 13.5V
VSS = -13.5V
150
100
VDD= 15V
VSS = -15V
50
0
-20
-15
VDD= 16.5V
VSS = -16.5V
-10
-5
0
5
10
Source or Drain Voltage (V)
15
20
D001
Figure 35. On-Resistance Variation With Supply and Input Voltage
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11 Layout
11.1 Layout Guidelines
Figure 36 illustrates an example of a PCB layout with the TMUX6104.
Some key considerations are:
1. Decouple the VDD and VSS pins with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure
that the capacitor voltage rating is sufficient for the VDD and VSS supplies.
2. Keep the input lines as short as possible.
3. Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
4. Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
Via to
ground plane
AO
A1
EN
GND
C
VDD
VSS
S1
Via to
ground plane
A1
EN
AO
11.2 Layout Example
TMUX6104
S3
S2
S4
D
NC
NC
NC
Copyright © 2018, Texas Instruments Incorporated
Figure 36. TMUX6104 Layout Example
24
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Copyright © 2018, Texas Instruments Incorporated
Product Folder Links: TMUX6104
TMUX6104
www.ti.com
SCDS376A – FEBRUARY 2018 – REVISED SEPTEMBER 2018
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
• ADS8664 12-Bit, 500-kSPS, 4- and 8-Channel, Single-Supply, SAR ADCs with Bipolar Input Ranges
(SBAS492)
• OPA192 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage, Low Input Bias Current Op Amp with
e-Trim™ (SBOS620)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: TMUX6104
25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMUX6104PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
MUX6104
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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