TMUX8212
ZHCSP22A – OCTOBER 2021 – REVISED DECEMBER 2021
具有闩锁效应抑制和 1.8V 逻辑电平的
TMUX821x 100V、扁平 Ron、1:1 (SPST)、四通道开关
1 特性
3 说明
• 支持高电源电压：
– 双电源：±10V 至 ±50V
– 单电源：10V 至 100V
– 非对称双电源运行
• 在整个电源电压范围内提供一致的参数性能
• 闩锁效应抑制
• 高持续电流：200mA
• 低串扰：-110dB
• 低输入泄漏电流：10pA
• 低导通电阻平坦度：0.05Ω
• 低导通电阻：5Ω
• 低电容：12pF
• 无需额外逻辑轨 (VL)
• 支持 1.8V 逻辑电平
• 失效防护逻辑：高达 48V（与电源无关）
• 逻辑引脚上的集成下拉电阻器
• 双向信号路径
• 宽工作温度 TA：–40°C 至 125°C
• 业界通用的 TSSOP 封装和
较小的 WQFN 封装
TMUX8211、TMUX8212 和 TMUX8213 是具有闩锁效
应抑制并支持高电压的现代模拟开关。每个器件均具有
四个独立可控的 1:1 单极单投 (SPST) 开关通道。此器
件可在双电源、单电源或非对称电源供电时正常运行，
最大电源电压为 100V。TMUX821x 器件可在整个电源
电压范围内提供一致的模拟参数性能。TMUX821x 系
列可在源极 (Sx) 和漏极 (Dx) 引脚上支持双向模拟和数
字信号。
此器件系列具有闩锁效应抑制功能，可防止器件内寄生
结构之间的大电流不良事件。闩锁状态通常会一直持续
到电源轨关闭为止，并可能导致器件故障。凭借闩锁效
应抑制功能，此系列多路复用器能够在恶劣的环境中使
用。
器件信息(1)
器件型号
2 应用
•
•
•
•
•
•
•
•
•
•
所有逻辑输入均支持 1.8V、3.3V 和 5V 的逻辑电平，
并可在电压高达 48V 时进行连接，从而通过控制信号
电压实现系统灵活性。失效防护逻辑电路允许在施加电
源引脚上的电压之前，先施加逻辑引脚上的电压，从而
保护器件免受潜在的损害。
TMUX8211
TMUX8212
TMUX8213
高电压双向切换
模拟和数字信号开关
半导体测试设备
LCD 测试设备
电池测试设备
数据采集系统 (DAQ)
数字万用表 (DMM)
工厂自动化和控制
可编程逻辑控制器 (PLC)
模拟输入模块
(1)
(2)
封装尺寸（标称值）
封装
TSSOP (16)
WQFN
(16)(2)
5.00mm × 4.40mm
4.00mm × 4.00mm
如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
预发布封装。
S1
D1
S1
D1
S1
D1
S2
D2
S2
D2
S2
D2
S3
D3
S3
D3
S3
D3
S4
D4
S4
D4
S4
D4
SEL1
SEL1
SEL1
SEL2
SEL2
SEL2
SEL3
SEL3
SEL3
SEL4
SEL4
SEL4
TMUX8211
TMUX8212
TMUX8213
ALL SWITCHES SHOWN FOR A LOGIC 0 INPUT
功能模块图
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCDS434
TMUX8212
www.ti.com.cn
ZHCSP22A – OCTOBER 2021 – REVISED DECEMBER 2021
Table of Contents
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 4
7.1 Absolute Maximum Ratings: TMUX821x Devices...... 4
7.2 ESD Ratings............................................................... 4
7.3 Recommended Operating Conditions:
TMUX821x Devices.......................................................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics (Global): TMUX821x
Devices..........................................................................6
7.6 Electrical Characteristics (±15-V Dual Supply)........... 6
7.7 Electrical Characteristics (±36-V Dual Supply)........... 8
7.8 Electrical Characteristics (±50-V Dual Supply)........... 9
7.9 Electrical Characteristics (72-V Single Supply).........10
7.10 Electrical Characteristics (100-V Single Supply).....11
7.11 Switching Characteristics: TMUX821x Devices...... 12
7.12 Typical Characteristics............................................ 13
8 Parameter Measurement Information.......................... 18
8.1 On-Resistance.......................................................... 18
8.2 Off-Leakage Current................................................. 18
8.3 On-Leakage Current................................................. 19
8.4 Device Turn-On and Turn-Off Time...........................19
8.5 Charge Injection........................................................20
8.6 Off Isolation...............................................................20
8.7 Crosstalk................................................................... 21
8.8 Bandwidth................................................................. 21
8.9 THD + Noise............................................................. 22
9 Detailed Description......................................................23
9.1 Overview................................................................... 23
9.2 Functional Block Diagram......................................... 23
9.3 Feature Description...................................................23
9.4 Device Functional Modes..........................................25
10 Application and Implementation................................ 26
10.1 Application Information........................................... 26
10.2 Typical Application.................................................. 26
11 Power Supply Recommendations..............................28
12 Layout...........................................................................29
12.1 Layout Guidelines................................................... 29
12.2 Layout Example...................................................... 29
13 Device and Documentation Support..........................30
13.1 Documentation Support.......................................... 30
13.2 接收文档更新通知................................................... 30
13.3 支持资源..................................................................30
13.4 Trademarks............................................................. 30
13.5 Electrostatic Discharge Caution..............................30
13.6 术语表..................................................................... 30
14 Mechanical, Packaging, and Orderable
Information.................................................................... 30
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (October 2021) to Revision A (December 2021)
Page
• 将数据表的状态从预告信息 更改为量产数据 ..................................................................................................... 1
2
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5 Device Comparison Table
PRODUCT
DESCRIPTION
TMUX8211
High Voltage, 4-channel, 1:1 (SPST) switches, (Logic Low)
TMUX8212
High Voltage, 4-channel, 1:1 (SPST) switches, (Logic High)
TMUX8213
High Voltage, 4-channel, 1:1 (SPST) switches, (Logic Low + Logic High)
N.C.
SEL4
6
11
SEL3
D4
7
10
D3
S4
8
9
S3
DD
SEL1
D2
12
13
5
SS
SS
1
2
12
SEL2
11
SEL3
10
N.C.
Thermal
GND
3
SEL4
4
Not to scale
图 6-1. PW Package
16-Pin TSSOP
Top View
Pad
9
8
GND
V
D3
V
S2
13
14
4
V
7
SEL2
S3
D2
14
S1
15
3
15
2
6
D1
SEL1
S4
S2
D1
16
5
1
D4
S1
16
6 Pin Configuration and Functions
V
DD
Not to scale
图 6-2. RUM Package (Preview)
16-Pin WQFN
Top View
表 6-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
TSSOP
WQFN(2)
S1
1
15
I/O
Source pin 1. Can be an input or output.
D1
2
16
I/O
Drain pin 1. Can be an input or output.
SEL1
3
2
I
Logic control input 1.
VSS
4
1
P
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling
capacitor ranging from 1 µF to 10 µF between VSS and GND.
GND
5
3
P
Ground (0 V) reference
SEL4
6
4
I
Logic control input 4.
D4
7
5
I/O
Drain pin 4. Can be an input or output.
S4
8
6
I/O
Source pin 4. Can be an input or output.
S3
9
7
I/O
Source pin 3. Can be an input or output.
D3
10
8
I/O
Drain pin 3. Can be an input or output.
SEL3
11
11
I
N.C.
12
10
—
No internal connection.
VDD
13
9
P
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 1 µF to 10 µF between VDD and GND.
SEL2
14
12
I
Logic control input 2.
D2
15
13
I/O
Drain pin 2. Can be an input or output.
S2
16
14
I/O
Source pin 2. Can be an input or output.
—
The thermal pad is not connected internally. It is recommended that the pad be tied to GND or VSS
for best performance.
NAME
Thermal Pad
(1)
(2)
Logic control input 3.
I = input, O = output, I/O = input and output, P = power
Preview package.
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7 Specifications
7.1 Absolute Maximum Ratings: TMUX821x Devices
over operating free-air temperature range (unless otherwise noted)(1)
MIN
VDD–VSS
Supply voltage
VDD
VSS
VSELx
Logic control input pin voltage (SELx)
ISELx
Logic control input pin current (SELx)
VS or VD
Source or drain voltage (Sx, Dx)
IDC
MAX
UNIT
110
V
–0.5
110
V
–110
0.5
V
–0.5
50
V
mA
–30
30
VSS–2
VDD+2
Source or drain continuous current (Sx, Dx)
–200
200
mA
Diode clamp current at 85°C
–100
100
mA
Diode clamp current at 125°C
–15
15
mA
Tstg
Storage temperature
–65
150
°C
TA
Ambient temperature
–55
150
°C
TJ
Junction temperature
150
°C
1680
mW
720
mW
IIK (2)
Ptot
(3)
Ptot (4)
(1)
(2)
(3)
(4)
Total power dissipation (QFN)
Total power dissipation (TSSOP)
V
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
Signal path pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum
ratings.
For QFN package: Ptot derates linearly above TA = 70°C by 24.0 mW/°C
For TSSOP package: Ptot derates linearly above TA = 70°C by 10.5 mW/°C
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2)
±2000
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions: TMUX821x Devices
over operating free-air temperature range (unless otherwise noted)
MIN
VDD – VSS (1) Power supply voltage differential
VDD
Positive power supply voltage
VS or VD (2)
Signal path input/output voltage (source or drain pin)
VSEL
Logic input pin voltage
TA
Ambient temperature
IDC 1ch.(3)
Continuous current through switch for TSSOP or QFN on 1 channel
IDC All ch.(4)
Continuous current through switch on all channels at the
same time, QFN package
IDC All
(1)
(2)
(3)
(4)
ch.(4)
NOM
10
Continuous current through switch on all channels at the
same time, TSSOP package
MAX
UNIT
100
V
10
100
V
VSS
VDD
V
0
48
V
–40
125
°C
200
mA
TA = 25°C
200
TA = 85°C
190
TA = 125°C
100
TA = 25°C
185
TA = 85°C
125
TA = 125°C
65
mA
mA
VDD and VSS can be any value as long as 10 V ≤ (VDD – VSS) ≤ 100 V, and the minimum VDD is met.
VS or VD is the voltage on any Source or Drain pins.
Max continuous current shown for a single channel at a time.
Max continuous current shown for all channels at a time. Refer to max power dissipation (Ptot) to ensure package limitations are not
violated.
7.4 Thermal Information
THERMAL
METRIC(1)
TMUX821x
TMUX821x
PW (TSSOP)
RUM (WQFN)
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
96.0
41.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
26.8
25.3
°C/W
RθJB
Junction-to-board thermal resistance
42.7
16.0
°C/W
ΨJT
Junction-to-top characterization parameter
1.2
0.3
°C/W
ΨJB
Junction-to-board characterization parameter
42.0
16.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
3.1
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics (Global): TMUX821x Devices
over operating free-air temperature range (unless otherwise noted)
typical at VDD = +36 V, VSS = –36 V, GND = 0 V and TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
LOGIC INPUTS
VIH
Logic voltage high
VIL
Logic voltage low
–40°C to +125°C
1.3
48
V
–40°C to +125°C
0
0.8
V
IIH
Input leakage current
Logic inputs = 0 V, 5 V, or 48 V
–40°C to +125°C
0.4
3.8
µA
IIL
Input leakage current
Logic inputs = 0 V, 5 V, or 48 V
–40°C to +125°C
–0.2 –0.005
µA
CIN
Logic input capacitance
–40°C to +125°C
3
pF
POWER SUPPLY
25°C
IDD
VDD supply current
Logic inputs = 0 V, 5 V, or 48 V
350
800
µA
800
µA
900
µA
800
µA
–40°C to +85°C
800
µA
–40°C to +125°C
900
µA
TYP
MAX
UNIT
5
7
–40°C to +85°C
–40°C to +125°C
25°C
ISS
VSS supply current
Logic inputs = 0 V, 5 V, or 48 V
350
7.6 Electrical Characteristics (±15-V Dual Supply)
VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V (unless otherwise noted)
Typical at TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
ANALOG SWITCH
25°C
RON
VS = –10 V to +10 V
ID = –10 mA
On-resistance
–40°C to +85°C
8
–40°C to +125°C
10
25°C
ΔRON
RON FLAT
On-resistance mismatch between VS = –10 V to +10 V
channels
ID = –10 mA
On-resistance flatness
RON DRIFT On-resistance drift
IS(OFF)
ID(OFF)
IS(ON)
ID(ON)
6
Drain off leakage
current(1)
Channel on leakage
ΔIS(ON)
ΔID(ON)
(1)
Source off leakage
current(1)
current(2)
Leakage current mismatch
between channels(2)
0.2
Ω
0.3
–40°C to +85°C
0.4
–40°C to +125°C
0.5
Ω
VS = –10 V to +10 V
ID = –10 mA
25°C
0.07
Ω
VS = 0 V, IS = –10 mA
–40°C to +125°C
0.03
Ω/°C
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
VD = –10 V / +10 V
25°C
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
VD = –10 V / +10 V
25°C
VDD = 16.5 V, VSS = –16.5 V
Switch state is on
VS = VD = ±10 V
VDD = 16.5 V, VSS = –16.5 V
Switch state is on
VS = VD = ±10 V
0.01
–40°C to +85°C
–4
4
–40°C to +125°C
–40
40
0.01
–40°C to +85°C
–4
4
–40°C to +125°C
–40
40
25°C
nA
0.01
–40°C to +85°C
–40°C to +125°C
25°C
nA
–1
1
–2
2
nA
5
85°C
35
125°C
120
pA
When VS is positive,VD is negative. And when VS is negative, VD is positive.
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When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating.
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7.7 Electrical Characteristics (±36-V Dual Supply)
VDD = +36 V ± 10%, VSS = –36 V ± 10%, GND = 0 V (unless otherwise noted)
Typical at TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
5
7
UNIT
ANALOG SWITCH
25°C
RON
VS = –25 V to +25 V
ID = –10 mA
On-resistance
–40°C to +85°C
8
–40°C to +125°C
10
25°C
ΔRON
RON FLAT
On-resistance mismatch between VS = –25 V to +25 V
channels
ID = –10 mA
On-resistance flatness
RON DRIFT On-resistance drift
IS(OFF)
ID(OFF)
IS(ON)
ID(ON)
8
Drain off leakage
current(1)
Channel on leakage
ΔIS(ON)
ΔID(ON)
(1)
(2)
Source off leakage
current(1)
current(2)
Leakage current mismatch
between channels(2)
0.1
Ω
0.3
–40°C to +85°C
0.4
–40°C to +125°C
0.5
Ω
VS = –25 V to +25 V
ID = –10 mA
25°C
0.12
Ω
VS = 0 V, IS = –10 mA
–40°C to +125°C
0.03
Ω/°C
VDD = 39.6 V, VSS = –39.6 V
Switch state is off
VS = +25 V / –25 V
VD = –25 V / +25 V
25°C
VDD = 39.6 V, VSS = –39.6 V
Switch state is off
VS = +25 V / –25 V
VD = –25 V / +25 V
25°C
VDD = 39.6 V, VSS = –39.6 V
Switch state is on
VS = VD = ±25 V
VDD = 39.6 V, VSS = –39.6 V
Switch state is on
VS = VD = ±25 V
0.01
–40°C to +85°C
–4
4
–40°C to +125°C
–40
40
nA
0.01
–40°C to +85°C
–40°C to +125°C
–4
4
–40
40
25°C
nA
0.01
–40°C to +85°C
–40°C to +125°C
25°C
–1
1
–2
2
nA
5
85°C
35
125°C
120
pA
When VS is positive,VD is negative. And when VS is negative, VD is positive.
When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating.
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7.8 Electrical Characteristics (±50-V Dual Supply)
VDD = +50 V, VSS = –50 V, GND = 0 V (unless otherwise noted)
Typical at TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
5
7
UNIT
ANALOG SWITCH
25°C
RON
VS = –45 V to 45 V
ID = –10 mA
On-resistance
–40°C to +85°C
8
–40°C to +125°C
10
25°C
ΔRON
RON FLAT
On-resistance mismatch between VS = –45 V to 45 V
channels
ID = –10 mA
On-resistance flatness
RON DRIFT On-resistance drift
IS(OFF)
ID(OFF)
IS(ON)
ID(ON)
ΔIS(ON)
ΔID(ON)
(1)
(2)
Source off leakage
Drain off leakage
current(1)
current(1)
Channel on leakage
current(2)
Leakage current mismatch
between channels(2)
0.2
Ω
0.3
–40°C to +85°C
0.4
–40°C to +125°C
0.5
Ω
VS = –45 V to 45 V
ID = –10 mA
25°C
0.13
Ω
VS = 0 V, IS = –10 mA
–40°C to +125°C
0.03
Ω/°C
VDD = 50 V, VSS = –50 V
Switch state is off
VS = +45 V / –45 V
VD = –45 V / +45 V
25°C
VDD = 50 V, VSS = –50 V
Switch state is off
VS = +45 V / –45 V
VD = –45 V / +45 V
25°C
VDD = 50 V, VSS = –50 V
Switch state is on
VS = VD = ±45 V
VDD = 50 V, VSS = –50 V
Switch state is on
VS = VD = ±45 V
0.01
–40°C to +85°C
–4
4
–40°C to +125°C
–40
40
–40°C to +85°C
–40°C to +125°C
0.01
–4
4
–40
40
25°C
–40°C to +85°C
–40°C to +125°C
25°C
nA
nA
0.01
–2
2
–5
5
nA
10
85°C
50
125°C
220
pA
When VS is positive,VD is negative. And when VS is negative, VD is positive.
When VS is at a voltage potential, VD is floating. And when VD is at a voltage potential, VS is floating.
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7.9 Electrical Characteristics (72-V Single Supply)
VDD = +72 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
5
7
UNIT
ANALOG SWITCH
25°C
RON
VS = 0 V to 60 V
ID = –10 mA
On-resistance
–40°C to +85°C
8
–40°C to +125°C
10
25°C
ΔRON
RON FLAT
On-resistance mismatch between VS = 0 V to 60 V
channels
ID = –10 mA
On-resistance flatness
RON DRIFT On-resistance drift
IS(OFF)
ID(OFF)
Source off leakage current(1)
Drain off leakage
current(1)
0.2
Channel on leakage
ΔIS(ON)
ΔID(ON)
(1)
(2)
10
current(2)
Leakage current mismatch
between channels(2)
0.3
–40°C to +85°C
0.4
–40°C to +125°C
0.5
Ω
VS = 0 V to 60 V
ID = –10 mA
25°C
0.05
Ω
VS = 0 V, IS = –10 mA
–40°C to +125°C
0.03
Ω/°C
25°C
0.01
Switch state is off
VS = +60 V / 1 V
VD = 1 V / +60 V
Switch state is off
VS = +60 V / 1 V
VD = 1 V / +60 V
–40°C to +85°C
–40°C to +125°C
–4
4
–40
40
25°C
Switch state is on
VS = VD = 1 V / +60 V
Switch state is on
VS = VD = 1 V / +60 V
nA
0.01
–40°C to +85°C
–4
4
–40°C to +125°C
–40
40
25°C
IS(ON)
ID(ON)
Ω
nA
0.01
–40°C to +85°C
–2
2
–40°C to +125°C
–5
5
25°C
15
85°C
75
125°C
300
nA
pA
When VS is 60 V, VD is 1 V. Or when VS is 1 V, VD is 60 V.
When VS is at a voltage potential, VD is floating. Or when VD is at a voltage potential, VS is floating.
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7.10 Electrical Characteristics (100-V Single Supply)
VDD = +100 V, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
5
7
UNIT
ANALOG SWITCH
25°C
RON
VS = 0 V to +95 V
ID = –10 mA
On-resistance
–40°C to +85°C
8
–40°C to +125°C
10
25°C
ΔRON
RON FLAT
On-resistance mismatch between VS = 0 V to +95 V
channels
ID = –10 mA
On-resistance flatness
RON DRIFT On-resistance drift
IS(OFF)
ID(OFF)
Source off leakage current(1)
Drain off leakage
current(1)
0.2
ΔIS(ON)
ΔID(ON)
(1)
(2)
Channel on leakage
current(2)
Leakage current mismatch
between channels(2)
0.3
–40°C to +85°C
0.4
–40°C to +125°C
0.5
Ω
VS = 0 V to +95 V
ID = –10 mA
25°C
0.07
Ω
VS = 50 V, IS = –10 mA
–40°C to +125°C
0.03
Ω/°C
25°C
0.01
Switch state is off
VS = +95 V / 1 V
VD = 1 V / +95 V
Switch state is off
VS = +95 V / 1 V
VD = 1 V / +95 V
–40°C to +85°C
–40°C to +125°C
–4
4
–40
40
25°C
Switch state is on
VS = VD = 1 V / +95 V
Switch state is on
VS = VD = 1 V / +95 V
nA
0.01
–40°C to +85°C
–4
4
–40°C to +125°C
–40
40
25°C
IS(ON)
ID(ON)
Ω
nA
0.01
–40°C to +85°C
–4
4
–40°C to +125°C
–10
10
25°C
15
85°C
100
125°C
450
nA
pA
When VS is 95 V, VD is 1 V. Or when VS is 1 V, VD is 95 V.
When VS is at a voltage potential, VD is floating. Or when VD is at a voltage potential, VS is floating.
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7.11 Switching Characteristics: TMUX821x Devices
over operating free-air temperature range (unless otherwise noted)
typical at VDD = +36 V, VSS = –36 V, GND = 0 V and TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
25°C
tON
(EN)
Turn-on time from enable
VS = 10 V
RL = 10 kΩ, CL = 15 pF
(EN)
Turn-off time from enable
MAX
UNIT
4
–40°C to +85°C
10
–40°C to +125°C
12
25°C
tOFF
TYP
µs
100
VS = 10 V
RL = 10 kΩ, CL = 15 pF
–40°C to +85°C
600
–40°C to +125°C
700
ns
tON (VDD)
Device turn on time
(VDD to output)
VDD ramp rate = 1 V/µs,
VS = 10 V
RL = 10 kΩ, CL = 15pF
25°C
tPD
Propagation delay
RL = 50 Ω , CL = 5 pF
25°C
190
ps
QINJ
Charge injection
VS = (VDD + VSS) / 2, CL = 1 nF
25°C
–1.3
nC
OISO
Off isolation
RL = 50 Ω , CL = 5 pF
VS = (VDD + VSS) / 2, f = 100 kHz
25°C
–110
dB
XTALK
Inter-channel crosstalk
RL = 50 Ω , CL = 5 pF
VS = (VDD + VSS) / 2, f = 100 kHz
25°C
–110
dB
BW
–3dB bandwidth
RL = 50 Ω , CL = 5 pF
VS = (VDD + VSS) / 2
25°C
420
IL
Insertion loss
RL = 50 Ω , CL = 5 pF
VS = (VDD + VSS) / 2, f = 1 MHz
25°C
–0.4
dB
THD+N
Total harmonic distortion + Noise
Dual supply voltage
VPP = 5 V, VBIAS = (VDD + VSS) / 2
25°C
RL = 1 kΩ , CL = 5 pF,
f = 20 Hz to 20 kHz
0.0008
%
CS(OFF)
Source off capacitance
VS = (VDD + VSS) / 2 V, f = 1 MHz 25°C
12
pF
CD(OFF)
Drain off capacitance
VS = (VDD + VSS) / 2 V, f = 1 MHz 25°C
12
pF
CS(ON),
CD(ON)
On capacitance
VS = (VDD + VSS) / 2 V, f = 1 MHz 25°C
14
pF
12
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7.12 Typical Characteristics
at TA = 25°C, VDD = +36 V, and VSS = –36 V (unless otherwise noted)
10
9
On Resistance ()
8
TA = 125C
7
6
TA = 85C
5
TA = 25C
4
3
2
-40
TA = -40C
-30
-20
-10
0
10
20
VS or VD - Source or Drain Voltage (V)
30
VDD = 36 V, VSS = –36 V
.
VDD = 36 V, VSS = –36 V
Flatest Ron Region
图 7-2. On-Resistance vs Source or Drain Voltage
图 7-1. On-Resistance vs Source or Drain Voltage
160
On Resistance ()
120
=
=
=
=
125C
85C
25C
-40C
On Resistance ()
140
TA
TA
TA
TA
100
80
60
40
20
0
-36
-28
-20
-12
-4 0 4
12
20
VS or VD - Source or Drain Voltage (V)
28
36
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
-40
VDD/VSS
VDD/VSS
VDD/VSS
VDD/VSS
VDD/VSS
VDD/VSS
-30
=
=
=
=
=
=
±39.6 V
±36 V
±32.4 V
±16.5 V
±15 V
±13.5 V
-20
-10
0
10
20
VS or VD - Source or Drain Voltage (V)
40
Dual Supply Voltages
.
VDD = 36 V, VSS = –36 V
.
图 7-4. On-Resistance vs Source or Drain Voltage
图 7-3. On-Resistance vs Source or Drain Voltage
160
12
TA
TA
TA
TA
11
10
=
=
=
=
125C
85C
25C
-40C
TA
TA
TA
TA
140
120
On Resistance ()
9
On Resistance ()
30
8
7
6
5
4
3
=
=
=
=
125C
85C
25C
-40C
100
80
60
40
2
20
1
0
-16
-12
-8
-4
0
4
8
VS or VD - Source or Drain Voltage (V)
12
16
0
-16
-12
VDD = 15 V, VSS = –15 V
-8
-4
0
4
8
VS or VD - Source or Drain Voltage (V)
12
16
VDD = 15 V, VSS = –15 V
图 7-5. On-Resistance vs Source or Drain Voltage
图 7-6. On-Resistance vs Source or Drain Voltage
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7.12 Typical Characteristics (continued)
at TA = 25°C, VDD = +36 V, and VSS = –36 V (unless otherwise noted)
160
12
TA
TA
TA
TA
11
10
125C
85C
25C
−40C
TA
TA
TA
TA
140
120
On Resistance ()
On Resistance ()
9
=
=
=
=
8
7
6
5
4
3
=
=
=
=
125C
85C
25C
−40C
100
80
60
40
2
20
1
0
0
5
0
10 15 20 25 30 35 40 45 50 55 60 65 70 75
VS or VD - Source or Drain Voltage (V)
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
VS or VD - Source or Drain Voltage (V)
VDD = 72 V, VSS = 0 V
VDD = 72 V, VSS = 0 V
图 7-7. On-Resistance vs Source or Drain Voltage
图 7-8. On-Resistance vs Source or Drain Voltage
160
12
TA
TA
TA
TA
11
9
125C
85C
25C
-40C
TA
TA
TA
TA
140
120
On Resistance ()
On Resistance ()
10
=
=
=
=
8
7
6
5
=
=
=
=
125C
85C
25C
-40C
100
80
60
40
4
20
3
2
0
10
20
30
40
50
60
70
80
VS or VD - Source or Drain Voltage (V)
90
0
100
0
10
20
30
40
50
60
70
80
VS or VD - Source or Drain Voltage (V)
VDD = 100 V, VSS = 0 V
图 7-10. On-Resistance vs Source or Drain Voltage
100
24
22
20
18
16
14
12
10
8
6
4
2
0
-2
ID(OFF) VS/VD: -25V/25V
ID(OFF) VS/VD: 25V-25V
IS(OFF) VS/VD: -25V/25V
IS(OFF) VS/VD: 25V/-25V
I(ON) VS = VD = -25V
I(ON) VS = VD = 25V
ID(OFF) VS/VD: -25V/25V
ID(OFF) VS/VD: 25V-25V
IS(OFF) VS/VD: -25V/25V
IS(OFF) VS/VD: 25V/-25V
I(ON) VS = VD = -25V
I(ON) VS = VD = 25V
10
Leakage Current (nA)
Leakage Current (nA)
100
VDD = 100 V, VSS = 0 V
图 7-9. On-Resistance vs Source or Drain Voltage
1
0.1
0.01
0
20
40
60
80
Temperature (C)
100
120
0.001
0
20
VDD = 36 V, VSS = –36 V
40
60
80
Temperature (C)
100
120
VDD = 36 V, VSS = –36 V
图 7-11. Leakage Current vs Temperature
14
90
图 7-12. Leakage Current vs Temperature
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7.12 Typical Characteristics (continued)
at TA = 25°C, VDD = +36 V, and VSS = –36 V (unless otherwise noted)
100
100
ID(OFF) VS/VD: 1V/60V
ID(OFF) VS/VD: 60V/1V
IS(OFF) VS/VD: 1V/60V
IS(OFF) VS/VD: 60V/1V
I(ON) VS = VD = 1V
I(ON) VS = VD = 60V
1
10
Leakage Current (nA)
Leakage Current (nA)
10
ID(OFF) VS/VD: 1V/95V
ID(OFF) VS/VD: 95V/1V
IS(OFF) VS/VD: 1V/95V
IS(OFF) VS/VD: 95V/1V
I(ON) VS = VD = 1V
I(ON) VS = VD = 95V
0.1
0.01
1
0.1
0.01
0.001
0.001
0
20
40
60
80
Temperature (C)
100
120
140
0
20
VDD = 72 V, VSS = 0 V
Leakage Current (nA)
Leakage Current (nA)
TA = 125C
TA = 85C
TA = 25C
20
15
10
5
0
-28
-20
-12
-4 0 4
12
20
VS or VD - Source or Drain Voltage (V)
28
36
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-36
-28
28
36
图 7-16. On-Leakage Current vs Source or Drain Voltage
30
0.7
TA = 125C
TA = 85C
TA = 25C
TA = 125C
TA = 85C
TA = 25C
0.6
0.5
Leakage Current (nA)
Leakage Current (nA)
-20
-12
-4 0 4
12
20
VS or VD - Source or Drain Voltage (V)
VDD = 36 V, VSS = –36 V
ION
图 7-15. Off-Leakage Current vs Source or Drain Voltage
20
15
10
5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
0
-5
-36
120
TA = 125C
TA = 85C
TA = 25C
VDD = 36 V, VSS = –36 V
IS(OFF) and ID(OFF)
25
100
图 7-14. Leakage Current vs Temperature
30
-5
-36
60
80
Temperature (C)
VDD = 100 V, VSS = 0 V
图 7-13. Leakage Current vs Temperature
25
40
-0.3
-0.4
-28
-20
-12
-4 0 4
12
20
VS or VD - Source or Drain Voltage (V)
28
36
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
VS or VD - Source or Drain Voltage (V)
VDD = 72 V, VSS = 0 V
VDD = 72 V, VSS = 0 V
图 7-17. Off-Leakage Current vs Source or Drain Voltage
图 7-18. On-Leakage Current vs Source or Drain Voltage
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7.12 Typical Characteristics (continued)
at TA = 25°C, VDD = +36 V, and VSS = –36 V (unless otherwise noted)
30
TA = 125C
TA = 85C
TA = 25C
Leakage Current (nA)
25
20
15
10
5
0
-5
0
10
20
30
40
50
60
70
80
VS or VD - Source or Drain Voltage (V)
90
100
VDD = 100 V, VSS = 0 V
IS(OFF) and ID(OFF)
VDD = 100 V, VSS = 0 V
ION
图 7-19. Off-Leakage Current vs Source or Drain Voltage
图 7-20. On-Leakage Current vs Source or Drain Voltage
0
400
Charge Injection (nC)
-0.4
=
=
=
=
125C
85C
25C
−40C
375
350
Supply Current (A)
TA
TA
TA
TA
-0.2
-0.6
-0.8
-1
-1.2
-1.4
300
275
250
225
VDD/VSS:
VDD/VSS:
VDD/VSS:
VDD/VSS:
72V/0V - All Channels Enabled
±36V - All Channels Enabled
72V/0V - All Channels Disabled
±36V - All Channels Disabled
200
175
-1.6
-1.8
-36
325
150
-28
-20
-12
-4 0 4
12
20
VS or VD - Source or Drain Voltage (V)
28
125
20
36
30
40
50
60
70
80
90
Temperature (C)
.
VDD = 36 V, VSS = –36 V
图 7-22. Supply Current vs Temperature
图 7-21. Charge Injection vs Source Voltage
5
T(ON)
T(OFF)
Magnitude (dB)
Time (s)
4
3
2
1
0
-36
-28
-20
-12
-4 0 4
12
20
VS or VD - Source or Drain Voltage (V)
28
36
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
10
VDD/VSS: ±36V
VDD/VSS: 72V/0V
100
1k
10k
100k
1M
Frequency (Hz)
10M
100M
1G
TA = 25°C
VDD = 36 V, VSS = –36 V
图 7-23. Turn-On and Turn-Off Times vs Source Voltage
16
100 110 120 130
图 7-24. Off Isolation vs Frequency
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7.12 Typical Characteristics (continued)
Magnitude (dB)
at TA = 25°C, VDD = +36 V, and VSS = –36 V (unless otherwise noted)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
10
VDD/VSS:
VDD/VSS:
VDD/VSS:
VDD/VSS:
100
±36V - Adjacent
±36V - Non-Adjacent
72V/0V - Adjacent
72V/0V - Non-Adjacent
1k
10k
100k
1M
Frequency (Hz)
10M
100M
1G
TA = 25°C
Bandwidth
图 7-25. Crosstalk vs Frequency
图 7-26. Insertion Loss vs Frequency
0.005
THD+N (%)
0.004
VDD/VSS: ±15V
VPP: 2V
RL: 50
VDD/VSS: ±15V
VPP: 5V
RL = 1k
VDD/VSS: ±36V
VPP: 5V
RL: 1k
1k
Frequency (Hz)
10k
0.003
0.002
0.001
0
10
100
TA = 25°C
图 7-27. THD+N vs Frequency
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8 Parameter Measurement Information
8.1 On-Resistance
The on-resistance of the TMUX821x is the ohmic resistance across the source (Sx) and drain (Dx) pins of the
device. The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote onresistance. 图 8-1 shows the measurement setup used to measure RON. ΔRON represents the difference
between the RON of any two channels, while RON_FLAT denotes the flatness that is defined as the difference
between the maximum and minimum value of on-resistance measured over the specified analog signal range.
V
VDD
VSS
410 =
VDD
Sx
VS
8
+5
VSS
IS
SW
Dx
GND
图 8-1. On-Resistance Measurement Setup
8.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current IS(OFF): the leakage current flowing into or out of the source pin when the switch
is off.
2. Drain off-leakage current ID(OFF): the leakage current flowing into or out of the drain pin when the switch is
off.
图 8-2 shows the setup used to measure both off-leakage currents.
VDD
Is (OFF)
S1
VSS
SW
S4
SW
S4
SW
D1
GND
D4
VD
GND
ID (OFF)
GND
GND
A
VD
VS
GND
GND
VD
D4
A
VS
A
...
GND
Is (OFF)
VS
ID (OFF)
SW
...
VD
VSS
...
...
...
...
GND
S1
D1
A
VS
VDD
GND
GND
IS(OFF)
ID(OFF)
图 8-2. Off-Leakage Measurement Setup
18
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8.3 On-Leakage Current
Source on-leakage current (IS(ON)) and drain on-leakage current (ID(ON)) denote the channel leakage currents
when the switch is in the on state. IS(ON) is measured with the drain floating, while ID(ON) is measured with the
source floating. 图 8-3 shows the circuit used for measuring the on-leakage currents.
VDD
VSS
Is (OFF)
VDD
SW
S1
N.C.
A
VS
GND
ID (OFF)
SW
S4
A
...
D4
...
SW
S4
...
Is (OFF)
D1
N.C.
...
GND
...
...
VS
N.C.
ID (OFF)
SW
S1
D1
A
VSS
D4
N.C.
A
VS
VS
GND
GND
GND
IS(ON)
GND
ID(ON)
图 8-3. On-Leakage Measurement Setup
8.4 Device Turn-On and Turn-Off Time
Turn-on time (tON) is defined as the time taken by the output of the TMUX8211, TMUX8212, and TMUX8213 to
rise to a 90% final value after the SELx signal has risen (for NC switches) or fallen (for NO switches) to a 50%
final value. Turn off time (tOFF) is defined as the time taken by the output of the TMUX8211, TMUX8212, and
TMUX8213 to fall to a 10% initial value after the SELx signal has fallen (for NC switches) or risen (for NO
switches) to a 50% initial value. 图 8-4 shows the setup used to measure tON and tOFF.
VDD
VSS
VDD
VSS
0.1 µF
0.1 µF
3V
GND
tr < 20 ns
VSEL
50%
50%
tf < 20 ns
GND
Sx
SW
Dx
Output
0V
VS
Output
tON
RL
SELx
0.9
tOFF
GND
0.1
CL
GND
GND
VSEL
GND
GND
图 8-4. Enable Delay Measurement Setup
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8.5 Charge Injection
Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during
switching, and is denoted by the symbol QINJ. 图 8-5 shows the setup used to measure charge injection from the
source to drain.
VDD
VSS
0.1 µF
0.1 µF
VDD
GND
GND
SW
S1
3V
VSELx
tr < 20 ns
D1
tf < 20 ns
...
...
VS
0V
GND
SW
S4
Output
VS
VSS
QINJ = CL ×
D4
Output
CL
GND
Output
VOUT
VOUT
CL
VS
SELx
GND
GND
VSELx
GND
图 8-5. Charge-Injection Measurement Setup
8.6 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (Dx) of the device when a signal is applied to the
source pin (Sx) of an off-channel. The characteristic impedance, ZO, for the measurement is 50 Ω. 图 8-6 shows
the setup used to measure off isolation.
VDD
VSS
VDD
VSS
0.1 µF
Network Analyzer
0.1 µF
GND
SX
RS
VS
VOUT
GND
SW
Dx
Other
Sx/ Dx
pins
SELx
50Ÿ
VSELx
GND
1BB +OKH=PEKJ = 20 × .KC
50Ÿ
8176
85
图 8-6. Off Isolation Measurement Setup
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8.7 Crosstalk
Crosstalk (XTALK) is defined as the ratio of the signal at the drain pin (Dx) of a different channel, when a signal is
applied at the source pin (Sx) of an on-channel. The characteristic impedance, ZO, for the measurement is 50 Ω,
as shown in 图 8-7.
VDD
VSS
0.1 µF
Network Analyzer
0.1 µF
VDD
GND
SX
RS
VSS
GND
SW
DX
SW
SY
DY
VOUT
Other
Sx/ Dx
pins
50Ÿ
VS
50Ÿ
50Ÿ
50Ÿ
INx
VINx
GND
+JPAN F ?D=JJAH %NKOOP=HG = 20 × .KC
8176
85
图 8-7. Inter-channel Crosstalk Measurement Setup
8.8 Bandwidth
Bandwidth (BW) is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied to
the source pin (Sx) of an on-channel, and the output is measured at the drain pin (Dx). 图 8-8 shows the setup
used to measure bandwidth of the switch.
VDD
VSS
VDD
VSS
0.1 µF
Network Analyzer
0.1 µF
GND
SX
RS
VS
VOUT
GND
SW
Dx
Other
Sx/ Dx
pins
SELx
50Ÿ
VSELx
GND
$=J@SE@PD = 20 × .KC
50Ÿ
8176
85
图 8-8. Bandwidth Measurement Setup
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8.9 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as
the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the
multiplexer output. The on-resistance of the device varies with the amplitude of the input signal and results in
distortion when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is
denoted as THD+N. 图 8-9 shows the setup used to measure THD+N of the devices.
VDD
VSS
VDD
VSS
0.1 µF
0.1 µF
GND
Audio Precision
SX
GND
SW
RS
Dx
VOUT
VS
RL
Other
Sx/ Dx
pins
SELx
VSELX
GND
50Ÿ
图 8-9. THD+N Measurement Setup
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9 Detailed Description
9.1 Overview
The TMUX8211, TMUX8212 and TMUX8213 are a modern complementary metal-oxide semiconductor (CMOS)
analog switches in quad single-pole single-throw configuration. The devices work well with dual supplies, a
single supply, or asymmetric supplies.
9.2 Functional Block Diagram
S1
D1
S1
D1
S1
D1
S2
D2
S2
D2
S2
D2
S3
D3
S3
D3
S3
D3
S4
D4
S4
D4
S4
D4
SEL1
SEL1
SEL1
SEL2
SEL2
SEL2
SEL3
SEL3
SEL3
SEL4
SEL4
SEL4
TMUX8211
TMUX8212
TMUX8213
ALL SWITCHES SHOWN FOR A LOGIC 0 INPUT
9.3 Feature Description
9.3.1 Bidirectional Operation
The devices conduct equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). Each signal
path has similar characteristics in both directions.
9.3.2 Flat On-Resistance
The TMUX821x devices are designed with a special switch architecture to produce ultra-flat on-resistance (RON)
across most of the switch input operating region. The flat RON response allows the device to be used in precision
sensor applications since the RON is controlled regardless of the signals sampled. The architecture is
implemented without a charge pump so no unwanted noise is produced from the device to affect sampling
accuracy.
The flatest on-resistance region extends from VSS to roughly 5 V below VDD. Once the signal is within 5 V of VDD
the on-resistance will expoentially increase and may impact desired signal transmission.
9.3.3 Protection Features
These devices offer a number of protection features to enable robust system implementations.
9.3.3.1 Fail-Safe Logic
Fail-safe logic circuitry allows voltages on the logic control pins to be applied before the supply pins, protecting
the device from potential damage. Additionaly the fail safe logic feature allows the logic inputs of the mux to be
interfaced with high voltages, allowing for simplified interfacing if only high voltage control signals are present.
The logic inputs are protected against positive faults of up to +48 V in powered-off condition, but do not offer
protection against negative overvoltage condition.
Fail-safe logic also allows the devices to interface with a voltage greater than VDD on the control pins during
normal operation to add maximum flexibility in system design. For example, with a VDD = 15 V, the logic control
pins could be connected to +24 V for a logic high signal which allows different types of signals, such as analog
feedback voltages, to be used when controlling the logic inputs. Regardless of the supply voltage, the logic
inputs can be interfaced as high as 48 V.
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9.3.3.2 ESD Protection
All pins support HBM ESD protection level up to ±2 kV, which helps protect the devices from ESD events during
the manufacturing process.
9.3.3.3 Latch-Up Immunity
Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition
is caused by a trigger (current injection or overvoltage), but once activated the low impedance path remains
even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic
damage due to excessive current levels. The latch-up condition typically requires a power cycle to eliminate the
low impedance path.
In the TMUX821x devices, an insulating oxide layer is placed on top of the silicon substrate to prevent any
parasitic junctions from forming. As a result, the devices are latch-up immune under all circumstances by device
construction.
The TMUX821x devices are constructed on silicon on insulator (SOI) based process where an oxide layer is
added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures from
forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events due to
overvoltage or current injections. The latch-up immunity feature allows the TMUX821x to be used in harsh
environments. For more information on latch-up immunity refer to Using Latch Up Immune Multiplexers to Help
Improve System Reliability.
9.3.4 1.8 V Logic Compatible Inputs
The TMUX821x devices have 1.8 V logic compatible control for all logic control inputs. 1.8 V logic level inputs
allows the TMUX821x to interface with processors that have lower logic I/O rails and eliminates the need for an
external translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations
refer to Simplifying Design with 1.8 V logic Muxes and Switches.
9.3.5 Integrated Pull-Down Resistor on Logic Pins
The TMUX821x have internal weak pull-down resistors to GND to ensure the logic pins are not left floating. The
value of this pull-down resistor is approximately 4 MΩ, but is clamped to 1 µA at higher voltages. This feature
integrates up to four external components and reduces system size and cost.
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9.4 Device Functional Modes
9.4.1 Normal Mode
In Normal Mode operation, signals of up to VDD and VSS can be passed through the switch from source (Sx) to
drain (Dx) or from drain (Dx) to source (Sx). The select (SELx) pins determine which switch path to turn on,
according to the Truth Table. The following conditions must be satisfied for the switch to stay in the ON condition:
• The difference between the primary supplies (VDD – VSS) must be greater than or equal to 10 V. With a
minimum VDD of 10 V.
• The input signals on the source (Sx) or the drain (Dx) must be be between VDD and VSS.
• The logic control (SELx) must have selected the switch.
9.4.2 Truth Tables
表 9-1, 表 9-2, and 表 9-3 show the truth tables for the TMUX8211, TMUX8212, and TMUX8213, respectively.
表 9-1. TMUX8211 Truth Table
SEL #(1)
(1)
CHANNEL #
0
Channel # ON
1
Channel # OFF
"#"designates the channel number controlled by SEL pin: "1, 2,
3, or 4"
表 9-2. TMUX8212 Truth Table
(1)
SEL #(1)
CHANNEL #
0
Channel # OFF
1
Channel # ON
"#"designates the channel number controlled by SEL pin: "1, 2,
3, or 4"
表 9-3. TMUX8213 Truth Table
SEL1 SEL2 SEL3 SEL4
(1)
ON / OFF CHANNELS
0
X(1)
X
X
CHANNEL 1 ON
1
X
X
X
CHANNEL 1 OFF
X
0
X
X
CHANNEL 2 OFF
X
1
X
X
CHANNEL 2 ON
X
X
0
X
CHANNEL 3 OFF
X
X
1
X
CHANNEL 3 ON
X
X
X
0
CHANNEL 4 ON
X
X
X
1
CHANNEL 4 OFF
"X" means "do not care."
If unused, SELx pins must be tied to GND or Logic High in order to ensure the device does not consume
additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path inputs (Sx
or Dx) should be connected to GND for best performance.
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10 Application and Implementation
备注
以下应用部分中的信息不属于 TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
The TMUX821x are high voltage switches capable of supporting analog and digital signals. The high voltage
capability of these multiplexers allow them to be used in systems with high voltage signal swings, or in systems
with high common mode voltages.
Additionally, the TMUX821x devices provide consistent analog parametric performance across the entire supply
voltage range allowing the devices to be powered by the most convient supply rails in the system while still
providing excellent performance.
10.2 Typical Application
A common feature of many PMUs (precision measurement units) is the ability to change current ranges. This
allows for a system defined current clamp when testing devices and reduces possible damage to the PMU and
DUT (device under test). In high voltage PMUs, large relays are often used to enable this switching, but this
comes with the trade-off of size. To reduce system size, a multi-channel high voltage switch can be added to
facilitate this switching with minimal impact to system size and performance. The TMUX821x allows for switching
between multiple current ranges, and has the added flexibility to use multiple channels in parallel for high current
applications.
VDD VSS
Gain / Filter
Network
VDD
10k
TMUX8212
DUT
+
DAC
High Voltage
+
Offset
–
VSS
VDD VSS
Gain / Filter
Network
VDD
10k
TMUX8212
DUT
+
DAC
High Voltage
+
Offset
–
VSS
图 10-1. TMUX8212 Application Schematic
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10.2.1 Design Requirements
表 10-1. Design Parameters
PARAMETERS
VALUES
Positive supply (VDD) mux and Op Amps
36 V
Positive supply (VSS) mux and Op Amps
-36 V
Maximum input or output signals with common mode shift
-36 V to 36 V
Control logic thresholds
1.8 V compatible, up to 48 V
Temperature range
-40°C to +125°C
10.2.2 Detailed Design Procedure
Multiplexing PMU systems enables a small, flexible solution that can be used over a wide range of current
ranges. TI’s high voltage multiplexers offer a size advantage over typical relay solutions while still achieving an
extremely low level of distortion, noise, and leakage. This high voltage multiplexer can be use in tandem with
high voltage operational amplifiers and DACs to create an accurate PMU with excellent signal-to-noise ratio.
In this example application, the TMUX8212 is paired with a high voltage amplifier and a DAC. The DAC
generates an arbitrary voltage signal that feeds into the amplifier. An additional high voltage offset is also fed into
the amplifier to add any needed common mode shift. This arbitrary signal is then passed through a current
limiting resistor before reaching the DUT. To change the current range of the system, different current limiting
resistors are added in series with each channel of the multiplexer. In this example, the first channel of the
multiplexer uses a 10 kΩ resistor for the low current clamp. This ensures the maximum output current of the
PMU in this range is 5 mA. During the system operation, the PMU is set to this lower current range in the
beginning of the test routine. After the DUT is initially checked in this range and is operating normally with no
unexpected shorts, the current range can be switched to high current. This ensures that the PMU and DUT will
not be unnecessarily damaged from excess current due to a short. In this example, the remaining three channels
of the TMUX8212 are connected in parallel, increasing the maximum current through the device and reducing
the low on-resistance. Because of the flexibility of the TMUX8212, this could easily be modified to fit any system
need. For example, if less maximum current is needed, then two channels could be connected in parallel instead
of three, and the additional single channel could be used to add a third current range option. The additional input
channels make this multiplexed application increasingly valuable by greatly reducing solution size.
The TMUX821x switches have exceptionally flat on-resistance and low leakage currents across the signal
voltage range. The ultra-flat on-resistance ensures that the current clamp stays constant across the signal
voltage range, and the low leakage current reduces the potential noise/offset when measuring on the lowest
current range. Additionally, excellent crosstalk and off-isolation performance allows the TMUX821x devices to
perform well in multi-channel switching applications without having an unselected channel impact the
measurement on selected channels.
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10.2.3 Application Curves
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-36
10
TA = 125C
TA = 85C
TA = 25C
9
8
On Resistance ()
Leakage Current (nA)
The example application utilizes the excellent leakage and on-resistance flatness performance of the TMUX821x
devices. 图 10-2 shows the leakage current for a channel that is ON across a varying source voltage. 图 10-3
shows the extremely flat on-resistance across source voltage while operating within the flatest RON range of the
TMUX821x devices. These features make the devices an ideal solution for applications that require excellent
linearity and low distortion.
TA = 125C
7
6
TA = 85C
5
TA = 25C
4
3
-28
-20
-12
-4 0 4
12
20
VS or VD - Source or Drain Voltage (V)
28
36
2
-40
TA = -40C
-30
.
-20
-10
0
10
20
VS or VD - Source or Drain Voltage (V)
30
.
图 10-2. On-Leakage
图 10-3. RON Flatness
11 Power Supply Recommendations
The TMUX821x devices operate across a wide supply range of ±10 V to ±50 V (10 V to 100 V in single-supply
mode). They also perform well with asymmetrical supplies such as VDD = 50 V and VSS= –10 V. For improved
supply noise immunity, use a supply decoupling capacitor ranging from 1 µF to 10 µF at both the VDD and VSS
pins to ground. An additional 0.1 µF capacitor placed closest to the supply pins will provide the best supply
decoupling solution. Always ensure the ground (GND) connection is established before supplies are ramped.
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12 Layout
12.1 Layout Guidelines
The image below illustrates an example of a PCB layout with the TMUX821x device. Some key considerations
are:
• For reliable operation, connect at least one decoupling capacitor ranging from 0.1 µF to 10 µF between VDD
and VSS to GND. We recommend a 0.1 µF and 1 µF capacitor, placing the lowest value capacitor as close to
the pin as possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.
• Keep the input lines as short as possible.
• Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
12.2 Layout Example
S1
Wide (low inductance)
trace for power
S2
VSS
C
D2
SEL2
C
D1
SEL1
Wide (low inductance)
trace for power
VDD
TMUX821x
C
C
GND
N.C.
SEL4
SEL3
D4
D3
S4
S3
Via to ground plane
图 12-1. TMUX821x TSSOP Layout Example
D2
SEL2
SEL3
GND
N.C.
SEL4
VDD
Wide (low inductance)
trace for power
D3
S3
S4
D4
C
S1
VSS
SEL1
C
Wide (low inductance)
trace for power
S2
D1
Via to ground plane
图 12-2. TMUX821x QFN Layout Example
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Implications of Slow or Floating CMOS Inputs application note
• Texas Instruments, Multiplexers and Signal Switches Glossary application report
• Texas Instruments, Using Latch-Up Immune Multiplexers to Help Improve System Reliability application
report
13.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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28-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
PTMUX8212PWR
ACTIVE
TSSOP
PW
16
2000
TBD
Call TI
Call TI
-40 to 125
TMUX8212PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TM8212
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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