TMUX6208PWR

TMUX6208, TMUX6209 SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 TMUX620x 36 V, Low-Ron, 8:1 1-Channel and 4:1, 2-Channel Precision Multiplexers with 1.8 V Logic 1 Features 3 Description • • • • • • The TMUX6208 is a precision 8:1, single channel multiplexer while the TMUX6209 is a 4:1, 2 channel multiplexer featuring low on resistance and charge injection. The devices work with a single supply (4.5 V to 36 V), dual supply (±4.5 V to ±18 V), or asymmetric supply (such as VDD = 12 V, VSS = –5 V). The TMUX620x supports bidirectional analog and digital signals onthe source (Sx) and drain (D) pins ranging from VSS to VDD. • • • • • • • Single supply range: 4.5 V to 36 V Dual supply range: ±4.5 V to ±18 V Low on-resistance: 4 Ω Low charge injection: 3 pC High current support: 400 mA (maximum) (WQFN) High current support: 300 mA (maximum) (TSSOP) –40°C to +125°C operating temperature 1.8 V logic compatible inputs Integrated pull-down resistor on logic pins Fail-safe logic Rail-to-rail operation Bidirectional signal path Break-before-make switching 2 Applications • • • • • • • • • • • Factory automation and control Programmable logic controllers (PLC) Analog input modules Semiconductor test equipment Battery test equipment Ultrasound scanners Patient monitoring and diagnostics Optical networking Optical test equipment Wired networking Data acquisition systems (DAQ) All logic control inputs support logic high levels from 1.8 V to VDD, ensuring both TTL and CMOS logic compatibility when operating in the valid supply voltage range. Fail-Safe Logic circuitry allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage. The TMUX620x are part of the precision switches and multiplexers family of devices. These devices have very low on and off leakage currents and low charge injection, allowing them to be used in high precision measurement applications. Device Information(1) PART NUMBER TMUX6208 TMUX6209 (1) VDD PACKAGE VSS 5.00 mm × 4.40 mm WQFN (16) (RUM) 4.00 mm × 4.00 mm For all available packages, see the package option addendum at the end of the data sheet. VDD SW BODY SIZE (NOM) TSSOP (16) (PW) VSS SW S1 S1A ... SW S2 S4A ... D DA SW SW S1B ... SW DB SW S4B S8 A0 A1 Logic Decoder EN A0 Logic Decoder EN A1 A2 TMUX6208 TMUX6209 TMUX6208 and TMUX6209 Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Comparison Table...............................................3 6 Pin Configuration and Functions...................................3 7 Specifications.................................................................. 5 7.1 Absolute Maximum Ratings ....................................... 5 7.2 ESD Ratings .............................................................. 5 7.3 Thermal Information ...................................................6 7.4 Recommended Operating Conditions ........................6 7.5 Source or Drain Continuous Current ..........................6 7.6 ±15 V Dual Supply: Electrical Characteristics ...........7 7.7 ±15 V Dual Supply: Switching Characteristics .......... 8 7.8 36 V Single Supply: Electrical Characteristics ........ 10 7.9 36 V Single Supply: Switching Characteristics ........11 7.10 12 V Single Supply: Electrical Characteristics ...... 13 7.11 12 V Single Supply: Switching Characteristics ......14 7.12 ±5 V Dual Supply: Electrical Characteristics .........16 7.13 ±5 V Dual Supply: Switching Characteristics ........ 17 7.14 Typical Characteristics............................................ 19 8 Parameter Measurement Information.......................... 24 8.1 On-Resistance.......................................................... 24 8.2 Off-Leakage Current................................................. 24 8.3 On-Leakage Current................................................. 25 8.4 Transition Time......................................................... 25 8.5 tON(EN) and tOFF(EN) .................................................. 26 8.6 Break-Before-Make...................................................26 8.7 tON (VDD) Time............................................................27 8.8 Propagation Delay.................................................... 27 8.9 Charge Injection........................................................28 8.10 Off Isolation.............................................................28 8.11 Crosstalk................................................................. 29 8.12 Bandwidth............................................................... 29 8.13 THD + Noise........................................................... 30 8.14 Power Supply Rejection Ratio (PSRR)................... 30 9 Detailed Description......................................................31 9.1 Overview................................................................... 31 9.2 Functional Block Diagram......................................... 31 9.3 Feature Description...................................................31 9.4 Device Functional Modes..........................................33 9.5 Truth Tables.............................................................. 33 10 Application and Implementation................................ 34 10.1 Application Information........................................... 34 10.2 Typical Application.................................................. 34 10.3 Design Requirements............................................. 35 10.4 Detailed Design Procedure..................................... 35 10.5 Application Curve....................................................36 11 Power Supply Recommendations..............................36 12 Layout...........................................................................37 12.1 Layout Guidelines................................................... 37 12.2 Layout Example...................................................... 38 13 Device and Documentation Support..........................39 13.1 Documentation Support.......................................... 39 13.2 Receiving Notification of Documentation Updates..39 13.3 Support Resources................................................. 39 13.4 Trademarks............................................................. 39 13.5 Electrostatic Discharge Caution..............................39 13.6 Glossary..................................................................39 14 Mechanical, Packaging, and Orderable Information.................................................................... 39 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (April 2021) to Revision C (August 2021) Page • Changed the status of the QFN package for the TMUX6208 and TMUX6209 from: preview to: active ............1 • Added ESD detail for RUM package.................................................................................................................. 5 • Added the Integrated Pull-Down Resistor on Logic Pins section......................................................................31 • Updated the Ultra-Low Charge Injection section.............................................................................................. 32 • Updated the TMUX620x Layout Example figures in the Layout Example section............................................38 Changes from Revision A (January 2021) to Revision B (April 2021) Page • Added thermal information for QFN package..................................................................................................... 6 • Added IDC specs for QFN package in Source or Drain Continuous Current table .............................................6 • Updated VDD rise time value from 100ns to 1µs in TON(VDD) test condition........................................................ 8 • Updated CL value from 1nF to 100pF in Charge Injection test condition............................................................8 Changes from Revision * (November 2020) to Revision A (January 2021) Page • Changed the document status From: Advanced Information To: Production Data ............................................1 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 5 Device Comparison Table PRODUCT DESCRIPTION TMUX6208 Low-Leakage-Current, Precision, 8:1, 1-Ch. multiplexer TMUX6209 Low-Leakage-Current, Precision, 4:1, 2-Ch. multiplexer 14 GND VSS 1 S1 4 13 VDD S1 2 S2 5 12 S5 S2 3 S3 6 11 S6 S3 4 S4 7 10 S7 D 8 9 S8 A2 3 13 VSS A0 A2 A1 A1 15 14 16 2 15 1 EN A0 EN 16 6 Pin Configuration and Functions 12 GND 11 VDD 10 S5 9 S6 Thermal 5 6 7 8 S4 D S8 S7 Pad Not to scale Not to scale Figure 6-1. TMUX6208: PW Package 16-Pin TSSOP Figure 6-2. TMUX6208: RUM Package 16-Pin WQFN Top View Top View Table 6-1. TMUX6208 Pin Functions PW NO. RUM NO. TYPE(1) DESCRIPTION(2) A0 1 15 I Logic control input, has internal 4 MΩ pull-down resistor. Controls the switch configuration as shown in Section 9.5. A1 16 14 I Logic control input, has internal 4 MΩ pull-down resistor. Controls the switch configuration as shown in Section 9.5. A2 15 13 I Logic control input, has internal 4 MΩ pull-down resistor. Controls the switch configuration as shown in Section 9.5. D 8 6 I/O EN 2 16 I Active high logic enable, has internal 4 MΩ pull-down resistor. When this pin is low, all switches are turned off. When this pin is high, the Ax logic input determines which switch is turned on. GND 14 12 P Ground (0 V) reference. S1 4 2 I/O Source pin 1. Can be an input or output. S2 5 3 I/O Source pin 2. Can be an input or output. S3 6 4 I/O Source pin 3. Can be an input or output. S4 7 5 I/O Source pin 4. Can be an input or output. S5 12 10 I/O Source pin 5. Can be an input or output. S6 11 9 I/O Source pin 6. Can be an input or output. S7 10 8 I/O Source pin 7. Can be an input or output. S8 9 7 I/O Source pin 8. Can be an input or output. VDD 13 11 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 μF to 10 μF between VDD and GND. VSS 3 1 P Negative power supply. This pin is the most negative power-supply potential. In singlesupply applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 0.1 μF to 10 μF between VSS and GND. NAME Thermal Pad (1) (2) — Drain pin. Can be an input or output. The thermal pad is not connected internally. No requirement to solder this pad, if connected it is recommended that the pad be left floating or tied to GND. I = input, O = output, I/O = input and output, P = power. Refer to Section 9.4 for what to do with unused pins. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 3 TMUX6208, TMUX6209 www.ti.com GND VSS 3 14 VDD S1A 4 13 S1B S2A 5 12 S2B S3A 6 11 S3B S4A 7 10 S4B DA 8 9 DB VSS 1 S1A 2 GND 15 A1 2 13 EN 14 A1 A0 16 15 1 EN A0 16 SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 12 VDD 11 S1B Th ermal 7 8 DB S4B 6 Not to scale DA 4 5 3 S3A S4A S2A Pad 10 S2B 9 S3B No t to scale Figure 6-3. TMUX6209: PW Package 16-Pin TSSOP Figure 6-4. TMUX6209: RUM Package 16-Pin WQFN Top View Top View Table 6-2. TMUX6209 Pin Functions NAME PW NO. RUM NO. DESCRIPTION(2) A0 1 15 I Logic control input, has internal pull-down resistor. Controls the switch configuration as shown in Section 9.5. A1 16 14 I Logic control input, has internal pull-down resistor. Controls the switch configuration as shown in Section 9.5. DA 8 6 I/O Drain Terminal A. Can be an input or an output. DB 9 7 I/O Drain Terminal B. Can be an input or an output. EN 2 16 I Active high logic enable, has internal pull-up resistor. When this pin is low, all switches are turned off. When this pin is high, the Ax logic input determines which switch is turned on. GND 15 13 P Ground (0 V) reference. S1A 4 2 I/O Source pin 1A. Can be an input or output. S1B 13 11 I/O Source pin 1B. Can be an input or output. S2A 5 3 I/O Source pin 2A. Can be an input or output. S2B 12 10 I/O Source pin 2B. Can be an input or output. S3A 6 4 I/O Source pin 3A. Can be an input or output. S3B 11 9 I/O Source pin 3B. Can be an input or output. S4A 7 5 I/O Source pin 4A. Can be an input or output. S4B 10 8 I/O Source pin 4B. Can be an input or output. VDD 14 12 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 μF to 10 μF between VDD and GND. VSS 3 1 P Negative power supply. This pin is the most negative power-supply potential. In singlesupply applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 0.1 μF to 10 μF between VSS and GND. __ The thermal pad is not connected internally. No requirement to solder this pad, if connected it is recommended that the pad be left floating or tied to GND. Thermal Pad (1) (2) 4 TYPE(1) I = input, O = output, I/O = input and output, P = power. Refer to Section 9.4 for what to do with unused pins. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) (2) MIN MAX VDD – VSS VDD Supply voltage VSS UNIT 38 V –0.5 38 V –38 0.5 V VADDRESS or VEN Logic control input pin voltage (EN, A0, A1, A2) –0.5 38 V IADDRESS or IEN Logic control input pin current (EN, A0, A1, A2) –30 30 mA VS or VD Source or drain voltage (Sx, D) VSS–0.5 VDD+0.5 IIK Diode clamp current(3) –30 30 mA IS or ID (CONT) Source or drain continuous current (Sx, D) IDC + 10 %(4) mA TA Ambient temperature –55 150 °C Tstg Storage temperature –65 150 °C TJ Junction temperature 150 °C 1650 mW 700 mW Total power dissipation (QFN Ptot (1) (2) (3) (4) (5) package)(5) Total power dissipation (TSSOP package)(5) V Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground, unless otherwise specified. Pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings. Refer to Source or Drain Continuous Current table for IDC specifications. For QFN package: Ptot derates linearily above TA = 70°C by 24.4mW/°C. For TSSOP package: Ptot derates linearily above TA = 70°C by 10.8mW/°C. 7.2 ESD Ratings VALUE UNIT TMUX6208 in PW package V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/ JEDEC JS-001, all pins(1) ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500 Human body model (HBM), per ANSI/ESDA/ JEDEC JS-001, all pins(1) ±1500 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500 Human body model (HBM), per ANSI/ESDA/ JEDEC JS-001, all pins(1) ±1000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500 V TMUX6209 in PW package V(ESD) Electrostatic discharge V TMUX6208 and TMUX6209 in RUM package V(ESD) (1) (2) Electrostatic discharge V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 5 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 7.3 Thermal Information TMUX620x THERMAL METRIC(1) PW (TSSOP) RUM (WQFN) 16 PINS 16 PINS UNIT RθJA Junction-to-ambient thermal resistance 93.5 41.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 24.9 24.5 °C/W RθJB Junction-to-board thermal resistance 40.0 16.1 °C/W ΨJT Junction-to-top characterization parameter 1.0 0.2 °C/W ΨJB Junction-to-board characterization parameter 39.4 16.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 2.8 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 7.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VDD – VSS (1) Power supply voltage differential NOM 4.5 MAX UNIT 36 V VDD Positive power supply voltage 4.5 36 V VS or VD Signal path input/output voltage (source or drain pin) (Sx, D) VSS VDD V VADDRESS or VEN Address or enable pin voltage 0 36 V IS or ID (CONT) Source or drain continuous current (Sx, D) TA (1) (2) Ambient temperature –40 IDC (2) mA 125 °C VDD and VSS can be any value as long as 4.5 V ≤ (VDD – VSS) ≤ 36 V, and the minimum VDD is met. Refer to Source or Drain Continuous Current table for IDC specifications. 7.5 Source or Drain Continuous Current at supply voltage of VDD ± 10%, VSS ± 10 % (unless otherwise noted) CONTINUOUS CURRENT PER CHANNEL (IDC) PACKAGE TEST CONDITIONS ±15 V Dual Supply +36 V Single PW (TSSOP) RUM (WQFN) (1) 6 Supply(1) TA = 25°C TA = 85°C TA = 125°C UNIT 300 190 110 mA 280 170 100 mA +12 V Single Supply 220 150 90 mA ±5 V Dual Supply 210 140 90 mA +5 V Single Supply 170 110 70 mA ±15 V Dual Supply 400 230 120 mA +36 V Single Supply(1) 380 220 110 mA +12 V Single Supply 310 190 100 mA ±5 V Dual Supply 300 190 100 mA +5 V Single Supply 230 150 90 mA Specified for nominal supply voltage only. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 7.6 ±15 V Dual Supply: Electrical Characteristics VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted) Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT 4 5.9 Ω 7.4 Ω 8.7 Ω 0.7 Ω 0.8 Ω 0.9 Ω 1.5 Ω –40°C to +85°C 1.7 Ω –40°C to +125°C 1.8 Ω ANALOG SWITCH RON VS = –10 V to +10 V ID = –10 mA Refer to On-Resistance On-resistance ΔRON RON FLAT V = –10 V to +10 V On-resistance mismatch between S ID = –10 mA channels Refer to On-Resistance On-resistance flatness VS = 0 V, IS = –10 mA Refer to On-Resistance RON DRIFT On-resistance drift IS(OFF) ID(OFF) IS(ON) ID(ON) Source off leakage current(1) Drain off leakage current(1) Channel on leakage VS = –10 V to +10 V IS = –10 mA Refer to On-Resistance current(2) 25°C –40°C to +85°C –40°C to +125°C 25°C 0.2 –40°C to +85°C –40°C to +125°C 25°C 0.4 –40°C to +125°C VDD = 16.5 V, VSS = –16.5 V Switch state is off VS = +10 V / –10 V VD = –10 V / + 10 V Refer to Off-Leakage Current 25°C VDD = 16.5 V, VSS = –16.5 V Switch state is off VS = +10 V / –10 V VD = –10 V / + 10 V Refer to Off-Leakage Current 25°C VDD = 16.5 V, VSS = –16.5 V Switch state is on VS = VD = ±10 V Refer to On-Leakage Current 0.02 –0.4 0.4 nA –40°C to +85°C –1 1 nA –40°C to +125°C –5 5 nA –0.4 0.04 Ω/°C 0.4 nA –40°C to +85°C –6 0.04 6 nA –40°C to +125°C –42 42 nA 25°C –0.4 0.4 nA –40°C to +85°C –5 0.04 5 nA –40°C to +125°C –40 40 nA 36 V LOGIC INPUTS (EN, A0, A1, A2) VIH Logic voltage high –40°C to +125°C 1.3 VIL Logic voltage low –40°C to +125°C 0 IIH Input leakage current –40°C to +125°C IIL Input leakage current –40°C to +125°C –0.005 µA CIN Logic input capacitance –40°C to +125°C 3.5 pF 25°C 35 0.4 –0.1 0.8 V 1.2 µA POWER SUPPLY IDD VDD supply current VDD = 16.5 V, VSS = –16.5 V Logic inputs = 0 V, 5 V, or VDD 57 µA –40°C to +85°C 60 µA –40°C to +125°C 75 µA 25°C ISS (1) (2) VSS supply current VDD = 16.5 V, VSS = –16.5 V Logic inputs = 0 V, 5 V, or VDD 14 µA –40°C to +85°C 3 15 µA –40°C to +125°C 22 µA When VS is positive, VD is negative, or when VS is negative, VD is positive. When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 7 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 7.7 ±15 V Dual Supply: Switching Characteristics VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V (unless otherwise noted) Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted) PARAMETER tTRAN tON Transition time from control input (EN) tOFF (EN) tBBM TEST CONDITIONS VS = 10 V RL = 300 Ω, CL = 35 pF Refer to Transition Time TYP MAX UNIT 140 195 ns –40°C to +85°C 220 ns –40°C to +125°C 240 ns 195 ns 220 ns 240 ns 268 ns –40°C to +85°C 285 ns –40°C to +125°C 298 ns VS = 10 V RL = 300 Ω, CL = 35 pF Refer to Turn-on and Turn-off Time 25°C Turn-on time from enable 25°C Turn-off time from enable VS = 10 V RL = 300 Ω, CL = 35 pF Refer to Turn-on and Turn-off Time Break-before-make time delay VS = 10 V, RL = 300 Ω, CL = 35 pF Refer to Break-Before-Make MIN 140 –40°C to +85°C –40°C to +125°C 200 25°C 60 –40°C to +85°C 1 –40°C to +125°C 1 ns ns ns 25°C 0.16 ms –40°C to +85°C 0.17 ms –40°C to +125°C 0.17 ms Device turn on time (VDD to output) VDD rise time = 1 µs RL = 300 Ω, CL = 35 pF Refer to Turn-on (VDD) Time tPD Propagation delay RL = 50 Ω , CL = 5 pF Refer to Propagation Delay 25°C 1.8 ns QINJ Charge injection VS = 0 V, CL = 100 pF Refer to Charge Injection 25°C 3 pC OISO Off-isolation RL = 50 Ω , CL = 5 pF VS = 0 V, f = 100 kHz Refer to Off Isolation 25°C –82 dB OISO Off-isolation RL = 50 Ω , CL = 5 pF VS = 0 V, f = 1 MHz Refer to Off Isolation 25°C –62 dB XTALK Crosstalk RL = 50 Ω , CL = 5 pF VS = 0 V, f = 100 kHz Refer to Crosstalk 25°C –85 dB XTALK Crosstalk RL = 50 Ω , CL = 5 pF VS = 0 V, f = 1MHz Refer to Crosstalk 25°C –65 dB BW –3dB Bandwidth (TMUX6208) RL = 50 Ω , CL = 5 pF VS = 0 V Refer to Bandwidth 25°C 30 MHz BW –3dB Bandwidth (TMUX6209) RL = 50 Ω , CL = 5 pF VS = 0 V Refer to Bandwidth 25°C 52 MHz IL Insertion loss RL = 50 Ω , CL = 5 pF VS = 0 V, f = 1 MHz 25°C –0.35 dB 25°C –74 dB TON (VDD) VPP = 0.62 V on VDD and VSS R = 50 Ω , CL = 5 pF, ACPSRR AC Power Supply Rejection Ratio L f = 1 MHz Refer to ACPSRR 8 TA 25°C THD+N Total Harmonic Distortion + Noise VPP = 15 V, VBIAS = 0 V RL = 10 kΩ , CL = 5 pF, f = 20 Hz to 20 kHz Refer to THD + Noise 25°C 0.0003 % CS(OFF) Source off capacitance VS = 0 V, f = 1 MHz 25°C 15 pF CD(OFF) Drain off capacitance (TMUX6208) VS = 0 V, f = 1 MHz 25°C 135 pF Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 7.7 ±15 V Dual Supply: Switching Characteristics (continued) VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V (unless otherwise noted) Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT CD(OFF) Drain off capacitance (TMUX6209) VS = 0 V, f = 1 MHz 25°C 68 pF CS(ON), CD(ON) On capacitance (TMUX6208) VS = 0 V, f = 1 MHz 25°C 185 pF CS(ON), CD(ON) On capacitance (TMUX6209) VS = 0 V, f = 1 MHz 25°C 115 pF Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 9 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 7.8 36 V Single Supply: Electrical Characteristics VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted) Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT 4 6.2 Ω 7.9 Ω 9.4 Ω 0.7 Ω 0.8 Ω 0.9 Ω 1.8 Ω –40°C to +85°C 2.5 Ω –40°C to +125°C 3.1 Ω ANALOG SWITCH RON VS = 0 V to 30 V ID = –10 mA Refer to On-Resistance On-resistance V = 0 V to 30 V On-resistance mismatch between S ID = –10 mA channels Refer to On-Resistance ΔRON RON FLAT On-resistance flatness VS = 18 V, IS = –10 mA Refer to On-Resistance RON DRIFT On-resistance drift IS(OFF) ID(OFF) IS(ON) ID(ON) Source off leakage current(1) Drain off leakage current(1) Channel on leakage VS = 0 V to 30 V IS = –10 mA Refer to On-Resistance current(2) 25°C –40°C to +85°C –40°C to +125°C 25°C 0.2 –40°C to +85°C –40°C to +125°C 25°C 0.4 –40°C to +125°C VDD = 39.6 V, VSS = 0 V Switch state is off VS = 30 V / 1 V VD = 1 V / 30 V Refer to Off-Leakage Current 25°C 0.015 –0.4 0.04 Ω/°C 0.4 nA –40°C to +85°C –2 2 nA –40°C to +125°C –10 10 nA VDD = 39.6 V, VSS = 0 V Switch state is off VS = 30 V / 1 V VD = 1 V / 30 V Refer to Off-Leakage Current 25°C –0.5 0.5 nA –40°C to +85°C –12 12 nA –40°C to +125°C –85 85 nA VDD = 39.6 V, VSS = 0 V Switch state is on VS = VD = 30 V or 1 V Refer to On-Leakage Current 25°C –0.5 0.05 0.5 nA –40°C to +85°C –11 0.05 11 nA –40°C to +125°C –78 78 nA 36 V LOGIC INPUTS (EN, A0, A1, A2) VIH Logic voltage high –40°C to +125°C 1.3 VIL Logic voltage low –40°C to +125°C 0 IIH Input leakage current –40°C to +125°C IIL Input leakage current –40°C to +125°C –0.005 µA CIN Logic input capacitance –40°C to +125°C 3.5 pF 25°C 55 0.4 –0.1 0.8 V 1.2 µA POWER SUPPLY IDD (1) (2) 10 VDD supply current VDD = 39.6 V, VSS = 0 V Logic inputs = 0 V, 5 V, or VDD 86 µA –40°C to +85°C 90 µA –40°C to +125°C 105 µA When VS is positive, VD is negative, and vice versa. When VS is at a voltage potential, VD is floating, and vice versa. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 7.9 36 V Single Supply: Switching Characteristics VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted) Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted) PARAMETER tTRAN tON (EN) tOFF (EN) tBBM Transition time from control input TEST CONDITIONS VS = 18 V RL = 300 Ω, CL = 35 pF Refer to Transition Time TA TYP MAX UNIT 105 200 ns –40°C to +85°C 225 ns –40°C to +125°C 240 ns 200 ns 220 ns 240 ns 290 ns –40°C to +85°C 305 ns –40°C to +125°C 315 ns VS = 18 V RL = 300 Ω, CL = 35 pF Refer to Turn-on and Turn-off Time 25°C Turn-on time from enable 25°C Turn-off time from enable VS = 18 V RL = 300 Ω, CL = 35 pF Refer to Turn-on and Turn-off Time Break-before-make time delay VS = 18 V, RL = 300 Ω, CL = 35 pF Refer to Break-Before-Make MIN 25°C 115 –40°C to +85°C –40°C to +125°C 90 25°C 40 –40°C to +85°C 1 –40°C to +125°C 1 ns ns ns 25°C 0.14 ms –40°C to +85°C 0.15 ms –40°C to +125°C 0.15 ms Device turn on time (VDD to output) VDD rise time = 1 µs RL = 300 Ω, CL = 35 pF Refer to Turn-on (VDD) Time tPD Propagation delay RL = 50 Ω , CL = 5 pF Refer to Propagation Delay 25°C 2.5 ns QINJ Charge injection VS = 18 V, CL = 100 pF Refer to Charge Injection 25°C 2 pC OISO Off-isolation RL = 50 Ω , CL = 5 pF VS = 6 V, f = 1 MHz Refer to Off Isolation 25°C –62 dB XTALK Crosstalk RL = 50 Ω , CL = 5 pF VS = 6 V, f = 100 kHz Refer to Crosstalk 25°C –85 dB XTALK Crosstalk RL = 50 Ω , CL = 5 pF VS = 6 V, f = 1MHz Refer to Crosstalk 25°C –65 dB BW –3dB Bandwidth (TMUX6208) RL = 50 Ω , CL = 5 pF VS = 6 V Refer to Bandwidth 25°C 30 MHz BW –3dB Bandwidth (TMUX6209) RL = 50 Ω , CL = 5 pF VS = 6 V 25°C 50 MHz IL Insertion loss RL = 50 Ω , CL = 5 pF VS = 6 V, f = 1 MHz 25°C –0.35 dB VPP = 0.62 V on VDD and VSS RL = 50 Ω , CL = 5 pF, f = 1 MHz Refer to ACPSRR 25°C –70 dB THD+N VPP =18 V, VBIAS = 18 V R = 10 kΩ , CL = 5 pF, Total Harmonic Distortion + Noise L f = 20 Hz to 20 kHz Refer to THD + Noise 25°C 0.0003 % CS(OFF) Source off capacitance VS = 18 V, f = 1 MHz 25°C 15 pF CD(OFF) Drain off capacitance (TMUX6208) VS = 18 V, f = 1 MHz 25°C 138 pF CD(OFF) Drain off capacitance (TMUX6209) VS = 18 V, f = 1 MHz 25°C 68 pF CS(ON), CD(ON) On capacitance (TMUX6208) VS = 18 V, f = 1 MHz 25°C 185 pF TON (VDD) ACPSRR AC Power Supply Rejection Ratio Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 11 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 7.9 36 V Single Supply: Switching Characteristics (continued) VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted) Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted) PARAMETER CS(ON), CD(ON) 12 On capacitance (TMUX6209) TEST CONDITIONS VS = 18 V, f = 1 MHz TA 25°C Submit Document Feedback MIN TYP 115 MAX UNIT pF Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 7.10 12 V Single Supply: Electrical Characteristics VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted) Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT ANALOG SWITCH RON VS = 0 V to 10 V ID = –10 mA Refer to On-Resistance On-resistance ΔRON RON FLAT V = 0 V to 10 V On-resistance mismatch between S ID = –10 mA channels Refer to On-Resistance On-resistance flatness VS = 6 V, IS = –10 mA Refer to On-Resistance RON DRIFT On-resistance drift IS(OFF) ID(OFF) IS(ON) ID(ON) Source off leakage current(1) Drain off leakage current(1) Channel on leakage VS = 0 V to 10 V IS = –10 mA Refer to On-Resistance current(2) 25°C 7 11.8 Ω 14.2 Ω 16.5 Ω 0.7 Ω 0.8 Ω 0.9 Ω 3.4 Ω –40°C to +85°C 3.8 Ω –40°C to +125°C 4.6 Ω –40°C to +85°C –40°C to +125°C 25°C 0.2 –40°C to +85°C –40°C to +125°C 25°C 1.7 –40°C to +125°C VDD = 13.2 V, VSS = 0 V Switch state is off VS = 10 V / 1 V VD = 1 V / 10 V Refer to Off-Leakage Current 25°C VDD = 13.2 V, VSS = 0 V Switch state is off VS = 10 V / 1 V VD = 1 V / 10 V Refer to Off-Leakage Current 25°C VDD = 13.2 V, VSS = 0 V Switch state is on VS = VD = 10 V or 1 V Refer to On-Leakage Current 0.03 –0.4 0.4 nA –40°C to +85°C –1 1 nA –40°C to +125°C –8 8 nA –0.4 0.04 Ω/°C 0.4 nA –40°C to +85°C –5 0.05 5 nA –40°C to +125°C –30 30 nA 25°C –0.4 0.4 nA –40°C to +85°C –4 0.05 4 nA –40°C to +125°C –28 28 nA 36 V LOGIC INPUTS (EN, A0, A1, A2) VIH Logic voltage high –40°C to +125°C 1.3 VIL Logic voltage low –40°C to +125°C 0 IIH Input leakage current –40°C to +125°C IIL Input leakage current –40°C to +125°C –0.005 µA CIN Logic input capacitance –40°C to +125°C 3.5 pF 25°C 30 0.4 –0.1 0.8 V 1.2 µA POWER SUPPLY IDD (1) (2) VDD supply current VDD = 13.2 V, VSS = 0 V Logic inputs = 0 V, 5 V, or VDD 48 µA –40°C to +85°C 54 µA –40°C to +125°C 65 µA When VS is positive, VD is negative, or when VS is negative, VD is positive. When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 13 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 7.11 12 V Single Supply: Switching Characteristics VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted) Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted) PARAMETER tTRAN tON Transition time from control input (EN) tOFF (EN) tBBM TEST CONDITIONS VS = 8 V RL = 300 Ω, CL = 35 pF Refer to Transition Time TA TYP MAX UNIT 180 210 ns –40°C to +85°C 245 ns –40°C to +125°C 276 ns 202 ns 235 ns 265 ns 318 ns –40°C to +85°C 350 ns –40°C to +125°C 370 ns VS = 8 V RL = 300 Ω, CL = 35 pF Refer to Turn-on and Turn-off Time 25°C Turn-on time from enable 25°C Turn-off time from enable VS = 8 V RL = 300 Ω, CL = 35 pF Refer to Turn-on and Turn-off Time Break-before-make time delay VS = 8 V, RL = 300 Ω, CL = 35 pF Refer to Break-Before-Make MIN 25°C 115 –40°C to +85°C –40°C to +125°C 290 25°C 50 –40°C to +85°C 1 –40°C to +125°C 1 ns ns ns 25°C 0.16 ms –40°C to +85°C 0.17 1 ms –40°C to +125°C 0.17 1 ms Device turn on time (VDD to output) VDD rise time = 1 µs RL = 300 Ω, CL = 35 pF Refer to Turn-on (VDD) Time tPD Propagation delay RL = 50 Ω , CL = 5 pF Refer to Propagation Delay 25°C 2.5 ns QINJ Charge injection VS = 6 V, CL = 100 pF Refer to Charge Injection 25°C 2 pC OISO Off-isolation RL = 50 Ω , CL = 5 pF VS = 6 V, f = 100 kHz 25°C –82 dB OISO Off-isolation RL = 50 Ω , CL = 5 pF VS = 6 V, f = 1 MHz Refer to Off Isolation 25°C –62 dB XTALK Crosstalk RL = 50 Ω , CL = 5 pF VS = 6 V, f = 100 kHz Refer to Crosstalk 25°C –85 dB XTALK Crosstalk RL = 50 Ω , CL = 5 pF VS = 6 V, f = 1MHz Refer to Crosstalk 25°C –65 dB BW –3dB Bandwidth (TMUX6208) RL = 50 Ω , CL = 5 pF VS = 6 V Refer to Bandwidth 25°C 28 MHz IL Insertion loss RL = 50 Ω , CL = 5 pF VS = 6 V, f = 1 MHz 25°C –0.6 dB VPP = 0.62 V on VDD and VSS RL = 50 Ω , CL = 5 pF, f = 1 MHz Refer to ACPSRR 25°C –74 dB THD+N VPP = 6 V, VBIAS = 6 V RL = 10 kΩ , CL = 5 pF, Total Harmonic Distortion + Noise f = 20 Hz to 20 kHz Refer to THD + Noise 25°C 0.0007 % CS(OFF) Source off capacitance VS = 6 V, f = 1 MHz 25°C 17 pF CD(OFF) Drain off capacitance (TMUX6208) VS = 6 V, f = 1 MHz 25°C 155 pF CD(OFF) Drain off capacitance (TMUX6209) VS = 6 V, f = 1 MHz 25°C 78 pF CS(ON), CD(ON) On capacitance (TMUX6208) VS = 6 V, f = 1 MHz 25°C 200 pF TON (VDD) ACPSRR AC Power Supply Rejection Ratio 14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 7.11 12 V Single Supply: Switching Characteristics (continued) VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted) Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted) PARAMETER CS(ON), CD(ON) On capacitance (TMUX6209) TEST CONDITIONS VS = 6 V, f = 1 MHz TA 25°C MIN TYP 122 MAX UNIT pF Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 15 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 7.12 ±5 V Dual Supply: Electrical Characteristics VDD = +5 V ± 10%, VSS = –5 V ±10%, GND = 0 V (unless otherwise noted) Typical at VDD = +5 V, VSS = –5 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT 7 13.5 Ω 16.2 Ω 18.5 Ω 0.7 Ω 0.8 Ω 0.9 Ω 3.8 Ω ANALOG SWITCH RON VDD = +4.5 V, VSS = –4.5 V VS = –4.5 V to +4.5 V ID = –10 mA On-resistance 25°C –40°C to +85°C –40°C to +125°C 25°C On-resistance mismatch between VS = –4.5 V to +4.5 V channels ID = –10 mA ΔRON 0.2 –40°C to +85°C –40°C to +125°C 25°C 2 VS = –4.5 V to +4.5 V ID = –10 mA –40°C to +85°C 4.2 Ω –40°C to +125°C 4.9 Ω RON DRIFT On-resistance drift VS = 0 V, IS = –10 mA –40°C to +125°C 25°C –0.5 IS(OFF) VDD = +5.5 V, VSS = –5.5 V Switch state is off VS = +4.5 V / –4.5 V VD = –4.5 V / + 4.5 V –40°C to +85°C –1.5 VDD = +5.5 V, VSS = –5.5 V Switch state is off VS = +4.5 V / –4.5 V VD = –4.5 V / + 4.5 V 25°C –0.5 –40°C to +85°C –40°C to +125°C 25°C –0.5 RON FLAT ID(OFF) IS(ON) ID(ON) On-resistance flatness Source off leakage Drain off leakage current(1) current(1) Channel on leakage current(2) VDD = +5.5 V, VSS = –5.5 V Switch state is on VS = VD = ±4.5 V 0.03 –40°C to +125°C 0.02 –8 Ω/°C 0.5 nA 1.5 nA 8 nA 0.5 nA –3.5 3.5 nA –28 28 nA 0.04 0.5 nA –40°C to +85°C –3 0.04 3 nA –40°C to +125°C –26 26 nA LOGIC INPUTS (EN, A0, A1, A2) VIH Logic voltage high –40°C to +125°C 1.3 36 V VIL Logic voltage low –40°C to +125°C 0 0.8 V IIH Input leakage current –40°C to +125°C 1.2 µA IIL Input leakage current –40°C to +125°C CIN Logic input capacitance 0.4 –0.1 –0.005 µA –40°C to +125°C 3.5 pF 25°C 25 POWER SUPPLY IDD VDD supply current VDD = +5.5 V, VSS = –5.5 V Logic inputs = 0 V, 5 V, or VDD –40°C to +85°C –40°C to +125°C ISS (1) (2) 16 VSS supply current µA 44 µA 55 µA 6.2 µA –40°C to +85°C 7 µA –40°C to +125°C 15 µA 25°C VDD = +5.5 V, VSS = –5.5 V Logic inputs = 0 V, 5 V, or VDD 38 2 When VS is positive, VD is negative, or when VS is negative, VD is positive. When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 7.13 ±5 V Dual Supply: Switching Characteristics VDD = +5 V ± 10%, VSS = –5 V ±10%, GND = 0 V (unless otherwise noted) Typical at VDD = +5 V, VSS = –5 V, TA = 25℃ (unless otherwise noted) PARAMETER tTRAN tON (EN) tOFF (EN) tBBM Transition time from control input TEST CONDITIONS VS = 3 V RL = 300 Ω, CL = 35 pF Refer to Transition Time TA TYP MAX UNIT 125 250 ns –40°C to +85°C 280 ns –40°C to +125°C 305 ns 245 ns 278 ns 305 ns 372 ns –40°C to +85°C 400 ns –40°C to +125°C 420 ns VS = 3 V RL = 300 Ω, CL = 35 pF Refer to Turn-on and Turn-off Time 25°C Turn-on time from enable 25°C Turn-off time from enable VS = 3 V RL = 300 Ω, CL = 35 pF Refer to Turn-on and Turn-off Time Break-before-make time delay VS = 3 V, RL = 300 Ω, CL = 35 pF Refer to Break-Before-Make MIN 25°C 128 –40°C to +85°C –40°C to +125°C 300 25°C 50 –40°C to +85°C 1 –40°C to +125°C 1 ns ns ns 25°C 0.16 ms –40°C to +85°C 0.17 1 ms –40°C to +125°C 0.17 1 ms Device turn on time (VDD to output) VDD rise time = 1 µs RL = 300 Ω, CL = 35 pF Refer to Turn-on (VDD) Time tPD Propagation delay RL = 50 Ω , CL = 5 pF Refer to Propagation Delay 25°C 2 ns QINJ Charge injection VS = 0 V, CL = 100 pF Refer to Charge Injection 25°C 1.2 pC OISO Off-isolation RL = 50 Ω , CL = 5 pF VS = 0 V, f = 100 kHz Refer to Off Isolation 25°C –82 dB OISO Off-isolation RL = 50 Ω , CL = 5 pF VS = 0 V, f = 1 MHz Refer to Off Isolation 25°C –62 dB XTALK Crosstalk RL = 50 Ω , CL = 5 pF VS = 0 V, f = 100 kHz Refer to Crosstalk 25°C –85 dB XTALK Crosstalk RL = 50 Ω , CL = 5 pF VS = 0 V, f = 1MHz Refer to Crosstalk 25°C –65 dB BW –3dB Bandwidth (TMUX6208) RL = 50 Ω , CL = 5 pF VS = 0 V Refer to Bandwidth 25°C 28 MHz BW –3dB Bandwidth (TMUX6209) RL = 50 Ω , CL = 5 pF VS = 0 V 25°C 54 MHz IL Insertion loss RL = 50 Ω , CL = 5 pF VS = 0 V, f = 1 MHz 25°C –0.7 dB VPP = 0.62 V on VDD and VSS RL = 50 Ω , CL = 5 pF, f = 1 MHz Refer to ACPSRR 25°C –76 dB THD+N VPP = 5 V, VBIAS = 0 V RL = 10 kΩ , CL = 5 pF, Total Harmonic Distortion + Noise f = 20 Hz to 20 kHz Refer to THD + Noise 25°C 0.0017 % CS(OFF) Source off capacitance VS = 0 V, f = 1 MHz 25°C 18 pF CD(OFF) Drain off capacitance (TMUX6208) VS = 0 V, f = 1 MHz 25°C 160 pF TON (VDD) ACPSRR AC Power Supply Rejection Ratio Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 17 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 7.13 ±5 V Dual Supply: Switching Characteristics (continued) VDD = +5 V ± 10%, VSS = –5 V ±10%, GND = 0 V (unless otherwise noted) Typical at VDD = +5 V, VSS = –5 V, TA = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT CD(OFF) Drain off capacitance (TMUX6209) VS = 0 V, f = 1 MHz 25°C 80 pF CS(ON), CD(ON) On capacitance (TMUX6208) VS = 0 V, f = 1 MHz 25°C 205 pF CS(ON), CD(ON) On capacitance (TMUX6209) VS = 0 V, f = 1 MHz 25°C 124 pF 18 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 7.14 Typical Characteristics at TA = 25°C (unless otherwise noted) 8 VDD = 18 V, V SS VDD = 15 V, V SS On Resistance ( ) 7
–18 V –15 V 6 5 4 3 2 -25 -20 -15 -10 -5 0 5 10 15 VS or VD - Source or Drain Voltage (V) 20 25 . . Figure 7-1. On-Resistance vs Source or Drain Voltage – Dual Supply Figure 7-2. On-Resistance vs Source or Drain Voltage – Dual Supply 12 VDD = 36 V, V SS = 0 V VDD = 24 V, V SS = 0 V VDD = 18 V, V SS = 0 V On Resistance (Ω) 10 8 6 4 2 0 4 8 12 16 20 24 28 VS or VD - Source or Drain Voltage (V) 32 36 D003 . . Figure 7-3. On-Resistance vs Source or Drain Voltage – Single Supply Figure 7-4. On-Resistance vs Source or Drain Voltage – Single Supply VDD = 15 V, VSS = -15 V Figure 7-5. On-Resistance vs Temperature VDD = 36 V, VSS = 0 V Figure 7-6. On-Resistance vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 19 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 7.14 Typical Characteristics (continued) at TA = 25°C (unless otherwise noted) VDD = 12 V, VSS = 0 V VDD = 5 V, VSS = -5 V Figure 7-7. On-Resistance vs Temperature Figure 7-8. On-Resistance vs Temperature VDD = 15 V, VSS = -15 V VDD = 36 V, VSS = 0 V Figure 7-9. Leakage Current vs Temperature Figure 7-10. Leakage Current vs Temperature 30 Leakage Current (nA) 20 10 ID(OFF) VS/VD = 4.5V/–4.5V ID(OFF) VS/VD = –4.5V/4.5V I(ON) –4.5V I(ON) 4.5V IS(OFF) VS/VD = 4.5V/–4.5V IS(OFF) VS/VD = –4.5V/4.5V 0 -10 -20 -30 -40 -25 -10 VDD = 12 V, VSS = 0 V Figure 7-11. Leakage Current vs Temperature 20 5 20 35 50 65 Temperature (°C) 80 95 110 125 D012 VDD = 5 V, VSS = -5 V Figure 7-12. Leakage Current vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 7.14 Typical Characteristics (continued) at TA = 25°C (unless otherwise noted) 60 Supply Current (μA) 50 45 40 35 30 40 VDD = 15 V, V SS = –15 V VDD = 5 V, V SS = –5 V 30 Charge Injection (pC) VDD = 15 V, V SS –15 V VDD = 5 V, V SS –5 V VDD = 12 V, V SS = 0 V VDD = 5 V, V SS = 0 V 55 20 10 0 -10 25 -20 20 15 0 4 8 12 16 20 24 Logic Voltage (V) 28 32 -30 -20 36 -15 -10 -5 0 5 Source Voltage (V) . 20 Figure 7-14. Charge Injection vs Source Voltage – Dual Supply 50 70 VDD = 15 V, V SS = –15 V VDD = 5 V, V SS = –5 V 40 VDD = 36 V, V SS = 0 V VDD = 20 V, V SS = 0 V VDD = 15 V, V SS = 0 V VDD = 12 V, V SS = 0 V VDD = 5 V, V SS = 0 V 60 50 Charge Injection (pC) 30 Charge Injection (pC) 15 . Figure 7-13. Supply Current vs Logic Voltage 20 10 0 -10 -20 -30 40 30 20 10 0 -10 -40 -20 -50 -20 -30 -15 -10 -5 0 5 Drain Voltage (V) 10 15 20 0 4 8 12 16 20 24 Source Voltage (V) . 28 32 36 . Figure 7-15. Charge Injection vs Drain Voltage – Dual Supply Figure 7-16. Charge Injection vs Source Voltage – Single Supply 145 90 80 70 60 50 40 30 20 10 0 -10 -20 -30 -40 VDD = 36 V, V SS = 0 V VDD = 20 V, V SS = 0 V VDD = 15 V, V SS = 0 V VDD = 12 V, V SS = 0 V VDD = 5 V, V SS = 0 V 140 135 VDD = 15V, V SS = –15V VDD = 36V, V SS = 0V VDD = 12V, V SS = 0V 130 125 Time (ns) Charge Injection (pC) 10 120 115 110 105 100 95 0 4 8 12 16 20 24 Drain Voltage (V) 28 32 36 90 -40 -25 -10 . 5 20 35 50 65 Temperature (°C) 80 95 110 125 . Figure 7-17. Charge Injection vs Drain Voltage – Single Supply Figure 7-18. TTRANSITION vs Temperature Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 21 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 7.14 Typical Characteristics (continued) at TA = 25°C (unless otherwise noted) 400 T(OFF) T(ON) Turn On/Off Time (ns) 360 320 280 240 200 160 120 80 -40 -25 -10 80 95 110 125 Figure 7-20. TON and TOFF vs Temperature Figure 7-19. TON and TOFF vs Temperature Off-Isolation (dB) 20 35 50 65 Temperature (°C) VDD = 36 V, VSS = 0 V VDD = 15 V, VSS = -15 V 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 5 VDD = 15V, V SS = –15V VDD = 36V, V SS = 0V VDD = 12V, V SS = 0V 1 10 100 1k 10k 100k Frequency (Hz) 1M 10M 100M . VDD = 15 V, VSS = -15 V . Figure 7-21. Off-Isolation vs Frequency 0.006 0.005 0.004 Figure 7-22. Crosstalk vs Frequency VDD = 15V, V SS = –15V VDD = 5V, V SS = –5V THD+N (%) 0.003 0.002 0.001 0.0007 0.0005 0.0004 0.0003 10 100 1k Frequency (Hz) 10k D028 . . Figure 7-23. THD+N vs Frequency (Dual Supply) 22 Figure 7-24. THD+N vs Frequency (Single Supply) Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 7.14 Typical Characteristics (continued) at TA = 25°C (unless otherwise noted) VDD = +15 V, VSS = -15 V Figure 7-25. On Response vs Frequency VDD = +15 V, VSS = -15 V Figure 7-26. ACPSRR vs Frequency VDD = +15 V, VSS = -15 V Figure 7-27. Capacitance vs Source Voltage or Drain Voltage VDD = 12 V, VSS = 0 V Figure 7-28. Capacitance vs Source Voltage or Drain Voltage Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 23 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 8 Parameter Measurement Information 8.1 On-Resistance The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device. The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-resistance. Figure 8-1 shows the measurement setup used to measure RON. Voltage (V) and current (ISD) are measured using this setup, and RON is computed with RON = V / ISD: V ISD Sx D VS RON Figure 8-1. On-Resistance Measurement Setup 8.2 Off-Leakage Current There are two types of leakage currents associated with a switch during the off state: • • Source off-leakage current Drain off-leakage current Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is off. This current is denoted by the symbol IS(OFF). Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off. This current is denoted by the symbol ID(OFF). Figure 8-2 shows the setup used to measure both off-leakage currents. VDD VSS VDD VSS Is (OFF) A S1 S1 ID (OFF) S2 S2 D D A VS S8 S8 VD VS VD GND GND IS(OFF) ID(OFF) Figure 8-2. Off-Leakage Measurement Setup 24 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 8.3 On-Leakage Current Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch is on. This current is denoted by the symbol IS(ON). Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is on. This current is denoted by the symbol ID(ON). Either the source pin or drain pin is left floating during the measurement. Figure 8-3 shows the circuit used for measuring the on-leakage current, denoted by IS(ON) or ID(ON). VDD VSS VDD VSS Is (ON) A S1 D N.C. N.C. ID (ON) S1 D A S2 S2 S8 S8 VS VD VS VS GND GND IS(ON) ID(ON) Figure 8-3. On-Leakage Measurement Setup 8.4 Transition Time Transition time is defined as the time taken by the output of the device to rise or fall 90% after the address signal has risen or fallen past the logic threshold. The 90% transition measurement is utilized to provide the timing of the device. System level timing can then account for the time constant added from the load resistance and load capacitance. Figure 8-4 shows the setup used to measure transition time, denoted by the symbol tTRANSITION. VDD 0.1 µF 0.1 µF 3V VADDRESS VSS tr < 20 ns 50% 50% VDD tf < 20 ns VS VSS S1 0V D tTRANSITION tTRANSITION Output S2 90% S8 RL CL Output 10% 0V A0 A1 VADDRESS A2 GND Figure 8-4. Transition-Time Measurement Setup Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 25 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 8.5 tON(EN) and tOFF(EN) Turn-on time is defined as the time taken by the output of the device to rise to 90% after the enable has risen past the logic threshold. The 90% measurement is utilized to provide the timing of the device. System level timing can then account for the time constant added from the load resistance and load capacitance. Figure 8-7 shows the setup used to measure turn-on time, denoted by the symbol tON(EN). Turn-off time is defined as the time taken by the output of the device to fall to 10% after the enable has fallen past the logic threshold. The 10% measurement is utilized to provide the timing of the device. System level timing can then account for the time constant added from the load resistance and load capacitance. Figure 8-7 shows the setup used to measure turn-off time, denoted by the symbol tOFF(EN). VSS VDD VSS 0.1 µF 0.1 µF 3V VEN VDD tr < 20 ns 50% 50% tf < 20 ns VS 0V S1 D Output tOFF tON S2 90% RL Output CL S8 10% 0V EN A0 A1 VEN A2 GND Figure 8-5. Turn-On and Turn-Off Time Measurement Setup 8.6 Break-Before-Make Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is switching. The output first breaks from the on-state switch before making the connection with the next on-state switch. The time delay between the break and the make is known as break-before-make delay. Figure 8-6 shows the setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM). VSS VDD VSS 0.1 µF 0.1 µF 3V VADDRESS VDD tr < 20ns tf < 20ns VS 0V S1 D Output S2-S7 RL Output 80% CL S8 tBBM 1 tBBM 2 A0 0V tOPEN (BBM) = min ( tBBM 1, tBBM 2) A1 VADDRESS A2 GND Figure 8-6. Break-Before-Make Delay Measurement Setup 26 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 8.7 tON (VDD) Time The tON (VDD) time is defined as the time taken by the output of the device to rise to 90% after the supply has risen past the supply threshold. The 90% measurement is used to provide the timing of the device turning on in the system. Figure 8-7 shows the setup used to measure turn on time, denoted by the symbol tON (VDD). VSS 0.1 µF 0.1 µF VDD VDD VS VSS S1 VDD Supply Ramp D tr = 10 µs Output 4.5 V S2 RL 0V CL S8 tON 90% Output A0 A1 0V EN 3V A2 GND Figure 8-7. tON (VDD) Time Measurement Setup 8.8 Propagation Delay Propagation delay is defined as the time taken by the output of the device to rise or fall 50% after the input signal has risen or fallen past the 50% threshold. Figure 8-8 shows the setup used to measure propagation delay, denoted by the symbol tPD. VDD 0.1 µF 0.1 µF 250 mV Input (VS) VSS tr < 40ps 50% 50% VDD tf < 40ps VS 0V tPD 1 50 VSS S1 tPD 2 D RL S8 Output 50% Output S2 CL 50% GND 0V tProp Delay = max ( tPD 1, tPD 2) Figure 8-8. Propagation Delay Measurement Setup Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 27 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 8.9 Charge Injection The TMUX6208 has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal. The amount of charge injected into the source or drain of the device is known as charge injection, and is denoted by the symbol QINJ. Figure 8-9 shows the setup used to measure charge injection from source (Sx) to drain (D). VDD VSS 0.1 µF 0.1 µF 3V VEN VDD tr < 20 ns 0V QINJ = CL × Output S2 N.C. S8 N.C. EN VOUT VOUT S1 D VD Output VD VSS tf < 20 ns CL VEN A0 A1 GND A2 Figure 8-9. Charge-Injection Measurement Setup 8.10 Off Isolation Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the source pin (Sx) of an off-channel. Figure 8-10 shows the setup used to measure, and the equation used to calculate off isolation. VDD VSS 0.1 µF Network Analyzer 0.1 µF VDD VS VSS S1 50Ÿ VSIG VOUT D 50Ÿ Sx 50Ÿ GND 1BB +OKH=PEKJ = 20 × .KC 8176 85 Figure 8-10. Off Isolation Measurement Setup 28 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 8.11 Crosstalk Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied at the source pin (Sx) of an on-channel. Figure 8-11 shows the setup used to measure, and the equation used to calculate crosstalk. VDD VSS VDD VSS 0.1 µF Network Analyzer 0.1 µF VS S1 D VOUT 50Ÿ VSIG S2 50Ÿ 50Ÿ Sx 50Q GND %NKOOP=HG = 20 × .KC 8176 85 Figure 8-11. Crosstalk Measurement Setup 8.12 Bandwidth Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. Figure 8-12 shows the setup used to measure bandwidth. VDD VSS VDD VSS 0.1 µF Network Analyzer 0.1 µF VS S1 VOUT 50Ÿ VSIG D 50Ÿ Sx 50Ÿ GND $=J@SE@PD = 20 × .KC 8176 85 Figure 8-12. Bandwidth Measurement Setup Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 29 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 8.13 THD + Noise The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the mux output. The on-resistance of the device varies with the amplitude of the input signal and results in distortion when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as THD+N. VDD VSS 0.1 µF 0.1 µF VDD VSS Audio Precision S1 40 Ÿ D VOUT VS RL Other Sx pins 50Ÿ GND Figure 8-13. THD+N Measurement Setup 8.14 Power Supply Rejection Ratio (PSRR) PSRR measures the ability of a device to prevent noise and spurious signals that appear on the supply voltage pin from coupling to the output of the switch. The DC voltage on the device supply is modulated by a sine wave of 620 mVPP. The ratio of the amplitude of signal on the output to the amplitude of the modulated signal is the ACPSRR. A high ratio represents a high degree of tolerance to supply rail variation. Figure 8-14 shows how the decoupling capacitors reduce high frequency noise on the supply pins. This helps stabilize the supply and immediately filter as much of the supply noise as possible. VDD Network Analyzer DC Bias Injector 50 Ÿ VSS With & Without Capacitor 0.1 µF VSS VDD 620 mVPP S1 VBIAS VIN 0.1 µF 50 Ÿ Sx 50 Ÿ VOUT RL D GND CL 2544 = 20 × .KC 8176 8+0 Figure 8-14. ACPSRR Measurement Setup 30 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 9 Detailed Description 9.1 Overview The TMUX6208 is an 8:1, 1-channel multiplexer and the TMUX6209 is a 4:1, 2 channel multiplexer. Each input is turned on or turned off based on the state of the address lines and enable pin. 9.2 Functional Block Diagram VDD VSS VDD VSS SW SW S1 S1A DA ... SW S2 SW S4A SW ... D S1B DB ... SW SW S4B S8 A0 A1 Logic Decoder EN A0 Logic Decoder EN A1 A2 TMUX6208 TMUX6209 9.3 Feature Description 9.3.1 Bidirectional Operation The TMUX6208 and TMUX6209 conduct equally well from source (Sx) to drain (D) or from drain (D) to source (Sx). Each channel has very similar characteristics in both directions and supports both analog and digital signals. 9.3.2 Rail-to-Rail Operation The valid signal path input or output voltage for TMUX6208 and TMUX6209 ranges from VSS to VDD. 9.3.3 1.8 V Logic Compatible Inputs TMUX6208 and TMUX6209 support 1.8-V logic compatible control for all logic control inputs. 1.8-V logic level inputs allows the to interface with processors that have lower logic I/O rails and eliminates the need for an external translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations refer to Simplifying Design with 1.8 V logic Muxes and Switches. 9.3.4 Integrated Pull-Down Resistor on Logic Pins The TMUX620x has internal weak pull-down resistors to GND to ensure the logic pins are not left floating. The value of this pull-down resistor is approximatly 4 MΩ, but is clamped to about 1 µA at higher voltages. This feature integrates up to four external components and reduces system size and cost. 9.3.5 Fail-Safe Logic TMUX6208 and TMUX6209 support Fail-Safe Logic on the control input pins (EN and Ax) allowing it to operate up to 36 V, regardless of the state of the supply pins. This feature allows voltages on the control pins to be applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic feature allows the TMUX6208 and TMUX6209 logic input pins to ramp up to +36 V while VDD and VSS = 0 V. The logic control inputs are protected against positive faults of up to +36 V in powered-off condition, but do not offer protection against negative overvoltage conditions. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 31 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 9.3.6 Latch-Up Immune Latch-Up is a condition where a low impedance path is created between a supply pin and ground. This condition is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic damage due to excessive current levels. The Latch-Up condition typically requires a power cycle to eliminate the low impedance path. The TMUX62xx family of devices are constructed on Silicon on Insulator (SOI) based process where an oxide layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events due to overvoltage or current injections. The latch-up immunity feature allows the TMUX62xx family of switches and multiplexers to be used in harsh environments. For more information on latch-up immunity refer to Using Latch Up Immune Multiplexers to Help Improve System Reliability. 9.3.7 Ultra-Low Charge Injection Figure 9-1 shows that the TMUX620x have a transmission gate topology. Any mismatch in the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed. OFF ON CGSN CGDN S D CGSP CGDP OFF ON Figure 9-1. Transmission Gate Topology The TMUX620x contain specialized architecture to reduce charge injection on the Drain (D). To further reduce charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the Source (Sx). This will ensure that excess charge from the switch transition will be pushed into the compensation capacitor on the Source (Sx) instead of the Drain (D). As a general rule of thumb, Cp should be 20x larger than the equivalent load capacitance on the Drain (D). Figure 9-2 shows charge injection variation with different compensation capacitors on the Source side. This plot was captured on the TMUX6219 as part of the TMUX62xx family with a 100pF load capacitance. Figure 9-2. Charge Injection Compesation 32 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 9.4 Device Functional Modes When the EN pin of the TMUX6208 is pulled high, one of the switches is closed based on the state of the Ax pin. Similarly, when the EN pin of the TMUX6209 is pulled high, two of the switches are closed based on the state of the address lines. When the EN pin is pulled low, all of the switches are in an open state regardless of the state of the Ax pin. The control pins can be as high as 36 V. The TMUX6208 and TMUX6209 can be operated without any external components except for the supply decoupling capacitors. The EN and Ax pins have internal pull-down resistors of 4 MΩ. If unused, Ax and EN pins must be tied to GND in order to ensure the device does not consume additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path inputs (Sx or D) should be connected to GND. 9.5 Truth Tables Table 9-1 shows the truth tables for the TMUX6208. Table 9-1. TMUX6208 Truth Table (1) EN A2 A1 A0 Selected Source Connected To Drain (D) Pin 0 X(1) X X All sources are off (HI-Z) 1 0 0 0 S1 1 0 0 1 S2 1 0 1 0 S3 1 0 1 1 S4 1 1 0 0 S5 1 1 0 1 S6 1 1 1 0 S7 1 1 1 1 S8 X denotes do not care. Table 9-2 show the truth tables for the TMUX6209. Table 9-2. TMUX6209 Truth Table (1) EN A0 A1 Selected Source Connected To Drain (D) Pin 0 X(1) X All sources are off (HI-Z) 1 0 0 S1x 1 0 1 S2x 1 1 0 S3x 1 1 1 S4x X denotes do not care. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 33 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 10 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 10.1 Application Information The TMUX6208 and TMUX6209 are part of the precision switches and multiplexers family of devices. These devices operate with dual supplies (±4.5 V to ±18 V), a single supply (4.5 V to 36 V), or asymmetric supplies (such as VDD = 12 V, VSS = –5 V), and offer true rail-to-rail input and output. The TMUX6208 and TMUX6209 offer low RON, low on and off leakage currents and ultra-low charge injection performance. These features make the TMUX62xx a family of precision, robust, high-performance analog multiplexers for high-voltage, industrial applications. 10.2 Typical Application One example to take advantage of TMUX6208 performance is the implementation of multiplexed data aquisition front end for multiple input sensors. Applications such as analog input modules for programmable logic controllers (PLCs), data aquisition (DAQ), and seminconducter test systems commonly need to monitor multiple signals into a single ADC channel. The multiple inputs can come from different system voltages being montitored, or environemental sensors such as temperature or humidity. Figure 9-1 shows a simplified example of monitoring multiple inputs into a single ADC using a multiplexer. Figure 10-1. Multiplexed Data Aqcuisition Front End 34 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 10.3 Design Requirements Table 10-1. Design Parameters PARAMETER VALUE Positive supply (VDD) +15 V Negative supply (VSS) -15 V Input / output signal range -12 V to 12 V (limit of ADC) Control logic thresholds 1.8 V compatible Temperature range -40°C to +125°C 10.4 Detailed Design Procedure The application shown in Figure 9-1 demonstrates how a multiplexer can be used to simplfy the signal chain and monitor multiple input signals to a single ADC channel. In this example the ADC (ADS8661) has software programmable input ranges up to ±12.288 V. The ADC also has overvotlage protection up to ±20 V which allows for the multiplexer to be powered with wider supply voltages than the input signal range to maximize on-resistance performance of the multiplxer, while still maintaining system level overvotlage protection beyond the usuable signal range. Both the multiplexer and the ADC are capable of operation in extended industrial temperature range of -40°C to +125°C allowing for use in a wider array of industrial systems. Many SAR ADCs have an analog input structure that consists of a sampling switch and a sampling capacitor. Many signal chains will have a driver amplifier to help charge the input of the ADC to meet a fast system aquisition time. However a driver amplifier is not always needed to drive SAR ADCs. Figure 9-2 shows a typical diagram of a sensor driving the SAR ADC input directly after being passed through the multiplxer. A filter capacitor (CFLT) is connected to the input of the ADC to reduce the sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold capacitor of the ADC. The sensor block simplifies the device into a Thevenin equivalant voltage source (VTH) and resistance (RTH) which can be extracted from the device datasheets. Similarly the multixplexer can be thought of as a series resistance (RON(MUX)) and capacitance (CON(MUX)). To ensure maximum precison of the signal chain the system should be able to settle within 1/2 of an LSB within the acquisition time of the ADC. Figure 9-2 shows the time constant can be calculated. This equation highlights the importance of selecting a multiplexer with low on-resistance to further reduce the system time constant. Additionaly low charge injection performance of the multiplexer is helpful to reduce conversion errors and improve accuracy of the measurements. Figure 10-2. Driving SAR ADC Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 35 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 10.5 Application Curve The low on and off leakage currents of TMUX620x and ultra-low charge injection performance make this device ideal for implementing high precision industrial systems. Figure 10-3 shows the plot for the charge injection versus source voltage for the TMUX6208. 50 VDD = 15 V, V SS = –15 V VDD = 5 V, V SS = –5 V 40 Charge Injection (pC) 30 20 10 0 -10 -20 -30 -40 -50 -20 -15 -10 -5 0 5 Drain Voltage (V) 10 15 20 TA = 25°C Figure 10-3. Charge Injection vs Drain Voltage 11 Power Supply Recommendations The TMUX6208 and TMUX6209 operate across a wide supply range of of ±4.5 V to ±18 V (4.5 V to 36 V in single-supply mode). The device also perform well with asymmetrical supplies such as VDD = 12 V and VSS = –5 V. Power-supply bypassing improves noise margin and prevents switching noise propagation from the supply rails to other components. Good power-supply decoupling is important to achieve optimum performance. For improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF at both the VDD and VSS pins to ground. Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall inductance and is beneficial for connections to ground and power planes. Always ensure the ground (GND) connection is established before supplies are ramped. 36 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 12 Layout 12.1 Layout Guidelines When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must turn corners. Figure 12-1 shows progressively better techniques of rounding corners. Only the last example (BEST) maintains constant trace width and minimizes reflections. BETTER BEST 2W WORST 1W min. W Figure 12-1. Trace Example Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference from the other layers of the board. Be careful when designing test points, through-hole pins are not recommended at high frequencies. Figure 12-2 and Figure 12-3 illustrate an example of a PCB layout with the TMUX6208. Some key considerations are: • • • • • For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD/VSS and GND. We recommend a 0.1 µF and 1 µF capacitor, placing the lowest value capacitor as close to the pin as possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage. Keep the input lines as short as possible. Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup. Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when necessary. Using multiple vias in parallel will lower the overall inductance and is beneficial for connection to ground planes. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 37 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 GND A0 A1 Wide (low inductance) trace for power VDD VSS S3B S4A S4B S3A DA S1B S2B DB S1A S2A Wide (low inductance) trace for power C C C C EN 12.2 Layout Example Via to ground plane Figure 12-2. TMUX6208 Layout Example Via to ground plane A0 A1 EN GND VSS VDD S1A S4A S4B DA DB Wide (low inductance) trace for power S2 S5 S3 S6 S7 VDD C GND S1 C VSS S4 C Wide (low inductance) trace for power A2 A1 S3B EN S2B S3A C C Wide (low inductance) trace for power C S1B TMUX6209 S2A S8 C A0 C D Wide (low inductance) trace for power Via to ground plane Via to ground plane Figure 12-3. TMUX6209 Layout Example 38 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 TMUX6208, TMUX6209 www.ti.com SCDS419C – NOVEMBER 2020 – REVISED AUGUST 2021 13 Device and Documentation Support 13.1 Documentation Support 13.1.1 Related Documentation • • • • • • • • • Texas Instruments, Improve Stability Issues with Low CON Multiplexers application brief. Texas Instruments, Improving Signal Measurement Accuracy in Automated Test Equipment application brief Texas Instruments, Sample & Hold Glitch Reduction for Precision Outputs Reference Design reference guide. Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches application brief. Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers application reports. Texas Instruments, True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC Circuit application reports. Texas Instruments, QFN/SON PCB Attachment application reports. Texas Instruments, Quad Flatpack No-Lead Logic Packages application reports. Texas Instruments, Using Latch Up Immune Multiplexers to Help Improve System Reliability application reports. 13.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 13.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 13.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 13.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 13.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMUX6208 TMUX6209 39 PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) TMUX6208PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 X208 TMUX6208RUMR ACTIVE WQFN RUM 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TMUX X208 TMUX6209PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 X209 TMUX6209RUMR ACTIVE WQFN RUM 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TMUX X209 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of