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TMUX6136
SCDS397 – NOVEMBER 2018
TMUX6136 ±16.5-V, Low Capacitance, Low-Leakage-Current, Precision, Dual SPDT Switch
1 Features
3 Description
•
The TMUX6136 is a complementary metal-oxide
semiconductor (CMOS) analog switch containing two
independently selectable SPDT switches.The devices
work well with dual supplies (±5 V to ±16.5 V), a
single supply (10 V to 16.5 V), or asymmetric
supplies. The digital select pin (SELx) has transistortransistor logic (TTL) compatible thresholds, ensuring
TTL/ CMOS logic compatibility.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Wide Supply Range: ±5 V to ±16.5 V (dual) or
10 V to 16.5 V (single)
Latch-Up Performance Meets 100 mA per
JESD78 Class II Level A on all Pins
Low On-Capacitance: 5.5 pF
Low Input Leakage: 0.5 pA
Low Charge Injection: –0.4 pC
Rail-to-Rail Operation
Low On-Resistance: 120 Ω
Fast Transition Time: 66 ns
Break-Before-Make Switching Action
SELx Pin Connectable to VDD With Integrated
Pull-down
Logic Levels: 2 V to VDD
Low Supply Current: 17 µA
Human Body Model (HBM) ESD Protection: ± 2kV
on All Pins
Industry-Standard TSSOP Package
2 Applications
•
•
•
•
•
•
Factory Automation and Industrial Process
Controls
Programmable Logic Controllers (PLC)
Analog Input Modules
ATE Test Equipment
Digital Multimeters
Battery Monitoring Systems
The TMUX6136 switches one of two inputs (Sx) to a
common output (D), depending on the status of the
SELx pins. Each switch conducts equally well in both
directions in the ON position and supports input
signal range up to the supplies. In the OFF condition,
signal levels up to the supplies are blocked. All
switches exhibit break-before-make (BBM) switching
action.
The TMUX6136 is part of Texas Instruments
Precision Switches and Multiplexers family. The
device has very low leakage current and charge
injection, allowing them to be used in high-precision
measurement applications. The devic also provides
excellent isolation by blocking signal levels up to the
supplies when the switches are in the OFF position.
Low supply current of 17 μA enables usage in
portable applications.
Device Information(1)
PART NUMBER
TMUX6136
PACKAGE
TSSOP (16)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
SPACER
Simplified Schematic
VDD
VSS
S1A
D1
S1B
SEL1
S2A
D2
S2B
SEL2
TMUX6136
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUX6136
SCDS397 – NOVEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
4
4
4
4
5
6
7
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Thermal Information ..................................................
Recommended Operating Conditions.......................
Electrical Characteristics (Dual Supplies: ±15 V) .....
Switching Characteristics (Dual Supplies: ±15 V).....
Electrical Characteristics (Single Supply: 12 V)........
Switching Characteristics (Single Supply: 12 V).......
Typical Characteristics ..............................................
7.3 Feature Description................................................. 18
7.4 Device Functional Modes........................................ 19
8
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application ................................................. 20
9 Power Supply Recommendations...................... 22
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 23
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description ............................................ 12
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
24
24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
November 2018
*
Initial release.
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5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
SEL1
1
I
S1A
2
I/O
Source pin 1A. Can be an input or output.
D1
3
I/O
Drain pin D1. Can be an input or output.
S1B
4
I/O
Source pin 1B. Can be an input or output.
VSS
5
P
GND
6
N.C.
7, 8, 14, 15,
16
Select line 0
Negative power supply. This pin is the most negative power-supply potential. In singlesupply applications, this pin can be connected to ground. For reliable operation, connect a
decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
Ground (0 V) reference
No Connect
No internal connection
SEL2
9
I
S2A
10
I/O
Select line 1
Source pin 2A. Can be an input or output.
D2
11
I/O
Drain pin D2. Can be an input or output.
S2B
12
I/O
Source pin 2B. Can be an input or output.
VDD
13
P
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and
GND.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VDD to VSS
VDD to GND
Supply voltage
VSS to GND
UNIT
36
V
–0.3
18
V
–18
0.3
V
GND –0.3
VDD+0.3
V
VDIG
Digital input pin (SEL1, SEL2) voltage
IDIG
Digital input pin (SEL1, SEL2) current
–30
30
VANA_IN
Analog input pin (Sx) voltage
VSS–0.3
VDD+0.3
IANA_IN
Analog input pin (Sx) current
–30
30
VANA_OUT
Analog output pin (D) voltage
VSS–0.3
VDD+0.3
IANA_OUT
Analog output pin (D) current
–30
30
mA
TA
Ambient temperature
–55
140
°C
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
(1)
–65
mA
V
mA
V
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Thermal Information
TMUX6136
THERMAL METRIC (1)
PW (TSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
111.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
41.7
°C/W
RθJB
Junction-to-board thermal resistance
57.2
°C/W
ΨJT
Junction-to-top characterization parameter
4.1
°C/W
ΨJB
Junction-to-board characterization parameter
56.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD to VSS
(1)
Power supply voltage differential
10
33
V
VDD to
GND
Positive power supply voltage (singlle supply, VSS = 0 V)
10
16.5
V
(1)
4
VDD and VSS can be any value as long as 10 V ≤ (VDD – VSS) ≤ 33 V.
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
VDD to
GND
Positive power supply voltage (dual supply)
VSS to
GND
Negative power supply voltage (dual supply)
VS
(1)
NOM
MAX
UNIT
5
16.5
V
–16.5
–5
V
Source pins voltage
VSS
VDD
V
VD
Drain pin voltage
VSS
VDD
V
VDIG
Digital input pin (SEL1, SEL2) voltage
0
VDD
V
ICH
Channel current (TA = 25°C )
–25
25
mA
TA
Ambient temperature
–40
125
°C
6.5 Electrical Characteristics (Dual Supplies: ±15 V)
at TA = 25°C, VDD = 15 V, and VSS = -15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG SWITCH
VA
Analog signal range
TA = –40°C to +125°C
VSS
VS = 0 V, IS = 1 mA
RON
On-resistance
VS = ±10 V, IS = 1 mA
VDD
V
120
135
Ω
140
160
Ω
TA = –40°C to +85°C
210
Ω
TA = –40°C to +125°C
245
Ω
2.5
ΔRON
On-resistance mismatch
between channels
VS = ±10 V, IS = 1 mA
6
Ω
TA = –40°C to +85°C
9
Ω
TA = –40°C to +125°C
11
Ω
33
Ω
35
Ω
23
RON_FLAT
RON_DRIFT
On-resistance flatness
On-resistance drift
VS = –10 V, 0 V, +10 V, IS
TA = –40°C to +85°C
= 1 mA
TA = –40°C to +125°C
VS = 0 V
0.42
Switch state is off, VS =
+10 V/ –10 V, VD = –10
V/ + 10 V
IS(OFF)
ID(ON)
Source off leakage current (1)
Drain on leakage current
37
–0.05
0.005
Ω
%/°C
0.05
nA
-0.17
0.1
nA
–1
0.25
nA
Switch state is off, VS =
+10 V/ –10 V, VD = –10
V/ + 10 V
TA = –40°C to +85°C
Switch state is off, VS =
+10 V/ –10 V, VD = –10
V/ + 10 V
TA = –40°C to +125°C
Switch state is on, VS =
+10 V/ –10 V, VD = –10
V/ +10 V
0.06
nA
TA = –40°C to +85°C
–0.25
0.15
nA
TA = –40°C to +125°C
–1.6
0.4
nA
–0.06
0.008
DIGITAL INPUT (EN, Ax pins)
VIH
Logic voltage high
VIL
Logic voltage low
RPD(EN)
Pull-down resistance on EN pin
2
V
0.8
6
V
MΩ
POWER SUPPLY
17
IDD
(1)
VDD supply current
VA = 0 V or 3.3 V, VS = 0
V
21
µA
TA = –40°C to +85°C
22
µA
TA = –40°C to +125°C
23
µA
When VS is positive, VD is negative, and vice versa.
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Electrical Characteristics (Dual Supplies: ±15 V) (continued)
at TA = 25°C, VDD = 15 V, and VSS = -15 V (unless otherwise noted)
ISS
PARAMETER
TEST CONDITIONS
VSS supply current
VA = 0 V or 3.3 V, VS = 0
V
TEST CONDITIONS
MIN
TYP
MAX
8
UNIT
10
µA
TA = –40°C to +85°C
11
µA
TA = –40°C to +125°C
12
µA
6.6 Switching Characteristics (Dual Supplies: ±15 V)
at TA = 25°C, VDD = 15 V, and VSS = -15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
66
78
ns
VS = 10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+85°C
107
ns
VS = 10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
117
ns
VS = 10 V, RL = 300 Ω , CL = 35 pF
tTRAN
Transition time
tBBM
Break-before-make time delay
VS = 10 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
QJ
Charge injection
OISO
Off-isolation
XTALK
Channel-to-channel crosstalk
IL
Insertion loss
ACPSRR
AC Power Supply Rejection
Ratio
40
ns
VS = 0 V, RS = 0 Ω , CL = 1 nF
–0.4
pC
RL = 50 Ω , CL = 5 pF, f = 1 MHz
–85
dB
RL = 50 Ω , CL = 5 pF, f = 1 MHz (Inter-channel: S1x
& S2x)
–105
dB
RL = 50 Ω , CL = 5 pF, f = 1 MHz (Intra-channel: SxA
& SxB)
–92
dB
RL = 50 Ω , CL = 5 pF, f = 1 MHz
20
UNIT
–7
dB
RL = 10 kΩ , CL = 5 pF, VPP= 0.62 V on VDD, f= 1
MHz
–59
dB
RL = 10 kΩ , CL = 5 pF, VPP= 0.62 V on VSS, f= 1
MHz
–59
dB
BW
-3dB Bandwidth
RL = 50 Ω , CL = 5 pF
670
MHz
THD
Total harmonic distortion +
noise
RL = 10k Ω , CL = 5 pF, f= 20Hz to 20kHz
0.08
%
CIN
Digital input capacitance
VIN = 0 V or VDD
1.5
CS(OFF)
Source off-capacitance
VS = 0 V, f = 1 MHz
2.4
3.3
pF
CS(ON),
CD(ON)
Source and drain oncapacitance
VS = 0 V, f = 1 MHz
5.5
7.5
pF
6
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6.7 Electrical Characteristics (Single Supply: 12 V)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG SWITCH
VA
Analog signal range
VSS
235
RON
On-resistance
VS = 10 V, IS = 1 mA
TA = –40°C to +85°C
TA = –40°C to +125°C
4
ΔRON
On-resistance mismatch
between channels
VS = 10 V, IS = 1 mA
RON_DRIFT
On-resistance drift
VS = 0 V
TA = –40°C to +85°C
TA = –40°C to +125°C
IS(OFF)
Source off leakage current
Drain on leakage current
Ω
400
Ω
440
Ω
12
Ω
19
Ω
23
Switch state is off, VS =
T = –40°C to +85°C
10 V/ 1 V, VD = 1 V/ 10 V A
TA = –40°C to +125°C
Switch state is on, VS =
floating, VD = 1 V/ 10 V
0.005
Ω
%/°C
0.03
nA
–0.1
0.07
nA
–0.8
0.2
nA
0.04
nA
–0.04
ID(ON)
V
345
0.47
–0.03
(1)
VDD
0.01
TA = –40°C to +85°C
–0.16
0.09
nA
TA = –40°C to +125°C
–1.2
0.3
nA
DIGITAL INPUT (EN, Ax pins)
VIH
Logic voltage high
VIL
Logic voltage low
RPD(EN)
Pull-down resistance on EN pin
2
V
0.8
6
V
MΩ
POWER SUPPLY
13
IDD
(1)
VDD supply current
VA = 0 V or 3.3 V, VS = 0
V
16
µA
TA = –40°C to +85°C
17
µA
TA = –40°C to +125°C
18
µA
When VS is positive, VD is negative, and vice versa.
6.8 Switching Characteristics (Single Supply: 12 V)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
72
84
ns
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+85°C
117
ns
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
128
ns
VS = 8 V, RL = 300 Ω , CL = 35 pF
tTRAN
Transition time
tBBM
Break-before-make time delay
VS = 8 V, RL = 300 Ω , CL = 35 pF, TA = –40°C to
+125°C
QJ
Charge injection
VS = 6 V, RS = 0 Ω , CL = 1 nF
OISO
Off-isolation
RL = 50 Ω , CL = 5 pF, f = 1 MHz
XTALK
Channel-to-channel crosstalk
20
UNIT
40
ns
–0.7
pC
-85
dB
RL = 50 Ω , CL = 5 pF, f = 1 MHz (Inter-channel: S1x
& S2x)
–110
dB
RL = 50 Ω , CL = 5 pF, f = 1 MHz (Inra-channel: SxA
& SxB)
–95
dB
IL
Insertion loss
RL = 50 Ω , CL = 5 pF, f = 1 MHz
–13
dB
ACPSRR
AC Power Supply Rejection
Ratio
RL= 10 kΩ , CL = 5 pF, VPP= 0.62 V, f= 1 MHz
–58
dB
BW
-3dB Bandwidth
RL = 50 Ω , CL = 5 pF
650
MHz
CIN
Digital input capacitance
VIN = 0 V or VDD
1.7
CS(OFF)
Source off-capacitance
VS = 6 V, f = 1 MHz
2.6
pF
3.7
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Switching Characteristics (Single Supply: 12 V) (continued)
at TA = 25°C, VDD = 12 V, and VSS = 0 V (unless otherwise noted)
PARAMETER
CS(ON),
CD(ON)
8
Source and drain oncapacitance
TEST CONDITIONS
VS = 6 V, f = 1 MHz
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MIN
TYP
MAX
6.3
8.5
UNIT
pF
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6.9 Typical Characteristics
at TA = 25°C, VDD = 15 V, and VSS = –15 V (unless otherwise noted)
650
250
600
VDD= 13.5V
VSS = -13.5V
VDD= 12V
VSS = -12V
550
On Resistance (:)
On Resistance (:)
200
150
100
0
-20
VDD= 16.5V
VSS = -16.5V
VDD= 15V
VSS = -15V
50
500
450
VDD= 12V
VSS = 0V
VDD= 10V
VSS = 0V
400
350
300
250
VDD= 14V
VSS = 0V
200
150
100
-15
-10
-5
0
5
10
Source or Drain Voltage (V)
15
0
20
2
4
6
8
10
Source or Drain Voltage (V)
D001
Dual Supply Operation (TA = 25°C)
12
14
D002
Single Supply Operation (TA = 25°C)
Figure 1. On-Resistance vs Source or Drain Voltage
Figure 2. On-Resistance vs Source or Drain Voltage
250
700
TA = 125qC
TA = 85qC
TA = 125qC
600
On Resistance (:)
On Resistance (:)
200
150
100
50
TA = 25qC
TA = -40qC
0
-15
TA = 85qC
500
400
300
200
100
TA = 25qC
-10
-5
0
5
Source or Drain Voltage (V)
10
15
0
2
D003
VDD = 15 V, VSS = –15 V
Figure 3. On-Resistance vs Source or Drain Voltage
10
12
D004
Figure 4. On-Resistance vs Source or Drain Voltage
400
ID(ON)+
0
-200
-400
IS(OFF)-600
-25
0
25
50
75
100
Ambient Temperature (qC)
ID(ON)_10V
0
-200
-400
IS(OFF)_1V
-600
ID(ON)_1V
ID(ON)-
-800
IS(OFF)_10V
200
Leakage Current (pA)
IS(OFF)+
200
Leakage Current (pA)
4
6
8
Source or Drain Voltage (V)
VDD = 12 V, VSS = 0 V
400
-1000
-50
TA = -40qC
0
-800
125
150
-1000
-50
-25
D005
VDD = 15 V, VSS = –15 V
0
25
50
75
100
Ambient Temperature (qC)
125
150
D006
VDD = 12 V, VSS = 0 V
Figure 5. Leakage Current vs Temperature
Figure 6. Leakage Current vs Temperature
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Typical Characteristics (continued)
120
2
1
Turn On/Off Time (ns)
Charge Injection (pC)
tON(VDD= 12V, VSS= 0V)
VDD= 15V
VSS = -15V
VDD= 12V
VSS = 0V
0
-1
90
60
-10
-5
tOFF(VDD= 15V, VSS= -15V)
30
VDD= 10V
VSS = -10V
-2
-15
tON(VDD= 15V, VSS= -15V)
tOFF(VDD= 12V, VSS= 0V)
0
5
Drain Voltage (V)
10
0
-50
15
-25
D007
0
25
50
75
100
Ambient Temperature (qC)
125
150
D008
TA = 25°C
Figure 7. Charge Injection vs Source Voltage
Figure 8. Transition Times vs Temperature
0
0
VDD = 12V
VSS= 0V
-20
Intra-Channel (SxA to SxB)
-40
-40
Crosstalk (dB)
Off Isolation (dB)
-20
-60
-80
VDD = 15V
VSS= -15V
-100
-80
-100
-120
-140
1E+5
-60
-120
1E+6
1E+7
Frequency (Hz)
1E+8
-140
1E+5
5E+8
Figure 9. Off Isolation vs Frequency
5E+8
D001
Figure 10. Crosstalk vs Frequency
Intra-Channel (SxA to SxB)
THD + N (%)
Crosstalk (dB)
1E+8
100
50
-20
-60
-80
Inter-Channel (S1x to S2x)
-120
1E+6
1E+7
Frequency (Hz)
1E+8
20
10
5
VDD= 5V
VSS= -5V
VDD= 15V
VSS= -15V
2
1
0.5
0.2
0.1
0.05
-100
5E+8
0.02
0.01
1E+1
D001
VDD = 12 V, VSS = 0 V, TA = 25°C
1E+2
1E+3
Frequency (Hz)
1E+4
1E+5
D001
TA = 25°C
Figure 11. Crosstalk vs Frequency
10
1E+7
Frequency (Hz)
VDD = 15 V, VSS = –15 V, TA = 25°C
0
-140
1E+5
1E+6
D009
TA = 25°C
-40
Inter-Channel (S1x to S2x)
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Figure 12. THD+N vs Frequency
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Typical Characteristics (continued)
10
-5
CS(ON), CD(ON)
Capactiance (pF)
Insertion Loss (dB)
8
-10
-15
6
CS(OFF)
4
2
-20
1E+5
1E+6
1E+7
Frequency(Hz)
1E+8
0
-15
1E+9
-12
D001
VDD = 15 V, VSS = –15 V, TA = 25°C
-9
-6
-3
0
3
6
Source Voltage (V)
9
12
15
D001
VDD = 15 V, VSS = –15 V, TA = 25°C
Figure 13. On Response vs Frequency
Figure 14. Capacitance vs Source Voltage
10
0
CS(ON), CD(ON)
-20
ACPSRR (dB)
Capactiance (pF)
8
6
CS(OFF)
4
VSS
-40
-60
VDD
2
-80
0
0
2
4
6
8
Source Voltage (V)
10
12
-100
1E+5
D001
VDD = 12 V, VSS = 0 V, TA = 25°C
2E+53E+5 5E+5
1E+6
2E+63E+6 5E+6
Frequency (Hz)
1E+7
D001
VDD = 15 V, VSS = –15 V, TA = 25°C
Figure 15. Capacitance vs Source Voltage
Figure 16. ACPSRR vs Frequency
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7 Detailed Description
7.1 Overview
7.1.1 On-Resistance
The on-resistance of the TMUX6136 is the ohmic resistance across the source (Sx) and drain (D) pins of the
device. The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote onresistance. The measurement setup used to measure RON is shown in Figure 17. Voltage (V) and current (ICH)
are measured using this setup, and RON is computed as shown in Equation 1:
V
D
S
ICH
VS
Figure 17. On-Resistance Measurement Setup
RON = V / ICH
(1)
7.1.2 Off-Leakage Current
Source off-leakage current is defined as the leakage current that flows into or out of the source pin when the
switch is in the off state. This current is denoted by the symbol IS(OFF). Drain off-leakage measurement is not
characterization since the drain pin is always connected to one of the two source pins.
The setup used to measure both off-leakage currents is shown in Figure 18
ID (OFF)
Is (OFF)
A
S
D
VS
A
VD
Figure 18. Off-Leakage Measurement Setup
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Overview (continued)
7.1.3 On-Leakage Current
On-leakage current is defined as the leakage current that flows into or out of the drain pin when the switch is in
the on state. The source pin is left floating during the measurement. Figure 19 shows the circuit used for
measuring the on-leakage current, denoted by ID(ON).
ID (ON)
D
S
A
NC
NC = No Connection
VD
Figure 19. On-Leakage Measurement Setup
7.1.4 Transition Time
Transition time is defined as the time taken by the output of the TMUX6136 to rise or fall to 90% of the transition
after the digital address signal has fallen or risen to 50% of the transition. Figure 20 shows the setup used to
measure transition time, denoted by the symbol tTRAN.
3V
VS
tr < 20 ns
VSEL
50%
50%
VDD
VSS
VDD
VSS
SB
Output
D
tf < 20 ns
SA
0V
SEL
VS
Output
300 Ÿ
35 pF
0.9 VS
tTRAN 2
tTRAN 1
0.1 VS
VSEL
GND
tTRAN = max ( tTRAN 1, tTRAN 2)
Figure 20. Transition-Time Measurement Setup
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Overview (continued)
7.1.5 Break-Before-Make Delay
Break-before-make delay is a safety feature that prevents two inputs from connecting when the TMUX6136 is
switching. The TMUX6136 output first breaks from the on-state switch before making the connection with the
next on-state switch. The time delay between the break and the make is known as break-before-make delay.
Figure 21 shows the setup used to measure break-before-make delay, denoted by the symbol tBBM.
3V
VS
tr < 20 ns
VSEL
VDD
VSS
VDD
VSS
SB
Output
D
tf < 20 ns
SA
0V
SELx
300 Ÿ
35 pF
VS
Output
0.8 VS
VSEL
GND
tBBM 2
tBBM 1
0V
tBBM = min ( tBBM 1, tBBM 2)
Figure 21. Break-Before-Make Delay Measurement Setup
7.1.6 Charge Injection
The TMUX6136 have a simple transmission-gate topology. Any mismatch in capacitance between the NMOS
and PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the
gate signal. The amount of charge injected into the source of the device is known as charge injection, and is
denoted by the symbol QINJ. Figure 22 shows the setup used to measure charge injection from drain (D) to
source (Sx).
3V
Output
VDD
VSS
VDD
VSS
SB
D
VSEL
NC
0V
SA
RS
VS
1 nF
SEL
Output
VS
QINJ = CL ×
VOUT
VOUT
VSEL
GND
Figure 22. Charge-Injection Measurement Setup
7.1.7 Off Isolation
Off isolation is defined as the voltage at the drain pin (D) of the TMUX6136 when a 1-VRMS signal is applied to
the source pin (Sx) of an off-channel. Figure 23 shows the setup used to measure off isolation. Use Equation 2
to compute off isolation.
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Overview (continued)
Network Analyzer
VDD
VSS
VDD
VSS
SA
50 Ÿ
NC SB
50 Ÿ
VOUT
D
VS
50 Ÿ
SEL
GND
VSEL
Figure 23. Off Isolation Measurement Setup
Off Isolation
§V
·
20 ˜ Log ¨ OUT ¸
V
© S ¹
(2)
7.1.8 Channel-to-Channel Crosstalk
There are two types of crosstalk that can be defined for the TMUX6136:
1. Intra-channel crosstalk: the voltage at the source pin (Sx) of an off-switch input, when a 1-VRMS signal is
applied at the source pin of an on-switch input in the same channel, as shown in Figure 24
2. Inter-channel crosstalk: the voltage at the source pin (Sx) of an on-switch input, when a 1-VRMS signal is
applied at the source pin of an on-switch input in a different channel, as shown in Figure 25
Network Analyzer
VDD
VSS
VDD
VSS
SxA
Dx
VOUT
SxB
50 Ÿ
50 Ÿ
SEL
VS
50 Ÿ
VSEL
GND
Figure 24. Intra-channel Crosstalk Measurement Setup
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Overview (continued)
Network Analyzer
VDD
VSS
VDD
VSS
S1A
D1
50 Ÿ
VS
S1B
N.C.
50 Ÿ
VOUT
S2A
D2
S2B
N.C.
50 Ÿ
50 Ÿ
SEL
GND
VSEL
Figure 25. Inter-channel Crosstalk Measurement Setup
Channel-to-Channel Crosstalk
§V
·
20 ˜ Log ¨ OUT ¸
V
© S ¹
(3)
7.1.9 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by < 3 dB when the input is applied to the
source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the TMUX6136. Figure 26
shows the setup used to measure bandwidth of the mux. Use Equation 4 to compute the attenuation.
Network Analyzer
VDD
VSS
VDD
VSS
SA
NC SB
50 Ÿ
VOUT
D
VS
50 Ÿ
SEL
GND
VSEL
Figure 26. Bandwidth Measurement Setup
Attenuation
§V ·
20 ˜ Log ¨ 2 ¸
© V1 ¹
(4)
7.1.10 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as the
ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the mux
output. The on-resistance of the TMUX6136 varies with the amplitude of the input signal and results in distortion
when the drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as
THD+N.
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Overview (continued)
Audio Precision
VDD
VSS
VDD
VSS
SA
NC SB
RS
VOUT
D
VS
10N Ÿ
SEL
GND
VSEL
Figure 27. THD+N Measurement Setup
7.1.11 AC Power Supply Rejection Ratio (AC PSRR)
AC PSRR measures the ability of a device to prevent noise and spurious signals that appear on the supply
voltage pin from coupling to the output of the switch. The DC voltage on the device supply is modulated by a sine
wave of 620 mVPP. The ratio of the amplitude of signal on the output to the amplitude of the modulated signal is
the AC PSRR.
VDD
Network Analyzer
DC Bias
Injector
VSS
VSS
VDD
620 mVPP
VBIAS
VIN
S1
S2
SW
SW
NC
VOUT
50 Ÿ
D
10N Ÿ
5 pF
VSEL
SEL
GND
VBIAS = 0 V
PSRR= 20 × Log (VOUT/ VIN)
Figure 28. AC PSRR Measurement Setup
The Functional Block Diagram section provides a top-level block diagram of the TMUX6136. The TMUX6136 is a
4-channel, single-ended, analog multiplexer. Each channel is turned on or turned off based on the state of the
address lines and enable pin.
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7.2 Functional Block Diagram
VDD
VSS
S1A
D1
S1B
SEL1
S2A
D2
S2B
SEL2
TMUX6136
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7.3 Feature Description
7.3.1 Ultralow Leakage Current
The TMUX6136 provide extremely low on- and off-leakage currents. The TMUX6136 is capable of switching
signals from high source-impedance inputs into a high input-impedance op amp with minimal offset error
because of the ultralow leakage currents. Figure 29 shows typical leakage currents of the TMUX6136 versus
temperature.
400
IS(OFF)+
Leakage Current (pA)
200
ID(ON)+
0
-200
-400
IS(OFF)-600
ID(ON)-
-800
-1000
-50
-25
0
25
50
75
100
Ambient Temperature (qC)
125
150
D005
Figure 29. Leakage Current vs Temperature
7.3.2 Ultralow Charge Injection
The TMUX6136 is implemented with simple transmission gate topology, as shown in Figure 30. Any mismatch in
the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch
is opened or closed.
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Feature Description (continued)
OFF ON
CGSN
CGDN
S
D
CGSP
CGDP
OFF ON
Figure 30. Transmission Gate Topology
The TMUX6136 utilizes special charge-injection cancellation circuitry that reduces the drain (D)-to-source (Sx)
charge injection to as low as –0.4 pC at VS = 0 V, as shown in Figure 31.
Charge Injection (pC)
2
1
VDD= 15V
VSS = -15V
VDD= 12V
VSS = 0V
0
-1
VDD= 10V
VSS = -10V
-2
-15
-10
-5
0
5
Drain Voltage (V)
10
15
D007
Figure 31. Charge Injection vs Drain Voltage
7.3.3 Bidirectional and Rail-to-Rail Operation
The TMUX6136 conducts equally well from source (Sx) to drain (D) or from drain (D) to source (Sx). Each
TMUX6136 channel has very similar characteristics in both directions. The valid analog signal for TMUX6136
ranges from VSS to VDD. The input signal to the TMUX6136 swings from VSS to VDD without any significant
degradation in performance.
7.4 Device Functional Modes
7.4.1 Truth Table
Table 1. TMUX6136 Truth Table
SELx
Switch A
Switch B
(S1A to D1 or S2A to D2)
(S1B to D1 or S2B to D2)
0
OFF
ON
1
ON
OFF
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TMUX6136 offers outstanding input/output leakage currents and ultralow charge injection. The device
operate up to 33 V (VDD to VSS dual supply) or 16.5 V (VDD single supply), and offer true rail-to-rail input and
output. The on-capacitance of the TMUX6136 is low. These features makes the TMUX6136 a precision, robust,
high-performance analog multiplexer for high-voltage, industrial applications.
8.2 Typical Application
One example to take advantage of TMUX6136’s precision performance is the implementation of parametric
measurement unit (PMU) in the semiconductor automatic test equipment (ATE) application. The PMU is
frequently used to characterize and measure the digital pin’s DC characteristics of a device under test (DUT).
Among all the PMU’s capabilities, force voltage, measure current (FVMC), and force current, measure voltage
(FCMV) are the two most typical configurations in DC characterizations.
Force
Amplifier
RSENSE
VIN
Force
±
Force
Amplifier
RSENSE
Force
±
Av
±
DUT
+
Current
Sense
Amplifier
Voltage
Sense
Amplifier
+
Sense
DUT
Av
+
+
±
Current
Sense
Amplifier
±
+
+
VIN
VOUT
±
VOUT
Figure 32. FVMC Measurement in PMU
Sense
Voltage
Sense
Amplifier
Figure 33. FCMV Measurement in PMU
Figure 32 shows a simplified diagram of the PMU in FVMC configuration. The control loop consists of the force
amplifier with the voltage sense amplifier (unity gain in this example) making up the feedback path. Current
flowing through the DUT is measured by sensing the current flowing through a sense resistor (RSENSE) in series
with the DUT. The current sense amplifier with a gain of Av generates a voltage (VOUT) at its output and the
voltage can then be measured by an ADC. The voltage produced at the DUT pin stays at the input voltage level
(IN) as long as the force amplifier doesn’t rail out (ie. IDUT × RSENSE x Av stays within the input voltage range of
the force amplifier). Depending on level of the DUT current to be measured, different gain settings need to be
configured for the current sense amplifier.
Figure 33 shows a simplified diagram of the PMU in FCMV mode. The voltage VIN is now converted to a current
through the following relationship:
Force Current = VIN / (RSENSE x Av)
(5)
The control loop consists of the force amplifier with the current sense amplifier making up the feedback path. The
voltage at the DUT is sensed across the voltage sense amplifier (unity gain in this example) and presented at the
output for sample.
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Typical Application (continued)
8.2.1 Design Requirements
The goal of this design example is to simplify the FVMC and FCMV functions of a PMU design using a SPDT
switch. The FVMC configuration is useful to test a device being used as a power supply, or in continuity or
leakage testing. In this configuration, the input voltage is directly applied to the DUT pin, and the current into/ out
of the DUT pin is converted to a voltage by a sense resistor and measured by an analog to digital converter
(ADC). In the FCMV mode, an input current is forced to the DUT and the produced voltage on the DUT pin is
directly measured. In this example, the PMU design is required to meet the following specifications:
• Force voltage range: –15 volts to +15 volts
• Force current range: ±5 µA to ±50 mA
• Measure voltage range: –15 volts to +15 volts
• Measure current range: ±5 µA to ±50 mA
In additional to the voltage and current requirements, fast throughput is also a key requirements in ATE because
it relates directly to the cost of manufacturing the DUT.
8.2.2 Detailed Design Procedure
DAC
+
Force
Amplifier
DAC
RSENSE
+
Force
Amplifier
RSENSE
DUT
±
A
Current
Sense
Amplifier
DUT
±
+
Av
±
A
B
A
ADC
+
+
B
TMUX6136
+
Av
±
B
A
ADC
Current
Sense
Amplifier
B
±
Voltage
Sense
Amplifier
TMUX6136
Figure 34. FVMC Implementation in PMU Using the
TMUX6136
±
Voltage
Sense
Amplifier
Figure 35. FCMV Implementation in PMU Using the
TMUX6136
The FVMC and FCMV modes implementations can be combined with the use of a dual SPDT switch such as the
TMUX6136. Figure 34 and Figure 35 shows simplified diagrams of such implementations. In the FVMC mode,
the switch is toggled to position A and this allows the voltage sense amplifier to become part of the feedback
loop and the voltage output of the current sense amplifier to be sampled by the ADC. In the FCMV mode, the
switch is toggled to position B, and this allows the current sense amplifier to become part of the feedback loop
and the voltage output of the voltage sense amplifier to be sampled by the ADC.
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Typical Application (continued)
8.2.3 Application Curve
The fast transition time of the TMUX6136 and low input/ output parasitic capacitance help minimize the settling
time, making the TMUX6136 an excellent candidate to implement the FVMC and FCMV functions of the PMU.
Figure 36 shows the plot for the transition time vs. temperature for the TMUX6136.
120
Turn On/Off Time (ns)
tON(VDD= 12V, VSS= 0V)
90
tON(VDD= 15V, VSS= -15V)
60
tOFF(VDD= 15V, VSS= -15V)
30
tOFF(VDD= 12V, VSS= 0V)
0
-50
-25
0
25
50
75
100
Ambient Temperature (qC)
125
150
D008
Figure 36. Transition Time VS Temperature for TMUX6136
9 Power Supply Recommendations
The TMUX6136 operates across a wide supply range of ±5 V to ±16.5 V (10 V to 16.5 V in single-supply mode).
The device also perform well with unsymmetric supplies such as VDD = 12 V and VSS= –5 V. For reliable
operation, use a supply decoupling capacitor ranging between 0.1 µF to 10 µF at both the VDD and VSS pins to
ground.
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10 Layout
10.1 Layout Guidelines
Figure 37 illustrates an example of a PCB layout with the TMUX6136.
Some key considerations are:
1. Decouple the VDD and VSS pins with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure
that the capacitor voltage rating is sufficient for the VDD and VSS supplies.
2. Keep the input lines as short as possible.
3. Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
4. Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
10.2 Layout Example
Via to
ground plane
SEL1
NC
S1A
NC
D1
NC
S1B
VSS
C
TMUX6136
C
VDD
S2B
GND
D2
NC
S2A
NC
SEL2
Via to
ground plane
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Figure 37. TMUX6136 Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
• ADS8664 12-Bit, 500-kSPS, 4- and 8-Channel, Single-Supply, SAR ADCs with Bipolar Input Ranges
(SBAS492)
• OPA192 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage, Low Input Bias Current Op Amp with
e-Trim™ (SBOS620)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMUX6136PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
MUX6136
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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