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TMUX1109
SCDS406 – DECEMBER 2018
TMUX1109 5 V, ±2.5 V, Low-Leakage-Current, 4:1, 2-Channel Precision Multiplexer
1 Features
3 Description
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The TMUX1109 is a precision complementary metaloxide semiconductor (CMOS) multiplexer (MUX). The
TMUX1109 offers differential 4:1 or dual 4:1 singleended channels. Wide operating supply of 1.08 V to
5.5 V allows for use in a broad array of applications
from medical equipment to industrial systems. The
device supports bidirectional analog and digital
signals on the source (Sx) and drain (D) pins ranging
from GND to VDD. All logic inputs have 1.8 V logic
compatible thresholds, ensuring both TTL and CMOS
logic compatibility when operating in the valid supply
voltage range. Fail-Safe Logic circuitry allows
voltages on the control pins to be applied before the
supply pin, protecting the device from potential
damage.
1
Single Supply Range: 1.08 V to 5.5 V
Dual Supply Range: ±2.75 V
Low Leakage Current: 3 pA
Low Charge Injection: 1 pC
Low On-Resistance: 1.8 Ω
-40°C to +125°C Operating Temperature
1.8 V Logic Compatible
Fail-Safe Logic
Rail to Rail Operation
Bidirectional Signal Path
Break-Before-Make Switching
ESD Protection HBM: 2000 V
The TMUX1109 is part of the precision switches and
multiplexers family of devices. These devices have
very low on and off leakage currents and low charge
injection, allowing them to be used in high precision
measurement applications. A low supply current of
8nA and small package options enable use in
portable applications.
2 Applications
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Ultrasound Scanners
Patient Monitoring & Diagnostics
Optical Networking
Optical Test Equipment
Remote Radio Unit
Wired Networking
ATE Test Equipment
Factory Automation and Industrial Controls
Programmable Logic Controllers (PLC)
Analog Input Modules
SONAR Receivers
Motor Drive
Servo Drive Position Feedback
Device Information(1)
PART NUMBER
TMUX1109
PACKAGE
BODY SIZE (NOM)
TSSOP (16)
5.00 mm × 4.40 mm
QFN (16)
2.60 mm x 1.80 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Application Example
Block Diagram
REFby2
4 Channels per ADC
INN_x
Cf1 3pF
Rg1 1kŸ
REFby2
2.048V
Vocm
+5V
Riso1
10Ÿ
+
-
+
100nF
SxA
Rg2 1kŸ
15pF
Cfil
150pF
Riso2
10Ÿ
Rf2 1kŸ
INP_x
Rfil1 30.1Ÿ
Rf1 1kŸ
-
Cf2 3pF
15pF
DA
4:1
Differential
MUX DB
Cf1 3pF
Rg1 1kŸ
+5V
Vocm
+
100nF
Riso1
10Ÿ
+
-
Dual,
SimultaneousSampling
Low-Latency
SAR ADC
Rfil1 30.1Ÿ
INP_x
Rg2 1kŸ
Cf2 3pF
S1A
S2A
S3A
S4A
DA
S1B
S2B
S3B
S4B
DB
AINM_A
ADS9224R
THS4551 (4x)
SxA
15pF
Cfil
150pF
Riso2
10Ÿ
Rf2 1kŸ
ADC_A
SxB
Rf1 1kŸ
REFby2
2.048V
AINP_A
Rfil2 30.1Ÿ
TMUX1109
INN_x
TMUX1109
1µF
REFby2
(2.048V output)
15pF
DA
4:1
Differential
MUX DB
AINP_B
1-OF-4
DECODER
ADC_B
AINM_B
Rfil2 30.1Ÿ
SxB
A0
THS4551 (4x)
4 Channels per ADC
A1
EN
TMUX1109
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMUX1109
SCDS406 – DECEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.4 Device Functional Modes........................................ 25
1
1
1
2
3
4
8
8.1
8.2
8.3
8.4
8.5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics (VDD = 5 V ±10 %) ............ 5
Electrical Characteristics (VDD = 3.3 V ±10 %) ......... 7
Electrical Characteristics (VDD = 2.5 V ±10 %), (VSS =
–2.5 V ±10 %) ............................................................ 9
6.8 Electrical Characteristics (VDD = 1.8 V ±10 %) ....... 11
6.9 Electrical Characteristics (VDD = 1.2 V ±10 %) ....... 13
6.10 Typical Characteristics .......................................... 15
7
Application and Implementation ........................ 26
Application Information............................................
Typical Application .................................................
Design Requirements..............................................
Detailed Design Procedure .....................................
Application Curve ....................................................
26
26
27
27
28
9 Power Supply Recommendations...................... 28
10 Layout................................................................... 29
10.1 Layout Guidelines ................................................. 29
10.2 Layout Example .................................................... 29
11 Device and Documentation Support ................. 30
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Detailed Description ............................................ 18
7.1 Overview ................................................................. 18
7.2 Functional Block Diagram ....................................... 23
7.3 Feature Description................................................. 23
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
30
30
12 Mechanical, Packaging, and Orderable
Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
December 2018
*
Initial release.
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SCDS406 – DECEMBER 2018
5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View
2
15
GND
VSS
3
14
VDD
S1A
4
13
S1B
S2A
5
12
S2B
S1A
S3A
6
11
S3B
S4A
7
10
S4B
DA
8
9
DB
GND
2
11
S1B
S2A
3
10
S2B
S3A
4
9
S3B
8
VDD
7
12
6
1
5
VSS
13
EN
A1
A1
14
16
A0
1
16
A0
15
EN
RSV Package
16-Pin QFN
Top View
S4B
DB
DA
S4A
Not to scale
Not to scale
Pin Functions
PIN
NAME
TYPE (1)
DESCRIPTION
TSSOP
UQFN
A0
1
15
I
Address line 0. Controls the switch configuration as shown in Table 1.
EN
2
16
I
Active high logic input. When this pin is low, all switches are turned off. When this pin is high,
the A[1:0] address inputs determine which switch is turned on.
VSS
3
1
P
Negative power supply. This pin is the most negative power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
VSS can be connected to ground for single supply applications.
S1A
4
2
I/O
Source pin 1A. Can be an input or output.
S2A
5
3
I/O
Source pin 2A. Can be an input or output.
S3A
6
4
I/O
Source pin 3A. Can be an input or output.
S4A
7
5
I/O
Source pin 4A. Can be an input or output.
DA
8
6
I/O
Drain pin A. Can be an input or output.
DB
9
7
I/O
Drain pin B. Can be an input or output.
S4B
10
8
I/O
Source pin 4B. Can be an input or output.
S3B
11
9
I/O
Source pin 3B. Can be an input or output.
S2B
12
10
I/O
Source pin 2B. Can be an input or output.
S1B
13
11
I/O
Source pin 1B. Can be an input or output.
VDD
14
12
P
Positive power supply. This pin is the most positive power-supply potential. For reliable
operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
GND
15
13
P
Ground (0 V) reference
A1
16
14
I
Address line 1. Controls the switch configuration as shown in Table 1.
(1)
I = input, O = output, I/O = input and output, P = power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
(2) (3)
VDD–VSS
VDD
Supply voltage
VSS
MIN
MAX
–0.5
6
UNIT
V
–0.5
6
V
V
–3.0
0.3
VSEL or VEN
Logic control input pin voltage (EN, A0, A1)
–0.5
6
V
ISEL or IEN
Logic control input pin current (EN, A0, A1)
–30
30
mA
VS or VD
Source or drain voltage (Sx, Dx)
–0.5
VDD+0.5
IS or ID (CONT)
Source or drain continuous current (Sx, Dx)
–30
30
mA
Tstg
Storage temperature
–65
150
°C
TJ
Junction temperature
150
°C
(1)
(2)
(3)
V
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
All voltages are with respect to ground, unless otherwise specified.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD
Positive power supply voltage (single)
1.08
5.5
V
VSS
Negative power supply voltage (dual)
-2.75
0
V
VDD - VSS
Supply rail voltage difference
1.08
5.5
V
VS or VD
Signal path input/output voltage (source or drain pin) (Sx, Dx)
VSS
VDD
V
VSEL or
VEN
Logic control input pin voltage
0
5.5
V
TA
Ambient temperature
–40
125
°C
6.4 Thermal Information
TMUX1109
THERMAL METRIC (1)
PW (TSSOP)
RSV (QFN)
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
118.9
134.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
49.3
74.3
°C/W
RθJB
Junction-to-board thermal resistance
65.2
62.8
°C/W
ΨJT
Junction-to-top characterization parameter
7.6
4.3
°C/W
ΨJB
Junction-to-board characterization parameter
64.6
61.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SCDS406 – DECEMBER 2018
6.5 Electrical Characteristics (VDD = 5 V ±10 %)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
RON
On-resistance
ΔRON
RON
On-resistance matching between
channels
On-resistance flatness
FLAT
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
ID(ON)
IS(ON)
Source off leakage current (1)
Drain off leakage current (1)
Channel on leakage current
Channel on leakage current
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
4
Ω
–40°C to +85°C
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VDD = 5 V
Switch Off
VD = 4.5 V / 1.5 V
VS = 1.5 V / 4.5 V
Refer to Off-Leakage Current
25°C
VDD = 5 V
Switch Off
VD = 4.5 V / 1.5 V
VS = 1.5 V / 4.5 V
Refer to Off-Leakage Current
25°C
VDD = 5 V
Switch On
VD = VS = 2.5 V
Refer to On-Leakage Current
25°C
VDD = 5 V
Switch On
VD = VS = 4.5 V / 1.5 V
Refer to On-Leakage Current
25°C
1.8
4.5
Ω
–40°C to +125°C
4.9
Ω
0.18
Ω
–40°C to +85°C
0.4
Ω
–40°C to +125°C
0.5
Ω
0.85
Ω
–40°C to +85°C
1.6
Ω
–40°C to +125°C
1.6
Ω
0.08
nA
–40°C to +85°C
–0.08
–0.3
0.3
nA
–40°C to +125°C
–0.9
0.9
nA
–0.1
±0.005
0.1
nA
–40°C to +85°C
–0.75
0.75
nA
–40°C to +125°C
–3.5
3.5
nA
0.025
nA
–0.025
±0.01
±0.003
–40°C to +85°C
–0.3
0.3
nA
–40°C to +125°C
–0.75
0.75
nA
–40°C to +85°C
–40°C to +125°C
0.1
nA
–0.75
–0.1
±0.01
0.75
nA
–3
3
nA
1.49
5.5
V
0
0.87
V
LOGIC INPUTS (EN, A0, A1)
VIH
Input logic high
VIL
Input logic low
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
–40°C to +125°C
25°C
±0.005
µA
±0.05
1
–40°C to +125°C
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
–40°C to +125°C
0.008
µA
1
µA
When VS is 4.5 V, VD is 1.5 V, and vice versa.
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Electrical Characteristics (VDD = 5 V ±10 %) (continued)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
tTRAN
tOPEN
Transition time between channels
Break before make time
(BBM)
tON(EN)
Enable turn-on time
tOFF(EN) Enable turn-off time
QC
OISO
XTALK
Charge Injection
Off Isolation
Crosstalk
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to Transition Time
25°C
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to Break-Before-Make
25°C
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
14
–40°C to +85°C
–40°C to +125°C
ns
18
ns
19
ns
8
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
12
ns
–40°C to +85°C
19
ns
–40°C to +125°C
20
ns
6
ns
–40°C to +85°C
8
ns
–40°C to +125°C
9
ns
VS = 1 V
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
–1
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
25°C
–45
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
25°C
–90
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Crosstalk
25°C
–80
dB
BW
Bandwidth
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
135
MHz
CSOFF
Source off capacitance
f = 1 MHz
25°C
7.5
pF
CDOFF
Drain off capacitance
f = 1 MHz
25°C
32
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
38
pF
6
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6.6 Electrical Characteristics (VDD = 3.3 V ±10 %)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
4
ANALOG SWITCH
RON
On-resistance
ΔRON
RON
On-resistance matching between
channels
On-resistance flatness
FLAT
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
Source off leakage current (1)
Drain off leakage current (1)
Channel on leakage current
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
8.75
Ω
–40°C to +85°C
9.5
Ω
–40°C to +125°C
9.75
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
VS = 1 V / 3 V
Refer to Off-Leakage Current
25°C
0.13
Ω
–40°C to +85°C
0.4
Ω
–40°C to +125°C
0.5
Ω
–40°C to +85°C
–40°C to +125°C
Ω
2
Ω
2.2
Ω
0.05
nA
–40°C to +85°C
–0.1
0.1
nA
–40°C to +125°C
–0.5
0.5
nA
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
VS = 1 V / 3 V
Refer to Off-Leakage Current
25°C
–0.1
0.1
nA
–40°C to +85°C
–0.5
0.5
nA
–2
2
nA
VDD = 3.3 V
Switch On
VD = VS = 3 V / 1 V
Refer to On-Leakage Current
25°C
–0.1
0.1
nA
–40°C to +85°C
–0.5
0.5
nA
–2
2
nA
1.35
5.5
V
0
0.8
V
–40°C to +125°C
–40°C to +125°C
–0.05
1.9
±0.001
±0.005
±0.005
LOGIC INPUTS (EN, A0, A1)
VIH
Input logic high
VIL
Input logic low
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
–40°C to +125°C
25°C
±0.005
µA
±0.05
1
–40°C to +125°C
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
–40°C to +125°C
0.006
µA
1
µA
When VS is 3 V, VD is 1 V, and vice versa.
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Electrical Characteristics (VDD = 3.3 V ±10 %) (continued)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
tTRAN
tOPEN
Transition time between channels
Break before make time
(BBM)
tON(EN)
Enable turn-on time
tOFF(EN) Enable turn-off time
QC
OISO
XTALK
Charge Injection
Off Isolation
Crosstalk
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to Transition Time
25°C
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to Break-Before-Make
25°C
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
15
–40°C to +85°C
–40°C to +125°C
ns
23
ns
23
ns
9
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
14
ns
–40°C to +85°C
25
ns
–40°C to +125°C
25
ns
7
ns
–40°C to +85°C
12
ns
–40°C to +125°C
12
ns
VS = 1 V
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
–1
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
25°C
–45
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
25°C
–90
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Crosstalk
25°C
–80
dB
135
MHz
BW
Bandwidth
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
CSOFF
Source off capacitance
f = 1 MHz
25°C
7
pF
CDOFF
Drain off capacitance
f = 1 MHz
25°C
32
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
38
pF
8
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SCDS406 – DECEMBER 2018
6.7 Electrical Characteristics (VDD = 2.5 V ±10 %), (VSS = –2.5 V ±10 %)
at TA = 25°C, VDD = +2.5 V, VSS = –2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
RON
On-resistance
ΔRON
RON
On-resistance matching between
channels
On-resistance flatness
FLAT
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
Source off leakage current (1)
Drain off leakage current (1)
Channel on leakage current
VS = VSS to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
4
Ω
–40°C to +85°C
VS = VSS to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VS = VSS to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VDD = +2.5 V, VSS = –2.5 V
Switch Off
VD = +2 V / –1 V
VS = –1 V / +2 V
Refer to Off-Leakage Current
25°C
VDD = +2.5 V, VSS = –2.5 V
Switch Off
VD = +2 V / –1 V
VS = –1 V / +2 V
Refer to Off-Leakage Current
25°C
VDD = +2.5 V, VSS = –2.5 V
Switch On
VD = VS = +2 V / –1 V
Refer to On-Leakage Current
1.8
4.5
Ω
–40°C to +125°C
4.9
Ω
0.18
Ω
–40°C to +85°C
0.4
Ω
–40°C to +125°C
0.5
Ω
0.85
Ω
–40°C to +85°C
1.6
Ω
–40°C to +125°C
1.6
Ω
0.08
nA
–40°C to +85°C
–0.08
–0.3
0.3
nA
–40°C to +125°C
–0.9
0.9
nA
0.1
nA
–40°C to +85°C
–0.75
0.75
nA
–40°C to +125°C
–3.5
3.5
nA
25°C
–0.1
0.1
nA
–0.75
0.75
nA
–3
3
nA
1.2
2.75
V
0
0.73
V
–40°C to +85°C
–40°C to +125°C
–0.1
±0.005
±0.01
±0.01
LOGIC INPUTS (EN, A0, A1)
VIH
Input logic high
VIL
Input logic low
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
–40°C to +125°C
25°C
±0.005
µA
±0.05
1
–40°C to +125°C
µA
pF
2
pF
POWER SUPPLY
IDD
ISS
(1)
VDD supply current
VSS supply current
Logic inputs = 0 V or 2.75 V
Logic inputs = 0 V or 2.75 V
25°C
0.008
–40°C to +125°C
25°C
–40°C to +125°C
µA
1
0.008
µA
µA
1
µA
When VS is positive, VD is negative, and vice versa.
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Electrical Characteristics (VDD = 2.5 V ±10 %), (VSS = –2.5 V ±10 %) (continued)
at TA = 25°C, VDD = +2.5 V, VSS = –2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
tTRAN
tOPEN
Transition time between channels
Break before make time
(BBM)
tON(EN)
Enable turn-on time
tOFF(EN) Enable turn-off time
QC
OISO
XTALK
Charge Injection
Off Isolation
Crosstalk
VS = 1.5 V
RL = 200 Ω, CL = 15 pF
Refer to Transition Time
25°C
VS = 1.5 V
RL = 200 Ω, CL = 15 pF
Refer to Break-Before-Make
25°C
VS = 1.5 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
VS = 1.5 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
14
–40°C to +85°C
–40°C to +125°C
ns
21
ns
21
ns
8
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
14
ns
–40°C to +85°C
21
ns
–40°C to +125°C
22
ns
8
ns
–40°C to +85°C
11
ns
–40°C to +125°C
12
ns
VS = –1 V
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
–1
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
25°C
–45
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
25°C
–90
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Crosstalk
25°C
–80
dB
135
MHz
BW
Bandwidth
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
CSOFF
Source off capacitance
f = 1 MHz
25°C
7
pF
CDOFF
Drain off capacitance
f = 1 MHz
25°C
32
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
38
pF
10
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SCDS406 – DECEMBER 2018
6.8 Electrical Characteristics (VDD = 1.8 V ±10 %)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
RON
On-resistance
ΔRON
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
On-resistance matching between
channels
Source off leakage current (1)
Drain off leakage current (1)
Channel on leakage current
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
VDD = 1.98 V
Switch Off
VD = 1.62 V / 1 V
VS = 1 V / 1.62 V
Refer to Off-Leakage Current
25°C
40
Ω
–40°C to +85°C
80
Ω
–40°C to +125°C
80
Ω
0.4
Ω
–40°C to +85°C
1.5
Ω
–40°C to +125°C
1.5
Ω
0.05
nA
–40°C to +85°C
–0.1
0.1
nA
–40°C to +125°C
–0.5
0.5
nA
VDD = 1.98 V
Switch Off
VD = 1.62 V / 1 V
VS = 1 V / 1.62 V
Refer to Off-Leakage Current
25°C
–0.1
0.1
nA
–40°C to +85°C
–0.5
0.5
nA
–2
2
nA
VDD = 1.98 V
Switch On
VD = VS = 1.62 V / 1 V
Refer to On-Leakage Current
25°C
–0.1
0.1
nA
–40°C to +85°C
–0.5
0.5
nA
–2
2
nA
1.07
5.5
V
0
0.68
V
–40°C to +125°C
–40°C to +125°C
–0.05
±0.003
±0.005
±0.005
LOGIC INPUTS (EN, A0, A1)
VIH
Input logic high
VIL
Input logic low
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
–40°C to +125°C
25°C
±0.005
µA
±0.05
1
–40°C to +125°C
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
–40°C to +125°C
0.001
µA
0.85
µA
When VS is 1.62 V, VD is 1 V, and vice versa.
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Electrical Characteristics (VDD = 1.8 V ±10 %) (continued)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
tTRAN
tOPEN
Transition time between channels
Break before make time
(BBM)
tON(EN)
Enable turn-on time
tOFF(EN) Enable turn-off time
QC
OISO
XTALK
Charge Injection
Off Isolation
Crosstalk
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Transition Time
25°C
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Break-Before-Make
25°C
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
28
–40°C to +85°C
–40°C to +125°C
ns
48
ns
48
ns
16
ns
–40°C to +85°C
1
ns
–40°C to +125°C
1
ns
28
ns
–40°C to +85°C
48
ns
–40°C to +125°C
48
ns
16
ns
–40°C to +85°C
27
ns
–40°C to +125°C
27
ns
VS = 1 V
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
–0.5
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
25°C
–45
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
25°C
–90
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Crosstalk
25°C
–80
dB
135
MHz
BW
Bandwidth
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
CSOFF
Source off capacitance
f = 1 MHz
25°C
7
pF
CDOFF
Drain off capacitance
f = 1 MHz
25°C
32
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
38
pF
12
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SCDS406 – DECEMBER 2018
6.9 Electrical Characteristics (VDD = 1.2 V ±10 %)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
RON
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
On-resistance matching between
channels
VS = 0 V to VDD
ISD = 10 mA
Refer to On-Resistance
25°C
25°C
Source off leakage current (1)
VDD = 1.32 V
Switch Off
VD = 1 V / 0.8 V
VS = 0.8 V / 1 V
Refer to Off-Leakage Current
On-resistance
ΔRON
IS(OFF)
ID(OFF)
ID(ON)
IS(ON)
Drain off leakage current (1)
Channel on leakage current
70
–40°C to +85°C
–40°C to +125°C
Ω
105
Ω
105
Ω
0.4
–40°C to +85°C
Ω
1.5
–40°C to +125°C
–0.05
±0.003
Ω
1.5
Ω
0.05
nA
–40°C to +85°C
–0.1
0.1
nA
–40°C to +125°C
–0.5
0.5
nA
VDD = 1.32 V
Switch Off
VD = 1 V / 0.8 V
VS = 0.8 V / 1 V
Refer to Off-Leakage Current
25°C
–0.1
0.1
nA
–40°C to +85°C
–0.5
0.5
nA
–2
2
nA
VDD = 1.32 V
Switch On
VD = VS = 1 V / 0.8 V
Refer to On-Leakage Current
25°C
–0.1
0.1
nA
–40°C to +85°C
–0.5
0.5
nA
–2
2
nA
0.96
5.5
V
0
0.36
V
–40°C to +125°C
–40°C to +125°C
±0.005
±0.005
LOGIC INPUTS (EN, A0, A1)
VIH
Input logic high
VIL
Input logic low
IIH
IIL
Input leakage current
25°C
IIH
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
–40°C to +125°C
25°C
±0.005
µA
±0.05
1
–40°C to +125°C
µA
pF
2
pF
POWER SUPPLY
IDD
(1)
VDD supply current
Logic inputs = 0 V or 5.5 V
25°C
–40°C to +125°C
0.001
µA
0.7
µA
When VS is 1 V, VD is 0.8 V, and vice versa.
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Electrical Characteristics (VDD = 1.2 V ±10 %) (continued)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Transition Time
25°C
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to Break-Before-Make
25°C
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
tOFF(EN) Enable turn-off time
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to tON(EN) and tOFF(EN)
25°C
QC
VS = 1 V
RS = 0 Ω, CL = 1 nF
Refer to Charge Injection
25°C
–0.5
pC
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Off Isolation
25°C
–65
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Off Isolation
25°C
–45
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to Crosstalk
25°C
–90
dB
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to Crosstalk
25°C
–80
dB
MHz
tTRAN
tOPEN
Transition time between channels
Break before make time
(BBM)
tON(EN)
OISO
XTALK
Enable turn-on time
Charge Injection
Off Isolation
Crosstalk
60
ns
–40°C to +85°C
210
ns
–40°C to +125°C
210
ns
28
–40°C to +85°C
1
–40°C to +125°C
1
ns
ns
ns
60
–40°C to +85°C
–40°C to +125°C
ns
190
ns
190
ns
45
ns
–40°C to +85°C
150
ns
–40°C to +125°C
150
ns
BW
Bandwidth
RL = 50 Ω, CL = 5 pF
Refer to Bandwidth
25°C
135
CSOFF
Source off capacitance
f = 1 MHz
25°C
7
pF
CDOFF
Drain off capacitance
f = 1 MHz
25°C
32
pF
CSON
CDON
On capacitance
f = 1 MHz
25°C
38
pF
14
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SCDS406 – DECEMBER 2018
6.10 Typical Characteristics
at TA = 25°C, VDD = 5 V (unless otherwise noted)
6
5
VDD = 3 V
4.5
4
VDD = 3.63 V
4
On Resistance (:)
On Resistance (:)
5
VDD = 4.5 V
3
VDD = 5.5 V
2
3.5
TA = 125qC
TA = -40qC
TA = 25qC
3
2.5
2
1.5
1
1
TA = 85qC
0.5
0
0
0
1
2
3
4
Source or Drain Voltage (V)
5
5.5
0
1
2
3
Source or Drain Voltage (V)
D001
TA = 25°C
5
D002
VDD = 5 V
Figure 1. On-Resistance vs Source or Drain Voltage
Figure 2. On-Resistance vs Temperature
6
8
7
5
4
On Resistance (:)
6
On Resistance (:)
4
VDD = 2.25V
VSS = -2.25V
3
2
TA = 85qC
TA = 125qC
TA = -40qC
TA = 25qC
5
4
3
2
1
VDD = 2.75 V
VSS = -2.75 V
0
-3
1
0
-2
-1
0
1
Source or Drain Voltage (V)
2
3
0
0.5
1
1.5
2
2.5
Source or Drain Voltage (V)
D003
TA = 25°C
3.5
D004
VDD = 3.3 V
Figure 3. On-Resistance vs Source or Drain Voltage
Figure 4. On-Resistance vs Temperature
40
80
VDD = 1.08 V
70
30
20
On-Leakage (pA)
60
On Resistance (:)
3
VDD = 1.32 V
50
40
VDD = 1.62 V
30
VDD = 1.32 V
VDD = 1.98 V
VDD = 3.63 V
10
0
-10
-20
20
VDD = 1.98 V
10
-30
-40
0
0
0.2
0.4
0.6 0.8
1
1.2 1.4
Source or Drain Voltage (V)
1.6
1.8
2
0
0.5
D005
TA = 25°C
1
1.5
2
2.5
3
Source or Drain Voltage (V)
3.5
4
D006
TA = 25°C
Figure 5. On-Resistance vs Source or Drain Voltage
Figure 6. On-Leakage vs Source or Drain Voltage
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Typical Characteristics (continued)
400
1
300
0.75
On-Leakage (pA)
VDD = 5 V
VSS = 0 V
Leakage Current (nA)
VDD = 2.5 V
VSS = -2.5 V
200
100
0
-100
-200
0.5
IS(OFF)
0.25
0
-0.25
ID(OFF)
-0.5
I(ON)
-300
-0.75
-400
-3
-2
-1
0
1
2
3
Source or Drain Voltage (V)
4
-1
-40
5
-20
0
20
40
60
Temperature (qC)
D007
TA = 25°C
80
100
120
D008
VDD = 3.3 V
Figure 7. On-Leakage vs Source or Drain Voltage
Figure 8. Leakage Current vs Temperature
.
3.5
0.4
2.5
Supply Current (PA)
Leakage Current (nA)
VDD = 5.5 V
0.3
1.5
IS(OFF)
0.5
-0.5
ID(OFF)
-1.5
ID(ON)
VDD = 3.63 V
0.2
VDD = 1.8 V
0.1
0
-2.5
VDD = 1.2 V
-3.5
-40
-20
0
20
40
60
Temperature (qC)
80
100
-0.1
-40
120
-20
0
20
D009
VDD = 5 V
20
1200
15
Charge Injection (pC)
Supply Current (PA)
120
140
D010
Figure 10. Supply Current vs Temperature
1400
1000
800
600
VDD = 5 V
400
200
VDD = 3.3 V
VSS = 0 V
10
5
VDD = 5 V
VSS = 0 V
0
-5
-10
VDD = 2.5 V
VSS = -2.5 V
-15
0
0
0.5
1
1.5
2
2.5
3
3.5
Logic Voltage (V)
4
4.5
5
-20
-3
D011
TA = 25°C
-2
-1
0
1
2
Source Voltage (V)
3
4
5
D012
TA = -40°C to 125°C
Figure 11. Supply Current vs Logic Voltage
16
100
VSEL = 5.5 V
Figure 9. Leakage Current vs Temperature
VDD = 3.3 V
40
60
80
Temperature (qC)
Figure 12. Charge Injection vs Source or Drain Voltage
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Typical Characteristics (continued)
5
30
27
24
VDD = 1.2 V
21
1
Time (ns)
Charge Injection (pC)
3
-1
18
TON
15
12
VDD = 1.8 V
9
-3
TOFF
6
-5
0
0.5
1
Source Voltage (V)
1.5
3
1.5
2
2
2.5
D013
TA = 25°C
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
D014
TA = 25°C
Figure 13. Charge Injection vs Source or Drain Voltage
Figure 14. TON (EN) and TOFF (EN) vs Supply Voltage
20
30
25
16
TON
Time (ns)
Time (ns)
20
12
TOFF
8
TTRANSITION_FALLING
15
10
4
0
-60
5
-30
0
30
60
Temperature (qC)
90
120
TTRANSITION_RISING
0
0.5
150
1.5
D015
VDD = 5 V
2.5
3.5
Supply Voltage (V)
4.5
5.5
D016
TA = 25°C
Figure 15. TON (EN) and TOFF (EN) vs Temperature
Figure 16. TTRANSITION vs Supply Voltage
0
Attenuation (dB)
-1
-2
-3
-4
-5
-6
1M
10M
Frequency (Hz)
100M
D018
TA = 25°C
Figure 17. Frequency Response
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7 Detailed Description
7.1 Overview
7.1.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-resistance.
The measurement setup used to measure RON is shown in Figure 18. Voltage (V) and current (ISD) are measured
using this setup, and RON is computed with RON = V / ISD:
V
ISD
Sx
D
VS
Figure 18. On-Resistance Measurement Setup
7.1.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF).
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF).
The setup used to measure both off-leakage currents is shown in Figure 19.
VDD
VSS
VDD
S1A
S1A
S2A
S3A
S4A
DA
A
VS
S4A
VD
Is (OFF)
VSS
ID (OFF)
DA
A
VD
VS
Is (OFF)
S1B
S2B
S3B
S4B
S1B
A
DB
VS
S4B
ID (OFF)
DB
VD
VD
GND
A
GND
VS
Figure 19. Off-Leakage Measurement Setup
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Overview (continued)
7.1.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON).
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON).
Either the source pin or drain pin is left floating during the measurement. Figure 20 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON).
VDD
VSS
VDD
VSS
IS (ON)
ID (ON)
S1A
S2A
S3A
S4A
N.C.
A
DA
A
VD
VS
VS
S1A
S2A
S3A
S4A
DA
S1B
S2B
S3B
S4B
DB
N.C.
VS
IS (ON)
ID (ON)
S1B
S2B
S3B
S4B
N.C.
A
DB
A
VD
VS
N.C.
GND
GND
VS
VS
Figure 20. On-Leakage Measurement Setup
7.1.4 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 10% after the address signal
has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the timing of
the device, system level timing can then account for the time constant added from the load resistance and load
capacitance. Figure 21 shows the setup used to measure transition time, denoted by the symbol tTRANSITION.
VSS
VDD
0.1…F
0.1…F
VDD
VSS
VDD
ADDRESS
DRIVE
(VSEL)
tf < 5ns
tr < 5ns
VIH
VS
VIL
0V
VS
tTRANSITION
tTRANSITION
S1A
S2A
S3A
S4A
DA
S1B
S2B
S3B
S4B
DB
OUTPUT
RL
CL
OUTPUT
RL
CL
90%
OUTPUT
A0
10%
VSEL
A1
GND
0V
Figure 21. Transition-Time Measurement Setup
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Overview (continued)
7.1.5 Break-Before-Make
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. Figure 22 shows
the setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM).
VSS
VDD
0.1…F
0.1…F
VSS
VDD
VDD
VS
ADDRESS
DRIVE
(VSEL)
tr < 5ns
tf < 5ns
S1A
S2A
S3A
S4A
DA
S1B
S2B
S3B
S4B
DB
OUTPUT
VS
90%
Output
tBBM 1
CL
RL
0V
OUTPUT
CL
RL
tBBM 2
0V
tOPEN (BBM) = min ( tBBM 1, tBBM 2)
A0
VSEL
A1
GND
Figure 22. Break-Before-Make Delay Measurement Setup
7.1.6 tON(EN) and tOFF(EN)
Turn-on time is defined as the time taken by the output of the device to rise to 10% after the enable has risen
past the logic threshold. The 10% measurement is utilized to provide the timing of the device, system level timing
can then account for the time constant added from the load resistance and load capacitance. Figure 23 shows
the setup used to measure turn-on time, denoted by the symbol tON(EN).
Turn-off time is defined as the time taken by the output of the device to fall to 90% after the enable has fallen
past the logic threshold. The 90% measurement is utilized to provide the timing of the device, system level timing
can then account for the time constant added from the load resistance and load capacitance. Figure 23 shows
the setup used to measure turn-off time, denoted by the symbol tOFF(EN).
VSS
VDD
0.1…F
VDD
ENABLE
DRIVE
(VEN)
0.1…F
tf < 5ns
tr < 5ns
VSS
VDD
VIH
VS
VIL
S1A
S2A
S3A
S4A
DA
S1B
S2B
S3B
S4B
DB
RL
0V
VS
tOFF (EN)
tON (EN)
OUTPUT
CL
OUTPUT
RL
CL
90%
EN
OUTPUT
10%
VEN
GND
0V
Figure 23. Turn-On and Turn-Off Time Measurement Setup
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Overview (continued)
7.1.7 Charge Injection
The TMUX1109 has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS
transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal.
The amount of charge injected into the source or drain of the device is known as charge injection, and is denoted
by the symbol QC. Figure 24 shows the setup used to measure charge injection from source (Sx) to drain (D).
VDD
VSS
0.1…F
0.1…F
VSS
VDD
VS
VDD
VEN
S1A
S2A
S3A
S4A
DA
S1B
S2B
S3B
S4B
DB
OUTPUT
VOUT
CL
0V
VS
Output
VOUT
VS
QC = CL ×
OUTPUT
VOUT
CL
VOUT
EN
VEN
GND
Figure 24. Charge-Injection Measurement Setup
7.1.8 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the
source pin (Sx) of an off-channel. Figure 25 shows the setup used to measure and the equation used to compute
off isolation.
VSS
VDD
0.1µF
0.1µF
NETWORK
VSS
VDD
ANALYZER
VS
50Q
S
VSIG
D
VOUT
RL
50Q
SX/DX
GND
RL
50Q
Figure 25. Off Isolation Measurement Setup
Off Isolation
§V
·
20 ˜ Log ¨ OUT ¸
V
© S ¹
(1)
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Overview (continued)
7.1.9 Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. Figure 26 shows the setup used to measure, and the equation used to
compute crosstalk.
VDD
VSS
0.1µF
0.1µF
NETWORK
VSS
VDD
ANALYZER
VOUT
S1A
DA
S1B
DB
RL
RL
50Q
50Q
VS
RL
50Q
50Q
SXA / SXB
VSIG
RL
GND
50Q
Figure 26. Crosstalk Measurement Setup
Channel-to-Channel Crosstalk
§V
·
20 ˜ Log ¨ OUT ¸
© VS ¹
(2)
7.1.10 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. Figure 27
shows the setup used to measure bandwidth.
VDD
VSS
0.1µF
0.1µF
NETWORK
VSS
VDD
VS
ANALYZER
50Q
S
VSIG
D
VOUT
RL
50Q
GND
Figure 27. Bandwidth Measurement Setup
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7.2 Functional Block Diagram
The TMUX1109 is an 4:1, differential (2-channel), multiplexer. Each switch is turned on or off based on the state
of the address lines and enable pin.
TMUX1109
S1A
S2A
S3A
S4A
DA
S1B
S2B
S3B
S4B
DB
1-OF-4
DECODER
A0
A1
EN
Figure 28. TMUX1109 Functional Block Diagram
7.3 Feature Description
7.3.1 Bidirectional Operation
The TMUX1109 conducts equally well from source (Sx) to drain (Dx) or from drain (Dx) to source (Sx). Each
channel has very similar characteristics in both directions and supports both analog and digital signals.
7.3.2 Rail to Rail Operation
The valid signal path input/output voltage for TMUX1109 ranges from VSS to VDD.
7.3.3 1.8 V Logic Compatible Inputs
The TMUX1109 has 1.8-V logic compatible control for all logic control inputs. The logic input thresholds scale
with supply but still provide 1.8-V logic control when operating at 5.5 V supply voltage. 1.8-V logic level inputs
allows the TMUX1109 to interface with processors that have lower logic I/O rails and eliminates the need for an
external translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations
refer to Simplifying Design with 1.8 V logic Muxes and Switches
7.3.4 Fail-Safe Logic
The TMUX1109 supports Fail-Safe Logic on the control input pins (EN, A0, A1) allowing for operation up to 5.5 V
above VSS, regardless of the state of the supply pin. This feature allows voltages on the control pins to be applied
before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity
by removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic
feature allows the select pins of the TMUX1109 to be ramped to 5.5 V while VDD = 0 V. Additionally, the feature
enables operation of the TMUX1109 with VDD = 1.2 V while allowing the select pins to interface with a logic level
of another device up to 5.5 V.
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Feature Description (continued)
7.3.5 Ultra-low Leakage Current
The TMUX1109 provides extremely low on-leakage and off-leakage currents. The TMUX1109 is capable of
switching signals from high source-impedance inputs into a high input-impedance op amp with minimal offset
error because of the ultralow leakage currents. Figure 29 shows typical leakage currents of the TMUX1109
versus temperature.
3.5
Leakage Current (nA)
2.5
1.5
IS(OFF)
0.5
-0.5
ID(OFF)
-1.5
ID(ON)
-2.5
-3.5
-40
-20
0
20
40
60
Temperature (qC)
80
100
120
D009
Figure 29. Leakage Current vs Temperature
7.3.6 Ultra-low Charge Injection
The TMUX1109 has a transmission gate topology, as shown in Figure 30. Any mismatch in the stray capacitance
associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.
OFF ON
CGSN
CGDN
S
D
CGSP
CGDP
OFF ON
Figure 30. Transmission Gate Topology
The TMUX1109 has special charge-injection cancellation circuitry that reduces the source-to-drain charge
injection to as low as 1 pC at VS = 1 V as shown in Figure 31.
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Feature Description (continued)
20
Charge Injection (pC)
15
VDD = 3.3 V
VSS = 0 V
10
5
VDD = 5 V
VSS = 0 V
0
-5
VDD = 2.5 V
VSS = -2.5 V
-10
-15
-20
-3
-2
-1
0
1
2
Source Voltage (V)
3
4
5
D012
Figure 31. Charge Injection vs Source Voltage
7.4 Device Functional Modes
When the EN pin of the TMUX1109 is pulled high, one of the switches is closed based on the state of the
address lines. When the EN pin is pulled low, all the switches are in an open state regardless of the state of the
address lines.
7.4.1 Truth Tables
Table 1. TMUX1109 Truth Table
EN
0
A1
A0
Selected Input Connected To Drain (DA, DB) Pins
X (1) X (1)
All channels are off
1
0
0
S1A and S1B
1
0
1
S2A and S2B
1
1
0
S3A and S3B
1
1
1
S4A and S4B
(1)
X denotes don't care.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TMUX11xx family offers ulta-low input/output leakage currents and low charge injection. These devices
operate up to 5.5 V, and offer true rail-to-rail input and output. The TMUX1109 has a low on-capacitance which
allows faster settling time when multiplexing inputs in the time domain. These features make the TMUX11xx
devices a family of precision, robust, high-performance analog multiplexer for low-voltage applications.
8.2 Typical Application
Figure 32 shows a 16-bit, simultaneous-sampling data-acquisition system. This example is typical in industrial
applications that require sampling simultaneous signals such as Optical Modules, Analog Input Modules, and
Motor Drive circuits for position feedback. The circuit uses eight Fully Differential Amplifiers (FDAs), a 16-bit, 3MSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along with a two differential
precision multiplexers. Refer to True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC
Circuit for more information.
REFby2
4 Channels per ADC
INN_x
Cf1 3pF
Rg1 1kŸ
REFby2
2.048V
Vocm
+5V
-
Riso1
10Ÿ
+
-
Rfil1 30.1Ÿ
SxA
Rg2 1kŸ
15pF
Cfil
150pF
Riso2
10Ÿ
Rf2 1kŸ
INP_x
REFby2
(2.048V output)
Rf1 1kŸ
+
100nF
1µF
Cf2 3pF
15pF
DA
4:1
Differential
MUX DB
Cf1 3pF
Rg1 1kŸ
+5V
Vocm
+
100nF
Riso1
10Ÿ
+
-
ADS9224R
THS4551 (4x)
Dual,
SimultaneousSampling
Low-Latency
SAR ADC
Rfil1 30.1Ÿ
SxA
INP_x
Rg2 1kŸ
15pF
Cfil
150pF
Riso2
10Ÿ
Rf2 1kŸ
Cf2 3pF
AINM_A
SxB
Rf1 1kŸ
REFby2
2.048V
ADC_A
Rfil2 30.1Ÿ
TMUX1109
INN_x
AINP_A
15pF
DA
4:1
Differential
MUX DB
AINP_B
ADC_B
AINM_B
Rfil2 30.1Ÿ
SxB
THS4551 (4x)
4 Channels per ADC
TMUX1109
Figure 32. Simultaneous-Sampling ADC Circuit
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8.3 Design Requirements
For this design example, use the parameters listed in Table 2.
Table 2. Design Parameters
PARAMETERS
VALUES
Supply (VDD)
5V
Vref
4.096 V
Vocm
2.048 V
Max Differential Voltage
3.636 V
Control logic thresholds
1.8 V compatible
8.4 Detailed Design Procedure
The TMUX1109 can be operated without any external components except for the supply decoupling capacitors. If
the device desired power-up state is disabled, the enable pin should have a weak pull-down resistor and be
controlled by the MCU via GPIO. All inputs being muxed to the ADC must fall within the recommend operating
conditions of the TMUX1109 including signal range and continuous current. System level design and component
selection are made according to True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC
Circuit.
1. The ADS9224R was selected because of the dual simultaneous sampling and high throughput (3-MSPS).
2. The TMUX1109 4:1 (2x) multiplexer was selected to support 4 differential inputs for each ADC.
3. Find ADC full-scale range, resolution and common-mode range specifications.
4. Determine the linear range of the FDA (THS4551) based on common-mode and output swing specification.
5. Select COG capacitors for all filter capacitors at the ADC input to minimize distortion.
6. Select the FDA gain resistors RF1,2 , RG1,2. Use 0.1% 20ppm/°C film resistors or better for good accuracy,
low gain drift and to minimize distortion.
7. Introduction to SAR ADC Front-End Component Selection covers the methods for selecting the charge
bucket circuit Rfil1, Rfil1 and Cfil. These component values are dependent on the amplifier bandwidth, data
converter sampling rare, and data converter design. The values shown here will give good settling and AC
performance for the amplifier and data converter in this example. If the design is modified, a different RC
filter must be selected.
8. The THS4551 is commonly used in high-speed precision fully differential SAR applications as it has sufficient
bandwidth to settle to charge kickback transients from the ADC input sampling, and multiplexer charge
injection and provides the common-mode level shifting to the voltage range of the SAR ADC.
9. The TMUX1109 is used in high-speed precision fully differential SAR applications as it has sufficient
bandwidth, low charge injection, and low on-resistance and capacitance. Low capacitance supports fast
switching between channels and allows the system to settle within required precision in the specified timing.
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8.5 Application Curve
Charge injection impacts system performance and settling characteristics of the charge bucket circuit. A
multiplexer with low charge injection and a flat response across input voltage allows the system to settle to the
required precision during the ADC acquisition period. Figure 33 shows the flat charge injection of the TMUX1109
at multiple supply voltages.
20
Charge Injection (pC)
15
VDD = 3.3 V
VSS = 0 V
10
5
VDD = 5 V
VSS = 0 V
0
-5
-10
VDD = 2.5 V
VSS = -2.5 V
-15
-20
-3
-2
-1
0
1
2
Source Voltage (V)
3
4
5
D012
TA = 25°C
Figure 33. Charge Injection vs Source Voltage
9 Power Supply Recommendations
The TMUX1109 operates across a wide supply range of 1.08 V to 5.5 V, or ±2.5 V. Do not exceed the absolute
maximum ratings because stresses beyond the listed ratings can cause permanent damage to the devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD and SS
supplies to other components. Good power-supply decoupling is important to achieve optimum performance. For
improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD and
VSS to ground. Place the bypass capacitors as close to the power supply pins of the device as possible using
low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low
equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes.
For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting
the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers
the overall inductance and is beneficial for connections to ground planes.
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10 Layout
10.1 Layout Guidelines
10.1.1 Layout Information
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners.Figure 34 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
BETTER
BEST
2W
WORST
1W min.
W
Figure 34. Trace Example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of
picking up interference from the other layers of the board. Be careful when designing test points, throughhole pins are not recommended at high frequencies.
Figure 35 illustrates an example of a PCB layout with the TMUX1109. Some key considerations are:
•
•
•
•
Decouple the VDD pin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
Keep the input lines as short as possible.
Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
10.2 Layout Example
Via to GND plane
Wide (low inductance)
trace for power
C
A0
A1
EN
GND
C
VSS
VDD
S1A
S1B
S2A
TMUX1109
Wide (low inductance)
trace for power
S2B
S3A
S3B
S4A
S4B
DA
DB
Figure 35. TMUX1109 Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
Texas Instruments, True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC Circuit.
Texas Instruments, Improve Stability Issues with Low CON Multiplexers.
Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches.
Texas Instruments, Eliminate Power Sequencing with Powered-off Protection Signal Switches.
Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers.
Texas Instruments, QFN/SON PCB Attachment.
Texas Instruments, Quad Flatpack No-Lead Logic Packages.
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMUX1109PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
TM1109
TMUX1109RSVR
ACTIVE
UQFN
RSV
16
3000
RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
1D1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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