TMUX6219
TMUX6219
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY
2021
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
www.ti.com
TMUX6219 36-V, Low Ron, 2:1 (SPDT) Switch with 1.8-V Logic
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
The TMUX6219 is a complementary metal-oxide
semiconductor (CMOS) switch in a single channel, 2:1
(SPDT) configuration. The device works with single
supply (4.5 V to 36 V), dual supplies (±4.5 V to ±18
V), or asymmetric supplies (such as VDD = 8 V, VSS =
–12 V). The TMUX6219 supports bidirectional analog
and digital signals on the source (Sx) and drain (D)
pins ranging from VSS to VDD.
Dual Supply Range: ±4.5 V to ±18 V
Single Supply Range: 4.5 V to 36 V
Low On-Resistance: 2.1 Ω
Low Charge Injection: -10 pC
High Current Support: 330 mA (Maximum)
–40°C to +125°C Operating Temperature
1.8 V Logic Compatible
Fail-Safe Logic
Rail to Rail Operation
Bidirectional Signal Path
Break-Before-Make Switching
The TMUX6219 can be enabled or disabled by
controlling the EN pin. When disabled, both signal
path switches are off. When enabled, the SEL pin can
be used to turn on signal path 1 (S1 to D) or signal
path 2 (S2 to D). All logic control inputs support logic
levels from 1.8 V to VDD, ensuring both TTL and
CMOS logic compatibility when operating in the valid
supply voltage range. Fail-Safe Logic circuitry allows
voltages on the control pins to be applied before the
supply pin, protecting the device from potential
damage.
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Factory Automation and Industrial Controls
Programmable Logic Controllers (PLC)
Analog Input Modules
Semiconductor Test
AC Charging (Pile) Station
Ultrasound Scanners
Patient Monitoring and Diagnostics
Optical Networking
Optical Test Equipment
Remote Radio Units
Wired Networking
Data Acquisition Systems
Gas Meters
Flow Transmitters
The TMUX6219 is part of the precision switches and
multiplexers family of devices. These devices have
very low on and off leakage currents and low charge
injection, allowing them to be used in high precision
measurement applications.
Device Information (1)
PART NUMBER
TMUX6219
(1)
VDD
PACKAGE
VSSOP (8) (DGK)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
VSS
S1
D
S2
Decoder
EN
SEL
TMUX6219 Block Diagram
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
Copyright
2021 Texas Instruments
Submit
Document
Feedback
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Product Folder Links: TMUX6219
1
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Thermal Information ...................................................4
6.4 Recommended Operating Conditions ........................5
6.5 Source or Drain Continuous Current ..........................5
6.6 ±15 V Dual Supply: Electrical Characteristics ...........6
6.7 ±15 V Dual Supply: Switching Characteristics .......... 7
6.8 36 V Single Supply: Electrical Characteristics .......... 8
6.9 36 V Single Supply: Switching Characteristics ......... 9
6.10 12 V Single Supply: Electrical Characteristics ...... 10
6.11 12 V Single Supply: Switching Characteristics ...... 11
6.12 ±5 V Dual Supply: Electrical Characteristics .........12
6.13 ±5 V Dual Supply: Switching Characteristics ........ 13
6.14 Typical Characteristics............................................ 14
7 Parameter Measurement Information.......................... 19
7.1 On-Resistance.......................................................... 19
7.2 Off-Leakage Current................................................. 19
7.3 On-Leakage Current................................................. 20
7.4 Transition Time......................................................... 20
7.5 tON(EN) and tOFF(EN) .................................................. 21
7.6 Break-Before-Make...................................................21
7.7 tON (VDD) Time............................................................22
7.8 Propagation Delay.................................................... 22
7.9 Charge Injection........................................................23
7.10 Off Isolation.............................................................23
7.11 Crosstalk................................................................. 24
7.12 Bandwidth............................................................... 24
7.13 THD + Noise........................................................... 24
7.14 Power Supply Rejection Ratio (PSRR)................... 25
8 Detailed Description......................................................26
8.1 Overview................................................................... 26
8.2 Functional Block Diagram......................................... 26
8.3 Feature Description...................................................26
8.4 Device Functional Modes..........................................28
8.5 Truth Tables.............................................................. 28
9 Application and Implementation.................................. 29
9.1 Application Information............................................. 29
9.2 Typical Application.................................................... 29
10 Power Supply Recommendations..............................30
11 Layout........................................................................... 31
11.1 Layout Guidelines................................................... 31
11.2 Layout Example...................................................... 31
12 Device and Documentation Support..........................32
12.1 Related Documentation.......................................... 32
12.2 Receiving Notification of Documentation Updates..32
12.3 Support Resources................................................. 32
12.4 Trademarks............................................................. 32
12.5 Electrostatic Discharge Caution..............................32
12.6 Glossary..................................................................32
13 Mechanical, Packaging, and Orderable
Information.................................................................... 32
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2020) to Revision B (January 2021)
Page
• Changed the document status From: Advanced Information To: Production Data ............................................1
2
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
5 Pin Configuration and Functions
D
1
8
S2
S1
2
7
VSS
GND
3
6
SEL
VDD
4
5
EN
Not to scale
Figure 5-1. DGK Package
8-Pin VSSOP
Top View
Pin Functions
NO.
TYPE(1)
D
1
I/O
Drain pin. Can be an input or output.
S1
2
I/O
Source pin 1. Can be an input or output.
GND
3
P
Ground (0 V) reference
VDD
4
P
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
EN
5
I
Active high logic enable, has internal pull-up resistor. When this pin is low, all switches are turned off.
When this pin is high, the SEL logic input determine which switch is turned on.
SEL
6
I
Logic control input, has internal pull-down resistor. Controls the switch connection as shown in Table
8-1.
VSS
7
P
Negative power supply. This pin is the most negative power-supply potential. In single-supply
applications, this pin can be connected to ground. For reliable operation, connect a decoupling
capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
S2
8
I/O
NAME
(1)
(2)
DESCRIPTION(2)
Source pin 2. Can be an input or output.
I = input, O = output, I/O = input and output, P = power.
Refer to Section 8.4 for what to do with unused pins.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
3
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
MAX
VDD – VSS
UNIT
38
V
Supply voltage
–0.5
38
V
–38
0.5
V
VSEL or VEN
Logic control input pin voltage (SEL, EN)(3)
–0.5
38
V
ISEL or IEN
Logic control input pin current (SEL, EN)(3)
–30
30
mA
VS or VD
Source or drain voltage (Sx, D)(3)
VSS–0.5
VDD+0.5
VDD
VSS
current(3)
IIK
Diode clamp
IS or ID (CONT)
Source or drain continuous current (Sx, D)
–30
V
30
mA
IDC + 10 %(4)
mA
TA
Ambient temperature
–55
150
°C
Tstg
Storage temperature
–65
150
°C
TJ
Junction temperature
150
°C
460
mW
Total power dissipation(5)
Ptot
(1)
(2)
(3)
(4)
(5)
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltages are with respect to ground, unless otherwise specified.
Pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings.
Refer to Source or Drain Continuous Current table for IDC specifications.
For DGK package: Ptot derates linearily above TA = 70°C by 6.7mW/°C.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Thermal Information
TMUX6219
THERMAL
METRIC(1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
152.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
48.4
°C/W
RθJB
Junction-to-board thermal resistance
73.2
°C/W
ΨJT
Junction-to-top characterization parameter
4.1
°C/W
ΨJB
Junction-to-board characterization parameter
71.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD – VSS (1)
Power supply voltage differential
NOM
4.5
MAX
UNIT
36
V
VDD
Positive power supply voltage
4.5
36
V
VS or VD
Signal path input/output voltage (source or drain pin) (Sx, D)
VSS
VDD
V
VSEL or VEN
Address or enable pin voltage
IS or ID (CONT)
Source or drain continuous current (Sx, D)
TA
Ambient temperature
(1)
(2)
0
36
–40
V
IDC (2)
mA
125
°C
VDD and VSS can be any value as long as 4.5 V ≤ (VDD – VSS) ≤ 36 V, and the minimum VDD is met.
Refer to Source or Drain Continuous Current table for IDC specifications.
6.5 Source or Drain Continuous Current
at supply voltage of VDD ± 10%, VSS ± 10 % (unless otherwise noted)
CONTINUOUS CURRENT PER CHANNEL (IDC)
PACKAGE
TEST CONDITIONS
±15 V Dual Supply
+36 V Single
DGK (VSSOP)
(1)
Supply(1)
TA = 25°C
TA = 85°C
TA = 125°C
UNIT
330
210
120
mA
300
190
110
mA
+12 V Single Supply
240
160
100
mA
±5 V Dual Supply
240
160
100
mA
+5 V Single Supply
180
120
80
mA
Specified for nominal supply voltage only.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
5
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
6.6 ±15 V Dual Supply: Electrical Characteristics
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
2.1
2.9
Ω
3.8
Ω
ANALOG SWITCH
RON
VS = –10 V to +10 V
ID = –10 mA
Refer to On-Resistance
On-resistance
V = –10 V to +10 V
On-resistance mismatch between S
ID = –10 mA
channels
Refer to On-Resistance
ΔRON
RON FLAT
On-resistance flatness
VS = 0 V, IS = –10 mA
Refer to On-Resistance
RON DRIFT On-resistance drift
IS(OFF)
ID(OFF)
IS(ON)
ID(ON)
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage
VS = –10 V to +10 V
IS = –10 mA
Refer to On-Resistance
current(2)
25°C
–40°C to +85°C
–40°C to +125°C
4.5
Ω
0.25
Ω
0.3
Ω
0.35
Ω
0.6
Ω
–40°C to +85°C
0.7
Ω
–40°C to +125°C
0.85
Ω
25°C
0.05
–40°C to +85°C
–40°C to +125°C
25°C
0.5
–40°C to +125°C
0.01
0.05
Ω/°C
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
VD = –10 V / + 10 V
Refer to Off-Leakage Current
25°C
–0.2
0.2
nA
–40°C to +85°C
–1.6
1.6
nA
–40°C to +125°C
–40
40
nA
VDD = 16.5 V, VSS = –16.5 V
Switch state is off
VS = +10 V / –10 V
VD = –10 V / + 10 V
Refer to Off-Leakage Current
25°C
–1
1
nA
–40°C to +85°C
–3
3
nA
–40°C to +125°C
–60
60
nA
VDD = 16.5 V, VSS = –16.5 V
Switch state is on
VS = VD = ±10 V
Refer to On-Leakage Current
25°C
–1
1
nA
–40°C to +85°C
–2
2
nA
–40°C to +125°C
–50
50
nA
36
V
0.05
0.04
LOGIC INPUTS (SEL / EN pins)
VIH
Logic voltage high
–40°C to +125°C
1.3
0
VIL
Logic voltage low
–40°C to +125°C
IIH
Input leakage current
–40°C to +125°C
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
–40°C to +125°C
0.005
–1
0.8
V
1
µA
–0.005
µA
3
pF
POWER SUPPLY
25°C
IDD
VDD supply current
40
µA
–40°C to +85°C
48
µA
–40°C to +125°C
62
µA
10
µA
15
µA
25
µA
VDD = 16.5 V, VSS = –16.5 V
Logic inputs = 0 V, 5 V, or VDD
VDD = 16.5 V, VSS = –16.5 V
Logic inputs = 0 V, 5 V, or VDD
–40°C to +85°C
–40°C to +125°C
30
25°C
ISS
(1)
(2)
6
VSS supply current
3
When VS is positive, VD is negative, or when VS is negative, VD is positive.
When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
6.7 ±15 V Dual Supply: Switching Characteristics
VDD = +15 V ± 10%, VSS = –15 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +15 V, VSS = –15 V, TA = 25℃ (unless otherwise noted)
PARAMETER
tTRAN
tON
(EN)
tOFF
(EN)
tBBM
Transition time from control input
TEST CONDITIONS
VS = 10 V
RL = 300 Ω, CL = 35 pF
Refer to Transition Time
TA
TYP
MAX
UNIT
120
175
ns
–40°C to +85°C
190
ns
–40°C to +125°C
210
ns
170
ns
185
ns
200
ns
180
ns
–40°C to +85°C
195
ns
–40°C to +125°C
210
ns
VS = 10 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
25°C
Turn-on time from enable
25°C
Turn-off time from enable
VS = 10 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
Break-before-make time delay
VS = 10 V,
RL = 300 Ω, CL = 35 pF
Refer to Break-Before-Make
MIN
25°C
100
–40°C to +85°C
–40°C to +125°C
100
25°C
50
–40°C to +85°C
1
–40°C to +125°C
1
25°C
ns
ns
ns
0.19
ms
–40°C to +85°C
0.2
ms
–40°C to +125°C
0.2
ms
Device turn on time
(VDD to output)
VDD rise time = 100ns
RL = 300 Ω, CL = 35 pF
Refer to Turn-on (VDD) Time
tPD
Propagation delay
RL = 50 Ω , CL = 5 pF
Refer to Propagation Delay
25°C
700
ps
QINJ
Charge injection
VD = 0 V, CL = 1 nF
Refer to Charge Injection
25°C
–10
pC
OISO
Off-isolation
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Off Isolation
25°C
–75
dB
OISO
Off-isolation
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 1 MHz
Refer to Off Isolation
25°C
–55
dB
XTALK
Crosstalk
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Crosstalk
25°C
–117
dB
XTALK
Crosstalk
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 1MHz
Refer to Crosstalk
25°C
–106
dB
BW
–3dB Bandwidth
RL = 50 Ω , CL = 5 pF
VS = 0 V
Refer to Bandwidth
25°C
40
IL
Insertion loss
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 1 MHz
25°C
–0.18
dB
25°C
–64
dB
TON (VDD)
VPP = 0.62 V on VDD and VSS
RL = 50 Ω , CL = 5 pF,
ACPSRR AC Power Supply Rejection Ratio
f = 1 MHz
Refer to ACPSRR
MHz
THD+N
Total Harmonic Distortion + Noise
VPP = 15 V, VBIAS = 0 V
RL = 10 kΩ , CL = 5 pF,
f = 20 Hz to 20 kHz
Refer to THD + Noise
25°C
0.0005
%
CS(OFF)
Source off capacitance
VS = 0 V, f = 1 MHz
25°C
33
pF
CD(OFF)
Drain off capacitance
VS = 0 V, f = 1 MHz
25°C
48
pF
CS(ON),
CD(ON)
On capacitance
VS = 0 V, f = 1 MHz
25°C
148
pF
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
7
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
6.8 36 V Single Supply: Electrical Characteristics
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
2.5
3.2
Ω
4.2
Ω
4.9
Ω
0.2
Ω
0.25
Ω
0.3
Ω
1
Ω
1.5
Ω
2
Ω
ANALOG SWITCH
RON
VS = 0 V to 30 V
ID = –10 mA
Refer to On-Resistance
On-resistance
V = 0 V to 30 V
On-resistance mismatch between S
ID = –10 mA
channels
Refer to On-Resistance
ΔRON
RON FLAT
On-resistance flatness
VS = 18 V, IS = –10 mA
Refer to On-Resistance
RON DRIFT On-resistance drift
IS(OFF)
VS = 0 V to 30 V
IS = –10 mA
Refer to On-Resistance
Source off leakage current(1)
25°C
–40°C to +85°C
–40°C to +125°C
25°C
0.1
–40°C to +85°C
–40°C to +125°C
25°C
0.3
–40°C to +85°C
–40°C to +125°C
–40°C to +125°C
0.009
VDD = 39.6 V, VSS = 0 V
Switch state is off
VS = 30 V / 1 V
VD = 1 V / 30 V
Refer to Off-Leakage Current
25°C
–0.3
0.3
nA
–40°C to +85°C
–3.5
3.5
nA
–40°C to +125°C
–60
60
nA
VDD = 39.6 V, VSS = 0 V
Switch state is off
VS = 30 V / 1 V
VD = 1 V / 30 V
Refer to Off-Leakage Current
25°C
VDD = 39.6 V, VSS = 0 V
Switch state is on
VS = VD = 30 V or 1 V
Refer to On-Leakage Current
1
nA
–40°C to +85°C
–6.2
6.2
nA
–40°C to +125°C
–80
80
nA
25°C
–0.4
0.4
nA
–40°C to +85°C
–4.5
4.5
nA
–40°C to +125°C
–70
70
nA
Logic voltage high
–40°C to +125°C
1.3
36
V
VIL
Logic voltage low
–40°C to +125°C
0
IIH
Input leakage current
–40°C to +125°C
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
–40°C to +125°C
ID(OFF)
IS(ON)
ID(ON)
Drain off leakage current(1)
Channel on leakage
current(2)
–1
0.05
Ω/°C
0.05
0.05
LOGIC INPUTS (SEL / EN pins)
VIH
0.005
–1
0.8
V
1
µA
–0.005
µA
3
pF
POWER SUPPLY
25°C
IDD
(1)
(2)
8
VDD supply current
VDD = 39.6 V, VSS = 0 V
Logic inputs = 0 V, 5 V, or VDD
28
50
µA
–40°C to +85°C
58
µA
–40°C to +125°C
70
µA
When VS is positive, VD is negative, or when VS is negative, VD is positive.
When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
6.9 36 V Single Supply: Switching Characteristics
VDD = +36 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +36 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
tTRAN
tON
(EN)
tOFF
(EN)
tBBM
Transition time from control input
TEST CONDITIONS
VS = 18 V
RL = 300 Ω, CL = 35 pF
Refer to Transition Time
TA
TYP
MAX
UNIT
110
170
ns
–40°C to +85°C
185
ns
–40°C to +125°C
200
ns
180
ns
190
ns
200
ns
180
ns
–40°C to +85°C
195
ns
–40°C to +125°C
200
ns
VS = 18 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
25°C
Turn-on time from enable
25°C
Turn-off time from enable
VS = 18 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
Break-before-make time delay
VS = 18 V,
RL = 300 Ω, CL = 35 pF
Refer to Break-Before-Make
MIN
25°C
110
–40°C to +85°C
–40°C to +125°C
90
25°C
44
–40°C to +85°C
1
–40°C to +125°C
1
ns
ns
ns
25°C
0.17
ms
–40°C to +85°C
0.19
ms
–40°C to +125°C
0.19
ms
Device turn on time
(VDD to output)
VDD rise time = 100ns
RL = 300 Ω, CL = 35 pF
Refer to Turn-on (VDD) Time
tPD
Propagation delay
RL = 50 Ω , CL = 5 pF
Refer to Propagation Delay
25°C
920
ps
QINJ
Charge injection
VD = 18 V, CL = 1 nF
Refer to Charge Injection
25°C
–13
pC
OISO
Off-isolation
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 100 kHz
Refer to Off Isolation
25°C
–75
dB
OISO
Off-isolation
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 1 MHz
Refer to Off Isolation
25°C
–55
dB
XTALK
Crosstalk
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 100 kHz
Refer to Crosstalk
25°C
–117
dB
XTALK
Crosstalk
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 1MHz
Refer to Crosstalk
25°C
–106
dB
BW
–3dB Bandwidth
RL = 50 Ω , CL = 5 pF
VS = 6 V,
Refer to Bandwidth
25°C
38
IL
Insertion loss
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 1 MHz
25°C
–0.19
dB
25°C
–60
dB
TON (VDD)
VPP = 0.62 V on VDD and VSS
RL = 50 Ω , CL = 5 pF,
ACPSRR AC Power Supply Rejection Ratio
f = 1 MHz
Refer to ACPSRR
MHz
THD+N
Total Harmonic Distortion + Noise
VPP =18 V, VBIAS = 18 V
RL = 10 kΩ , CL = 5 pF,
f = 20 Hz to 20 kHz
Refer to THD + Noise
25°C
0.0004
%
CS(OFF)
Source off capacitance
VS = 6 V, f = 1 MHz
25°C
35
pF
CD(OFF)
Drain off capacitance
VS = 6 V, f = 1 MHz
25°C
49
pF
CS(ON),
CD(ON)
On capacitance
VS = 6 V, f = 1 MHz
25°C
146
pF
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
9
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
6.10 12 V Single Supply: Electrical Characteristics
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
ANALOG SWITCH
RON
VS = 0 V to 10 V
ID = –10 mA
Refer to On-Resistance
On-resistance
V = 0 V to 10 V
On-resistance mismatch between S
ID = –10 mA
channels
Refer to On-Resistance
ΔRON
RON FLAT
On-resistance flatness
VS = 6 V, IS = –10 mA
Refer to On-Resistance
RON DRIFT On-resistance drift
IS(OFF)
ID(OFF)
IS(ON)
ID(ON)
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage
VS = 0 V to 10 V
IS = –10 mA
Refer to On-Resistance
current(2)
25°C
4.6
6
Ω
7.5
Ω
8.4
Ω
0.2
Ω
0.32
Ω
0.35
Ω
2
Ω
–40°C to +85°C
2.2
Ω
–40°C to +125°C
2.4
Ω
–40°C to +85°C
–40°C to +125°C
25°C
0.08
–40°C to +85°C
–40°C to +125°C
25°C
1.2
–40°C to +125°C
VDD = 13.2 V, VSS = 0 V
Switch state is off
VS = 10 V / 1 V
VD = 1 V / 10 V
Refer to Off-Leakage Current
25°C
0.017
–0.5
0.05
Ω/°C
0.5
nA
–40°C to +85°C
–2
2
nA
–40°C to +125°C
–30
30
nA
VDD = 13.2 V, VSS = 0 V
Switch state is off
VS = 10 V / 1 V
VD = 1 V / 10 V
Refer to Off-Leakage Current
25°C
–0.5
VDD = 13.2 V, VSS = 0 V
Switch state is on
VS = VD = 10 V or 1 V
Refer to On-Leakage Current
0.5
nA
–40°C to +85°C
–3
0.05
3
nA
–40°C to +125°C
–50
50
nA
25°C
–1.5
1.5
nA
–40°C to +85°C
–3
0.05
3
nA
–40°C to +125°C
–40
40
nA
36
V
LOGIC INPUTS (SEL / EN pins)
VIH
Logic voltage high
–40°C to +125°C
1.3
0
VIL
Logic voltage low
–40°C to +125°C
IIH
Input leakage current
–40°C to +125°C
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
–40°C to +125°C
0.005
–1
0.8
V
1
µA
–0.005
µA
3
pF
POWER SUPPLY
25°C
IDD
(1)
(2)
10
VDD supply current
VDD = 13.2 V, VSS = 0 V
Logic inputs = 0 V, 5 V, or VDD
10
35
µA
–40°C to +85°C
45
µA
–40°C to +125°C
55
µA
When VS is positive, VD is negative, or when VS is negative, VD is positive.
When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
6.11 12 V Single Supply: Switching Characteristics
VDD = +12 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted)
Typical at VDD = +12 V, VSS = 0 V, TA = 25℃ (unless otherwise noted)
PARAMETER
tTRAN
tON
(EN)
tOFF
(EN)
tBBM
Transition time from control input
TEST CONDITIONS
VS = 8 V
RL = 300 Ω, CL = 35 pF
Refer to Transition Time
TA
TYP
MAX
UNIT
180
185
ns
–40°C to +85°C
215
ns
–40°C to +125°C
235
ns
180
ns
210
ns
230
ns
210
ns
–40°C to +85°C
235
ns
–40°C to +125°C
250
ns
VS = 8 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
25°C
Turn-on time from enable
25°C
Turn-off time from enable
VS = 8 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
Break-before-make time delay
VS = 8 V,
RL = 300 Ω, CL = 35 pF
Refer to Break-Before-Make
MIN
25°C
120
–40°C to +85°C
–40°C to +125°C
130
25°C
40
–40°C to +85°C
1
–40°C to +125°C
1
25°C
ns
ns
ns
0.19
ms
–40°C to +85°C
0.2
ms
–40°C to +125°C
0.2
ms
Device turn on time
(VDD to output)
VDD rise time = 100ns
RL = 300 Ω, CL = 35 pF
Refer to Turn-on (VDD) Time
tPD
Propagation delay
RL = 50 Ω , CL = 5 pF
Refer to Propagation Delay
25°C
740
ps
QINJ
Charge injection
VD = 6 V, CL = 1 nF
Refer to Charge Injection
25°C
–6
pC
OISO
Off-isolation
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 100 kHz
Refer to Charge Injection
25°C
–75
dB
OISO
Off-isolation
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 1 MHz
Refer to Off Isolation
25°C
–55
dB
XTALK
Crosstalk
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 100 kHz
Refer to Crosstalk
25°C
–117
dB
XTALK
Crosstalk
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 1MHz
Refer to Crosstalk
25°C
–106
dB
BW
–3dB Bandwidth
RL = 50 Ω , CL = 5 pF
VS = 6 V
Refer to Bandwidth
25°C
42
IL
Insertion loss
RL = 50 Ω , CL = 5 pF
VS = 6 V, f = 1 MHz
25°C
–0.3
dB
25°C
–65
dB
TON (VDD)
VPP = 0.62 V on VDD and VSS
RL = 50 Ω , CL = 5 pF,
ACPSRR AC Power Supply Rejection Ratio
f = 1 MHz
Refer to ACPSRR
MHz
THD+N
Total Harmonic Distortion + Noise
VPP = 6 V, VBIAS = 6 V
RL = 10 kΩ , CL = 5 pF,
f = 20 Hz to 20 kHz
Refer to THD + Noise
25°C
0.0009
%
CS(OFF)
Source off capacitance
VS = 6 V, f = 1 MHz
25°C
38
pF
CD(OFF)
Drain off capacitance
VS = 6 V, f = 1 MHz
25°C
56
pF
CS(ON),
CD(ON)
On capacitance
VS = 6 V, f = 1 MHz
25°C
150
pF
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
11
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
6.12 ±5 V Dual Supply: Electrical Characteristics
VDD = +5 V ± 10%, VSS = –5 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +5 V, VSS = –5 V, TA = 25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX
UNIT
4
7.2
Ω
8.6
Ω
ANALOG SWITCH
RON
VDD = +4.5 V, VSS = –4.5 V
VS = –4.5 V to +4.5 V
ID = –10 mA
Refer to On-Resistance
On-resistance
V = –4.5 V to +4.5 V
On-resistance mismatch between S
ID = –10 mA
channels
Refer to On-Resistance
ΔRON
RON FLAT
On-resistance flatness
VS = 0 V, IS = –10 mA
Refer to On-Resistance
RON DRIFT On-resistance drift
IS(OFF)
ID(OFF)
IS(ON)
ID(ON)
Source off leakage current(1)
Drain off leakage current(1)
Channel on leakage
VS = –4.5 V to +4.5 V
ID = –10 mA
Refer to On-Resistance
current(2)
25°C
–40°C to +85°C
–40°C to +125°C
10
Ω
0.3
Ω
–40°C to +85°C
0.35
Ω
–40°C to +125°C
0.4
Ω
25°C
0.1
25°C
2.2
Ω
–40°C to +85°C
1.3
2.5
Ω
–40°C to +125°C
2.8
Ω
–40°C to +125°C
VDD = +5.5 V, VSS = –5.5 V
Switch state is off
VS = +4.5 V / –4.5 V
VD = –4.5 V / + 4.5 V
Refer to Off-Leakage Current
25°C
0.019
–0.3
0.05
Ω/°C
0.3
nA
–40°C to +85°C
–1
1
nA
–40°C to +125°C
–30
30
nA
VDD = +5.5 V, VSS = –5.5 V
Switch state is off
VS = +4.5 V / –4.5 V
VD = –4.5 V / + 4.5 V
Refer to Off-Leakage Current
25°C
–0.4
0.4
nA
VDD = +5.5 V, VSS = –5.5 V
Switch state is on
VS = VD = ±4.5 V
Refer to On-Leakage Current
0.05
–40°C to +85°C
–3
3
nA
–40°C to +125°C
–50
50
nA
25°C
–0.4
0.4
nA
0.05
–40°C to +85°C
–3
3
nA
–40°C to +125°C
–40
40
nA
36
V
LOGIC INPUTS (SEL / EN pins)
VIH
Logic voltage high
–40°C to +125°C
1.3
0
VIL
Logic voltage low
–40°C to +125°C
IIH
Input leakage current
–40°C to +125°C
IIL
Input leakage current
–40°C to +125°C
CIN
Logic input capacitance
–40°C to +125°C
0.005
–1
0.8
V
1
µA
–0.005
µA
3
pF
POWER SUPPLY
25°C
IDD
VDD supply current
35
µA
–40°C to +85°C
40
µA
–40°C to +125°C
50
µA
5
µA
8
µA
15
µA
VDD = +5.5 V, VSS = –5.5 V
Logic inputs = 0 V, 5 V, or VDD
VDD = +5.5 V, VSS = –5.5 V
Logic inputs = 0 V, 5 V, or VDD
–40°C to +85°C
–40°C to +125°C
20
25°C
ISS
(1)
(2)
12
VSS supply current
0.001
When VS is positive, VD is negative, or when VS is negative, VD is positive.
When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
6.13 ±5 V Dual Supply: Switching Characteristics
VDD = +5 V ± 10%, VSS = –5 V ±10%, GND = 0 V (unless otherwise noted)
Typical at VDD = +5 V, VSS = –5 V, TA = 25℃ (unless otherwise noted)
PARAMETER
tTRAN
tON
(EN)
tOFF
(EN)
tBBM
Transition time from control input
TEST CONDITIONS
VS = 3 V
RL = 300 Ω, CL = 35 pF
Refer to Transition Time
TA
TYP
MAX
UNIT
300
400
ns
–40°C to +85°C
490
ns
–40°C to +125°C
550
ns
300
ns
350
ns
380
ns
280
ns
–40°C to +85°C
330
ns
–40°C to +125°C
350
ns
VS = 3 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
25°C
Turn-on time from enable
25°C
Turn-off time from enable
VS = 3 V
RL = 300 Ω, CL = 35 pF
Refer to Turn-on and Turn-off
Time
Break-before-make time delay
VS = 3 V,
RL = 300 Ω, CL = 35 pF
Refer to Break-Before-Make
MIN
25°C
220
–40°C to +85°C
–40°C to +125°C
210
25°C
50
–40°C to +85°C
1
–40°C to +125°C
1
ns
ns
ns
25°C
0.19
ms
–40°C to +85°C
0.19
1
ms
–40°C to +125°C
0.19
1
ms
Device turn on time
(VDD to output)
VDD rise time = 100ns
RL = 300 Ω, CL = 35pF
Refer to Turn-on (VDD) Time
tPD
Propagation delay
RL = 50 Ω , CL = 5 pF
Refer to Propagation Delay
25°C
650
ps
QINJ
Charge injection
VD = 0 V, CL = 1 nF
Refer to Charge Injection
25°C
–5
pC
OISO
Off-isolation
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Off Isolation
25°C
–75
dB
OISO
Off-isolation
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 1 MHz
Refer to Off Isolation
25°C
–55
dB
XTALK
Crosstalk
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 100 kHz
Refer to Crosstalk
25°C
–117
dB
XTALK
Crosstalk
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 1MHz
Refer to Crosstalk
25°C
–106
dB
BW
–3dB Bandwidth
RL = 50 Ω , CL = 5 pF
VS = 0 V,
Refer to Bandwidth
25°C
43
IL
Insertion loss
RL = 50 Ω , CL = 5 pF
VS = 0 V, f = 1 MHz
25°C
–0.35
dB
25°C
–68
dB
TON (VDD)
VPP = 0.62 V on VDD and VSS
RL = 50 Ω , CL = 5 pF,
ACPSRR AC Power Supply Rejection Ratio
f = 1 MHz
Refer to ACPSRR
MHz
THD+N
Total Harmonic Distortion + Noise
VPP = 5 V, VBIAS = 0 V
RL = 10 kΩ , CL = 5 pF,
f = 20 Hz to 20 kHz
Refer to THD + Noise
25°C
0.001
%
CS(OFF)
Source off capacitance
VS = 0 V, f = 1 MHz
25°C
40
pF
CD(OFF)
Drain off capacitance
VS = 0 V, f = 1 MHz
25°C
60
pF
CS(ON),
CD(ON)
On capacitance
VS = 0 V, f = 1 MHz
25°C
150
pF
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
13
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
6.14 Typical Characteristics
at TA = 25°C
4
VDD = 18 V, V SS = –18 V
VDD = 15 V, V SS = –15 V
)On
Ω Resistance (
3.5
3
2.5
2
1.5
1
-20
-15
-10
-5
0
5
10
VS or VD - Source or Drain Voltage (V)
15
20
Figure 6-1. On-Resistance vs Source or Drain Voltage – Dual
Supply
Figure 6-2. On-Resistance vs Source or Drain Voltage – Dual
Supply
5
VDD = 36 V, V SS = 0 V
VDD = 24 V, V SS = 0 V
VDD = 18 V, V SS = 0 V
)On
Ω Resistance (
4
3
2
1
0
4
8
12
16
20
24
28
VS or VD - Source or Drain Voltage (V)
32
36
Figure 6-3. On-Resistance vs Source or Drain Voltage – Single
Supply
Figure 6-4. On-Resistance vs Source or Drain Voltage – Single
Supply
VDD = 15 V, VSS = -15 V
VDD = 5 V, VSS = -5 V
Figure 6-5. On-Resistance vs Temperature
14
Figure 6-6. On-Resistance vs Temperature
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
6.14 Typical Characteristics (continued)
at TA = 25°C
VDD = 12 V, VSS = 0 V
VDD = 36 V, VSS = 0 V
Figure 6-7. On-Resistance vs Temperature
Figure 6-8. On-Resistance vs Temperature
15
Leakage Current (nA)
10
5
ID(OFF) VS/VD = –4.5 V/4.5 V
ID(OFF) VS/VD = 4.5 V/–4.5 V
ION –4.5 V
ION 4.5 V
IS(OFF) VS/VD = –4.5 V/4.5 V
IS(OFF) VS/VD = 4.5 V/–4.5 V
0
-5
-10
-15
-40
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
VDD = 5 V, VSS = -5 V
VDD = 15 V, VSS = -15 V
Figure 6-9. Leakage Current vs Temperature
Figure 6-10. Leakage Current vs Temperature
VDD = 36 V, VSS = 0 V
VDD = 12 V, VSS = 0 V
Figure 6-11. Leakage Current vs Temperature
Figure 6-12. Leakage Current vs Temperature
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
15
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
6.14 Typical Characteristics (continued)
at TA = 25°C
50
100
VDD = 15 V, V SS = –15 V
VDD = 5 V, V SS = –5 V
VDD = 12 V, V SS = 0 V
VDD = 5 V, V SS = 0 V
A)
Supply
Current (
μ
40
35
30
25
20
60
40
20
0
-20
-40
15
0
4
8
12
16
20
24
Logic Voltage (V)
28
32
-60
-20
36
-15
-10
D015
-5
0
5
Source Voltage (V)
10
15
20
Figure 6-14. Charge Injection vs Source Voltage – Dual Supplies
Figure 6-13. Supply Current vs Logic Voltage
130
80
VDD = 15 V, V SS = –15 V
VDD = 5 V, V SS = –5 V
60
VDD = 36 V, V SS = 0 V
VDD = 20 V, V SS = 0 V
VDD = 15 V, V SS = 0 V
VDD = 12 V, V SS = 0 V
VDD = 5 V, V SS = 0 V
110
90
Charge Injection (pC)
Charge Injection (pC)
VDD = 15 V, V SS = –15 V
VDD = 5 V, V SS = –5 V
80
Charge Injection (pC)
45
40
20
0
70
50
30
10
-10
-30
-20
-50
-40
-20
-70
-15
-10
-5
0
5
Drain Voltage (V)
10
15
20
Figure 6-15. Charge Injection vs Drain Voltage – Dual Supplies
0
4
8
12
16
20
24
Source Voltage (V)
28
32
36
D018
Figure 6-16. Charge Injection vs Source Voltage – Single
Supplies
120
VDD = 36 V, V SS = 0 V
VDD = 20 V, V SS = 0 V
VDD = 15 V, V SS = 0 V
VDD = 12 V, V SS = 0 V
VDD = 5 V, V SS = 0 V
100
Charge Injection (pC)
80
60
40
20
0
-20
-40
-60
0
4
8
12
16
20
24
Drain Voltage (V)
28
32
36
VDD = 15 V, VSS = -15 V
Figure 6-17. Charge Injection vs Drian Voltage – Single Supplies
16
Figure 6-18. TTRANSITION vs Temperature
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
6.14 Typical Characteristics (continued)
at TA = 25°C
120
Transiton_Falling
Transiton_Rising
115
Time (ns)
110
105
100
95
90
85
80
-40
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
VDD = 36 V, VSS = 0 V
VDD = 15 V, VSS = -15 V
Figure 6-19. TTRANSITION vs Temperature
Figure 6-20. TON and TOFF vs Temperature
120
T(OFF)
T(ON)
110
Off-Isolation (dB)
Turn On/Off Time (ns)
115
105
100
95
90
85
80
-40
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
100
VDD = 15V, V SS = –15V
VDD = 36V, V SS = 0V
1k
10k
100k
1M
Frequency (Hz)
10M
100M
VDD = 36 V, VSS = 0 V
Figure 6-21. TON and TOFF vs Temperature
Figure 6-22. Off-Isolation vs Frequency
Switch ON (EN = 1)
Switch OFF (EN = 0)
Figure 6-23. Crosstalk vs Frequency
Figure 6-24. Crosstalk vs Frequency
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
17
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
6.14 Typical Characteristics (continued)
at TA = 25°C
0.002
THD + N (%)
VDD = 15 V, V SS = –15 V
VDD = 5 V, V SS = –5V
0.001
0.0008
0.0007
0.0006
0.0005
0.0004
0.0003
10
100
1k
10k
Frequency (Hz)
Figure 6-25. THD+N vs Frequency (Dual Supplies)
Figure 6-26. THD+N vs Frequency (Single Supplies)
VDD = 15 V, VSS = -15 V
VDD = +15 V, VSS = -15 V
Figure 6-27. On Response vs Frequency
Figure 6-28. ACPSRR vs Frequency
VDD = +15 V, VSS = -15 V
VDD = 12 V, VSS = 0 V
Figure 6-29. Capacitance vs Source Voltage or Drain Voltage
18
Figure 6-30. Capacitance vs Source Voltage or Drain Voltage
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
7 Parameter Measurement Information
7.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote onresistance. Figure 7-1 shows the measurement setup used to measure RON. Voltage (V) and current (ISD) are
measured using the following setup, where RON is computed as RON = V / ISD:
V
ISD
Sx
Dx
VS
RON
Figure 7-1. On-Resistance
7.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current.
2. Drain off-leakage current.
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF).
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF).
Figure 7-2 shows the setup used to measure both off-leakage currents.
VDD
VSS
VDD
VSS
Is (OFF)
A
ID (OFF)
S1
S1
D
D
A
S2
S2
VS
VD
VS
VD
GND
GND
IS(OFF)
ID(OFF)
Figure 7-2. Off-Leakage Measurement Setup
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
19
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
7.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON).
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON).
Either the source pin or drain pin is left floating during the measurement. Figure 7-3 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON).
VDD
VSS
VDD
VSS
Is (ON)
S1
A
D
N.C.
S2
ID (ON)
S1
N.C.
D
A
S2
VS
VS
V
VS
GND
GND
IS(ON)
ID(ON)
Figure 7-3. On-Leakage Measurement Setup
7.4 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 90% after the address signal
has risen or fallen past the logic threshold. The 90% transition measurement is utilized to provide the timing of
the device. System level timing can then account for the time constant added from the load resistance and load
capacitance. Figure 7-4 shows the setup used to measure transition time, denoted by the symbol tTRANSITION.
VSS
VDD
VSS
0.1 µF
0.1 µF
3V
VSEL
VDD
tr < 20 ns
50%
50%
tf < 20 ns
VS
S1
0V
D
tTRANSITIO N
90%
RL
CL
SEL
Output
0V
Output
S2
tTRANSITIO N
10%
GND
VSEL
Figure 7-4. Transition-Time Measurement Setup
20
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
7.5 tON(EN) and tOFF(EN)
Turn-on time is defined as the time taken by the output of the device to rise to 90% after the enable has risen
past the logic threshold. The 90% measurement is utilized to provide the timing of the device. System level
timing can then account for the time constant added from the load resistance and load capacitance. Figure 7-5
shows the setup used to measure turn-on time, denoted by the symbol tON(EN).
Turn-off time is defined as the time taken by the output of the device to fall to 10% after the enable has fallen
past the logic threshold. The 10% measurement is utilized to provide the timing of the device. System level
timing can then account for the time constant added from the load resistance and load capacitance. Figure 7-5
shows the setup used to measure turn-off time, denoted by the symbol tOFF(EN).
VDD
0.1 µF
0.1 µF
3V
VEN
VSS
tr < 20 ns
50%
50%
VDD
tf < 20 ns
VS
0V
tON
VSS
S1
D
Output
S2
tOFF
90%
RL
CL
EN
Output
10%
0V
GND
VEN
Figure 7-5. Turn-On and Turn-Off Time Measurement Setup
7.6 Break-Before-Make
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. Figure 7-6 shows
the setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM).
VDD
0.1 µF
0.1 µF
3V
VSEL
VSS
tr < 20ns
VDD
tf < 20ns
VS
0V
VSS
S1
D
Output
S2
Output
RL
80%
CL
SEL
tBBM 1
tBBM 2
0V
VSEL
GND
tOPEN (BBM) = min ( tBBM 1, tBBM 2)
Figure 7-6. Break-Before-Make Delay Measurement Setup
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
21
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
7.7 tON (VDD) Time
The tON (VDD) time is defined as the time taken by the output of the device to rise to 90% after the supply has
risen past the supply threshold. The 90% measurement is used to provide the timing of the device turning on in
the system. Figure 7-7 shows the setup used to measure turn on time, denoted by the symbol tON (VDD).
VSS
0.1 µF
VDD
Supply
Ramp
0.1 µF
VDD
tr = 10 µs
VDD
4.5 V
VS
0V
VSS
S2
D
Output
S1
tON
90%
RL
CL
EN
Output
3V
SEL
GND
0V
Figure 7-7. tON (VDD) Time Measurement Setup
7.8 Propagation Delay
Propagation delay is defined as the time taken by the output of the device to rise or fall 50% after the input signal
has risen or fallen past the 50% threshold. Figure 7-8 shows the setup used to measure propagation delay,
denoted by the symbol tPD.
VDD
0.1 µF
0.1 µF
250 mV
Input
(VS)
VSS
tr < 40ps
50%
50%
VDD
tf < 40ps
VS
0V
tPD 1
50
tPD 2
VSS
S1
D
Output
S2
RL
Output
50%
CL
50%
GND
0V
tProp Delay = max ( tPD 1, tPD 2)
Figure 7-8. Propagation Delay Measurement Setup
22
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
7.9 Charge Injection
The TMUX6219 has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS
transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal.
The amount of charge injected into the source or drain of the device is known as charge injection, and is
denoted by the symbol QC. Figure 7-9 shows the setup used to measure charge injection from source (Sx) to
drain (D).
VDD
VSS
0.1 µF
0.1 µF
3V
VEN
VDD
tr < 20 ns
VSS
tf < 20 ns
S1
0V
Output
D
VD
S2
CL
N.C.
Output
QINJ = CL ×
VD
EN
VOUT
VOUT
GND
VEN
Figure 7-9. Charge-Injection Measurement Setup
7.10 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the
source pin (Sx) of an off-channel. Figure 7-10 shows the setup used to measure, and the equation used to
calculate off isolation.
VDD
VSS
0.1 µF
Network Analyzer
0.1 µF
VDD
VS
VSS
S1
VOUT
50Ÿ
VSIG
D
50Ÿ
S2
50Ÿ
GND
1BB +OKH=PEKJ = 20 × .KC
8176
85
Figure 7-10. Off Isolation Measurement Setup
Off Isolation
§V
·
20 ˜ Log ¨ OUT ¸
© VS ¹
(1)
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
23
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
7.11 Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. Figure 7-11 shows the setup used to measure, and the equation used to
calculate crosstalk.
VDD
VSS
VDD
VSS
0.1 µF
Network Analyzer
0.1 µF
VS
S1
D
50Ÿ
VSIG
VOUT
S2
50Ÿ
50Ÿ
GND
%NKOOP=HG = 20 × .KC
8176
85
Figure 7-11. Crosstalk Measurement Setup
7.12 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. Figure
7-12 shows the setup used to measure bandwidth.
VDD
VSS
VDD
VSS
0.1 µF
Network Analyzer
0.1 µF
VS
S1
50Ÿ
VSIG
VOUT
D
50Ÿ
S2
50Ÿ
GND
$=J@SE@PD = 20 × .KC
8176
85
Figure 7-12. Bandwidth Measurement Setup
7.13 THD + Noise
The total harmonic distortion (THD) of a signal is a measurement of the harmonic distortion, and is defined as
the ratio of the sum of the powers of all harmonic components to the power of the fundamental frequency at the
mux output.
24
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
The on-resistance of the device varies with the amplitude of the input signal and results in distortion when the
drain pin is connected to a low-impedance load. Total harmonic distortion plus noise is denoted as THD + N.
VDD
VSS
0.1 µF
0.1 µF
VDD
VSS
Audio Precision
S1
40 Ÿ
D
VOUT
VS
RL
Other
Sx pins
50Ÿ
GND
Figure 7-13. THD + N Measurement Setup
7.14 Power Supply Rejection Ratio (PSRR)
PSRR measures the ability of a device to prevent noise and spurious signals that appear on the supply voltage
pin from coupling to the output of the switch. The DC voltage on the device supply is modulated by a sine wave
of 620 mVPP. The ratio of the amplitude of signal on the output to the amplitude of the modulated signal is the
ACPSRR. A high ratio represents a high degree of tolerance to supply rail variation.
Figure 6-28 shows how the de-coupling capacitors reduce high frequency noise on the supply pins. This helps
stabilize the supply and immediately filter as much of the supply noise as possible.
VDD
Network Analyzer
DC Bias
Injector
50 Ÿ
VSS
With & Without
Capacitor
0.1 µF
VSS
VDD
620 mVPP
S1
VBIAS
VIN
0.1 µF
50 Ÿ
S2
50 Ÿ
VOUT
D
RL
GND
CL
2544 = 20 × .KC
8176
8+0
Figure 7-14. ACPSRR Measurement Setup
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
25
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
8 Detailed Description
8.1 Overview
The TMUX6219 is a 2:1, 1-channel switch. Each input is turned on or turned off based on the state of the select
line and enable pin.
8.2 Functional Block Diagram
VDD
VSS
S1
D
S2
Decoder
EN
SEL
Figure 8-1. TMUX6219 Functional Block Diagram
8.3 Feature Description
8.3.1 Bidirectional Operation
The TMUX6219 conducts equally well from source (Sx) to drain (D) or from drain (D) to source (Sx). Each
channel has very similar characteristics in both directions and supports both analog and digital signals.
8.3.2 Rail to Rail Operation
The valid signal path input or output voltage for TMUX6219 ranges from VSS to VDD.
8.3.3 1.8 V Logic Compatible Inputs
The TMUX6219 has 1.8-V logic compatible control for all logic control inputs. 1.8-V logic level inputs allows the
TMUX6219 to interface with processors that have lower logic I/O rails and eliminates the need for an external
translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations refer to
Simplifying Design with 1.8 V logic Muxes and Switches.
8.3.4 Fail-Safe Logic
The TMUX6219 supports Fail-Safe Logic on the control input pins (EN, SEL) allowing for operation up to 36 V
above ground, regardless of the state of the supply pins. This feature allows voltages on the control pins to be
applied before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system
complexity by removing the need for power supply sequencing on the logic control pins. For example, the FailSafe Logic feature allows the logic input pins of the TMUX6219 to be ramped to +36 V while VDD and VSS = 0 V.
The logic control inputs are protected against positive faults of up to +36 V in powered-off condition, but do not
offer protection against negative overvoltage conditions.
26
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
8.3.5 Latch-Up Immune
Latch-Up is a condition where a low impedance path is created between a supply pin and ground. This condition
is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains
even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic
damage due to excessive current levels. The Latch-Up condition typically requires a power cycle to eliminate the
low impedance path.
The TMUX62xx family of devices are constructed on Silicon on Insulator (SOI) based process where an oxide
layer is added between the PMOS and NMOS transistor of each CMOS switch to prevent parasitic structures
from forming. The oxide layer is also known as an insulating trench and prevents triggering of latch up events
due to overvoltage or current injections. The latch-up immunity feature allows the TMUX62xx family of switches
and multiplexers to be used in harsh environments.
8.3.6 Ultra-Low Charge Injection
The TMUX6219 has a transmission gate topology, as shown in Figure 8-2. Any mismatch in the stray
capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is
opened or closed.
OFF ON
CGSN
CGDN
S
D
CGSP
CGDP
OFF ON
Figure 8-2. Transmission Gate Topology
The TMUX6219contains specialized architecture to reduce charge injection on the source (Sx). To further reduce
charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the drain (D). This
will ensure that excess charge from the switch transition will be pushed into the compensation capacitor on the
drain (D) instead of the source (Sx). As a general rule of thumb, Cp should be 20× larger than the equivalent
load capacitance on the source (Sx). Figure 8-3 shows charge injection variation with source voltage with
different compensation capacitors on the Drain side.
Figure 8-3. Charge Injection Compensation
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
27
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
8.4 Device Functional Modes
When the EN pin of the TMUX6219 is pulled high, one of the switches is closed based on the state of the SEL
pin. When the EN pin is pulled low, both of the switches are in an open state regardless of the state of the SEL
pin. The control pins can be as high as 36 V.
The TMUX6219 can be operated without any external components except for the supply decoupling capacitors.
The EN pin has an internal pull-up resistor of 4 MΩ and SEL pin has internal pull-down resistor of 4 MΩ. If
unused, EN pin must be tied to VDD and SEL pin must be tied to GND in order to ensure the device does not
consume additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path
inputs (S1, S2, or D) should be connected to GND.
8.5 Truth Tables
Table 8-1 show the truth tables for the TMUX6219.
Table 8-1. TMUX6219 Truth Table
EN
SEL
Selected Source Connected To Drain (D) Pin
0
X(1)
All sources are off (HI-Z)
1
0
S1
1
1
S2
(1)
28
X denotes don't care.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
TMUX6219 is part of the precision switches and multiplexers family of devices. TMUX6219 offers low RON, low
on and off leakage currents and ultra-low charge injection performance. These properties make TMUX6219 ideal
for implementing high precision industrial systems requiring selection of one of two inputs or outputs.
9.2 Typical Application
9.2.1 Power Amplifier Gate Driver
One application of the TMUX6219 is for input control of a power amplifier gate driver. Utilizing a switch allows a
system to control when the DAC is connected to the power amplifier, and can stop biasing the power amplifier by
switching the gate to VSS. The wide dual supply range of ±4.5 V to ±18 V allows the switch to work with GaN
power amplifiers and the wide single supply range 4.5 V to 36 V works well with LDMOS power amplifiers.
Figure 9-1 shows the TMUX6219 configured for control of the power amplifier gate driver in GaN application.
DAC
8V
Output
voltage
VDD
RF Tx/Rx
TMUX6219
1.8 V
±12 V/0 V
±12 V
RF Input
MCU
0 V to 1.8 V
VSS
Figure 9-1. Power Amplifier Gate Driver
9.2.2 Design Requirements
For the design example, use the parameters listed in Table 9-1.
Table 9-1. Design Parameters
PARAMETERS
Supply (VDD)
VALUES
GAN application
LDMOS application
8V
5V
Supply (VSS)
-12 V
0V
MUX I/O signal range
-12 V to 8 V (Rail-to-Rail)
0 V to 5 V (Rail-to-Rail)
Control logic thresholds
1.8 V compatiable (up to VDD)
1.8 V compatiable (up to VDD)
EN
EN pulled high to enable the switch
EN pulled high to enable the switch
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
29
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
9.2.3 Detailed Design Procedure
The application shown in Power Amplifier Gate Driver figure demonstrates how to toggle between the DAC
output and low signal voltage for control of a GaN power amplifier using a single control input. The DAC output is
utilized to bias the gate of the power amplifier and can be disconnected from the circuit using the select pin of
the switch. The TMUX6219 can support 1.8 V logic signals on the control input, allowing the device to interface
with low logic controls of an FPGA or MCU. The TMUX6219 can be operated without any external components
except for the supply decoupling capacitors. The select pin has an internal pull-down resistor to prevent floating
input logic. All inputs to the switch must fall within the recommend operating conditions of the TMUX6219
including signal range and continuous current. For this design with a positive supply of 8 V on VDD, and negative
supply of -12 V on VSS, the signal range can be 8 V to -12 V. The max continuous current (IDC) can be up to 330
mA as shown in the Recommended Operating Conditions table for wide-range current measurement.
9.2.4 Application Curve
The low on and off leakage currents of TMUX6219 and ultra-low charge injection performance make this device
ideal for implementing high precision industrial systems. Figure 9-2 shows the plot for the charge injection versus
source voltage for the TMUX6219.
80
VDD = 15 V, V SS = –15 V
VDD = 5 V, V SS = –5 V
Charge Injection (pC)
60
40
20
0
-20
-40
-20
-15
-10
-5
0
5
Drain Voltage (V)
10
15
20
Figure 9-2. Charge Injection vs Drain Voltage
10 Power Supply Recommendations
The TMUX6219 operates across a wide supply range of of ±4.5 V to ±18 V (4.5 V to 36 V in single-supply
mode). As shown in Figure 9-1, the device also performs well with asymmetrical supplies such as VDD = 8 V and
VSS = –12 V.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the supply rails
to other components. Good power-supply decoupling is important to achieve optimum performance. For
improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF at both the VDD
and VSS pins to ground. Place the bypass capacitors as close to the power supply pins of the device as possible
using low-impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer
low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling
purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for
connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in
parallel lowers the overall inductance and is beneficial for connections to power and ground planes. Always
ensure the ground (GND) connection is established before supplies are ramped.
30
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
11 Layout
11.1 Layout Guidelines
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. Figure 11-1 shows progressively better techniques of rounding corners. Only the last example
(BEST) maintains constant trace width and minimizes reflections.
BETTER
BEST
2W
WORST
1W min.
W
Figure 11-1. Trace Example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance
changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via
introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference
from the other layers of the board. Be careful when designing test points, through-hole pins are not
recommended at high frequencies.
Figure 11-2 illustrates an example of a PCB layout with the TMUX6219. Some key considerations are:
•
•
•
•
•
Decouple the supply pins with a 0.1-µF and 1 µF capacitor, placed lowest value capacitor as close to the pin
as possible. Make sure that the capacitor voltage rating is sufficient for the supply voltage.
Keep the input lines as short as possible.
Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
Using multiple vias in parallel will lower the overall inductance and is beneficial for connection to ground
planes.
11.2 Layout Example
S2
D
TMUX6219
S1
VSS
EN
C
SEL
VDD
C
GND
Wide (low inductance)
trace for power
C
C
Wide (low inductance)
trace for power
Via to ground plane
Figure 11-2. TMUX6219 Layout Example
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
31
TMUX6219
www.ti.com
SCDS420B – SEPTEMBER 2020 – REVISED JANUARY 2021
12 Device and Documentation Support
12.1 Related Documentation
Texas Instruments, Improve Stability Issues with Low CON Multiplexers.
Texas Instruments, Improving Signal Measurement Accuracy in Automated Test Equipment.
Texas Instruments, Multiplexers and Signal Switches Glossary.
Texas Instruments, QFN/SON PCB Attachment.
Texas Instruments, Quad Flatpack No-Lead Logic Packages.
Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches.
Texas Instruments, System-Level Protection for High-Voltage Analog Multiplexers.
Texas Instruments, True Differential, 4 x 2 MUX, Analog Front End, Simultaneous-Sampling ADC Circuit.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
32
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TMUX6219
PACKAGE OPTION ADDENDUM
www.ti.com
27-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TMUX6219DGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
X219
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
