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TPA2010D1
SLOS417D – OCTOBER 2003 – REVISED NOVEMBER 2015
TPA2010D1 2.5-W Mono Filter-Free Class-D Audio Power Amplifier
1 Features
2 Applications
•
•
•
•
•
1
•
•
Maximum Battery Life and Minimum Heat
– Efficiency with an 8-Ω Speaker:
– 88% at 400 mW
– 80% at 100 mW
– 2.8-mA Quiescent Current
– 0.5-µA Shutdown Current
Only Three External Components
– Optimized PWM Output Stage Eliminates LC
Output Filter
– Internally Generated 250-kHz Switching
Frequency Eliminates Capacitor and Resistor
– Improved PSRR (–75 dB) and Wide Supply
Voltage (2.5 V to 5.5 V) Eliminates Need for a
Voltage Regulator
– Fully Differential Design Reduces RF
Rectification and Eliminates Bypass Capacitor
– Improved CMRR Eliminates Two Input
Coupling Capacitors
Die-size ball grid (DSBGA)
– NanoFree™ Lead-Free (YZF)
– NanoStar™ SnPb (YEF)
Wireless or Cellular Handsets and PDAs
Personal Navigation Devices
General Portable Audio Devices
Linear Vibrator Drivers
3 Description
The TPA2010D1 (sometimes referred to as
TPA2010) is a 2.5-W high efficiency filter-free class-D
audio power amplifier (class-D amp) in a 1,45 mm ×
1,45 mm die-size ball grid array (DSBGA) that
requires only three external components.
Features like 88% efficiency, –75-dB PSRR,
improved RF-rectification immunity, and 8 mm2 total
PCB area make the TPA2010D1 (TPA2010) class-D
amp ideal for cellular handsets. A fast start-up time of
1 ms with minimal pop makes the TPA2010D1
(TPA2010) ideal for PDA applications.
In cellular handsets, the earpiece, speaker phone,
and melody ringer can each be driven by the
TPA2010D1. The TPA2010D1 allows independent
gain while summing signals from separate sources
and has a low 36 µV noise floor that is A-weighted.
Device Information(1)
PART NUMBER
PACKAGE
DSBGA YEF (9)
TPA2010D1
DSBGA YZF (9)
BODY SIZE (NOM)
1.50 mm × 1.50 mm
(1) For all available packages, see the Orderable Addendum at
the end of the data sheet.
4 TPA2010D1 With Differential Input For A Wireless Phone
To Battery
Internal
Oscillator
+
RI
-
SHUTDOWN
RI
CS
IN_
Differential
Input
VDD
+
PWM
HBridge
VO+
VO-
IN+
Bias
Circuitry
GND
TPA2010D1
Filter-Free Class D
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA2010D1
SLOS417D – OCTOBER 2003 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
TPA2010D1 With Differential Input For A
Wireless Phone ......................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
2
3
3
4
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
4
4
4
4
5
5
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Operating Characteristics..........................................
Dissipation Ratings ...................................................
Typical Characteristics ..............................................
1
1
1
10.2 Functional Block Diagram ..................................... 11
10.3 Feature Description............................................... 11
10.4 Device Functional Modes...................................... 15
11 Application and Implementation........................ 19
9 Parameter Measurement Information ................ 10
10 Detailed Description ........................................... 11
10.1 Overview ............................................................... 11
11.1 Application Information.......................................... 19
11.2 Typical Applications .............................................. 19
12 Power Supply Recommendations ..................... 23
12.1 Power Supply Decoupling Capacitors................... 23
13 Layout................................................................... 23
13.1 Layout Guidelines ................................................. 23
13.2 Board Layout......................................................... 23
13.3 Layout Example .................................................... 25
14 Device and Documentation Support ................. 26
14.1
14.2
14.3
14.4
14.5
Device Support......................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
15 Mechanical, Packaging, and Orderable
Information ........................................................... 27
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2007) to Revision D
•
2
Page
Added Pin Configuration and Functions section, Thermal Information table, ESD Ratings table, Feature Description
section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations
section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable
Information section ................................................................................................................................................................ 1
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SLOS417D – OCTOBER 2003 – REVISED NOVEMBER 2015
6 Device Comparison Table
PART NUMBER
SPEAKER
CHANNELS
SPEAKER AMP
TYPE
OUTPUT POWER (W)
PSRR (dB)
TPA2010D1
Mono
Class D
2.5
75
TPA2005D1
Mono
Class D
1.4
75
TPA2011D1
Mono
Class D
3.2
86
7 Pin Configuration and Functions
YZF and YEF Package
9-Pin DSBGA
Top View
1,55 mm
1,40 mm
IN+
GND
VO-
A1
A2
A3
VDD
PVDD
GND
B1
B2
B3
INC1
SHUTDOWN VO+
C2
C3
1,55 mm
1,40 mm
Note: Pin A1 is marked with a “0” for
Pb-free (YZF) and a “1” for SnPb (YEF).
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
A1
IN+
I
Positive differential input
A2
GND
I
High-current ground
A3
VO-
O
Negative BTL output
B1
VDD
I
Power supply
B2
PVDD
I
Power supply
B3
GND
I
High-current ground
C1
IN-
I
Negative differential input
C2
SHUTDOWN
I
Shutdown terminal (active low logic)
C3
VO+
O
Positive BTL output
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8 Specifications
8.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
In active mode
MIN
MAX
UNIT
–0.3
6
V
VDD
Supply voltage
VI
Input voltage
–0.3
7
V
Continuous total power dissipation
–0.3
VDD + 0.3
V
See Dissipation Ratings
°C
In SHUTDOWN mode
TA
Operating free-air temperature
TJ
Operating junction temperature
–40
Lead temperature 1,6 mm (1/16 inch) from case
for 10 seconds
Tstg
(1)
YZF
YEF
Storage temperature
–65
85
°C
260
°C
235
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VDD
Supply voltage
2.5
5.5
VIH
High-level input voltage
SHUTDOWN
V
1.3
VDD
V
VIL
Low-level input voltage
SHUTDOWN
RI
Input resistor
Gain ≤ 20 V/V (26 dB)
0
0.35
VIC
Common mode input voltage range VDD = 2.5 V, 5.5 V, CMRR ≤ –49 dB
0.5
VDD – 0.8
V
TA
Operating free-air temperature
–40
85
°C
15
V
kΩ
8.4 Thermal Information
TPA2010D1
THERMAL METRIC (1)
YZF (DSBGA)
UNIT
9 PINS
RθJA
Junction-to-ambient thermal resistance
100.3
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
0.7
°C/W
Junction-to-board thermal resistance
24.7
°C/W
ψJT
Junction-to-top characterization parameter
3.5
°C/W
ψJB
Junction-to-board characterization parameter
24.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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8.5 Electrical Characteristics
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1
25
mV
|VOS|
Output offset voltage
(measured differentially)
VI = 0 V, AV = 2 V/V, VDD = 2.5 V to 5.5 V
PSRR
Power supply rejection ratio
VDD = 2.5 V to 5.5 V
–75
–55
dB
CMRR
Common mode rejection ratio
VDD = 2.5 V to 5.5 V, VIC = VDD / 2 to 0.5 V,
VIC = VDD / 2 to VDD – 0.8 V
–68
–49
dB
|IIH|
High-level input current
VDD = 5.5 V, VI = 5.8 V
100
µA
|IIL|
Low-level input current
VDD = 5.5 V, VI = –0.3 V
5
µA
I(Q)
Quiescent current
I(SD)
Shutdown current
rDS(on)
Static drain-source on-state
resistance
f(sw)
VDD = 5.5 V, no load
3.4
VDD = 3.6 V, no load
2.8
4.9
VDD = 2.5 V, no load
2.2
3.2
V(SHUTDOWN) = 0.35 V, VDD = 2.5 V to 5.5 V
0.5
2
VDD = 2.5 V
700
VDD = 3.6 V
500
VDD = 5.5 V
400
mA
µA
mΩ
Output impedance in SHUTDOWN
V(SHUTDOWN) = 0.35 V
Switching frequency
VDD = 2.5 V to 5.5 V
200
250
>1
300
Gain
VDD = 2.5 V to 5.5 V
285 kW
RI
300 kW
RI
315 kW
RI
Resistance from shutdown to GND
kΩ
kHz
V
V
300
kΩ
8.6 Operating Characteristics
TA = 25°C, Gain = 2 V/V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VDD = 5 V
THD + N = 10%, f = 1 kHz, RL = 4 Ω
THD + N = 1%, f = 1 kHz, RL = 4 Ω
PO
Output power
THD + N = 10%, f = 1 kHz, RL = 8 Ω
THD + N = 1%, f = 1 kHz, RL = 8 Ω
Total harmonic distortion plus
noise
VDD = 3.6 V
1.3
VDD = 2.5 V
0.52
VDD = 5 V
2.08
VDD = 3.6 V
1.06
VDD = 2.5 V
0.42
VDD = 5 V
1.45
VDD = 3.6 V
0.73
VDD = 2.5 V
0.33
VDD = 5 V
1.19
VDD = 3.6 V
0.59
0.18%
VDD = 3.6 V, PO = 0.5 W, RL = 8 Ω, f = 1 kHz
0.19%
VDD = 2.5 V, PO = 200 mW, RL = 8 Ω, f = 1 kHz
0.20%
f = 217 Hz,
V(RIPPLE) = 200 mVpp
kSVR
Supply ripple rejection ratio
SNR
Signal-to-noise ratio
VDD = 5 V, PO = 1 W, RL = 8 Ω
Vn
Output voltage noise
VDD = 3.6 V, f = 20 Hz to 20 kHz,
Inputs ac-grounded with Ci = 2 µF
No weighting
48
A weighting
36
CMRR
Common mode rejection ratio
VDD = 3.6 V, VIC = 1 Vpp
f = 217 Hz
–63
ZI
Input impedance
142
VDD = 3.6 V
W
W
W
W
0.26
VDD = 5 V, PO = 1 W, RL = 8 Ω, f = 1 kHz
VDD = 3.6 V, Inputs ac-grounded
with Ci = 2 µF
Start-up time from shutdown
UNIT
2.5
VDD = 2.5 V
THD+N
TYP MAX
–67
dB
97
dB
150
µVRMS
dB
158
1
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8.7 Dissipation Ratings
(1)
PACKAGE
DERATING FACTOR (1)
TA ≤ 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
YZF
7.8 mW/°C
780 mW
429 mW
312 mW
Derating factor measure with High K board.
8.8 Typical Characteristics
100
90
90
80
VDD = 5 V,
RL = 8 Ω, 33 µH
VDD = 2.5 V,
RL = 8 Ω, 33 µH
Efficiency − %
70
60
50
40
Class AB.
VDD = 5 V,
RL = 8 Ω
30
20
VDD = 5 V,
RL = 4 Ω,
VDD = 3.6 V,
33 µH
RL = 4 Ω, 33 µH
70
60
Efficiency − %
80
VDD = 2.5 V,
RL = 4 Ω, 33 µH
50
40
Class AB.
VDD = 5 V,
RL = 4 Ω
30
20
10
10
0 0
0
0.4
0.2
0.6
1
0.8
0
1.2
0.2 0.4 0.6 0.8 1
1.2 1.4 1.6 1.8 2
PO − Output Power − W
PO − Output Power − W
Figure 1. Efficiency versus Output Power
Figure 2. Efficiency versus Output Power
1.4
0.7
Class-AB 5 V, 4 Ω
0.6
P D − Power Dissipation − W
P D − Power Dissipation − W
1.2
1
Class-AB 5 V, 8 Ω
0.8
0.6
VDD = 5 V, RL = 4 Ω,
0.4
0.2
VDD = 5 V, RL = 8 Ω
0
0
0.5
1
1.5
2
Class-AB 3.6 V, 4 Ω
0.5
Class-AB 3.6 V, 8 Ω
0.4
0.3
VDD = 3.6 V, RL = 4 Ω
0.2
0.1
VDD = 3.6 V,
RL = 8 Ω, 33 µH
0
2.5
0
0.2
0.4
0.6
0.8
1
1.2
PO − Output Power − W
PO − Output Power − W
Figure 3. Power Dissipation versus Output Power
Figure 4. Power Dissipation versus Output Power
600
I DD − Supply Current − mA
400
VDD = 2.5 V
300
200
100
RL = 8 Ω, 33 µH
250
VDD = 3.6 V
500
I DD − Supply Current − mA
300
RL = 4 Ω, 33 µH
VDD = 5 V,
VDD = 3.6 V
200
150
100
VDD = 2.5 V
50
VDD = 5 V
0
0
0.5
1
1.5
2
0
2.5
0
PO − Output Power − W
Figure 5. Supply Current versus Output Power
6
0.2
0.4
0.6
0.8
1.2
1
PO − Output Power − W
1.4
Figure 6. Supply Current versus Output Power
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Typical Characteristics (continued)
2
I (SD) − Shutdown Current − µ A
I DD − Supply Current − mA
5
4.5
RL = 8 Ω, (resistive)
4
RL = 8 Ω,
33 µH
3.5
3
2.5
No Load
2
2.5
3
3.5
4
4.5
5
1.5
VDD = 5 V
1
VDD = 3.6 V
VDD = 2.5 V
0.5
0
5.5
0
0.1
0.2
0.3
0.4
Shutdown Voltage − V
VDD − Supply Voltage − V
Figure 7. Supply Current versus Supply Voltage
Figure 8. Supply Current versus Shutdown Voltage
3
2.5
PO at 10% THD
Gain = 2 V/V
f = 1 kHz
2
VDD = 5 V
PO − Output Power − W
PO − Output Power − W
2.5
2
VDD = 3.6 V
1.5
VDD = 2.5 V
1
PO at 1% THD
Gain = 2 V/V
f = 1 kHz
VDD = 5 V
1.5
VDD = 3.6 V
1
VDD = 2.5 V
0.5
0.5
0
0
4
8
12
16
20
24
28
32
4
RL − Load Resistance − Ω
3
2.5
Gain = 2 V/V
f = 1 kHz
RL = 4 Ω, 10% THD
2
RL = 4 Ω, 1% THD
1.5
1
0.5
0
2.5
RL = 8 Ω,10% THD
RL = 8 Ω,1% THD
3
3.5
4
4.5
VCC − Supply Voltage − V
5
Figure 11. Output Power versus Supply Voltage
8
12
16
20
24
RL − Load Resistance − Ω
28
32
Figure 10. Output Power versus Load Resistance
THD+N − Total Harmonic Distortion + Noise − %
Figure 9. Output Power versus Load Resistance
PO − Output Power − W
0.5
20
10
5
2
RL = 4 Ω,
f = 1 kHz,
Gain = 2 V/V
2.5 V
3V
3.6 V
1
5V
0.5
0.2
0.1
20m
50m 100m 200m 500m 1
PO − Output Power − W
2
3
Figure 12. Total Harmonic Distortion + Noise versus Output
Power
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THD+N − Total Harmonic Distortion + Noise − %
20
RL = 8 Ω,
f = 1 kHz,
Gain = 2 V/V
10
2.5 V
5
3V
3.6 V
2
5V
1
0.5
0.2
0.1
5m 10m 20m 50m 100m 200m 500m 1
2
THD+N − Total Harmonic Distortion + Noise − %
Typical Characteristics (continued)
10
VDD = 5 V
CI = 2 µF
RL = 8 Ω
Gain = 2 V/V
5
2
PO = 250 mW
1
0.5
PO = 1W
0.2
0.1
0.05
0.02
0.01
20
50 100 200
PO − Output Power − W
PO = 25 mW
PO = 125 mW
1
0.5
PO = 500 mW
0.2
0.1
0.05
0.02
0.01
0.005
20
50 100 200 500 1k 2k
f − Frequency − Hz
5k 10k 20k
THD+N − Total Harmonic Distortion + Noise − %
8
10
PO = 250 mW
CI = 2 µF
RL = 4 Ω
Gain = 2 V/V
2
1
VDD = 3.6 V
VDD = 3 V
0.5
0.2
VDD = 2.5 V
0.1
0.05
0.02
0.01
VDD = 4 V
20
50 100 200
VDD = 5 V
500 1k 2k
5k 10k 20k
10
VDD = 2.5 V
CI = 2 µF
RL = 8 Ω
Gain = 2 V/V
5
2
PO = 15 mW
PO = 75 mW
1
0.5
PO = 200 mW
0.2
0.1
0.05
0.02
0.01
20
50 100 200 500 1k 2k
5k 10k 20k
f − Frequency − Hz
Figure 15. Total Harmonic Distortion + Noise versus
Frequency
5
THD+N − Total Harmonic Distortion + Noise − %
2
2k
Figure 14. Total Harmonic Distortion + Noise versus
Frequency
5k 10k 20k
Figure 16. Total Harmonic Distortion + Noise versus
Frequency
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
VDD = 3.6 V
CI = 2 µF
RL = 8 Ω
Gain = 2 V/V
500 1k
f − Frequency − Hz
Figure 13. Total Harmonic Distortion + Noise versus Output
Power
5
PO = 50 mW
10
f = 1 kHz
PO = 200 mW
VDD = 2.5 V
1
VDD = 5 V
VDD = 3.6 V
0.1
0
0.5
1
1.5 2
2.5
3
3.5
4 4.5
5
f − Frequency − Hz
VIC − Common Mode Input Voltage − V
Figure 17. Total Harmonic Distortion + Noise versus
frequency
Figure 18. Total Harmonic Distortion + Noise versus
Common Mode Input Voltage
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Typical Characteristics (continued)
−30
Inputs ac-grounded
CI = 2 mF
RL = 8 W
Gain = 2 V/V
−40
−50
Supply Ripple Rejection Ratio − dB
Supply Ripple Rejection Ratio − dB
−30
VDD = 2. 5 V
VDD = 3.6 V
−60
−70
−80
Inputs ac-grounded
CI = 2 mF
RL = 4 W
Gain = 2 V/V
−40
VDD = 2.5 V
−50
−60
VDD = 3.6 V
−70
−80
VDD = 5 V
VDD = 5 V
−90
−90
20
100
20
10 k 20 k
1k
100
10 k 20 k
1k
f − Frequency − Hz
f − Frequency − Hz
Figure 19. Supply Ripple Rejection Ratio versus Frequency
Figure 20. Supply Ripple Rejection Ratio versus Frequency
Supply Ripple Rejection Ratio − dB
−30
Inputs floating
RL = 8 W
−40
C1 − High
3.6 V
VDD
200 mV/div
−50
C1 − Amp
512 mV
VDD = 5 V
−60
C1 − Duty
12%
−70
VOUT
20 mV/div
VDD = 3.6 V
−80
VDD = 2.5 V
−90
20
100
1k
10 k 20 k
f − Frequency − Hz
t − Time − 2 ms/div
−50
VO − Output Voltage − dBV
−100
0
VDD Shown in Figure 22
CI = 2 µF,
Inputs ac-grounded
Gain = 2V/V
−50
−150
−100
Figure 22. GSM Power Supply Rejection versus Time
0
Supply Ripple Rejection Ratio − dB
0
V DD − Supply Voltage − dBV
Figure 21. Supply Ripple Rejection Ratio versus Frequency
−150
−10
−20
−30
−40
VDD = 3.6 V
VDD = 2. 5 V
−50
VDD = 5 V
−60
−70
−80
0
400
800
1200
1600
2000
0
f − Frequency − Hz
0.5
1
1.5
2
2.5
3
3.5 4
4.5 5
DC Common Mode Voltage − V
Figure 23. GSM Power Supply Rejection versus Frequency
Figure 24. Supply Ripple Rejection Ratio versus DC
Common Mode Voltage
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−50
VIC = 200 mVPP
RL = 8 Ω
Gain = 2 V/V
−55
−60
VDD = 3.6 V
−65
−70
−75
20
100
1k
f − Frequency − Hz
10 k 20 k
CMRR − Common Mode Rejection Ratio − dB
CMRR − Common Mode Rejection Ratio − dB
Typical Characteristics (continued)
0
−10
−20
−30
−40
VDD = 3.6 V
VDD = 2.5 V
−50
−60
−70
−80
VDD = 5 V,
Gain = 2
−90
−100
0
1
2
3
4
5
VIC − Common Mode Input Voltage − V
Figure 25. Common-Mode Rejection Ratio versus
Frequency
Figure 26. Common-Mode Rejection Ratio versus
Common-Mode Input Voltage
9 Parameter Measurement Information
All parameters are measured according to the conditions described in the Specifications section.
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10 Detailed Description
10.1 Overview
The TPA2010D1 is a high-efficiency filter-free Class-D audio amplifier capable of delivering up to 2.5 W into 4-Ω
loads with 5-V power supply. The fully-differential design of this amplifier avoids the usage of bypass capacitors
and the improved CMRR eliminates the usage of input-coupling capacitors. This makes the device size a perfect
choice for small, portable applications because only three external components are required. The advanced
modulation used in the TPA2010D1 PWM output stage eliminates the need for an output filter.
10.2 Functional Block Diagram
*Gain =
150 kΩ
RI
*Gain = 2 V/V
B1, B2
VDD
150 kΩ
IN- C1
_
+
VDD
+
_
Deglitch
Logic
Gate
Drive
+
_
Deglitch
Logic
Gate
Drive
A3
VO-
_
+
_
+
+
_
IN+ A1
150 kΩ
C2
SHUTDOWN
TTL
SD Input
Buffer
300 kΩ
Notes:
* Total gain =
2x
Biases
and
References
Ramp
Generator
Startup
Protection
Logic
C3
VO+
OC
Detect
A2, B3
GND
150 kΩ
RI
10.3 Feature Description
10.3.1 Fully Differential Amplifier
The TPA2010D1 is a fully differential amplifier with differential inputs and outputs. The fully differential amplifier
consists of a differential amplifier and a common-mode amplifier. The differential amplifier ensures that the
amplifier outputs a differential voltage on the output that is equal to the differential input times the gain. The
common-mode feedback ensures that the common-mode voltage at the output is biased around VDD/2 regardless
of the common-mode voltage at the input. The fully differential TPA2010D1 can still be used with a single-ended
input; however, TI recommends using the TPA2010D1 with differential inputs when in a noisy environment, like a
wireless handset, to ensure maximum noise rejection.
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Feature Description (continued)
10.3.2 Advantages of Fully Differential Amplifiers
• Input-coupling capacitors not required:
– The fully differential amplifier allows for input bias at voltage other than mid-supply. For example, if a
codec has a midsupply lower than the midsupply of the TPA2010D1, the common-mode feedback circuit
adjusts, and the TPA2010D1 outputs remain biased at midsupply of the TPA2010D1. The inputs of the
TPA2010D1 can be biased from 0.5 V to VDD –0.8 V. If the inputs are biased outside of that range, inputcoupling capacitors are required.
• Midsupply bypass capacitor, C(BYPASS), not required:
– The fully differential amplifier does not require a bypass capacitor because any shift in the midsupply
affects both positive and negative channels equally and cancels at the differential output.
• Better RF-immunity:
– GSM handsets save power by turning on and shutting off the RF transmitter at a rate of 217 Hz. The
transmitted signal is picked up on input and output traces. The fully differential amplifier cancels the signal
better than the typical audio amplifier.
10.3.3 Efficiency and Thermal Information
The maximum ambient temperature depends on the PCB system heatsinking ability. The derating factor for the
YEF and YEZ packages appear in the dissipation rating table. Converting this to θJA:
EJA =
1
1
=
= 128.2°C/W
Derating Factor 0.0078
(1)
Given θJA of 128.2°C/W, the maximum allowable junction temperature of 150°C, and the maximum internal
dissipation of 0.4 W (2.25 W, 4-Ω load, 5-V supply, from Figure 3), the maximum ambient temperature can be
calculated with the following equation.
TA:max ; = TJ:max ; F EJA × PD:max ; = 150 F 128 × (0.4) = 98.72°C
(2)
Equation 2 shows that the calculated maximum ambient temperature is 98.72°C at maximum power dissipation
with a 5-V supply and 4-Ω a load. See Figure 3. The TPA2010D1 is designed with thermal protection that turns
the device off when the junction temperature surpasses 165°C ~ 190°C to prevent damage to the IC. Using
speakers more resistive than 4-Ω dramatically increases the thermal performance by reducing the output current
and increasing the efficiency of the amplifier.
10.3.4 Eliminating the Output Filter With the TPA2010D1
This section describes why the user can eliminate the output filter with the TPA2010D1.
10.3.4.1 Effect on Audio
The class-D amplifier outputs a pulse-width modulated (PWM) square wave, which is the sum of the switching
waveform and the amplified input audio signal. The human ear acts as a band-pass filter such that only the
frequencies between approximately 20 Hz and 20 kHz are passed. The switching frequency components are
much greater than 20 kHz, so the only signal heard is the amplified input audio signal.
10.3.4.2 Traditional Class-D Modulation Scheme
The traditional class-D modulation scheme, which is used in the TPA005Dxx family, has a differential output
where each output is 180 degrees out of phase and changes from ground to the supply voltage, VDD. Therefore,
the differential pre-filtered output varies between positive and negative VDD, where filtered 50% duty cycle yields
0 volts across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown
in Figure 27.
NOTE
Even at an average of 0 volts across the load (50% duty cycle), the current to the load is
high causing a high loss and thus causing a high supply current.
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Feature Description (continued)
OUT+
OUT+5 V
Differential Voltage
Across Load
0V
-5 V
Current
Figure 27. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms into an
Inductive Load with No Input
10.3.4.3 TPA2010D1 Modulation Scheme
The TPA2010D1 uses a modulation scheme that still has each output switching from 0 to the supply voltage.
However, OUT+ and OUT– are now in phase with each other with no input. The duty cycle of OUT+ is greater
than 50% and OUT– is less than 50% for positive voltages. The duty cycle of OUT+ is less than 50% and OUT–
is greater than 50% for negative voltages. The voltage across the load sits at 0 volts throughout most of the
switching period greatly reducing the switching current, which reduces any I2R losses in the load.
OUT+
OUTDifferential
Voltage
Across
Load
Output = 0 V
+5 V
0V
-5 V
Current
OUT+
OUTDifferential
Voltage
Across
Load
Output > 0 V
+5 V
0V
-5 V
Current
Figure 28. The TPA2010D1 Output Voltage and Current Waveforms into an Inductive Load
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Feature Description (continued)
10.3.4.4 Efficiency: Use a Filter With the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results
in maximum current flow. This causes more loss in the load, causing lower efficiency. The ripple current is large
for the traditional modulation scheme because the ripple current is proportional to voltage multiplied by the time
at that voltage. The differential voltage swing is 2 × VDD and the time at each voltage is half the period for the
traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for the
next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive,
whereas an LC filter is almost purely reactive.
The TPA2010D1 modulation scheme has very little loss in the load without a filter because the pulses are very
short and the change in voltage is VDD instead of 2 × VDD. As the output power increases, the pulses widen
making the ripple current larger. Ripple current can be filtered with an LC filter for increased efficiency, but for
most applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance than the speaker that results in less power
dissipated, which increases efficiency.
10.3.4.5 Effects of Applying a Square Wave into a Speaker
If the amplitude of a square wave is high enough and the frequency of the square wave is within the bandwidth
of the speaker, a square wave causes the voice coil to jump out of the air gap and/or scar the voice coil.
However, a 250-kHz switching frequency is not significant because the speaker cone movement is proportional
to 1/f2 for frequencies beyond the audio band. Therefore, the amount of cone movement at the switching
frequency is very small. However, damage could occur to the speaker if the voice coil is not designed to handle
the additional power. To size the speaker for added power, the ripple current dissipated in the load needs to be
calculated by subtracting the theoretical supplied power, PSUP THEORETICAL, from the actual supply power, PSUP, at
maximum output power, POUT. The switching power dissipated in the speaker is the inverse of the measured
efficiency, ηMEASURED, minus the theoretical efficiency, ηTHEORETICAL.
PSPKR = PSUP F PSUP
THEORETICAL
where
•
the speaker is operating at maximum power
PSUP PSUP THEORETICAL
PSPKR =
F
POUT
POUT
1
1
PSPKR = POUT × l
F
p
¸MEASURED
¸THEORETICAL
RL
¸THEORETICAL =
R L + 2 × rDS :on ;
(3)
(4)
(5)
(6)
The maximum efficiency of the TPA2010D1 with a 3.6 V supply and an 8-Ω load is 86% from Equation 6. Using
equation Equation 5 with the efficiency at maximum power (84%), we see that there is an additional 17 mW
dissipated in the speaker. The added power dissipated in the speaker is not an issue as long as it is taken into
account when choosing the speaker.
10.3.4.6 When to Use an Output Filter
Design the TPA2010D1 without an output filter if the traces from amplifier to speaker are short. The TPA2010D1
passed FCC and CE radiated emissions with no shielding with speaker trace wires 100 mm long or less.
Wireless handsets and PDAs are great applications for class-D without a filter.
A ferrite bead filter can often be used if the design is failing radiated emissions without an LC filter, and the
frequency sensitive circuit is greater than 1 MHz. This is good for circuits that just have to pass FCC and CE
because FCC and CE only test radiated emissions greater than 30 MHz. If choosing a ferrite bead, choose one
with high impedance at high frequencies, but very low impedance at low frequencies.
Use an LC output filter if there are low frequency (< 1 MHz) EMI sensitive circuits and/or there are long leads
from amplifier to speaker.
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Feature Description (continued)
Figure 29 and Figure 30 show typical ferrite bead and LC output filters.
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 29. Typical Ferrite Chip Bead Filter (Chip Bead Example: NEC/Tokin: N2012zps121)
33 µH
OUTP
1 µF
33 µH
OUTN
1 µF
Figure 30. Typical LC Output Filter, Cutoff Frequency Of 27 kHz
10.4 Device Functional Modes
10.4.1 Summing Input Signals with the TPA2010D1
Most wireless phones or PDAs must sum signals at the audio power amplifier or have two signals sources that
need separate gain. The TPA2010D1 makes it easy to sum signals or use separate signal sources with different
gains. Many phones now use the same speaker for the ear-piece and ringer, where the wireless phone would
require a much lower gain for the phone ear-piece than for the ringer. PDAs and phones that have stereo
headphones require summing of the right and left channels to output the stereo signal to the mono speaker.
10.4.1.1 Summing Two Differential Inputs
Two extra resistors are needed for summing differential signals (a total of 5 components). The gain for each input
source can be set independently (see Equation 7 and Equation 8, and Figure 31).
VO 2 × 150 •À
=
Vl1
R I1
VO 2 × 150 •À
Gain 2 =
=
VI2
R I2
Gain 1 =
V
l p
V
V
l p
V
(7)
(8)
If summing left and right inputs with a gain of 1 V/V, use RI1 = RI2 = 300 kΩ.
If summing a ring tone and a phone signal, set the ring-tone gain to Gain 2 = 2 V/V, and the phone gain to gain
1 = 0.1 V/V. The resistor values would be: RI1 = 3 MΩ, and = RI2 = 150 kΩ.
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Device Functional Modes (continued)
Differential
Input 1
+
RI1
-
RI1
+
RI2
To Battery
Internal
Oscillator
Differential
Input 2
RI2
CS
IN_
-
VDD
PWM
HBridge
VO+
VO-
+
IN+
GND
SHUTDOWN
Bias
Circuitry
Filter-Free Class D
Figure 31. TPA2010D1 Summing Two Differential Inputs
10.4.1.2 Summing a Differential Input Signal and a Single-Ended Input Signal
Figure 32 shows how to sum a differential input signal and a single-ended input signal. Ground noise can couple
in through IN+ with this method. It is better to use differential inputs. The corner frequency of the single-ended
input is set by CI2, shown in Equation 11. To assure that each input is balanced, the single-ended input must be
driven by a low-impedance source even if the input is not in use.
VO
150 •À V
=2×
l p
VI1
R I1
V
VO
150 •À V
Gain 2 =
=2×
l p
VI2
R I2
V
1
CI2 =
tN × R I2 × fC2
Gain 1 =
(9)
(10)
(11)
If summing a ring tone and a phone signal, the phone signal should use a differential input signal while the ring
tone might be limited to a single-ended signal. Phone gain is set at Gain 1 = 0.1 V/V, and the ring-tone gain is
set to Gain 2 = 2 V/V, the resistor values would be: RI1 = MΩ, and RI2 = 150 kΩ.
The high pass corner frequency of the single-ended input is set by capacitor CI2. If the desired corner frequency
is less than 20 Hz.
CI2 >
1
> 53 pF
tN × 150 •À × 20 Hz
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Device Functional Modes (continued)
RI1
Differential
Input 1
Single-Ended
Input 2
RI1
CI2 R
I2
To Battery
Internal
Oscillator
CS
IN_
RI2
VDD
PWM
HBridge
VO+
VO-
+
IN+
CI2
SHUTDOWN
GND
Bias
Circuitry
Filter-Free Class D
Figure 32. TPA2010D1 Summing Differential Input and Single-Ended Input Signals
10.4.1.3 TPA2010D1 Summing Two Single-Ended Inputs
Four resistors and three capacitors are needed for summing single-ended input signals. The gain and corner
frequencies (fc1 and fc2) for each input source can be set independently (see Equation 13 through Equation 16,
and Figure 33). Resistor, RP, and capacitor, CP, are needed on the IN+ terminal to match the impedance on the
IN– terminal. The single-ended inputs must be driven by low impedance sources even if one of the inputs is not
outputting an AC signal.
VO
150 •À V
=2×
l p
VI1
R I1
V
VO
150 •À V
Gain 2 =
=2×
l p
VI2
R I2
V
1
CI1 =
:tN × R I1 × fC1 ;
1
CI2 =
:tN × R I2 × fC2 ;
CP = CI1 + CI2
R I1 × R I2
RP =
:R I1 + R I2 ;
Gain 1 =
(13)
(14)
(15)
(16)
(17)
(18)
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Device Functional Modes (continued)
Single-Ended
Input 1
Single-Ended
Input 2
CI1 R
I1
To Battery
CI2 R
I2
Internal
Oscillator
CS
IN_
RP
VDD
PWM
HBridge
VO+
VO-
+
IN+
CP
GND
SHUTDOWN
Bias
Circuitry
Filter-Free Class D
Figure 33. TPA2010D1 Summing Two Single-Ended Inputs
10.4.2 Shutdown Mode
The TPA2010D1 can be put in shutdown mode when asserting SHUTDOWN pin to a logic LOW. While in
shutdown mode, the device output stage is turned off and set into high impedance, making the current
consumption very low. The device exits shutdown mode when a HIGH logic level is applied to the SHUTDOWN
pin.
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11 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
11.1 Application Information
These typical connection diagrams highlight the required external components and system level connections for
proper operation of the device in several popular use cases. Each of these configurations can be created using
the Evaluation Modules (EVMs) for the device. These flexible modules allow full evaluation of the device in the
most common modes of operation. Any design variation can be supported by TI through schematic and layout
reviews. Visit TI.com for design assistance and join the audio amplifier discussion forum for additional
information.
11.2 Typical Applications
Figure 34 shows the TPA2010D1 typical schematic with differential inputs and Figure 38 shows the TPA2010D1
with differential inputs and input capacitors, and Figure 39 shows the TPA2010D1 with single-ended inputs.
Differential inputs should be used whenever possible because the single-ended inputs are more susceptible to
noise.
11.2.1 TPA200110D1 With Differential Input
Use the values listed in Table 1 as the design requirements. The TPA2010D1 can be used with differential input
without input capacitors. This section describes the design considerations for this application.
To Battery
Internal
Oscillator
+
RI
-
CS
IN_
Differential
Input
VDD
PWM
HBridge
VO-
+
RI
VO+
IN+
GND
Bias
Circuitry
SHUTDOWN
TPA2010D1
Filter-Free Class D
Figure 34. TPA2010D1 with Differential Input
11.2.1.1 Design Requirements
Use the values listed in Table 1 as the design requirements.
Table 1. Design Requirements
PARAMETER
EXAMPLE VALUE
Power supply
5V
Shutdown input
Speaker
High > 2 V
Low < 0.8 V
8Ω
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11.2.1.2 Detailed Design Procedure
Table 2 lists the typical components values.
Table 2. Typical Component Values
REF DES
VALUE
EIA SIZE
MANUFACTURER
RI
150 kΩ (±0.5%)
0402
Panasonic
ERJ2RHD154V
CS
1 µF (+22%, –80%)
0402
Murata
GRP155F50J105Z
CI (1)
3.3 nF (±10%)
0201
Murata
GRP033B10J332K
(1)
PART NUMBER
CI is only needed for single-ended input or if VICM is not between 0.5 V and VDD – 0.8 V. CI = 3.3 nF
(with RI = 150 kΩ) gives a high-pass corner frequency of 321 Hz.
11.2.1.2.1 Input Resistors (RI)
The input resistors (RI) set the gain of the amplifier according to Equation 19.
Gain =
2 × 150 •À V
l p
RI
V
(19)
Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic
distortion diminish if resistor mismatch occurs. Therefore, TI recommends to use 1% tolerance resistors or better
to keep the performance optimized. Matching is more important than overall tolerance. Resistor arrays with 1%
matching can be used with a tolerance greater than 1%.
Place the input resistors very close to the TPA2010D1 to limit noise injection on the high-impedance nodes.
For optimal performance, set the gain to 2 V/V or lower. Lower gain allows the TPA2010D1 to operate at its best,
and keeps a high voltage at the input making the inputs less susceptible to noise.
11.2.1.2.2 Decoupling Capacitor (CS)
The TPA2010D1 is a high-performance class-D audio amplifier that requires adequate power supply decoupling
to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients,
spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically
1 µF, placed as close as possible to the device VDD lead works best. Placing this decoupling capacitor close to
the TPA2010D1 is very important for the efficiency of the class-D amplifier, because any resistance or
inductance in the trace between the device and the capacitor can cause a loss in efficiency. For filtering lowerfrequency noise signals, a 10 µF or greater capacitor placed near the audio power amplifier would also help, but
it is not required in most applications because of the high PSRR of this device.
11.2.1.3 Application Curves
3
2.5
PO at 10% THD
Gain = 2 V/V
f = 1 kHz
2
VDD = 5 V
PO − Output Power − W
PO − Output Power − W
2.5
2
VDD = 3.6 V
1.5
VDD = 2.5 V
1
1.5
VDD = 3.6 V
1
VDD = 2.5 V
0.5
0.5
0
0
4
8
12
16
20
24
28
32
4
RL − Load Resistance − Ω
Figure 35. Output Power versus Load Resistance
20
VDD = 5 V
PO at 1% THD
Gain = 2 V/V
f = 1 kHz
8
12
16
20
24
RL − Load Resistance − Ω
28
32
Figure 36. Output Power versus Load Resistance
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3
PO − Output Power − W
2.5
Gain = 2 V/V
f = 1 kHz
RL = 4 Ω, 10% THD
2
RL = 4 Ω, 1% THD
1.5
1
RL = 8 Ω,10% THD
0.5
0
2.5
RL = 8 Ω,1% THD
3
3.5
4
4.5
VCC − Supply Voltage − V
5
Figure 37. Output Power versus Load Resistance
11.2.2 TPA20010D1 With Differential Input and Input Capacitors
The TPA20010D1 supports differential input operation with input capacitors. This section describes the design
considerations for this application.
To Battery
CI
Differential
Input
Internal
Oscillator
RI
RI
CS
IN_
CI
VDD
PWM
HBridge
VO+
VO-
+
IN+
GND
Bias
Circuitry
SHUTDOWN
TPA2010D1
Filter-Free Class D
Figure 38. TPA2010D1 With Differential Input and Input Capacitors
11.2.2.1 Design Requirements
Refer to the Design Requirements section.
11.2.2.2 Detailed Design Procedure
Refer to the Detailed Design Procedure section.
11.2.2.2.1 Input Capacitors (CI)
The TPA2010D1 does not require input coupling capacitors if the design uses a differential source that is biased
from 0.5 V to VDD –0.8 V (shown in Figure 34). If the input signal is not biased within the recommended commonmode input range, if needing to use the input as a high pass filter (shown in Figure 38), or if using a single-ended
source (shown in Figure 39), input coupling capacitors are required.
The input capacitors and input resistors form a high-pass filter with the corner frequency, fc, determined in
Equation 20.
fC =
1
:tN × R I × CI ;
(20)
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The value of the input capacitor is important to consider as it directly affects the bass (low frequency)
performance of the circuit. Speakers in wireless phones cannot usually respond well to low frequencies, so the
corner frequency can be set to block low frequencies in this application.
Equation 21 is reconfigured to solve for the input coupling capacitance.
CI =
1
:tN × R I × B% ;
(21)
If the corner frequency is within the audio band, the capacitors should have a tolerance of ±10% or better,
because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below.
For a flat low-frequency response, use large input coupling capacitors (1 µF). However, in a GSM phone the
ground signal is fluctuating at 217 Hz, but the signal from the codec does not have the same 217 Hz fluctuation.
The difference between the two signals is amplified, sent to the speaker, and heard as a 217 Hz hum.
11.2.2.3 Application Curves
Refer to the Application Curves section.
11.2.3 TPA20010D1 with Single-Ended Input
The TPA20010D1 can be used with Single-Ended inputs, using Input capacitors. This section describes the
design considerations for this application.
To Battery
CI
Single-ended
Input
Internal
Oscillator
RI
CS
IN_
RI
VDD
PWM
HBridge
VO+
VO-
+
IN+
CI
GND
Bias
Circuitry
SHUTDOWN
TPA2010D1
Filter-Free Class D
Figure 39. TPA2010D1 with Single-Ended Input
11.2.3.1 Design Requirements
Refer to the Design Requirements section.
11.2.3.2 Detailed Design Procedure
Refer to the Detailed Design Procedure section.
11.2.3.3 Application Curves
Refer to the Application Curves section.
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12 Power Supply Recommendations
The TPA2010D1 is designed to operate from an input voltage supply range between 2.5-V and 5.5-V. Therefore,
the output voltage range of power supply should be within this range and well regulated. The current capability of
upper power should not exceed the maximum current limit of the power switch.
12.1 Power Supply Decoupling Capacitors
The TPA2010D1 requires adequate power supply decoupling to ensure a high efficiency operation with low total
harmonic distortion (THD). Place a low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1 µF,
within 2 mm of the VDD pin. This choice of capacitor and placement helps with higher frequency transients,
spikes, or digital hash on the line. In addition to the 0.1 µF ceramic capacitor, is recommended to place a 2.2 µF
to 10 µF capacitor on the VDD supply trace. This larger capacitor acts as a charge reservoir, providing energy
faster than the board supply, thus helping to prevent any drop in the supply voltage.
13 Layout
13.1 Layout Guidelines
13.2 Board Layout
In making the pad size for the DSBGA balls, TI recommends that the layout use nonsolder mask defined (NSMD)
land. With this method, the solder mask opening is made larger than the desired land area, and the opening size
is defined by the copper pad width. Figure 42 and Table 3 show the appropriate diameters for a DSBGA layout.
The TPA2010D1 evaluation module (EVM) layout is shown in the next section as a layout example.
Follow these guidelines:
• Circuit traces from NSMD defined PWB lands should be 75 µm to 100 µm wide in the exposed area inside
the solder mask opening. Wider trace widths reduce device stand off and impact reliability.
• Recommend solder paste is Type 3 or Type 4.
• Best reilability results are achieved when the PWB laminate glass transition temperature is above the
operating the range of the intended application.
• For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 µm to avoid a reduction in
thermal fatigue performance.
• Solder mask thickness should be less than 20 µm on top of the copper circuit pattern.
• Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically
etched stencils results in inferior solder paste volume control.
• Trace routing away from DSBGA device should be balanced in X and Y directions to avoid unintentional
component movement due to solder wetting forces.
13.2.1 Component Location
Place all the external components very close to the TPA2010D1. The input resistors need to be very close to the
TPA2010D1 input pins so noise does not couple on the high impedance nodes between the input resistors and
the input amplifier of the TPA2010D1. Placing the decoupling capacitor, CS, close to the TPA2010D1 is
important for the efficiency of the class-D amplifier. Any resistance or inductance in the trace between the device
and the capacitor can cause a loss in efficiency.
13.2.2 Trace Width
Recommended trace width at the solder balls is 75 µm to 100 µm to prevent solder wicking onto wider PCB
traces. Figure 40 shows the layout of the TPA2010D1 evaluation module (EVM).
For high current pins (VDD, GND VO+, and VO–) of the TPA2010D1, use 100-µm trace widths at the solder balls
and at least 500-µm PCB traces to ensure proper performance and output power for the device.
For input pins (IN–, IN+, and SHUTDOWN) of the TPA2010D1, use 75-µm to 100-µm trace widths at the solder
balls. IN– and IN+ pins need to run side-by-side to maximize common-mode noise cancellation. Placing input
resistors, RIN, as close to the TPA2010D1 as possible is recommended.
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TPA2010D1
SLOS417D – OCTOBER 2003 – REVISED NOVEMBER 2015
www.ti.com
Board Layout (continued)
75 μm
100 μm
100 μm
100 μm
375 μm
(+0, -25 μm)
275 μm
(+0, -25 μm)
100 μm
Circular Solder Mask Opening
Paste Mask (Stencil)
= Copper Pad Size
75 μm
100 μm
75 μm
Figure 40. Close Up of TPA2010D1 Land Pattern from TPA2010D1 EVM
24
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TPA2010D1
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SLOS417D – OCTOBER 2003 – REVISED NOVEMBER 2015
13.3 Layout Example
Input Resistors
placed as close as
possible to the device
IN +
OUT -
Decoupling capacitor
placed as close as
possible to the device
0.1µF
A1
A2
A3
B1
B2
B3
C1
C2
C3
TPA2010D1
IN -
OUT +
SHUTDOWN
Top Layer Ground Plane
Top Layer Traces
Pad to Top Layer Ground Plane
Via to Power Supply
Via to Bottom Layer Ground Plane
Figure 41. TPA2010D1 Layout Example
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TPA2010D1
SLOS417D – OCTOBER 2003 – REVISED NOVEMBER 2015
www.ti.com
14 Device and Documentation Support
14.1 Device Support
14.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
14.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
14.3 Trademarks
NanoFree, NanoStar, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
14.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
14.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
26
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TPA2010D1
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SLOS417D – OCTOBER 2003 – REVISED NOVEMBER 2015
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copper
Trace Width
Solder
Pad Width
Solder Mask
Opening
Copper Trace
Thickness
Solder Mask
Thickness
Figure 42. Land Pattern Dimensions
Table 3. Land Pattern Dimensions
SOLDER PAD
DEFINITIONS
COPPER PAD
SOLDER MASK
OPENING
COPPER
THICKNESS
STENCIL
OPENING
STENCIL
THICKNESS
Nonsolder mask
defined (NSMD)
275 µm
(+0.0, –25 µm)
375 µm
(+0.0, –25 µm)
1 oz max (32 µm)
275 µm × 275 µm Sq.
(rounded corners)
125 µm thick
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27
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPA2010D1YZFR
ACTIVE
DSBGA
YZF
9
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
AK0
TPA2010D1YZFT
ACTIVE
DSBGA
YZF
9
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
AK0
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
TPA2010D1YZFR
DSBGA
YZF
9
3000
180.0
8.4
TPA2010D1YZFT
DSBGA
YZF
9
250
180.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1.65
1.65
0.81
4.0
8.0
Q1
1.65
1.65
0.81
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPA2010D1YZFR
DSBGA
YZF
9
3000
182.0
182.0
20.0
TPA2010D1YZFT
DSBGA
YZF
9
250
182.0
182.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YZF0009
DSBGA - 0.625 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
C
0.625 MAX
SEATING PLANE
BALL TYP
0.35
0.15
0.05 C
1 TYP
SYMM
C
1
TYP
SYMM
B
0.5
TYP
A
9X
0.015
0.35
0.25
C A B
1
2
3
0.5 TYP
4219558/A 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YZF0009
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
9X ( 0.245)
1
2
3
A
(0.5) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 40X
0.05 MAX
0.05 MIN
METAL UNDER
SOLDER MASK
( 0.245)
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
( 0.245)
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219558/A 10/2018
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZF0009
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
(R0.05) TYP
9X ( 0.25)
1
2
3
A
(0.5) TYP
SYMM
B
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 40X
4219558/A 10/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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