TPA2035D1YZFR

TPA2035D1 www.ti.com ................................................................................................................................................................................................ SLOS562 – AUGUST 2008 2.75-W FIXED GAIN MONO FILTER-FREE CLASS-D AUDIO POWER AMPLIFIER FEATURES APPLICATIONS • Maximize Battery Life and Minimize Heat – 0.5-µA Shutdown Current – 3-mA Quiescent Current – High Efficiency Class-D – 88% at 400mW at 8Ω – 80% at 100mW at 8Ω • Short Circuit Auto-recovery • Gain of 2 V/V (6dB) • Only One External Component Required – Internal Matched Input Gain and Feedback Resistors for Excellent PSRR and CMRR – Optimized PWM Output Stage Eliminates LC Output Filter – PSRR (–75 dB) and Wide Supply Voltage (2.5 V to 5.5 V) Eliminates Need for a Dedicated Voltage Regulator – Fully Differential Design Reduces RF Rectification and Eliminates Bypass Capacitor – CMRR (–69 dB)Eliminates Two Input Coupling Capacitors • Thermal and Short-Circuit Protection • Pinout Similar to the TPA2010D1 • Wafer Chip Scale Packaging (WCSP) – NanoFree™ (YZF) • 1 2 Wireless Handsets, PDAs, and other mobile devices DESCRIPTION The TPA2035D1 is a 2.75-W high efficiency filter-free class-D audio power amplifier in an approximately 1.5-mm × 1.5-mm wafer chip scale package (WCSP) that requires only one external component. The pinout is the same as the TPA2010D1 (SLOS417) except that the external gain setting input resistors required by the TPA2010D1 are integrated into the fixed gain of the TPA2035D1. Features like –75dB PSRR and improved RF-rectification immunity with a small PCB footprint (WCSP amplifier plus single decoupling cap) make the TPA2035D1 ideal for wireless handsets. A fast start-up time of 3.2 ms with minimal pop makes the TPA2035D1 ideal for PDA applications. In wireless handsets, the earpiece, speaker phone, and melody ringer can each be driven by the TPA2035D1. The TPA2035D1 has a low 27-µV noise floor, A-weighted. APPLICATION CIRCUIT VDD IN− _ Differential Input PWM 2035D1 CS ~ 2,5 mm VO − H− Bridge 9-BALL WAFER CHIP SCALE, YZF PACKAGE, (TOP VIEW OF PCB) VO + + IN+ GND SHUTDOWN ~1,7 mm TPA To Battery Internal Oscillator 0402 CS Bias Circuitry TPA2035D1 1,4 mm 1,55 mm IN+ GND A1 A2 VDD PV DD B1 B2 VO− A3 PGND B3 IN− SHUTDWN VO+ C1 C2 C3 1,4 mm 1,55 mm Note: Pin A1 is marked with a “0” . 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated TPA2035D1 SLOS562 – AUGUST 2008 ................................................................................................................................................................................................ www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TA PACKAGE (YZF) (1) –40°C to 85°C 9 balls, 1.5 mm × 1.5 mm WCSP (0.05/-0.1 mm tolerance) PART NUMBER TPA2035D1YZF SYMBOL (2) CGD For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. The YZF package is only available taped and reeled. To order add the suffix R to the end of the part number for a reel of 3000, or add the suffix T to the end of the part number for a reel of 250 (e.g. TPA2035D1YZFR). (2) ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TPA2035D1 VDD Supply voltage VI Input voltage In active mode –0.3 V to 6 V In SHUTDOWN mode –0.3 V to 7 V –0.3 V to VDD + 0.3 V Continuous total power dissipation See Dissipation Rating Table TA Operating free-air temperature –40°C to 85°C TJ Operating junction temperature –40°C to 125°C Tstg Storage temperature –65°C to 150°C ESD Electro-Static Discharge Tolerance - Human Body Model (HBM) for all pins (2) (1) 2KV Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The output pins Vo– and Vo+ are tolerant to 1.5KV HBM ESD (2) RECOMMENDED OPERATING CONDITIONS MIN VDD Supply voltage VIH High-level input voltage SHUTDOWN VIL Low-level input voltage SHUTDOWN VIC Common mode input voltage range VDD = 2.5 V, 5.5 V TA Operating free-air temperature –40 NOM MAX UNIT 2.5 5.5 V 1.3 VDD V 0 0.35 V 0.5 VDD–0.8 V 85 °C PACKAGE DISSIPATION RATINGS (1) (2) 2 PACKAGE DERATING FACTOR (1 / θJA) TA ≤ 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING YZF 4.8 mW/°C (1) 480 mW 264 mW 192 mW YZF (2) 750 mW 412 mW 300 mW 7.5 mW/°C Derating factor measured with JEDEC Low-K board; 1S0P - One signal layer and zero plane layers. Derating factor measured with JEDEC High K board; 1S2P - One signal layer and two plane layers. Please see JEDEC Standard 51-3 for Low-K board, JEDEC Standard 51-7 for High-K board, and JEDEC Standard 51-12 for using package thermal information. Please see JEDEC document page for downloadable copies: http://www.jedec.org/download/default.cfm. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA2035D1 TPA2035D1 www.ti.com ................................................................................................................................................................................................ SLOS562 – AUGUST 2008 ELECTRICAL CHARACTERISTICS TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS |VOS| Output offset voltage (measured differentially) Inputs AC grounded, VDD = 2.5 V to 5.5 V PSRR Power supply rejection ratio VDD = 2.5 V to 5.5 V MIN TYP MAX UNIT 5 25 mV dB –75 -61 VDD = 2.5 V –69 -52 VDD = 3.6 V –69 -52 VDD = 5.5 V –69 -52 CMRR Common mode rejection ratio VIC = 0.5 V to (VDD –0.8 V) |IIH| High-level input current VDD = 5.5 V, VI = 5.8 V 50 µA |IIL| Low-level input current VDD = 5.5 V, VI = –0.3 V 5 µA VDD = 5.5 V, no load I(Q) Quiescent current I(SD) Shutdown current rDS(on) Static drain-source on-state resistance f(sw) 5.7 VDD = 3.6 V, no load 3 VDD = 2.5 V, no load 2.2 3.7 mA V(SHUTDOWN)= 0.35 V, VDD = 2.5 V to 5.5 V 0.5 0.8 VDD = 2.5 V 550 VDD = 3.6 V 420 VDD = 5.0 V 350 µA mΩ Output impedance in SHUTDOWN V(SHUTDOWN)