TPA3001D1
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SLOS398E – DECEMBER 2002 – REVISED AUGUST 2010
20-W MONO CLASS-D AUDIO POWER AMPLIFIER
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FEATURES
DESCRIPTION
•
The TPA3001D1 (sometimes referred to as
TPA3001) is a 20-W monaural bridge-tied load (BTL)
class-D audio power amplifier (class-D amp) with high
efficiency, eliminating the need for heat sinks. The
TPA3001D1 can drive 4-Ω or 8-Ω speakers with only
a ferrite bead filter required to reduce EMI.
1
23
•
•
•
•
•
20 W Into 8-Ω Load From 18-V Supply (10%
THD+N)
Short-Circuit Protection (Short to VCC, Short to
GND, Short Between Outputs)
Third-Generation Modulation Technique:
– Replaces Large LC Filter With Small,
Low-Cost Ferrite Bead Filter in Most
Applications
– Improved Efficiency
– Improved SNR
Low Supply Current: 8 mA Typ at 12 V
Shutdown Control: < 1 mA Typ
Space-Saving, Thermally-Enhanced
PowerPAD™ Packaging
The amplifier also includes depop circuitry to reduce
the amount of pop at power-up and when cycling
SHUTDOWN.
The TPA3001D1 (TPA3001) is available in the 24-pin
thermally enhanced TSSOP package (PWP), which
eliminates the need for an external heat sink.
APPLICATIONS
•
•
•
The gain of the amplifier is controlled by two input
terminals, GAIN1 and GAIN0. This allows the
amplifier to be configured for a gain of 12, 18, 23.6,
or 36 dB. The differential input stage provides high
common-mode rejection and improved power-supply
rejection.
LCD Monitors/TVs
Hands-Free Car Kits
Powered Speakers
EFFICIENCY
vs
OUTPUT POWER
MAXIMUM OUTPUT POWER
vs
LOAD IMPEDANCE
90
21
8Ω
80
PO − Maximum Output Power − W
4Ω
70
Efficiency − %
60
50
40
30
20
17
15
VCC = 15 V
13
11
VCC = 12 V
9
7
10
VCC = 18 V
0
0
4
VCC = 18 V
19
8
12
PO − Output Power − W
16
20
TA = 25°C,
10% THD Maximum
5
3.6 4
5
6
7
8
ZL − Load Impedance − Ω
9
10
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2010, Texas Instruments Incorporated
TPA3001D1
SLOS398E – DECEMBER 2002 – REVISED AUGUST 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS (1)
PACKAGED DEVICES
TA
TSSOP (PWP) (2)
–40°C to 85°C
(1)
(2)
TPA3001D1PWP
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
The PWP package is available taped and reeled. To order a taped and reeled part, add the suffix R to the part number (e.g.,
TPA3001D1PWPR).
PWP PACKAGE
(TOP VIEW)
INN
INP
GAIN0
GAIN1
SHUTDOWN
PGND
VCLAMP
BSN
PVCC
OUTN
OUTN
PGND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
VREF
BYPASS
COSC
ROSC
AGND
AGND
BSP
PVCC
OUTP
OUTP
PGND
Pin Functions
PIN
NAME
NO.
AGND
18, 19
I/O
DESCRIPTION
Analog ground terminal
BSN
8
I
Bootstrap terminal for high-side gate drive of negative BTL output (connect a 0.22-mF capacitor with a 51-Ω
resistor in series from OUTN to BSN)
BSP
17
I
Bootstrap terminal for high-side gate drive of positive BTL output (connect a 0.22-mF capacitor with a 51-Ω
resistor in series from OUTP to BSP)
BYPASS
22
I
Connect 1-mF capacitor to ground for BYPASS voltage filtering
COSC
21
I
Connect a 220-pF capacitor to ground to set oscillation frequency
GAIN0
3
I
Bit 0 of gain control (see Table 1 for gain settings)
GAIN1
4
I
Bit 1 of gain control (see Table 1 for gain settings)
INN
1
I
Negative differential input
INP
2
I
Positive differential input
OUTN
10, 11
O
Negative BTL output, connect Schottky diode from PGND to OUTN for short-circuit protection
OUTP
14, 15
O
Positive BTL output, connect Schottky diode from PGND to OUTP for short-circuit protection
PGND
6, 12, 13
PVCC
9, 16
I
High-voltage power supply (for output stages)
ROSC
20
I
Connect a 120-kΩ resistor to ground to set oscillation frequency
SHUTDOWN
5
I
Shutdown terminal (negative logic), TTL compatible, 21-V compliant
VCC
24
I
Analog high-voltage power supply
VCLAMP
7
O
Connect 1-mF capacitor to ground to provide reference voltage for H-bridge gates
VREF
23
O
5-V internal regulator for control circuitry (connect a 0.1-mF to 1-mF capacitor to ground)
Thermal pad
–
–
Connect to AGND and PGND – should be star point for both grounds. Internal resistive connection to AGND.
Thermal vias on the PCB should connect this pad to a large copper area on an internal or bottom layer for the
best thermal performance. The PAD must be soldered to the PCB for mechanical reliability.
2
Power ground
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FUNCTIONAL BLOCK DIAGRAM
VREF
AGND
VREF
VCC
VCLAMP
VCC
Clamp
Reference
BSN
PVCC
+
_
Gain
Adjust
INN
Deglitch
Logic
Gate
Drive
OUTN
_
PGND
+
_
BSP
+
_
PVCC
+
Gain
Adjust
INP
+
_
_
+
Deglitch
Logic
Gate
Drive
OUTP
PGND
SD
SHUTDOWN
GAIN1
2
GAIN0
Gain
Biases
and
References
Ramp
Generator
COSC
ROSC
BYPASS
Short-Circuit
Detect
Start-Up
Protection
Logic
Thermal
VCC OK
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
Supply voltage: VCC, PVCC
–0.3 V to 21 V
≥ 3.6 Ω
Load impedance, ZL
SHUTDOWN
Input voltage
–0.3 V to VCC + 0.3 V
GAIN0, GAIN1
–0.3 V to 5.5 V
INN, INP
–0.3 V to 7 V
Continuous total power dissipation
See the Thermal Information Table
Operating free-air temperature range, TA
–40°C to 85°C
Operating junction temperature range, TJ
–40°C to 150°C
Storage temperature range, Tstg
–65°C to 150°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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THERMAL INFORMATION
TPA3001D1
THERMAL METRIC (1) (2)
qJA
Junction-to-ambient thermal resistance
qJCtop
Junction-to-case (top) thermal resistance
qJB
Junction-to-board thermal resistance
15.2
yJT
Junction-to-top characterization parameter
0.9
yJB
Junction-to-board characterization parameter
8.4
qJCbot
Junction-to-case (bottom) thermal resistance
1.2
(1)
(2)
UNITS
PWP (24 Pins)
36.2
32
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
RECOMMENDED OPERATING CONDITIONS
ZL ≥ 3.6 Ω
Supply voltage, VCC, PVCC
(1)
Load impedance, ZL
MAX
8
18
UNIT
V
Ω
3.6
High-level input voltage, VIH
GAIN0, GAIN1, SHUTDOWN
Low-level input voltage, VIL
GAIN0, GAIN1, SHUTDOWN
Operating free-air temperature, TA
(1)
MIN
2
V
–40
0.8
V
85
°C
The TPA3001D1 must not be used with any speaker or load (including speaker with output filter) that could vary below 3.6 Ω over the
audio frequency band.
ELECTRICAL CHARACTERISTICS
TA = 25°C, PVCC = VCC = 12 V (unless otherwise noted)
PARAMETERS
TEST CONDITIONS
MIN
TYP MAX UNIT
|VOS|
Output offset voltage (measured
differentially)
VI = 0 V, AV = 12, 18, 23.6 dB
50
PSRR
Power supply rejection ratio
PVCC = 11.5 V to 12.5 V
|IIH|
High-level input current
PVCC = 12 V, VI = PVCC
1
|IIL|
Low-level input current
PVCC = 12 V, VI = 0 V
1
mA
15
mA
VI = 0 V, AV = 36 dB
100
–73
SHUTDOWN = 2 V, no load
Supply current
SHUTDOWN = VCC, VCC = 18 V, PO = 20 W,
RL = 8 Ω
ICC(SD)
Supply current, shutdown mode
SHUTDOWN = 0.8 V
fs
Switching frequency
ROSC = 120 kΩ, COSC = 220 pF
rds(on)
Output transistor on resistance (total)
IO = 1 A, TJ = 25°C
G
Gain
dB
8
ICC
mV
1.3
mA
A
1
2
250
mA
kHz
0.2
0.3
0.7
Ω
GAIN1 = 0.8 V, GAIN0 = 0.8 V
10.9
12
12.8
dB
GAIN1 = 0.8 V, GAIN0 = 2 V
17.1
18
18.7
dB
GAIN1 = 2 V, GAIN0 = 0.8 V
22.7
23.6
24.3
dB
GAIN1 = 2 V, GAIN0 = 2 V
34.9
36
36.7
dB
OPERATING CHARACTERISTICS
PVCC = VCC = 12 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Continuous output power at 10%
THD+N
f = 1 kHz, RL = 4 Ω
f = 1 kHz, RL = 8 Ω
9
Continuous output power at 1%
THD+N
f = 1 kHz, RL = 4 Ω
10.3
f = 1 kHz, RL = 8 Ω
7.2
THD+N
Total harmonic distortion plus noise
PO = 10 W, RL = 4 Ω, f = 20 Hz to 20 kHz
BOM
Maximum output-power bandwidth
THD = 1%
PO
4
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MAX
UNIT
12.8
W
0.2%
20
kHz
Copyright © 2002–2010, Texas Instruments Incorporated
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OPERATING CHARACTERISTICS (continued)
PVCC = VCC = 12 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
kSVR
Supply ripple rejection ratio
f = 1 kHz, C(BYPASS) = 1 mF
SNR
Signal-to-noise ratio
PO = 10 W, RL = 4 Ω
95
dB
C(BYPASS) = 1 mF, f = 20 Hz to 22 kHz, no weighting
filter used, gain = 12 dB
86
mV(rms)
Vn
–70
Noise output voltage
C(BYPASS) = 1 mF, f = 20 Hz to 22 kHz, A-weighted
filter, gain = 12 dB
ZI
Input impedance
See Table 1.
dB
–81
dBV
66
mV(rms)
–84
dBV
> 23
kΩ
OPERATING CHARACTERISTICS
PVCC = VCC = 18 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
f = 1 kHz, RL = 4 Ω
Output power at 10% THD+N
PO
Output power at 1% THD+N
20
f = 1 kHz, RL = 4 Ω
10.3
f = 1 kHz, RL = 8 Ω
BOM
Maximum output-power bandwidth
THD = 1%
kSVR
Supply ripple rejection ratio
SNR
Signal-to-noise ratio
PO = 2 W, RL = 8Ω, f = 20 Hz to 20 kHz
0.3%
20
kHz
f = 1 kHz, CBYPASS = 1 mF
–70
dB
PO = 15 W, RL = 8 Ω
102
dB
86
mV(rms)
Noise output voltage
C(BYPASS) = 1 mF, f = 20 Hz to 22 kHz, A-weighted
filter, gain = 12 dB
Input impedance
W
1%
C(BYPASS) = 1 mF, f = 20 Hz to 20 kHz, no weighting
filter used, gain = 12 dB
ZI
UNIT
16
PO = 15 W, RL = 8Ω, f = 20 Hz to 20 kHz
Total harmonic distortion plus noise
MAX
12.8
f = 1 kHz, RL = 8 Ω
THD+N
Vn
TYP
See Table 1.
–81
dBV
66
mV(rms)
84
dBV
>23
kΩ
SPACER
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Efficiency
vs Output power
PO
Maximum output power
vs Load impedance
ICC
Supply current
ICC(SD)
Shutdown current
THD+N
Total harmonic distortion + noise
kSVR
Supply voltage rejection ratio
vs Supply voltage
vs Output power
vs Frequency
Gain and phase
CMRR
Common-mode rejection ratio
VIO
Input offset voltage
1
2, 3, 4
5
6
7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
17, 18
19, 20, 21, 22, 23, 24, 25
26
vs Frequency
27
28
vs Common-mode input voltage
29
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EFFICIENCY
vs
OUTPUT POWER
MAXIMUM OUTPUT POWER
vs
LOAD IMPEDANCE
21
90
8Ω
80
PO − Maximum Output Power − W
70
Efficiency − %
60
50
40
30
20
17
15
VCC = 15 V
13
11
VCC = 12 V
9
7
10
VCC = 12 V
0
0
2
4
6
8
VCC = 18 V
19
4Ω
10
12
TA = 25°C,
10% THD Maximum
5
3.6 4
14
5
PO − Output Power − W
Figure 1.
Figure 2.
MAXIMUM OUTPUT POWER
vs
LOAD IMPEDANCE
MAXIMUM OUTPUT POWER
vs
LOAD IMPEDANCE
21
10
TA = 60°C
19
19
VCC = 18 V
PO − Maximum Output Power − W
PO − Maximum Output Power − W
9
21
TA = 45°C
17
15
VCC = 15 V
13
11
VCC = 12 V
9
7
5
3.6 4
VCC = 18 V
17
15
13
VCC = 15 V
11
9
VCC = 12 V
7
5
6
7
8
ZL − Load Impedance − Ω
9
10
5
3.6 4
Figure 3.
6
6
7
8
ZL − Load Impedance − Ω
5
6
7
8
ZL − Load Impedance − Ω
9
10
Figure 4.
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SUPPLY CURRENT
vs
SUPPLY VOLTAGE
SHUTDOWN CURRENT
vs
SUPPLY VOLTAGE
5
11
ICC(SD) − Shutdown Current − µA
SHUTDOWN = 0.8 V
ICC − Supply Current − mA
10
9
8
7
4
3
2
1
0
6
8
10
12
14
16
8
18
10
14
16
Figure 5.
Figure 6.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
18
10
THD+N − Total Harmonic Distortion + Noise − %
10
THD+N − Total Harmonic Distortion + Noise − %
12
VCC − Supply Voltage − V
VCC − Supply Voltage − V
VCC = 18 V
RL = 8 Ω
Gain = 12 dB
1
1 kHz
0.1
20 kHz
0. 01
20 Hz
VCC = 18 V
RL = 8 Ω
Gain = 36 dB
1
1 kHz
20 kHz
0.1
20 Hz
0.01
0.001
0
5
10
15
20
0
PO − Output Power − W
5
10
15
20
PO − Output Power − W
Figure 7.
Figure 8.
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TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
VCC = 15 V
RL = 8 Ω
Gain = 12 dB
1
1 kHz
20 kHz
20 Hz
0.1
0. 01
0.001
VCC = 15 V
RL = 8 Ω
Gain = 36 dB
1
20 kHz
1 kHz
0.01
0
5
10
15
20
0
5
PO − Output Power − W
15
Figure 9.
Figure 10.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
20
10
VCC = 15 V
RL = 4 Ω
Gain = 12 dB
1
1 kHz
0.1
20 Hz
20 kHz
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
PO − Output Power − W
10
VCC = 15 V
RL = 4 Ω
Gain = 36 dB
1
1 kHz
0.1
20 Hz
20 kHz
0.01
0.01
0
5
10
0
5
10
PO − Output Power − W
PO − Output Power − W
Figure 11.
8
20 Hz
0.1
Figure 12.
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TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
VCC = 12 V
RL = 8 Ω
Gain = 12 dB
1
1 kHz
20 kHz
20 Hz
0.1
0. 01
VCC = 12 V
RL = 8 Ω
Gain = 36 dB
1
1 kHz
20 kHz
20 Hz
0.1
0.01
0.001
0
5
10
0
15
5
15
Figure 13.
Figure 14.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
10
VCC = 12 V
RL = 4 Ω
Gain = 12 dB
1
1 kHz
0.1
20 Hz
20 kHz
0. 01
0.001
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
PO − Output Power − W
PO − Output Power − W
VCC = 12 V
RL = 4 Ω
Gain = 36 dB
1
1 kHz
0.1
20 kHz
20 Hz
0.01
0
5
10
0
PO − Output Power − W
5
10
PO − Output Power − W
Figure 15.
Figure 16.
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TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
VCC = 8 V
RL = 4 Ω
Gain = 12 dB
1
1 kHz
0.1
20 Hz
20 kHz
0.01
VCC = 8 V
RL = 4 Ω
Gain = 36 dB
1
1 kHz
0.1
20 kHz
20 Hz
0.01
0
2
4
6
0
2
PO − Output Power − W
Figure 18.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
1
VCC = 18 V
RL = 8 Ω
PO = 10 W
PO = 500 mW
0.1
PO = 2 W
0.01
100
1k
10k 20k
VCC = 15 V
RL = 8 Ω
PO = 10 W
0.1
PO = 500 mW
0.01
PO = 2 W
0.001
20
f − Frequency − Hz
100
1k
10k 20k
f − Frequency − Hz
Figure 19.
10
6
Figure 17.
1
0.001
20
4
PO − Output Power − W
Figure 20.
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TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
1
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
1
VCC = 15 V
RL = 4 Ω
PO = 10 W
0.1
PO = 500 mW
0.01
0.001
20
PO = 2 W
100
1k
VCC = 12 V
RL = 8 Ω
PO = 5 W
PO = 250 mW
0.1
0.01
PO = 1 W
0.001
20
10k 20k
100
f − Frequency − Hz
Figure 22.
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
VCC = 12 V
RL = 4 Ω
PO = 2 W
PO = 500 mW
0.01
PO = 7.5 W
0.001
20
10k 20k
Figure 21.
1
0.1
1k
f − Frequency − Hz
100
1k
10k 20k
VCC = 8 V
RL = 8 Ω
PO = 3 W
1
PO = 250 mW
0.1
PO = 1 W
0.01
0.001
20
f − Frequency − Hz
100
1k
10k 20k
f − Frequency − Hz
Figure 23.
Figure 24.
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TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
SUPPLY VOLTAGE REJECTION RATIO
vs
FREQUENCY
THD+N − Total Harmonic Distortion + Noise − %
10
−50
kSVR − Supply Voltage Rejection Ratio − dB
VCC = 8 V
RL = 4 Ω
PO = 5 W
1
PO = 1 W
0.1
PO = 250 mW
0.01
0.001
20
100
−60
VCC = 8 V
−70
VDD = 15 V
−80
−90
20
10k 20k
1k
C(Bypass) = 1 µF
RL = 8 Ω
100
Figure 26.
GAIN AND PHASE
vs
FREQUENCY
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
30
20
12
10
0
10
−20
Phase
6
−30
−40
4
−50
−60
VCC = 8 V
RL = 8 Ω
−70
0
100
1k
10k
−80
100k
Phase − °
Gain − dB
−10
8
VCC = 8 V to 18 V
RL = 8 Ω
−41
−42
−43
−44
−45
−46
20
f − Frequency − Hz
100
1k
10k 20k
f − Frequency − Hz
Figure 27.
12
30k
−40
CMRR − Common-Mode Rejection Ratio − dB
Gain
20
10k
Figure 25.
14
2
1k
f − Frequency − Hz
f − Frequency − Hz
Figure 28.
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INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
6
VIO − Input Offset Voltage − mV
5
VCC = 8 V to 18 V
4
3
2
1
0
−1
−2
−3
−4
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VIC − Common-Mode Input Voltage − V
Figure 29.
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APPLICATION INFORMATION
APPLICATION CIRCUIT
U1
TPA3001D1
C1
IN–
0.47 µF
1
2
IN+
C2
0.47 µF
3
GAIN SELECT
4
GAIN SELECT
5
SHUTDOWN
CONTROL
6
7
C10
1 µF
VCC
R2
C8
0.22 µF
51 Ω
8
9
10
C7
10 µF
C5
1 µF
11
12
VCC
INN
VCC
INP
VREF
GAIN0
BYPASS
GAIN1
COSC
23
C3
1 µF
22
21
ROSC
PGND
AGND
C4
1 µF
C11
1 µF
C12
220 pF R1
20
SHUTDOWN
120 kΩ
19
18
VCLAMP
AGND
BSN
BSP
PVCC
PVCC
OUTN
OUTP
OUTN
OUTP
PGND
PGND
D2
24
17
R3
16
51 Ω
C9
0.22 µF
15
VCC
C6
1 µF
14
13
D1
PowerPAD
L2
(Ferrite
Bead)
L1
(Ferrite
Bead)
C15
1 nF
C14
1 nF
L1, L2: Fair-Rite, Part Number 2512067007Y3
D1, D2: Diodes, Inc., Part Number B130
Figure 30. Typical Application Circuit
CLASS-D OPERATION
This section focuses on the class-D operation of the TPA3001D1.
TRADITIONAL CLASS-D MODULATION SCHEME
The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output
where each output is 180 degrees out of phase and changes from ground to the supply voltage, VCC. Therefore,
the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields 0
V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in
Figure 31. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high,
causing high loss, thus causing a high supply current.
14
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OUTP
OUTN
+12 V
Differential Voltage
Across Load
0V
–12 V
Current
Figure 31. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms Into an
Inductive Load With No Input
TPA3001D1 MODULATION SCHEME
The TPA3001D1 uses a modulation scheme that still has each output switching from ground to VCC. However,
OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater than 50%
and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and OUTN is
greater than 50% for negative output voltages. The voltage across the load is 0 V throughout most of the
switching period, greatly reducing the switching current, which reduces any I2R losses in the load. (See
Figure 32.)
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OUTP
OUTN
Differential
Voltage
Across
Load
Output = 0 V
+12 V
0V
–12 V
Current
OUTP
OUTN
Differential
Voltage
Output > 0 V
+12 V
0V
Across
Load
–12 V
Current
Figure 32. The TPA3001D1 Output Voltage and Current Waveforms Into an Inductive Load
MAXIMUM ALLOWABLE OUTPUT POWER (SAFE OPERATING AREA)
The TPA3001D1 can drive load impedances as low as 3.6 Ω from power supply voltages ranging from 8 V to
18 V. To prevent device failure, however, the output power of the TPA3001D1 must be limited. Figure 33 shows
the maximum allowable output power versus load impedance for three power-supply voltages at an ambient
temperature of 25°C. (For ambient temperatures of 45°C and 60°C, see Figure 3 and Figure 4.)
16
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21
VCC = 18 V
PO − Maximum Output Power − W
19
17
15
VCC = 15 V
13
11
VCC = 12 V
9
7
TA = 25°C,
10% THD Maximum
5
3.6 4
5
6
7
8
ZL − Load Impedance − Ω
9
10
Figure 33. Output Power
DRIVING A LOW-IMPEDANCE LOAD FROM A HIGH POWER-SUPPLY VOLTAGE
When driving low-impedance loads (e.g., a 4-Ω speaker), the output power can be limited by reducing the
maximum audio input signal level or by reducing the gain of the TPA3001D1. The maximum input voltage may
be calculated with Equation 1.
Vin(pp),max =
8PO(avg),max ´ ZL
AV
(1)
where
PO(avg),max = maximum continuous output power (W)
ZL = load impedance (Ω)
æ G(dB) ö
A V = voltage gain (V/V) = ç
÷
è 20 ø
For example, consider an application in which the TPA3001D1 drives a 4-Ω speaker from an 18-V power supply.
The gain is selected to be 18 dB. The maximum allowable output power for a 4-Ω load impedance is 12.8 W.
From Equation 1, the input voltage must not exceed 2.54 Vpp.
In this same example, however, if the maximum output voltage of audio signal source is 5 Vpp, then the gain of
the TPA3001D1 should be reduced to 12 dB to eliminate the need for limiting the input signal.
The input voltage may be limited using a variety of methods, depending on what is known about the audio signal
source. If the maximum output voltage of the source is known, a resistive voltage divider in conjunction with
proper TPA3001D1 gain selection may be used to prevent distortion. If the maximum audio source voltage is
unknown, diodes may be used to clamp the input voltage, at the cost of distortion when the input signal level
exceeds the required clamping voltage.
DRIVING THE OUTPUT INTO CLIPPING
The output of the TPA3001D1 may be driven into clipping to attain a higher output power than is possible with no
distortion. Clipping is typically quantified by a THD measurement of 10%. The amount of additional power into
the load may be calculated with Equation 2.
P O(10% THD) + P O(1% THD)
1.25
(2)
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For example, consider an application in which the TPA3001D1 drives an 8-Ω speaker from an 18-V power
supply. The maximum output power with no distortion (less than 1% THD) is 16 W, which corresponds to a
maximum peak output voltage of 16 V. For the same output voltage level driven into clipping (10% THD), the
output power is increased to 20 W.
OUTPUT FILTER CONSIDERATIONS
A ferrite bead filter (shown in Figure 34) should be used in order to pass FCC and/or CE radiated emissions
specifications and if a frequency-sensitive circuit operating higher than 1 MHz is nearby. The ferrite filter reduces
EMI around 1 MHz and higher (FCC and CE only test radiated emissions greater than 30 MHz). When selecting
a ferrite bead, choose one with high impedance at high frequencies, but very low impedance at low frequencies.
Use an additional LC output filter if there are low frequency (
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