TPA3117D2
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SLOS672 – OCTOBER 2010
15-W Filter-Free Stereo Class-D Audio Power Amplifier with SpeakerGuard™
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FEATURES
APPLICATIONS
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1
2
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•
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15-W/ch into 8Ω Loads at 10% THD+N From a
16V Supply
10-W/ch into 8Ω Loads at 10% THD+N From a
13V Supply
90% Efficient Class-D Operation Eliminates
Need for Heat Sinks
Wide Supply Voltage Range Allows Operation
from 8V to 26V
Filter-Free Operation
SpeakerGuard™ Speaker Protection Includes
Adjustable Power Limiter
Excellent THD+N / Pop-Free Performance
Four Selectable, Fixed Gain Settings
Differential Inputs
Selectable Switching Frequency (290kHz or
390kHz) Allows Multiple Devices to be Used in
One System
Integrated 5V Regulator With up to 30 mA of
Output Current for Powering External Data
Converters
5mm x 5mm QFN Packaging
Televisions
Consumer Audio Equipment
All-in-One Computers
DESCRIPTION
The TPA3117D2 is a 15W (per channel) efficient,
Class-D audio power amplifier for driving bridged-tied
stereo speakers. Advanced EMI Suppression
Technology enables the use of inexpensive ferrite
bead filters at the outputs while meeting EMC
requirements. SpeakerGuard™ speaker protection
circuitry includes an adjustable power limiter. The
adjustable power limiter allows the user to set a
"virtual" voltage rail lower than the chip supply to limit
the amount of current through the speaker.
The TPA3117D2 can drive stereo speakers as low as
4Ω. The high efficiency of the TPA3117D2, 90%,
eliminates the need for an external heat sink when
playing music.
The outputs are also fully protected against shorts to
GND, VCC, and output-to-output. The short-circuit
protection and thermal protection includes an
auto-recovery feature.
SPACER
1mF
Audio
Source
OUTL+
LINP
OUTL-
LINN
OUTR+
RINP
OUTR-
TPA3117D2
RINN
VDD
GAIN0
GAIN1
REG_OUT
2.2mF
10W
OUTPL
OUTNL
OUTPR
OUTNR
FERRITE
BEAD
FILTER
15W
8W
FERRITE
BEAD
FILTER
15W
8W
PLIMIT
PBTL
FSEL
SD
PVCC
8 to 26V
Figure 1. TPA3117D2 Simplified Application Schematic
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SpeakerGuard is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPA3117D2
SLOS672 – OCTOBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VCC
Supply voltage
AVCC, PVCC
–0.3V to 30V
SD, GAIN0, GAIN1, PBTL, FSEL (2)
VI
Interface pin voltage
–0.3V to VCC + 0.3V
PLIMIT
–0.3V to REG_OUT + 0.3V
RINN, RINP, LINN, LINP
–0.3V to 6.3V
Continuous total power dissipation
See Dissipation Rating Table
TA
Operating free-air temperature range
–40°C to 85°C
TJ
Operating junction temperature range (3)
–40°C to 150°C
Tstg
Storage temperature range
–65°C to 150°C
RL
Minimum Load Resistance
BTL: PVCC > 15V
4.8
BTL: PVCC ≤ 15V
3.2
PBTL
ESD
(1)
(2)
(3)
(4)
(5)
Electrostatic discharge
3.2
Human body model
(4)
Charged-device model
(all pins)
(5)
±2kV
(all pins)
±500V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For input voltage >6V, a series current limiting resistor of at least 100kΩ is recommended.
The TPA3117D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown.
In accordance with JEDEC Standard 22, Test Method A114-B.
In accordance with JEDEC Standard 22, Test Method C101-A
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage
PARAMETER
PVCC, AVCC
TEST CONDITIONS
8
26
VIH
High-level input voltage
SD, GAIN0, GAIN1, PBTL, FSEL
2
VIL
Low-level input voltage
SD, GAIN0, GAIN1, PBTL, FSEL
0.8
V
IIH
High-level input current
SD, GAIN0, GAIN1, PBTL, FSEL, VI = 2V, VCC = 18V
50
µA
IIL
Low-level input current
SD, GAIN0, GAIN1, PBTL, FSEL, VI = 0.8V, VCC = 18V
5
µA
TA
Operating free-air temperature
85
°C
–40
UNIT
V
V
THERMAL INFORMATION
THERMAL METRIC (1)
TPA3117D2
RHB (32 PINS)
qJA
Junction-to-ambient thermal resistance
33.7
qJC(top)
Junction-to-case(top) thermal resistance
36.3
qJB
Junction-to-board thermal resistance
9.8
yJT
Junction-to-top characterization parameter
0.6
yJB
Junction-to-board characterization parameter
9.5
qJC(bottom)
Junction-to-case(bottom) thermal resistance
3.2
(1)
2
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SLOS672 – OCTOBER 2010
DC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
| VOS |
Class-D output offset voltage (measured
differentially)
VI = 0V, Gain = 18.2dB
ICC
Quiescent supply current
ICC(SD)
Quiescent supply current in shutdown mode
rDS(on)
UNIT
15
mV
SD = 2V, no load, VCC = 26V
25
50
mA
SD = 0.8V, no load, VCC = 24V
2.5
5
mA
Gain
GAIN1 = 2V
ton
Turn-on time
SD = 2V
tOFF
Turn-off time
SD = 0.8V
High Side
240
Low side
240
GAIN0 = 0.8 V
GAIN1 = 0.8V
G
TYP MAX
1.5
VCC = 12V, IO = 500mA,
TJ = 25°C
Drain-source on-state resistance
MIN
mΩ
8
9
10
GAIN0 = 2 V
11.1
12.1
13.1
GAIN0 = 0.8 V
14.2
15.2
16.2
GAIN0 = 2 V
17.2
18.2
19.2
dB
dB
14
ms
2
ms
DC CHARACTERISTICS
TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
| VOS |
Class-D output offset voltage (measured
differentially)
VI = 0V, Gain = 18.2dB
ICC
Quiescent supply current
ICC(SD)
Quiescent supply current in shutdown mode
rDS(on)
UNIT
15
mV
SD = 2V, no load, VCC = 12V
15
35
mA
SD = 0.8V, no load, VCC = 12V
2.5
5
mA
Gain
GAIN1 = 2V
tON
Turn-on time
SD = 2V
tOFF
Turn-off time
SD = 0.8V
High Side
240
Low side
240
GAIN0 = 0.8 V
GAIN1 = 0.8V
G
TYP MAX
1.5
VCC = 12V, IO = 500mA,
TJ = 25°C
Drain-source on-state resistance
MIN
mΩ
8
9
10
GAIN0 = 2 V
11.1
12.1
13.1
GAIN0 = 0.8 V
14.2
15.2
16.2
GAIN0 = 2 V
17.2
18.2
19.2
dB
dB
14
ms
2
ms
LDO CHARACTERISTICS
TA = 25°C, VCC = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
MAX
8
12
26
UNIT
V
30
mA
Input voltage
IO
Continuous output current
VO
Output voltage
0 < IO < 30mA, 10.8V < VIN < 13.2
5
V
Line regulation
IL = 5mA, 10.8V < VIN < 13.2V
6
µV
Load regulation
IL = 0 - 30mA, VIN = 12V,
Measurement taken with an external 10Ω series
resistor
Power supply ripple rejection
VCC = 12V, IL = 20mA
PSRR
VCC
MIN
VI
10.2
f = 100Hz
92
f = 1kHz
72
mV / mA
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AC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
KSVR
Power Supply ripple rejection
200mVPP ripple at 1kHz,
Gain = 18.2dB, Inputs ac-coupled to AGND
PO
Continuous output power
THD+N
Total harmonic distortion + noise
Vn
TYP
MAX
UNIT
–70
dB
THD+N = 10%, f = 1kHz, VCC = 16V
15
W
VCC = 16V, f = 1kHz, PO = 7.5W (half-power)
0.1
%
55
µV
Output integrated noise
20Hz to 22kHz, A-weighted filter, Gain = 9dB
Crosstalk
VO = 1Vrms, Gain = 9dB, f = 1kHz
SNR
Signal-to-noise ratio
fOSC
Oscillator frequency
–85
dBV
–100
dB
Maximum output at THD+N < 1%, f = 1kHz,
Gain = 9dB, A-weighted
102
dB
FSEL = 0.8V
290
FSEL = 2V
390
Thermal trip point
Thermal hysteresis
kHz
150
°C
15
°C
AC CHARACTERISTICS
TA = 25°C, VCC = 12 V, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
KSVR
Supply ripple rejection
200mVPP ripple from 20Hz – 1kHz,
Gain = 18.2dB, Inputs ac-coupled to AGND
PO
Continuous output power
THD+N = 10%, f = 1kHz; VCC = 13V
THD+N
Total harmonic distortion + noise
RL = 8Ω, f = 1kHz, PO = 5W (half-power)
Vn
Output integrated noise
20Hz to 22kHz, A-weighted filter, Gain = 9dB
Crosstalk
Po = 1W, Gain = 9dB, f = 1kHz
SNR
Signal-to-noise ratio
fOSC
Oscillator frequency
TYP
MAX
UNIT
–70
dB
10
W
0.06
%
48
µV
–86
dBV
–100
dB
Maximum output at THD+N < 1%, f = 1kHz,
Gain = 9dB, A-weighted
102
dB
FSEL = 0.8V
290
FSEL = 2V
390
Thermal trip point
Thermal hysteresis
kHz
150
°C
15
°C
28
BSPL
29
PVCCL
NC
30
PVCCL
SD
31
NC
FSEL
32
27
26
25
LINN
1
24
OUTPL
GAIN0
2
23
PGND
3
22
OUTNL
AVCC
4
21
BSNL
AGND
5
20
BSNR
6
19
OUTNR
PLIMIT
7
18
PGND
RINN
8
17
OUTPR
9
10
11
12
13
14
15
16
NC
PBTL
NC
NC
PVCCR
PVCCR
BSPR
REG_OUT
Thermal
Pad
RINP
GAIN1
4
LINP
RHB (QFN) PACKAGE
(TOP VIEW)
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PIN FUNCTIONS
PIN
NAME
NUMBER
I/O/P
DESCRIPTION
LINN
1
I
Negative audio input for left channel. Biased at 3V.
GAIN0
2
I
Gain select least significant bit. TTL logic levels with compliance to AVCC.
GAIN1
3
I
Gain select most significant bit. TTL logic levels with compliance to AVCC.
AVCC
4
P
Analog supply
AGND
5
REG_OUT
6
O
5V regulated output. Connect 2.2µF to AGND after the series 10 Ω resistor.
PLIMIT
7
I
Power limit level adjust. Connect a resistor divider from REG_OUT to AGND to set power limit.
Connect directly to REG_OUT for no power limit.
RINN
8
I
Negative audio input for right channel. Biased at 3V.
9
I
Positive audio input for right channel. Biased at 3V.
RINP
NC
PBTL
Analog signal ground. Connect to the thermal pad.
10, 12, 13,
28, 29
Not connected
11
I
Parallel BTL mode switch (low = BTL mode, high = PBTL mode)
14, 15
P
Power supply for right channel H-bridge. Right channel and left channel power supply inputs are
connected internally. PVCCR and PVCCL must be connected together on the PCB.
BSPR
16
I
Bootstrap I/O for right channel, positive high-side FET.
OUTPR
17
O
Class-D H-bridge positive output for right channel.
PGND
18
OUTNR
19
O
Class-D H-bridge negative output for right channel.
BSNR
20
I
Bootstrap I/O for right channel, negative high-side FET.
BSNL
21
I
Bootstrap I/O for left channel, negative high-side FET.
OUTNL
22
O
Class-D H-bridge negative output for left channel.
PGND
23
OUTPL
24
O
Class-D H-bridge positive output for left channel.
BSPL
25
I
Bootstrap I/O for left channel, positive high-side FET.
26, 27
P
Power supply for left channel H-bridge. Right channel and left channel power supply inputs are
connected internally. PVCCR and PVCCL must be connected together on the PCB.
SD
30
I
Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels
with compliance to AVCC.
FSEL
31
I
Frequency select input pin (low = 300kHz, high = 400kHz)
LINP
32
I
Positive audio input for left channel. Biased at 3V.
PVCCR
PVCCL
Power ground for the H-bridges.
Power ground for the H-bridges.
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FUNCTIONAL BLOCK DIAGRAM
REG_OUT
PVCCL
BSPL
PVCCL
PBTL Select
OUTPL FB
Gate
Drive
OUTPL
OUTPL FB
LINN
Gain
Control
PGND
PWM
Logic
PLIMIT
REG_OUT
LINP
PVCCL
BSNL
PVCCL
OUTNL FB
OUTNL FB
Gate
Drive
OUTNL
SD
FSEL
GAIN0
TTL
Buffer
SC Detect
PGND
Gain
Control
GAIN1
FSEL
Ramp
Generator
Biases and
References
Startup Protection
Logic
PLIMIT
Reference
PLIMIT
Thermal
Detect
UVLO/OVLO
REG_OUT
AVDD
AVCC
PVCCR
BSNR
PVCCR
LDO
Regulator
REG_OUT
Gate
Drive
REG_OUT
OUTNR
OUTNR_FB
OUTNR FB
RINN
Gain
Control
PLIMIT
PWM
Logic
RINP
PGND
REG_OUT
PVCCR
BSPR
PVCCR
OUTPR_FB
Gate
Drive
PBTL
TTL
Buffer
PBTL
Select
OUTPR
PBTL Select
OUTPR FB
AGND
PGND
6
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TYPICAL CHARACTERISTICS
(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3117D2 EVM which is
available at ti.com.)
TOTAL HARMONIC DISTORTION
vs
FREQUENCY (BTL)
TOTAL HARMONIC DISTORTION
vs
FREQUENCY (BTL)
10
Gain = 18.2 dB
VCC = 12 V
ZL = 8 Ω + 66 µH
THD − Total Harmonic Distortion − %
THD − Total Harmonic Distortion − %
10
1
0.1
PO = 5 W
PO = 0.5 W
0.01
Gain = 18.2 dB
VCC = 18 V
ZL = 8 Ω + 66 µH
1
0.1
PO = 10 W
PO = 1 W
0.01
PO = 5 W
PO = 2.5 W
0.001
20
100
1k
10k
0.001
20
20k
100
f − Frequency − Hz
1k
10k
G001
G002
Figure 2.
Figure 3.
TOTAL HARMONIC DISTORTION
vs
FREQUENCY (BTL)
TOTAL HARMONIC DISTORTION
vs
FREQUENCY (BTL)
10
Gain = 18.2 dB
VCC = 24 V
ZL = 8 Ω + 66 µH
THD − Total Harmonic Distortion − %
THD − Total Harmonic Distortion − %
10
1
0.1
20k
f − Frequency − Hz
PO = 10 W
PO = 1 W
0.01
Gain = 18.2 dB
VCC = 12 V
ZL = 6 Ω + 47 µH
1
0.1
PO = 5 W
PO = 0.5 W
0.01
PO = 2.5 W
PO = 5 W
0.001
20
100
1k
10k
20k
0.001
20
f − Frequency − Hz
100
1k
10k
20k
f − Frequency − Hz
G003
Figure 4.
G004
Figure 5.
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TYPICAL CHARACTERISTICS (continued)
(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3117D2 EVM which is
available at ti.com.)
TOTAL HARMONIC DISTORTION
vs
FREQUENCY (BTL)
TOTAL HARMONIC DISTORTION
vs
FREQUENCY (BTL)
10
Gain = 18.2 dB
VCC = 18 V
ZL = 6 Ω + 47 µH
THD − Total Harmonic Distortion − %
THD − Total Harmonic Distortion − %
10
1
PO = 10 W
0.1
0.01
PO = 1 W
Gain = 18.2 dB
VCC = 12 V
ZL = 4 Ω + 33 µH
1
0.1
PO = 10 W
PO = 1 W
0.01
PO = 5 W
PO = 5 W
0.001
20
100
1k
10k
0.001
20
20k
100
1k
f − Frequency − Hz
10k
G005
G006
Figure 6.
Figure 7.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER (BTL)
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER (BTL)
10
Gain = 18.2 dB
VCC = 12 V
ZL = 8 Ω + 66 µH
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
1
f = 20 Hz
0.1
f = 1 kHz
0.01
f = 10 kHz
0.001
0.01
0.1
1
PO − Output Power − W
10
50
Gain = 18.2 dB
VCC = 18 V
ZL = 8 Ω + 66 µH
1
f = 1 kHz
f = 20 Hz
0.1
0.01
f = 10 kHz
0.001
0.01
G007
Figure 8.
8
20k
f − Frequency − Hz
0.1
1
PO − Output Power − W
10
50
G008
Figure 9.
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TYPICAL CHARACTERISTICS (continued)
(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3117D2 EVM which is
available at ti.com.)
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER (BTL)
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER (BTL)
10
Gain = 18.2 dB
VCC = 12 V
ZL = 6 Ω + 47 µH
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
1
f = 1 kHz
0.1
f = 20 Hz
0.01
f = 10 kHz
0.001
0.01
0.1
1
10
PO − Output Power − W
1
f = 1 kHz
f = 20 Hz
0.1
0.01
f = 10 kHz
0.001
0.01
50
0.1
1
10
PO − Output Power − W
G010
Figure 10.
Figure 11.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER (BTL)
MAXIMUM OUTPUT POWER
vs
PLIMIT VOLTAGE (BTL)
10
50
G011
16
Gain = 18.2 dB
VCC = 12 V
ZL = 4 Ω + 33 µH
PO(Max) − Maximum Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
Gain = 18.2 dB
VCC = 18 V
ZL = 6 Ω + 47 µH
1
f = 1 kHz
0.1
0.01
f = 20 Hz
14
Gain = 18.2 dB
VCC = 24 V
ZL = 8 Ω + 66 µH
12
10
8
6
4
2
f = 10 kHz
0.001
0.01
0.1
1
PO − Output Power − W
10
50
0
0.0
G012
Figure 12.
0.5
1.0
1.5
2.0
2.5
VPLIMIT − PLIMIT Voltage − V
3.0
G013
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3117D2 EVM which is
available at ti.com.)
OUTPUT POWER
vs
PLIMIT VOLTAGE (BTL)
OUTPUT POWER
vs
SUPPLY VOLTAGE (BTL)
30
35
Gain = 18.2 dB
VCC = 12 V
ZL = 4 Ω + 33 µH
25
25
PO − Output Power − W
PO − Output Power − W
30
Gain = 18.2 dB
ZL = 8 Ω + 66 µH
20
15
10
20
THD = 10%
15
THD = 1%
10
5
5
0
0
0
1
2
3
4
5
VPLIMIT − PLIMIT Voltage − V
6
6
8
10
G014
Note: Dashed Lines represent thermally limited regions.
Figure 14.
14
16
20
22
24
26
G016
EFFICIENCY
vs
OUTPUT POWER (BTL)
25
100
Gain = 18.2 dB
ZL = 4 Ω + 33 µH
VCC = 12 V
90
20
VCC = 18 V
VCC = 24 V
80
70
η − Efficiency − %
THD = 10%
15
THD = 1%
10
60
50
40
30
5
20
Gain = 18.2 dB
ZL = 8 Ω + 66 µH
10
0
0
6
8
10
12
14
16
VCC − Supply Voltage − V
Figure 16.
18
0
5
10
15
20
25
30
35
PO − Output Power − W
G017
Note: Dashed Lines represent thermally limited regions.
10
18
Note: Dashed Lines represent thermally limited regions.
Figure 15.
OUTPUT POWER
vs
SUPPLY VOLTAGE (BTL)
PO − Output Power − W
12
VCC − Supply Voltage − V
40
G018
Note: Dashed Lines represent thermally limited regions.
Figure 17.
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TYPICAL CHARACTERISTICS (continued)
(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3117D2 EVM which is
available at ti.com.)
EFFICIENCY
vs
OUTPUT POWER (BTL with LC FILTER)
EFFICIENCY
vs
OUTPUT POWER (BTL)
100
100
VCC = 12 V
90
VCC = 18 V
90
80
VCC = 24 V
η − Efficiency − %
70
60
50
40
30
60
50
40
30
20
20
Gain = 18.2 dB
LC Filter = 22 µH + 0.68 µF
RL = 8 Ω
10
Gain = 18.2 dB
ZL = 6 Ω + 47 µH
10
0
0
0
5
10
15
20
PO − Output Power − W
25
0
5
10
15
20
PO − Output Power − W
G032
25
G019
Note: Dashed Lines represent thermally limited regions.
Figure 19.
Figure 18.
EFFICIENCY
vs
OUTPUT POWER (BTL with LC FILTER)
EFFICIENCY
vs
OUTPUT POWER (BTL)
100
100
90
90
VCC = 12 V
VCC = 12 V
80
80
VCC = 18 V
70
η − Efficiency − %
70
η − Efficiency − %
VCC = 18 V
80
70
η − Efficiency − %
VCC = 12 V
60
50
40
30
60
50
40
30
20
20
Gain = 18.2 dB
LC Filter = 22 µH + 0.68 µF
RL = 6 Ω
10
Gain = 18.2 dB
ZL = 4 Ω + 33 µH
10
0
0
0
5
10
15
PO − Output Power − W
20
25
0
G033
Figure 20.
3
6
9
12
15
PO − Output Power − W
18
G020
Figure 21.
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TYPICAL CHARACTERISTICS (continued)
(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3117D2 EVM which is
available at ti.com.)
EFFICIENCY
vs
OUTPUT POWER (BTL with LC FILTER)
SUPPLY CURRENT
vs
TOTAL OUTPUT POWER (BTL)
2.6
100
2.4
90
ICC − Supply Current − A
2.0
70
η − Efficiency − %
VCC = 18 V
2.2
VCC = 12 V
80
60
50
40
30
1.8
1.6
VCC = 12 V
1.4
1.2
VCC = 24 V
1.0
0.8
0.6
20
Gain = 18.2 dB
LC Filter = 22 µH + 0.68 µF
RL = 4 Ω
10
0.4
Gain = 18.2 dB
ZL = 8 Ω + 66 µH
0.2
0.0
0
0
5
10
15
20
0
25
5
10
20
25
35
40
G021
Note: Dashed Lines represent thermally limited regions.
Figure 23.
SUPPLY CURRENT
vs
TOTAL OUTPUT POWER (BTL)
CROSSTALK
vs
FREQUENCY (BTL)
3.2
−20
Gain = 18.2 dB
ZL = 4 Ω + 33 µH
2.8
−30
−40
2.4
Gain = 18.2 dB
VCC = 12 V
VO = 1 Vrms
ZL = 8 Ω + 66 µH
−50
Crosstalk − dB
2.0
VCC = 12 V
1.6
1.2
−60
−70
−80
Right to Left
−90
−100
0.8
Left to Right
−110
0.4
−120
0.0
0
5
10
15
20
25
PO(Tot) − Total Output Power − W
30
−130
20
G022
Note: Dashed Lines represent thermally limited regions.
Figure 24.
12
30
G034
Figure 22.
ICC − Supply Current − A
15
PO(Tot) − Total Output Power − W
PO − Output Power − W
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100
1k
10k
20k
f − Frequency − Hz
G023
Figure 25.
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TYPICAL CHARACTERISTICS (continued)
(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3117D2 EVM which is
available at ti.com.)
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY (BTL)
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY (PBTL)
−20
10
Gain = 18.2 dB
Vripple = 200 mVpp
ZL = 8 Ω + 66 µH
THD+N − Total Harmonic Distortion + Noise − %
KSVR − Supply Ripple Rejection Ratio − dB
0
−40
−60
VCC = 12 V
−80
−100
−120
20
100
1k
10k
Gain = 18.2 dB
VCC = 24 V
ZL = 4 Ω + 33 µH
1
PO = 5 W
0.1
PO = 0.5 W
0.01
PO = 2.5 W
0.001
20
20k
100
1k
10k
20k
f − Frequency − Hz
f − Frequency − Hz
G025
G024
Figure 26.
Figure 27.
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER (PBTL)
OUTPUT POWER
vs
SUPPLY VOLTAGE (PBTL)
40
Gain = 18.2 dB
VCC = 24 V
ZL = 4 Ω + 33 µH
Gain = 18.2 dB
ZL = 4 Ω + 33 µH
35
30
1
PO − Output Power − W
THD+N − Total Harmonic Distortion + Noise − %
10
f = 1 kHz
0.1
25
THD = 10%
20
THD = 1%
15
10
0.01
f = 20 Hz
5
f = 10 kHz
0.001
0.01
0
0.1
1
PO − Output Power − W
Figure 28.
10
50
6
8
10
12
14
16
18
VCC − Supply Voltage − V
G026
20
G028
Note: Dashed Lines represent thermally limited regions.
Figure 29.
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TYPICAL CHARACTERISTICS (continued)
(All Measurements taken at 1 kHz, unless otherwise noted. Measurements were made using the TPA3117D2 EVM which is
available at ti.com.)
EFFICIENCY
vs
OUTPUT POWER (PBTL)
SUPPLY CURRENT
vs
OUTPUT POWER (PBTL)
2.8
100
2.4
80
2.2
η − Efficiency − %
70
ICC − Supply Current − A
VCC = 18 V
VCC = 12 V
60
50
40
30
2.0
1.8
VCC = 12 V
1.6
1.4
VCC = 18 V
1.2
1.0
0.8
0.6
20
0.4
Gain = 18.2 dB
ZL = 4 Ω + 33 µH
10
0.2
0.0
0
0
5
10
15
20
25
30
35
40
0
45
15
20
25
30
35
40
G029
Figure 31.
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY (PBTL)
SUPPLY RIPPLE REJECTION RATIO
vs
FREQUENCY (REG_OUT)
45
G030
0
PSRR – Power Supply Rejection Ratio – dB
Gain = 18.2 dB
Vripple = 200 mVpp
ZL = 8 Ω + 66 µH
−40
−60
VCC = 12 V
−80
−100
−120
20
10
Figure 30.
0
−20
5
PO − Output Power − W
PO − Output Power − W
KSVR − Supply Ripple Rejection Ratio − dB
Gain = 18.2 dB
ZL = 4 Ω + 33 µH
2.6
90
100
1k
10k
20k
–20
VCC = 12 V,
VO = 4.9 V,
IL = 20 mA
–40
–60
–80
–100
–120
20
f − Frequency − Hz
100
1k
f – Frequency – Hz
10k 20k
G031
Figure 32.
14
Figure 33.
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DEVICE INFORMATION
Gain setting via GAIN0 and GAIN1 inputs
The gain of the TPA3117D2 is set by two input terminals, GAIN0 and GAIN1.
The gains listed in Table 1 are realized by changing the taps on the input resistors inside the amplifier. This
causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings are controlled by
ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance from part-to-part
at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors.
For design purposes, the input network (discussed in the next section) should be designed assuming an input
impedance of 60 kΩ, which is the absolute minimum input impedance of the TPA3117D2. At the lower gain
settings, the input impedance could increase as high as 256 kΩ
Table 1. Gain Setting
GAIN1
GAIN0
AMPLIFIER GAIN (dB)
INPUT IMPEDANCE
(kΩ)
TYP
TYP
0
0
9
213
0
1
12.1
149
1
0
15.2
104
1
1
18.2
74
SD OPERATION
The TPA3117D2 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute
minimum level during periods of nonuse for power conservation. The SD input terminal should be held high (see
specification table for trip point) during normal operation when the amplifier is in use. Pulling SD low causes the
outputs to mute and the amplifier to enter a low-current state. Never leave SD unconnected, because amplifier
operation would be unpredictable.
For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power
supply voltage. 5V regulator (REG_OUT) is active in the shutdown state.
PLIMIT
The voltage at pin 7 can used to limit the power to levels below that which is possible based on the supply rail.
Add a resistor divider from REG_OUT to ground to set the voltage at the PLIMIT pin. An external reference may
also be used if tighter tolerance is required. Also add a 1mF capacitor from pin 7 to ground.
Vinput
PLIMIT = REG_OUT Pout = 11.8W
PLIMIT = 3V Pout = 10W
PLIMIT = 1.8V Pout = 5W
TPA3117D2 Power Limit Function
Vin=1.13VPP Freq=1kHz RLoad=8W
Figure 34. PLIMIT Circuit Operation
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The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle
to fixed maximum value. This limit can be thought of as a "virtual" voltage rail which is lower than the supply
connected to PVCC. This "virtual" rail is 4 times the voltage at the PLIMIT pin. This output voltage can be used to
calculate the maximum output power for a given maximum input voltage and speaker impedance.
POUT
ææ
ö
ö
RL
çç ç
÷ x VP ÷÷
è RL + 2 x RS ø
ø
= è
2 x RL
2
for unclipped power
(1)
Where:
RS is the total series resistance including RDS(on), and any resistance in the output filter.
RL is the load resistance.
VP is the peak amplitude of the output possible within the supply rail.
VP = 4 × PLIMIT voltage if PLIMIT < 4 × VP
POUT (10% THD) = 1.25 × POUT (unclipped)
REG_OUT Regulator
The TPA3117D2 has an integrated 5V regulator for driving external circuitry. Maximum output current is 30mA.
The regulator is always active when power is applied to the device. The SD pin does not disable operation.
Connect a series 10Ω resister followed by a 2.2µF capacitor to AGND before routing to the external circuitry.
When not used for powering external devices, a series 10Ω resistor with 2.2 µF of decoupling is still required.
PBTL Select
TPA3117D2 offers the feature of parallel BTL operation with two outputs of each channel connected directly. If
the PBTL pin (pin 11) is tied high, the positive and negative outputs of each channel (left and right) are
synchronized and in phase. To operate in this PBTL (mono) mode, apply the input signal to the RIGHT input and
place the speaker between the LEFT and RIGHT outputs. Connect the positive and negative output together for
best efficiency.
For normal BTL operation, connect the PBTL pin to local ground.
SHORT-CIRCUIT PROTECTION
TPA3117D2 has protection from overcurrent conditions caused by a short circuit on the output stage. Amplifier
outputs are switched to a Hi-Z state when the short circuit protection latch is engaged. After a typical delay of
250ms, the outputs will resume normal operation until another short occurs. It is not necessary to cycle pin SD to
restart the device operation after a short circuit event.
THERMAL PROTECTION
Thermal protection on the TPA3117D2 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature
exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not
a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15°C. The device
begins normal operation at this point with no external system interaction.
It is not necessary to cycle SD terminal to restart device operation after a short circuit event.
FSEL FUNCTIONALITY
This terminal is used to select the switching frequency of the amplifier. In applications where more than one
device is needed, configure one device with FSEL = LOW (290kHz switching) and the other device with
FSEL = HIGH (390kHz switching).
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APPLICATION INFORMATION
PVCC
100 μF
0.1 μF
1000 pF
100 kΩ
Control
System
30
31
1 mF
32
1 mF
1
2
3
PVCC
4
1 mF
5
1 mF
2.2 mF
10 W
6
10 kW
7
SD
PVCCL
FSEL
PVCCL
LINP
BSPL
LINN
OUTPL
GAIN0
PGND
GAIN1
OUTNL
BSNL
AVCC
TPA3117D2
BSNR
AGND
REG_OUT
OUTNR
PGND
PLIMIT
27
26
25
0.22 μF
FB
24
1000 pF
23
22
1000 pF
21
0.22 μF
20
0.22 μF
FB
FB
19
1000 pF
18
10 kΩ
1 mF
Audio
Source
8
9
RINN
OUTPR
RINP
BSPR
1 mF
PVCCR
11
PBTL
GND
PVCCR
17
1000 pF
16
FB
0.22 μF
15
100 μF
14
0.1 μF
1000 pF
Thermal
Pad
PVCC
Note: Pins 10, 12, 13, 28 and 29 are NC (not internally connected)
Figure 35. Stereo Class-D Amplifier with BTL Output and Single-Ended Inputs
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TPA3117D2 Modulation Scheme
The TPA3117D2 uses a modulation scheme that allows operation without the classic LC reconstruction filter
when the amp is driving an inductive load. Each output is switching from 0 volts to the supply voltage. The OUTP
and OUTN are in phase with each other with no input so that there is little or no current in the speaker. The duty
cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of
OUTP is less than 50% and OUTN is greater than 50% for negative output voltages. The voltage across the load
sits at 0V throughout most of the switching period, reducing the switching current, which reduces any I2R losses
in the load.
OUTP
OUTN
OUTP
OUTP-OUTN
No Output
0V
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
OUTP-OUTN 0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
OUTP-OUTN
0V
-PVCC
Speaker 0A
Current
Figure 36. The TPA3117D2 Output Voltage and Current Waveforms Into an Inductive Load
Ferrite Bead Filter Considerations
Using the Advanced Emissions Suppression Technology in the TPA3117D2 amplifier it is possible to design a
high efficiency Class-D audio amplifier while minimizing interference to surrounding circuits. It is also possible to
accomplish this with only a low-cost ferrite bead filter. In this case it is necessary to carefully select the ferrite
bead used in the filter.
One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite
material is alike, so it is important to select a material that is effective in the 10 to 100 MHz range which is key to
the operation of the Class D amplifier. Many of the specifications regulating consumer electronics have
emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30 MHz
and above range from appearing on the speaker wires and the power supply lines which are good antennas for
these signals. The impedance of the ferrite bead can be used along with a small capacitor with a value in the
range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best performance,
the resonant frequency of the ferrite bead/ capacitor filter should be less than 10 MHz.
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Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected
for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In
this case it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak
current the amplifier will see. If these specifications are not available, it is also possible to estimate the bead
current handling capability by measuring the resonant frequency of the filter output at low power and at maximum
power. A change of resonant frequency of less than fifty percent under this condition is desirable. Examples of
ferrite beads which have been tested and work well with the TPA3117D2 include 28L0138-80R-10 and
HI1812V101R-10 from Steward and the 742792510 from Wurth Electronics.
A high quality ceramic capacitor (x5R or better) is also needed for the ferrite bead filter. A low ESR capacitor with
good temperature and voltage characteristics will work best.
Additional EMC improvements may be obtained by adding snubber networks from each of the class D outputs to
ground. Suggested values for a simple RC series snubber network would be 10 Ω in series with a 330 pF
capacitor although design of the snubber network is specific to every application and must be designed taking
into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate
the stress on the component in the snubber network especially if the amplifer is running at high PVCC. Also,
make sure the layout of the snubber network is tight and returns directly to the PGND or the thermal pad beneath
the chip.
Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results
in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is
large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the
time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is half the period for
the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for
the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive,
whereas an LC filter is almost purely reactive.
The TPA3117D2 modulation scheme has little loss in the load without a filter because the pulses are short and
the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen, making the
ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most
applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
When to Use an Output Filter for EMI Suppression
The TPA3117D2 has been tested with a simple ferrite bead filter for a variety of applications including long
speaker wires up to 125 cm and high power. The TPA3117D2 EVM passes FCC Class B specifications under
these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet
application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency.
There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These
circumstances might occur if there are nearby circuits which are sensitive to noise. In these cases a classic
second order Butterworth filter similar to those shown in the figures below can be used.
Some systems have little power supply decoupling from the AC line but are also subject to line conducted
interference (LCI) regulations. These include systems powered by "wall warts" and "power bricks." In these
cases, an LC reconstruction filter can be the lowest cost means to pass LCI tests. Common mode chokes using
low frequency ferrite material can also be effective at preventing line conducted interference.
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33 mH
OUTP
L1
C2
1 mF
33 mH
OUTN
L2
C3
1 mF
Figure 37. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω
15 mH
OUTP
L1
C2
2.2 mF
15 mH
OUTN
L2
C3
2.2 mF
Figure 38. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 4 Ω
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 39. Typical Ferrite Chip Bead Filter (Chip Bead Example: )
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INPUT RESISTANCE
Changing the gain setting can vary the input resistance of the amplifier from its smallest value, ±20%, to the
largest value, ±20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or cutoff
frequency may change when changing gain steps.
Zf
Ci
IN
Input
Signal
Zi
The -3-dB frequency can be calculated using Equation 2. Use the ZI values given in Table 1.
f =
1
2p Zi Ci
(2)
INPUT CAPACITOR, CI
In the typical application, an input capacitor (CI) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, CI and the input impedance of the amplifier (ZI) form a
high-pass filter with the corner frequency determined in Equation 3.
-3 dB
fc =
1
2p Zi Ci
fc
(3)
The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider
the example where ZI is 60 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 3 is
reconfigured as Equation 4.
Ci =
1
2p Zi fc
(4)
In this example, CI is 0.13 µF; so, one would likely choose a value of 0.15 mF as this value is commonly used. If
the gain is known and is constant, use ZI from Table 1 to calculate CI. A further consideration for this capacitor is
the leakage path from the input source through the input network (CI) and the feedback network to the load. This
leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially
in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When
polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most
applications as the dc level there is held at 3 V, which is likely higher than the source dc level. Note that it is
important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset
voltages and it is important to ensure that boards are cleaned properly.
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POWER SUPPLY DECOUPLING, CS
The TPA3117D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. Optimum decoupling is
achieved by using a network of capacitors of different types that target specific types of noise on the power
supply leads. For higher frequency transients due to parasitic circuit elements such as bond wire and copper
trace inductances as well as lead frame capacitance, a good quality low equivalent-series-resistance (ESR)
ceramic capacitor of value between 220 pF and 1000 pF works well. This capacitor should be placed as close to
the device PVCC pins and system ground (either PGND pins or PowerPad) as possible. For mid-frequency noise
due to filter resonances or PWM switching transients as well as digital hash on the line, another good quality
capacitor typically 0.1 mF to 1 µF placed as close as possible to the device PVCC leads works best For filtering
lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 mF or greater placed near the
audio power amplifier is recommended. The 220 mF capacitor also serves as a local storage capacitor for
supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the power
to the output transistors, so a 220 µF or larger capacitor should be placed on each PVCC terminal. A 10 µF
capacitor on the AVCC terminal is adequate. Also, a small decoupling resistor between AVCC and PVCC can be
used to keep high frequency class D noise from entering the linear input amplifiers.
BSN and BSP CAPACITORS
The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 0.22 mF ceramic capacitor, rated for at least 25 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 0.22 mF capacitor must be
connected from OUTPx to BSPx, and one 0.22 mF capacitor must be connected from OUTNx to BSNx. (See the
application circuit diagram in Figure 1.)
The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating
power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching
cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs
turned on.
DIFFERENTIAL INPUTS
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3117D2 with a differential source, connect the positive lead of the audio source to the INP input and
the negative lead from the audio source to the INN input. To use the TPA3117D2 with a single-ended source, ac
ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply
the audio source to either input. In a single-ended input application, the unused input should be ac grounded at
the audio source instead of at the device input for best noise performance. For good transient performance, the
impedance seen at each of the two differential inputs should be the same.
The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to
allow the input dc blocking capacitors to become completely charged during the 14 ms power-up time. If the input
capacitors are not allowed to completely charge, there will be some additional sensitivity to component matching
which can result in pop if the input components are not well matched.
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance,
the more the real capacitor behaves like an ideal capacitor.
22
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Product Folder Link(s) :TPA3117D2
TPA3117D2
www.ti.com
SLOS672 – OCTOBER 2010
PRINTED-CIRCUIT BOARD (PCB) LAYOUT
The TPA3117D2 can be used with a small, inexpensive ferrite bead output filter for most applications. However,
since the Class-D switching edges are fast, it is necessary to take care when planning the layout of the printed
circuit board. The following suggestions will help to meet EMC requirements.
• Decoupling capacitors—The high-frequency decoupling capacitors should be placed as close to the PVCC
and AVCC terminals as possible. Large (220 µF or greater) bulk power supply decoupling capacitors should
be placed near the TPA3117D2 on the PVCCL and PVCCR supplies. Local, high-frequency bypass
capacitors should be placed as close to the PVCC pins as possible. These caps can be connected to the
thermal pad directly for an excellent ground connection. Consider adding a small, good quality low ESR
ceramic capacitor between 220 pF and 1000 pF and a larger mid-frequency cap of value between 0.1mF and
1mF also of good quality to the PVCC connections at each end of the chip.
• Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to
PGND as small and tight as possible. The size of this current loop determines its effectiveness as an
antenna.
• Grounding—The AVCC (pin 4) decoupling capacitor should be grounded to analog ground (AGND). The
PVCC decoupling capacitors should connect to PGND. Analog ground and power ground should be
connected at the thermal pad, which should be used as a central ground connection or star ground for the
TPA3117D2.
• Output filter—The ferrite EMI filter (Figure 39) should be placed as close to the output terminals as possible
for the best EMI performance. The LC filter (Figure 37 and Figure 38) should be placed close to the outputs.
The capacitors used in both the ferrite and LC filters should be grounded to power ground.
• Thermal Pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal
reliability. For recommended PCB footprints, see figures at the end of this data sheet.
For an example layout, see the TPA3117D2 Evaluation Module (TPA3117D2EVM) User Manual. Both the EVM
user manual and the thermal pad application report are available on the TI Web site at http://www.ti.com.
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23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPA3117D2RHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPA3117
TPA3117D2RHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPA3117
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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