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TPA3136D2, TPA3136AD2
SLOS938F – MAY 2016 – REVISED JANUARY 2020
TPA3136D2, TPA3136AD2 10-W Inductor Free Stereo (BTL) Class-D Audio Amplifier with
Ultra Low EMI
1 Features
3 Description
•
The TPA3136D2, TPA3136AD2 device an efficient,
Class-D audio power amplifier for driving bridged-tied
stereo speakers at up to 10 W, 6 Ω, or 8 Ω (per
channel).
1
•
•
•
•
•
•
•
•
•
•
•
2 × 10 W/ch into 6-Ω loads at 10% THD+N from a
12-V supply
2 × 10 W/ch into 8-Ω loads at 10% THD+N from a
13-V supply
Up to 90% Efficient class-D operation (8 Ω)
eliminates need for heat sinks
240VAC
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA3136D2, TPA3136AD2
SLOS938F – MAY 2016 – REVISED JANUARY 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
6
7.1
7.2
7.3
7.4
7.5
7.6
7.7
6
6
6
7
7
7
8
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
9.1 Overview ................................................................. 11
9.2 Functional Block Diagram ....................................... 12
9.3 Feature Description................................................. 13
9.4 Device Functional Modes........................................ 16
10 Application and Implementation........................ 17
10.1 Application Information.......................................... 17
10.2 Typical Applications ............................................. 17
11 Power Supply Recommendations ..................... 24
11.1 Power Supply Decoupling, CS ............................. 24
12 Layout................................................................... 25
12.1 Layout Guidelines ................................................. 25
12.2 Layout Example .................................................... 26
13 Device and Documentation Support ................. 27
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
Device Support ....................................................
Documentation Support .......................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
27
27
27
27
27
27
27
14 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (December 2017) to Revision F
•
Page
Changed the Functional Block Diagram, missing and unconnected lines .......................................................................... 12
Changes from Revision D (March 2017) to Revision E
Page
•
Changed the Supply Voltage (AVCC to GND, PVCC to GND) MAX value From: 16 V To: 20 V in the Absolute
Maximum Ratings ................................................................................................................................................................... 6
•
Changed Figure 18 .............................................................................................................................................................. 17
•
Changed Figure 19 .............................................................................................................................................................. 18
Changes from Revision C (March 2017) to Revision D
Page
•
Changed text From: "channel exceeds 14% (for example, +57%, –43%)." To: "channel exceeds 24% (±10%)." in the
DC Detect section................................................................................................................................................................. 14
•
Deleted text "The inputs must remain at or above the voltage..." from the DC Detect section............................................ 14
Changes from Revision B (June 2016) to Revision C
•
Page
Added TPA3136AD2 device to data sheet............................................................................................................................. 1
Changes from Revision A (June 2016) to Revision B
Page
•
Updated Thermal Characteristics .......................................................................................................................................... 7
•
Fixed Output Power characteristic to match initial description .............................................................................................. 7
•
Fixed duplicate graph issue ................................................................................................................................................... 8
2
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SLOS938F – MAY 2016 – REVISED JANUARY 2020
Changes from Original (May 2016) to Revision A
•
Page
Changed data sheet from Product Preview to Production Data ............................................................................................ 4
Copyright © 2016–2020, Texas Instruments Incorporated
Product Folder Links: TPA3136D2 TPA3136AD2
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TPA3136D2, TPA3136AD2
SLOS938F – MAY 2016 – REVISED JANUARY 2020
www.ti.com
5 Device Comparison Table
DEVICE NAME
DESCRIPTION
TPA3110D2
15-W Filter-Free Class-D Stereo Amplifier with
SpeakerGuard™
TPA3140D2
10-W Inductor-Free Class-D Stereo Amplifier with
Ultra Low EMI and AGL
6 Pin Configuration and Functions
PWP Package
28-Pin HTSSOP
(Top View)
SD
1
28
PVCC
FA ULT
2
27
PVCC
LINP
3
26
BSPL
LINN
4
25
OUTPL
NC
5
24
GND
NC
6
23
OUTNL
AVCC
7
22
BSNL
21
BSNR
Th ermal
GND
8
GVDD
9
20
OUTNR
PLIMIT
10
19
GND
RINN
11
18
OUTPR
RINP
12
17
BSPR
NC
13
16
PVCC
PBTL
14
15
PVCC
Pad
No t to scale
Pin Functions
PIN
NAME
NUMBER
I/O/P (1)
DESCRIPTION
SD
1
I
Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels
with compliance to AVCC.
FAULT
2
O
Open drain output used to display short circuit or dc detect fault status. Voltage compliant to AVCC.
Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise, both
short circuit faults and dc detect faults must be reset by cycling PVCC.
LINP
3
I
Positive audio input for left channel. Biased at 3 V.
LINN
4
I
Negative audio input for left channel. Biased at 3 V.
5, 6, 13
I
No Connect Pin. Can be shorted to PVCC or shorted to GND or left open.
AVCC
7
P
Analog supply
GND
8
P
Analog signal ground.
NC
(1)
4
I = Input, O = Output, P = Power
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SLOS938F – MAY 2016 – REVISED JANUARY 2020
Pin Functions (continued)
PIN
NAME
NUMBER
I/O/P (1)
DESCRIPTION
GVDD
9
O
High-side FET gate drive supply. Nominal voltage is 7 V.
PLIMIT
10
I
Power Limiter Control pin
RINN
11
I
Negative audio input for right channel. Biased at 3 V.
RINP
12
I
Positive audio input for right channel. Biased at 3 V.
PBTL
14
I
Parallel BTL mode select pin. L=Stereo BTL mode, H=Mono PBTL mode
PVCC
15, 16
P
Power supply for right channel H-bridge. Right channel and left channel power supply inputs are
connected internally.
BSPR
17
I
Bootstrap I/O for right channel, positive high-side FET.
OUTPR
18
O
Class-D H-bridge positive output for right channel.
GND
19
P
Power ground for the H-bridges.
OUTNR
20
O
Class-D H-bridge negative output for right channel.
BSNR
21
I
Bootstrap I/O for right channel, negative high-side FET.
BSNL
22
I
Bootstrap I/O for left channel, negative high-side FET.
OUTNL
23
O
Class-D H-bridge negative output for left channel.
GND
24
P
Power ground for the H-bridges.
OUTPL
25
O
Class-D H-bridge positive output for left channel.
BSPL
26
I
Bootstrap I/O for left channel, positive high-side FET.
PVCC
27, 28
P
Power supply for left channel H-bridge. Right channel and left channel power supply inputs are
connected internally.
P
Connect to GND for best thermal and electrical performance.
Thermal Pad
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TPA3136D2, TPA3136AD2
SLOS938F – MAY 2016 – REVISED JANUARY 2020
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage
AVCC to GND, PVCC to GND
Input current
To any pin except supply pins
MIN
MAX
UNIT
–0.3
20
V
10
mA
–0.3
AVCC + 0.3
V
10
V/ms
6.3
V
Voltage
SD, FAULT to GND (2)
Voltage
RINN, RINP, LINN, LINP
–0.3
BTL, PVCC > 12 V
4.8
BTL, PVCC ≤ 12 V
3.2
PBTL, PVCC > 12 V
2.5
Minimum load resistance, RL
PBTL, PVCC ≤ 12 V
Ω
1.8
Continuous total power dissipation
See the Thermal Information Table
Operating free-air temperature range, TA (3)
–40
85
°C
Temperature range
–65
150
°C
Storage temperature range, Tstg
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100 kΩ resister in series
with the pins.
The TPA3136D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged device model (CDM), per JEDEC specification JESD22-C101
UNIT
±1000
(2)
V
±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN MAX
VCC
Supply voltage
PVCC, AVCC
TPA3136
VCC
Supply voltage
PVCC, AVCC
TPA3136A
VIH
High-level input voltage
VIL
Low-level input voltage
VOL
Low-level output voltage
IIH
IIL
TA
Operating free-air
temperature (1)
TJ
Operating junction
temperature (1)
(1)
6
UNIT
4.5
14.4
V
8
14.4
V
2
AVC
C
V
SD, PBTL
0.8
V
FAULT, RPULL-UP=100 k, PVCC=14.4 V
0.8
V
High-level input current
SD, PBTL, VI = 2 V, AVCC = 12 V
50
µA
Low-level input current
SD, PBTL, VI = 0.8 V, AVCC = 12 V
5
µA
–40
85
°C
-40
150
°C
SD, PBTL
The TPA3136D2, TPA3136AD2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must
be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal
protection shutdown. See TI Technical Briefs SLMA002 for more information about using the TSSOP thermal pad.
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SLOS938F – MAY 2016 – REVISED JANUARY 2020
7.4 Thermal Information
THERMAL METRIC
TPA3136D2,
TPA3136AD2
(1)
UNIT
PWP (HTSSOP)
28 PINS
RθJA
Junction-to-ambient thermal resistance
30.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
33.5
°C/W
RθJB
Junction-to-board thermal resistance
17.5
°C/W
ψJT
Junction-to-top characterization parameter
0.9
°C/W
ψJB
Junction-to-board characterization parameter
7.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
TA = 25°C, AVCC = PVCC = 12 V, RL = 6 Ω (unless otherwise noted). (1) Over operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI = 0 V, Gain = 26 dB
1.5
15
mV
35
40
mA
40
60
µA
DC CHARACTERISTICS
| VOS |
Class-D output offset voltage (measured
differentially)
ICC
Quiescent supply current
SD = 2 V, no load, 300 ohm Ferrite Bead + 1nF Output
Filter
ICC(SD)
Quiescent supply current in shutdown mode
SD = 0.8 V, no load
rDS(on)
Drain-source on-state resistance
IO = 500 mA, TJ = 25°C High Side
Excluding Metal and
Low side
Bond Wire Resistance
G
Gain
ton
Turn-on time
SD = 2 V
tOFF
Turn-off time
SD = 0.8 V
GVDD
Gate drive supply
IGVDD = 2 mA
DC detect time
VRINN = 3.1 V and VRINN = 2.9 V, or VRINN = 2.9 V and
VRINN = 3.1 V
950
ms
–65
dB
tDCDET
240
mΩ
240
25
26
27
14
2.5
6.4
6.9
dB
ms
µs
7.4
V
AC CHARACTERISTICS
PSRR
Power supply ripple rejection
200-mVPP ripple at 1 kHz,
Gain = 26 dB, Inputs ac-coupled to GND
PO
Continuous output power
THD+N = 10%, f = 1 kHz
10
W
PO
Continuous output power
THD+N = 10%, f = 1 kHz, PVCC = 13 V, RL = 8 Ω
10
W
PO
Continuous output power, PBTL (mono)
THD+N = 10%, f = 1 kHz, PVCC = 13 V, RL = 4 Ω
20
W
THD+N
Total harmonic distortion + noise
f = 1 kHz, PO = 5 W (half-power)
Vn
Output integrated noise
20 Hz to 22 kHz, A-weighted filter, Gain = 26 dB
Crosstalk
SNR
Signal-to-noise ratio
OTE
Thermal trip point
0.06%
91
µV
–81
dBV
VO = 1 Vrms, Gain = 26 dB, f = 1 kHz
–75
dB
Maximum output at THD+N < 1%, f = 1 kHz,
Gain = 26 dB, A-weighted
102
dB
150
°C
15
°C
Thermal hysteresis
(1)
Using the TPA3136D2 EVM (SLOU444), unless otherwise noted.
7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
fOSC, SS
Oscillator frequency, Spread Spectrum ON
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MIN
NOM
MAX
UNIT
255
315
355
kHz
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TPA3136D2, TPA3136AD2
SLOS938F – MAY 2016 – REVISED JANUARY 2020
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7.7 Typical Characteristics
All Measurements taken at 26dB closed loop gain, 1-kHz audio, T A= 25°C unless otherwise noted. Measurements were
made with AES17 filter using the TPA3136D2 EVM, which is available at ti.com.
10
10
1W
2.5W
5W
1W
2.5W
5W
1
THD + N (%)
THD + N (%)
1
0.1
0.1
0.01
0.01
0.001
20
50
100
200
500 1k
2k
Frequency (Hz)
5k
10k
0.001
20
20k
50
AVCC=PVCC = 12 V, Load = 6 Ω + 47 µH, 1 W, 2.5 W, 5 W
5k
10k
20k
D002
Figure 2. Total Harmonic Distortion vs Frequency (BTL)
10
10
20 Hz
1 kHz
1
THD + N (%)
THD + N (%)
500 1k
2k
Frequency (Hz)
Figure 1. Total Harmonic Distortion vs Frequency (BTL)
0.1
0.01
10m 20m
50m 100m200m 500m 1
Output Power (W)
2
5
10
1
0.1
0.01
10m 20m
20
D003
AVCC=PVCC = 12 V, Load = 6 Ω + 47 µH, 20 Hz, 1 kHz
50m 100m200m 500m 1
Output Power (W)
2
5
10
20
D004
AVCC=PVCC = 13 V, Load = 8 Ω + 66 µH, 20 Hz, 1 kHz
Figure 3. Total Harmonic Distortion + Noise vs Output
Power (BTL)
Figure 4. Total Harmonic Distortion + Noise vs Output
Power (BTL)
20
16
18
14
Power @ 10% THD + N (W)
Power @ 10% THD + N (W)
200
AVCC=PVCC = 13 V, Load = 8 Ω + 66 µH, 1 W, 2.5 W, 5 W
20 Hz
1 kHz
16
14
12
10
8
6
4
12
10
8
6
4
2
2
0
0
4
5
6
7
8
9
10 11
Supply Voltage (V)
12
13
14
15
Figure 5. Output Power vs Supply Voltage (BTL)
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4
5
6
D005
AVCC=PVCC = 4.5 V to 14.4 V, Load = 6 Ω + 47 µH
8
100
D001
7
8
9
10 11
Supply Voltage (V)
12
13
14
15
D006
AVCC=PVCC = 4.5 V to 14.4 V, Load = 8 Ω + 66 µH
Figure 6. Output Power vs Supply Voltage (BTL)
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Typical Characteristics (continued)
36
300
100
32
240
90
28
180
80
24
120
20
60
16
0
12
-60
8
-120
20
4
Gain
-180
Phase
-240
10k 20k
10
0
20
50
100
200
500 1k
Frequency
2k
5k
Efficiency (%)
70
Phase (o)
Gain (dB)
All Measurements taken at 26dB closed loop gain, 1-kHz audio, T A= 25°C unless otherwise noted. Measurements were
made with AES17 filter using the TPA3136D2 EVM, which is available at ti.com.
60
50
40
30
PVcc = 6V
PVcc = 12V
PVcc = 14.4V
0
0
2.5
5
7.5 10 12.5 15 17.5
Total Output Power (W)
D007
AVCC=PVCC = 12 V, Load = 6 Ω + 47 µH (device pins)
20
22.5
25
D008
AVCC=PVCC = 6 V, 12 V, 14.4 V, Load = 6 Ω + 47 µH
Figure 7. Gain/Phase vs Frequency (BTL)
Figure 8. Efficiency vs Output Power (BTL)
100
0
90
-10
Ch 2 to Ch1
Ch 1 to Ch2
-20
80
-30
Crosstalk (dB)
Efficiency (%)
70
60
50
40
30
-40
-50
-60
-70
-80
-90
20
PVcc = 6V
PVcc = 13V
PVcc = 14.4V
10
-100
-110
-120
20
0
0
2.5
5
7.5
10 12.5 15 17.5
Output Power (W)
20
22.5
25
AVCC=PVCC= 6 V, 13 V, 14.4 V, Load = 8 Ω + 66 µH
Figure 9. Efficiency vs Output Power (BTL)
200
500 1k
2k
Frequency (Hz)
5k
10k
20k
D010
Figure 10. Crosstalk vs Frequency (BTL)
10
5
-10
-20
-30
THD + N (%)
PVcc PSRR (dB)
100
AVCC=PVCC = 12 V, 1 W, Load = 6 Ω + 47 µH
0
-40
-50
-60
2
1
0.5
1W
2.5 W
5W
0.2
0.1
0.05
0.02
0.01
0.005
-70
-80
-90
-100
20
50
D009
50
100
200
500 1k
2k
Frequency (Hz)
5k
10k
20k
0.002
0.001
20
50
100
D011
AVCC=PVCC = 12 V, Load = 4 Ω + 33 µH
200
500 1k
2k
Frequency (Hz)
5k
10k
20k
D012
AVCC=PVCC = 13 V, Load = 4 Ω + 33 µH, 1 W, 2.5 W, 5 W
Figure 11. Supply Ripple Rejection Ratio vs Frequency
(BTL)
Figure 12. Total Harmonic Distortion + Noise vs Frequency
(PBTL)
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Typical Characteristics (continued)
All Measurements taken at 26dB closed loop gain, 1-kHz audio, T A= 25°C unless otherwise noted. Measurements were
made with AES17 filter using the TPA3136D2 EVM, which is available at ti.com.
32
10
28
Power @ 10% THD + N (W)
THD + N (%)
20 Hz
1 kHz
1
0.1
24
20
16
12
8
4
0.01
10m 20m
0
50m 100m200m 500m 1
2
Output Power (W)
5
10
20
4
5
6
7
8
9
10 11
Supply Voltage (V)
D013
AVCC=PVCC = 13 V, Load = 4 Ω + 33 µH, 20 Hz, 1 kHz
12
13
14
15
D014
AVCC=PVCC = 4.5 V to 14.4 V, Load = 4 Ω + 33 µH
Figure 13. Total Harmonic Distortion + Noise vs Output
Power (PBTL)
Figure 14. Output Power vs Supply Voltage (PBTL)
100
90
80
Efficiency (%)
70
60
50
40
30
20
PVcc = 6V
PVcc = 13V
PVcc = 14.4V
10
0
0
2.5
5
7.5 10 12.5 15 17.5
Total Output Power (W)
20
22.5
25
D015
AVCC=PVCC = 6 V, 13 V, 14.4 V, Load = 4 Ω + 33 µH
Figure 15. Efficiency vs Output Power (PBTL)
8 Parameter Measurement Information
All parameters are measured according to the conditions described in the Specifications section.
Most audio analyzers will not give correct readings of Class-D amplifiers’ performance due to their sensitivity to
out of band noise present at the amplifier output. An AES-17 pre analyzer filter is recommended to use for ClassD amplifier measurements. In absence of such filter, a 30-kHz low-pass filter (10 Ω + 47 nF) can be used to
reduce the out of band noise remaining on the amplifier outputs.
10
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SLOS938F – MAY 2016 – REVISED JANUARY 2020
9 Detailed Description
9.1 Overview
To facilitate system design, the TPA3136D2, TPA3136AD2 needs only a single power supply between 4.5 V (8V
for TPA3136AD2) and 14.4 V for operation. An internal voltage regulator provides suitable voltage levels for the
gate driver, digital, and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply,
as in the high-side gate drive, is accommodated by built-in bootstrap circuitry with integrated boot strap diodes
requiring only an external capacitor for each half-bridge.
The audio signal path, including the gate drive and output stage, is designed as identical, independent fullbridges. All decoupling capacitors should be placed as close to their associated pins as possible. In general, the
physical loop with the power supply pins, decoupling capacitors and GND return path to the device pins must be
kept as short as possible and with as little area as possible to minimize induction (see reference board
documentation for additional information).
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BSXX) to the power-stage output pin (OUTXX). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive power-supply pin (GVDD) and the bootstrap
pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential
and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching
frequencies in the range of 315 kHz, use ceramic capacitors with at least 220-nF capacitance, size 0603 or 0805,
for the bootstrap supply. These capacitors ensure sufficient energy storage, even during clipped low frequency
audio signals, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of its
ON cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. For optimal electrical performance, EMI compliance, and system reliability, each PVCC
pin should be decoupled with ceramic capacitors that are placed as close as possible to each supply pin. It is
recommended to follow the PCB layout of the TPA3136D2, TPA3136AD2 reference design. For additional
information on recommended power supply and required components, see the application diagrams in this data
sheet.
The PVCC power supply should have low output impedance and low noise. The power-supply ramp and SD
release sequence is not critical for device reliability as facilitated by the internal power-on-reset circuit, but it is
recommended to release SD after the power supply is settled for minimum turn on audible artifacts.
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9.2 Functional Block Diagram
GVDD
BSPL
PVCC
PVCC
OUTPL
FB
Gate
Drive
PBTL Select
OUTPL
OUTPL FB
LINP
PWM
Logic
PLIMIT
GND
BSNL
GVDD
LINN
PVCC
PVCC
OUTNL FB
OUTNL
FB
FAULT
SD
Gate
Drive
TTL
Buffer
OUTNL
SD Detect
GND
Spread Spectrum
Control
Ramp
Generator
DC Detect
Startup
Protection
Logic
Biases and
References
Thermal
Detect
UVLO/
OVLO
LIMITER
Reference
PLIMIT
AVCC
PVCC
PVCC
LDO
Regulator
GVDD
Gate
Drive
GVDD
OUTNR
FB
±
+
RINP
OUTNR
+
OUTNR FB
RINN
BSNR
GVDD
AVDD
±
±
+
±
+
GND
PWM
Logic
PLIMIT
BSPR
GVDD
+
PVCC
PVCC
OUTNR FB
±
Gate
Drive
PBTL Select
PBTL
OUTPR
OUTPR
FB
PBTL
Control
GND
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9.3 Feature Description
9.3.1 Fixed Analog Gain
The analog gain of the TPA3136D2, TPA3136AD2 is fixed to 26 dB.
9.3.2
SD Operation
The TPA3136D2, TPA3136AD2 device employs a shutdown mode of operation designed to reduce supply
current (ICC) to the absolute minimum level during periods of nonuse for power conservation. The SD input pin
should be held high (see specification table for trip point) during normal operation when the amplifier is in use.
Pulling SD low causes the outputs to mute and the amplifier to enter a low-current state. Never leave SD
unconnected, because amplifier operation would be unpredictable.
For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power
supply voltage.
9.3.3 PLIMIT
The PLIMIT operation will, if selected, limit the output voltage level to a voltage level below the supply rail. In this
case, the amplifier operates as if it was powered by a lower supply voltage, and thereby limiting the output power
by voltage clipping. PLIMIT threshold is set by the PLIMIT pin voltage.
Figure 16. PLIMIT Circuit Operation
The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle
to a fixed maximum value. The limit can be thought of as a "virtual" voltage rail which is lower than the supply
connected to PVCC. The "virtual" rail is approximately four times the voltage at the PLIMIT pin. The output
voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker
impedance.
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Feature Description (continued)
ææ
ö
ö
RL
çç ç
÷ ´ VP ÷÷
è RL + 2 ´ RS ø
ø
= è
2 ´ RL
POUT
2
for unclipped power
where
•
•
•
•
POUT (10%THD) = 1.25 × POUT (unclipped)
RL is the load resistance.
RS is the total series resistance including RDS(on), and output filter resistance.
VP is the peak amplitude, which is limited by "virtual" voltage rail.
(1)
9.3.4 Spread Spectrum and De-Phase Control
The TPA3136D2, TPA3136AD2 device has built-in spread spectrum control of the oscillator frequency and dephase of the PWM outputs to improve EMI performance. The spread spectrum schemes is internally fixed is
always turned on.
De-phase inverts the phase of the output PWM such that the idle output PWM waveforms of the two audio
channels are inverted. De-phase does not affect the audio signal, or its polarity.
9.3.5 GVDD Supply
The GVDD Supply is used to power the gates of the output full bridge transistors. Add a 1-μF capacitor to ground
at this pin.
9.3.6 DC Detect
The TPA3136D2, TPA3136AD2 device has circuitry which will protect the speakers from DC current which might
occur due to defective capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect
fault will be reported on the FAULT pin as a low state. The DC Detect fault will also cause the amplifier to
shutdown by changing the state of the outputs to Hi-Z.
A DC Detect Fault is issued when the output differential duty-cycle of either channel exceeds 24% (±10%) for
more than 950 msec at the same polarity. This feature protects the speaker from large DC currents or AC
currents less than 2 Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low at power-up
until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive and
negative inputs to avoid nuisance DC detect faults.
The minimum differential input voltage required to trigger the DC detect is 130 mV.
9.3.7 PBTL Select
The TPA3136D2, TPA3136AD2 device offers the feature of parallel BTL operation with two outputs of each
channel connected directly. If the PBTL (pin 14) is tied high, the positive and negative outputs of each channel
(left and right) are synchronized and in phase. To operate in this PBTL (mono) mode, tie PBTL pin to VCC and
apply the input signal to the RINP and RINN inputs and place the speaker between the LEFT and RIGHT outputs
with OUTPL connected to OUTNL and OUTPR connected to OUTNR to parallel the output half bridges for
highest power efficiency. For an example of the PBTL connection, see the schematic in the Typical Applications
section.
9.3.8 Short-Circuit Protection and Automatic Recovery Feature
The TPA3136D2, TPA3136AD2 device has protection from overcurrent conditions caused by a short circuit on
the output stage. The short circuit protection fault is reported on the FAULT pin as a low state. The amplifier
outputs are switched to a Hi-Z state when the short circuit protection latch is engaged. The latch can be cleared
by cycling the SD pin through the low state.
If automatic recovery from the short circuit protection latch is desired, connect the FAULT pin directly to the SD
pin. This allows the FAULT pin function to automatically drive the SD pin low which clears the short-circuit
protection latch.
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Feature Description (continued)
9.3.9 Thermal Protection
Thermal protection on the TPA3136D2, TPA3136AD2 device prevents damage to the device when the internal
die temperature exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die
temperature exceeds the thermal trip point, the device enters into the shutdown state and the outputs are
disabled. This is a latched fault.
Thermal protection faults are reported on the FAULT pin.
If automatic recovery from the thermal protection latch is desired, connect the FAULT pin directly to the SD pin.
This allows the FAULT pin function to automatically drive the SD pin low which clears the thermal protection
latch.
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9.4 Device Functional Modes
The TPA3136D2, TPA3136AD2 device is running in BD-modulation.
This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is
driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage.
The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the
speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages.
The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The
voltage across the load sits at 0 V throughout most of the switching period, reducing the switching current, which
reduces any I2R losses in the load.
OUTP
OUTN
No Output
OUTP- OUTN
0V
Speaker
Current
OUTP
OUTN
Positive Output
PVCC
OUTP-OUTN
0V
Speaker
Current
0A
OUTP
Negative Output
OUTN
OUTP - OUTN
0V
- PVCC
Speaker
Current
0A
Figure 17. BD Mode Modulation
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TPA3136D2, TPA3136AD2 device is designed for use in inductor free applications with limited distance wire
length) between amplifier and speakers like in TV sets, sound docks and Bluetooth speakers. The TPA3136D2,
TPA3136AD2 device can either be configured in stereo or mono mode, depending on output power conditions.
Depending on output power requirements and necessity for (speaker) load protection, the built in PLIMIT circuit
can be used to control system power, see functional description of these features.
PVCC
PVCCL
OUTPL
FB1
3.1A
C2
100 µF
C3
0.1µF
C4
1000pF
C7
1000pF
SPEAKER L+
10.2 Typical Applications
C6
1000pF
R2
68
PVCC
GND
GND
GND
6R
GND
PVCCR
GND
OUTNL
C11
LINP
IN_LEFT
1µF
C15
GND
GND
7
C1
1µF
R5
R6
39k
56k
9
C16
1µF
GND
GND
GND
AVCC
C24
RINP
PVCCL
PVCCL
16
15
PVCCR
PVCCR
PVCC
3
4
LINP
LINN
RINN
RINP
11
12
RINN
RINP
SD
1
PLIMIT
10
1µF
R9
100k
PBTL
GND
/SHUTDOWN
25
23
OUTPL
OUTNL
OUTNR
OUTPR
20
18
OUTNR
OUTPR
BSPL
26
BSNL
BSNR
LINP
LINN
RINN
OUTPL
OUTNL
GVDD
28
27
GND
1µF
C25
C13
1000pF
U1
LINN
IN_RIGHT
FB2
3.1A
GND
PVCC
1µF
SPEAKER L-
C10
1000pF
SD
BSPR
PBTL
5
6
13
NC
NC
NC
21
17
2
PGND
PGND
24
19
GND
PAD
C17
0.22µF
C18
0.22µF
C19
0.22µF
C20
0.22µF
22
FAULT
PLIMIT
14
GND
C14
1000pF
R4
68
GND
OUTNR
FB3
3.1A
C22
1000pF
FAULT
GND
C23
1000pF
R8
68
6R
GND
8
OUTPR
29
FB4
3.1A
C28
1000pF
TPA3136D2
GND
GND
GND
SPEAKER R-
C9
0.1µF
SPEAKER R+
C8
100 µF
C27
1000pF
R11
68
GND
GND
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Figure 18. Stereo Class-D Amplifier with BTL Output and Single-Ended Inputs with Spread Spectrum
Modulation
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Typical Applications (continued)
PVCC
L1
10µH
C2
100 µF
PVCC
GND
C3
0.1µF
GND
C4
1000pF
C6
0.68uF
GND
GND
GND
C9
0.1µF
GND
C10
1000pF
SPEAKER+
C8
100 µF
GND
PVCC
U1
C1
1µF
R6
39k
56k
9
C16
1µF
GND
GND
AVCC
28
27
PVCCL
PVCCL
16
15
PVCCR
PVCCR
C24
RINP
1µF
C25
PVCC
SD
LINP
LINN
11
12
RINN
RINP
1
RINN
PLIMIT
10
R9
100k
PVCC
14
GND
5
6
13
R10
100k
/SHUTDOWN
BSNL
BSNR
3
4
1µF
25
23
20
18
BSPL
GND
IN
OUTPL
OUTNL
OUTNR
OUTPR
GVDD
SD
BSPR
FAULT
PLIMIT
PBTL
NC
NC
NC
PGND
PGND
GND
PAD
4R
C17
0.47µF
26
22
SPEAKER-
7
R5
C19
0.47µF
21
17
FAULT
2
24
19
8
L2
29
10µH
TPA3136D2
GND
GND
C27
0.68uF
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 19. Stereo Class-D Amplifier with PBTL Output and Single-Ended Input with Spread Spectrum
Modulation
10.2.1 Design Requirements
10.2.1.1 PCB Material Recommendation
FR-4 Glass Epoxy material with 1 oz. (35 µm) is recommended for use with the TPA3136D2, TPA3136AD2. The
use of this material can provide for higher power output, improved thermal performance, and better EMI margin
(due to lower PCB trace inductance). It is recommended to use several GND underneath the device thermal pad
for thermal coupling to a bottom side copper GND plane for best thermal performance.
10.2.1.2 PVCC Capacitor Recommendation
The large capacitors used in conjunction with each full-bridge, are referred to as the PVCC Capacitors. These
capacitors should be selected for proper voltage margin and adequate capacitance to support the power
requirements. In practice, with a well designed system power supply, 100 μF, 16 V will support most applications
with 12-V power supply. 25-V capacitor rating is recommended for power supply voltage higher than 12 V. For
The PVCC capacitors should be low ESR type because they are used in a circuit associated with high-speed
switching.
10.2.1.3 Decoupling Capacitor Recommendations
In order to design an amplifier that has robust performance, passes regulatory requirements, and exhibits good
audio performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this
application.
The voltage of the decoupling capacitors should be selected in accordance with good design practices.
Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the
selection of the ceramic capacitors that are placed on the power supply to each full-bridge. They must withstand
the voltage overshoot of the PWM switching, the heat generated by the amplifier during high power output, and
the ripple current created by high power output. A minimum voltage rating of 16 V is required for use with a 12-V
power supply.
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Typical Applications (continued)
10.2.2 Detailed Design Procedure
A rising-edge transition on SD input allows the device to start switching. It is recommended to ramp the PVCC
voltage to its desired value before releasing SD for minimum audible artifacts.
The device is non-inverting the audio signal from input to output.
The GVDD pin is not recommended to be used as a voltage source for external circuitry.
10.2.2.1 Ferrite Bead Filter Considerations
Using the Advanced Emissions Suppression Technology in the TPA3136D2, TPA3136AD2 amplifier it is possible
to design a high efficiency Class-D audio amplifier while minimizing interference to surrounding circuits. It is also
possible to accomplish this with only a low-cost ferrite bead filter. In this case it is necessary to carefully select
the ferrite bead used in the filter.
One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite
material is alike, so it is important to select a material that is effective in the 10 to 100 MHz range which is key to
the operation of the Class-D amplifier. Many of the specifications regulating consumer electronics have
emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30-MHz
and above range from appearing on the speaker wires and the power supply lines which are good antennas for
these signals. The impedance of the ferrite bead can be used along with a small capacitor with a value in the
range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best performance,
the resonant frequency of the ferrite bead/ capacitor filter should be less than 10 MHz.
Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected
for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In
this case it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak
current the amplifier will see. If these specifications are not available, it is also possible to estimate the bead's
current handling capability by measuring the resonant frequency of the filter output at low power and at maximum
power. A change of resonant frequency of less than fifty percent under this condition is desirable. Examples of
ferrite beads which have been tested and work well with the TPA3136D2, TPA3136AD2 device include
NFZ2MSM series from Murata.
A high quality ceramic capacitor is also needed for the ferrite bead filter. A low ESR capacitor with good
temperature and voltage characteristics will work best.
Additional EMC improvements may be obtained by adding snubber networks from each of the class-D outputs to
ground. Suggested values for a simple RC series snubber network would be 68 Ω in series with a 100-pF
capacitor although design of the snubber network is specific to every application and must be designed taking
into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate
the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make
sure the layout of the snubber network is tight and returns directly to the GND or the thermal pad beneath the
chip.
10.2.2.2 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results
in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is
large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the
time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is half the period for
the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for
the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive,
whereas an LC filter is almost purely reactive.
The TPA3136D2, TPA3136AD2 modulation scheme has little loss in the load without a filter because the pulses
are short and the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen,
making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for
most applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
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Typical Applications (continued)
10.2.2.3 When to Use an Output Filter for EMI Suppression
The TPA3136D2 device has been tested with a simple ferrite bead filter for a variety of applications including
long speaker wires up to 100 cm and high power. The TPA3136D2 EVM passes FCC Class B specifications
under these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet
application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency.
There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These
circumstances might occur if there are nearby circuits which are sensitive to noise. In these cases, a classic
second order Butterworth filter similar to those shown in the following figures can be used.
Some systems have little power supply decoupling from the AC line, but are also subject to line conducted
interference (LCI) regulations. These include systems powered by "wall warts" and "power bricks." In these
cases, LC reconstruction filters can be the lowest cost means to pass LCI tests. Common mode chokes using
low frequency ferrite material can also be effective at preventing line conducted interference.
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 20. Typical Ferrite Chip Bead Filter (Chip Bead Example: NFZ2MSM series from Murata)
33 mH
OUTP
L1
C2
1 mF
33 mH
OUTN
L2
C3
1 mF
Figure 21. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8 Ω
15 mH
OUTP
L1
C2
2.2 mF
15 mH
OUTN
L2
C3
2.2 mF
Figure 22. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 6 Ω
10.2.2.4 Input Resistance
The typical input resistance of the amplifier is fixed to 30 kΩ ±20%.
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Typical Applications (continued)
Zf
Ci
IN
Input
Signal
Zi
10.2.2.5 Input Capacitor, Ci
In the typical application, an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, Ci and the input impedance of the amplifier (Zi) form a highpass filter with the corner frequency determined in Equation 2.
-3 dB
fc =
1
2p Zi Ci
fc
(2)
The value of Ci is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider
the example where Zi is 30 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 2 is
reconfigured as Equation 3.
Ci =
1
2p Zi fc
(3)
In this example, Ci is 0.27 µF; so, one would likely choose a value of 0.33 μF as this value is commonly used. A
further consideration for this capacitor is the leakage path from the input source through the input network (Ci)
and the feedback network to the load. This leakage current creates a dc offset voltage at the input to the
amplifier that reduces useful headroom. For this reason, a low-leakage tantalum or ceramic capacitor is the best
choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in
most applications as the dc level there is held at 3 V, which is likely higher than the source dc level. Note that it
is important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset
voltages and it is important to ensure that boards are cleaned properly.
10.2.2.6 BSN and BSP Capacitors
The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 0.22-μF ceramic capacitor, rated for at least 25 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 0.22-μF capacitor must be
connected from OUTPx to BSPx, and one 0.22-μF capacitor must be connected from OUTNx to BSNx. (See the
application circuit diagram in Figure 18.)
The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating
power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching
cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs
turned on.
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Typical Applications (continued)
10.2.2.7 Differential Inputs
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3136D2, TPA3136AD2 device with a differential source, connect the positive lead of the audio
source to the INP input and the negative lead from the audio source to the INN input. To use the TPA3136D2,
TPA3136AD2 with a single-ended source, ac ground the INP or INN input through a capacitor equal in value to
the input capacitor on INN or INP and apply the audio source to either input. In a single-ended input application,
the unused input should be ac grounded at the audio source instead of at the device input for best noise
performance. For good transient performance, the impedance seen at each of the two differential inputs should
be the same.
The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to
allow the input dc blocking capacitors to become completely charged during the 14-ms power-up time. If the input
capacitors are not allowed to completely charge, there is some additional sensitivity to component matching
which can result in pop if the input components are not well matched.
10.2.2.8 Using Low-ESR Capacitors
Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance,
the more the real capacitor behaves like an ideal capacitor.
22
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Typical Applications (continued)
10.2.3 Application Performance Curves
10.2.3.1 EN55013 Radiated Emissions Results
TPA3136D2 EVM, PVCC = 12 V, 8-Ω speakers, PO = 4 W
Figure 23. Radiated Emission - Horizontal
Figure 24. Radiated Emission - Vertical
10.2.3.2 EN55022 Conducted Emissions Results
TPA3136D2 EVM, PVCC = 12 V, 8-Ω speakers, PO = 4 W
EN55022 Class B
EN55022 Class B
80
80
QP readings
QP limit
60
50
40
30
20
0.15
70
Level (dBPV)
Level (dBPV)
70
QP readings
QP limit
60
50
40
30
0.3
0.5
1
2
3
5
Frequency (MHz)
10
Figure 25. Conducted Emission - Line
20 30
20
0.15
0.3
0.5
1
2
3
5
Frequency (MHz)
10
20 30
Figure 26. Conducted Emission - Neutral
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11 Power Supply Recommendations
11.1 Power Supply Decoupling, CS
The TPA3136D2, TPA3136AD2 device is a high-performance CMOS audio amplifier that requires adequate
power supply decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power
supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker.
Optimum decoupling is achieved by using a network of capacitors of different types that target specific types of
noise on the power supply leads. For higher frequency transients due to parasitic circuit elements such as bond
wire and copper trace inductances as well as lead frame capacitance, a good quality low equivalent-seriesresistance (ESR) ceramic capacitor of value between 220 pF and 1000 pF works well. This capacitor should be
placed as close to the device PVCC pins and system ground (either GND pins or thermal pad) as possible. For
mid-frequency noise due to filter resonances or PWM switching transients as well as digital hash on the line,
another good quality capacitor typically 0.1 μF to 1 µF placed as close as possible to the device PVCC leads
works best. For filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 100 μF or
greater placed near the audio power amplifier is recommended. The 100-μF capacitor also serves as a local
storage capacitor for supplying current during large signal transients on the amplifier outputs. The PVCC pins
provide the power to the output transistors, so a 100-µF or larger capacitor should be placed on each PVCC pin.
A 1-µF capacitor on the AVCC pin is adequate. Also, a small decoupling resistor between AVCC and PVCC can
be used to keep high frequency class-D noise from entering the linear input amplifiers.
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SLOS938F – MAY 2016 – REVISED JANUARY 2020
12 Layout
12.1 Layout Guidelines
The TPA3136D2, TPA3136AD2 device can be used with a small, inexpensive ferrite bead output filter for most
applications. However, since the Class-D switching edges are fast, it is necessary to take care when planning the
layout of the printed circuit board. The following suggestions will help to meet EMC requirements.
• Decoupling capacitors—The high-frequency decoupling capacitors should be placed as close to the PVCC
and AVCC pins as possible. Large (100-µF or greater) bulk power supply decoupling capacitors should be
placed near the TPA3136D2, TPA3136AD2 device on the PVCC supplies. Local, high-frequency bypass
capacitors should be placed as close to the PVCC pins as possible. These caps can be connected to the
thermal pad directly for an excellent ground connection. Consider adding a small, good quality low ESR
ceramic capacitor between 220 pF and 1000 pF and a larger mid-frequency cap of value between 0.1 μF and
1 μF also of good quality to the PVCC connections at each end of the chip.
• Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to
GND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna.
• Grounding—The AVCC (pin 14) decoupling capacitor should be connected to ground (GND). The PVCC
decoupling capacitors should connect to GND. Analog ground and power ground should be connected at the
thermal pad, which should be used as a central ground connection or star ground for the TPA3136D2,
TPA3136AD2.
• Output filter—The ferrite EMI filter (Figure 20) should be placed as close to the output pins as possible for the
best EMI performance. The capacitors used in the ferrite should be grounded to power ground.
• Thermal Pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the thermal pad and thermal land should be 6.46 mm × 2.35 mm. Six rows of
solid vias (three vias per row, 0.3302 mm or 13 mils diameter) should be equally spaced underneath the
thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom
layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See the TI Application
Report SLMA002 for more information about using the TSSOP thermal pad. For recommended PCB
footprints, see figures at the end of this data sheet.
For an example layout, see the TPA3136D2 Evaluation Module (TPA3136D2EVM) User Manual. Both the EVM
user manual and the thermal pad application report are available on the TI Web site at http://www.ti.com.
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12.2 Layout Example
100PF
100nF
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
2118
9
20
10
19
11
18
12
17
13
16
14
15
FB
1nF
1nF
0.22PF
1nF
FB
0.22PF
1PF
0.22PF
FB
1PF
1nF
0.22PF
1nF
1nF
FB
100nF
100PF
Top Layer Ground and Thermal Pad
Via to Bottom Ground Plane
Pad to Top Layer Ground Pour
Top Layer Signal Traces
Figure 27. BTL Layout Example
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SLOS938F – MAY 2016 – REVISED JANUARY 2020
13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Documentation Support
13.2.1 Related Documentation
PowerPAD™ Thermally Enhanced Package Application Report (SLMA002)
13.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 1. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPA3136D2
Click here
Click here
Click here
Click here
Click here
TPA3136AD2
Click here
Click here
Click here
Click here
Click here
13.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.6 Trademarks
SpeakerGuard, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.7 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
TPA3136AD2PWP
ACTIVE
HTSSOP
PWP
28
50
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPA3136AD2
TPA3136AD2PWPR
ACTIVE
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPA3136AD2
TPA3136D2PWP
ACTIVE
HTSSOP
PWP
28
50
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TPA3136D2
TPA3136D2PWPR
ACTIVE
HTSSOP
PWP
28
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TPA3136D2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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